LLVM  10.0.0svn
PPCMachineScheduler.cpp
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1 //===- PPCMachineScheduler.cpp - MI Scheduler for PowerPC -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "PPCMachineScheduler.h"
11 
12 using namespace llvm;
13 
14 static cl::opt<bool>
15 DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
16  cl::desc("Disable scheduling addi instruction before"
17  "load for ppc"), cl::Hidden);
18 
19 bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
20  SchedCandidate &TryCand,
21  SchedBoundary &Zone) const {
23  return false;
24 
25  auto isADDIInstr = [&] (const MachineInstr &Inst) {
26  return Inst.getOpcode() == PPC::ADDI || Inst.getOpcode() == PPC::ADDI8;
27  };
28 
29  SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
30  SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
31  if (isADDIInstr(*FirstCand.SU->getInstr()) &&
32  SecondCand.SU->getInstr()->mayLoad()) {
33  TryCand.Reason = Stall;
34  return true;
35  }
36  if (FirstCand.SU->getInstr()->mayLoad() &&
37  isADDIInstr(*SecondCand.SU->getInstr())) {
38  TryCand.Reason = NoCand;
39  return true;
40  }
41 
42  return false;
43 }
44 
46  SchedCandidate &TryCand,
47  SchedBoundary *Zone) const {
48  GenericScheduler::tryCandidate(Cand, TryCand, Zone);
49 
50  if (!Cand.isValid() || !Zone)
51  return;
52 
53  // Add powerpc specific heuristic only when TryCand isn't selected or
54  // selected as node order.
55  if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
56  return;
57 
58  // There are some benefits to schedule the ADDI before the load to hide the
59  // latency, as RA may create a true dependency between the load and addi.
60  if (biasAddiLoadCandidate(Cand, TryCand, *Zone))
61  return;
62 }
63 
65  // Custom PPC PostRA specific behavior here.
67 }
68 
70  // Custom PPC PostRA specific behavior here.
72 }
73 
75  // Custom PPC PostRA specific initialization here.
77 }
78 
80  // Custom PPC PostRA specific scheduling here.
81  return PostGenericScheduler::pickNode(IsTopNode);
82 }
83 
void leaveMBB() override
Tell the strategy that current MBB is done.
Each Scheduling boundary is associated with ready queues.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void initialize(ScheduleDAGMI *Dag) override
Initialize the strategy after building the DAG for a new region.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule.
virtual void enterMBB(MachineBasicBlock *MBB)
Tell the strategy that MBB is about to be processed.
void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override
Apply a set of heuristics to a new candidate.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule.
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
virtual void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const
Apply a set of heuristics to a new candidate.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void initialize(ScheduleDAGMI *Dag) override
Initialize the strategy after building the DAG for a new region.
void enterMBB(MachineBasicBlock *MBB) override
Tell the strategy that MBB is about to be processed.
virtual void leaveMBB()
Tell the strategy that current MBB is done.
static cl::opt< bool > DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", cl::desc("Disable scheduling addi instruction before" "load for ppc"), cl::Hidden)
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242