LLVM  9.0.0svn
PPCRegisterInfo.h
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1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 
17 #include "PPC.h"
18 #include "llvm/ADT/DenseMap.h"
19 
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
22 
23 namespace llvm {
24 
25 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
26  unsigned Reg = 0;
27  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
28  SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
29  Reg = PPC::CR0;
30  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
31  SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
32  Reg = PPC::CR1;
33  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
34  SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
35  Reg = PPC::CR2;
36  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
37  SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
38  Reg = PPC::CR3;
39  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
40  SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
41  Reg = PPC::CR4;
42  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
43  SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
44  Reg = PPC::CR5;
45  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
46  SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
47  Reg = PPC::CR6;
48  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
49  SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
50  Reg = PPC::CR7;
51 
52  assert(Reg != 0 && "Invalid CR bit register");
53  return Reg;
54 }
55 
57  DenseMap<unsigned, unsigned> ImmToIdxMap;
58  const PPCTargetMachine &TM;
59 
60 public:
62 
63  /// getPointerRegClass - Return the register class to use to hold pointers.
64  /// This is used for addressing modes.
65  const TargetRegisterClass *
66  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
67 
68  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
69  MachineFunction &MF) const override;
70 
71  const TargetRegisterClass *
73  const MachineFunction &MF) const override;
74 
75  /// Code Generation virtual methods...
76  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
77  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
79  CallingConv::ID CC) const override;
80  const uint32_t *getNoPreservedMask() const override;
81 
82  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
83 
84  BitVector getReservedRegs(const MachineFunction &MF) const override;
85  bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
86 
87  /// We require the register scavenger.
88  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
89  return true;
90  }
91 
92  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
93 
94  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
95  return true;
96  }
97 
98  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
99  return true;
100  }
101 
105  unsigned FrameIndex) const;
107  unsigned FrameIndex) const;
109  unsigned FrameIndex) const;
111  unsigned FrameIndex) const;
113  unsigned FrameIndex) const;
115  unsigned FrameIndex) const;
116 
117  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
118  int &FrameIdx) const override;
120  unsigned FIOperandNum,
121  RegScavenger *RS = nullptr) const override;
122 
123  // Support for virtual base registers.
124  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
126  unsigned BaseReg, int FrameIdx,
127  int64_t Offset) const override;
128  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
129  int64_t Offset) const override;
130  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
131  int64_t Offset) const override;
132 
133  // Debug information queries.
134  unsigned getFrameRegister(const MachineFunction &MF) const override;
135 
136  // Base pointer (stack realignment) support.
137  unsigned getBaseRegister(const MachineFunction &MF) const;
138  bool hasBasePointer(const MachineFunction &MF) const;
139 
140  /// stripRegisterPrefix - This method strips the character prefix from a
141  /// register name so that only the number is left. Used by for linux asm.
142  static const char *stripRegisterPrefix(const char *RegName) {
143  switch (RegName[0]) {
144  case 'r':
145  case 'f':
146  case 'q': // for QPX
147  case 'v':
148  if (RegName[1] == 's')
149  return RegName + 2;
150  return RegName + 1;
151  case 'c': if (RegName[1] == 'r') return RegName + 2;
152  }
153 
154  return RegName;
155  }
156 };
157 
158 } // end namespace llvm
159 
160 #endif
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction&#39;s frame index reference would be better served by a base register oth...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
unsigned Reg
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool hasBasePointer(const MachineFunction &MF) const
static const char * stripRegisterPrefix(const char *RegName)
stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned getBaseRegister(const MachineFunction &MF) const
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Common code between 32-bit and 64-bit PowerPC targets.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:63
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override