LLVM  8.0.0svn
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
16 #include "PPC.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
25 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 
45 static cl::opt<bool>
46  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
47  cl::desc("enable coalescing of duplicate branches for PPC"));
48 static cl::
49 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
50  cl::desc("Disable CTR loops for PPC"));
51 
52 static cl::
53 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
54  cl::desc("Disable PPC loop preinc prep"));
55 
56 static cl::opt<bool>
57 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
58  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
59 
60 static cl::
61 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
62  cl::desc("Disable VSX Swap Removal for PPC"));
63 
64 static cl::
65 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
66  cl::desc("Disable QPX load splat simplification"));
67 
68 static cl::
69 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
70  cl::desc("Disable machine peepholes for PPC"));
71 
72 static cl::opt<bool>
73 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
74  cl::desc("Enable optimizations on complex GEPs"),
75  cl::init(true));
76 
77 static cl::opt<bool>
78 EnablePrefetch("enable-ppc-prefetching",
79  cl::desc("disable software prefetching on PPC"),
80  cl::init(false), cl::Hidden);
81 
82 static cl::opt<bool>
83 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
84  cl::desc("Add extra TOC register dependencies"),
85  cl::init(true), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableMachineCombinerPass("ppc-machine-combiner",
89  cl::desc("Enable the machine combiner pass"),
90  cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93  ReduceCRLogical("ppc-reduce-cr-logicals",
94  cl::desc("Expand eligible cr-logical binary ops to branches"),
95  cl::init(false), cl::Hidden);
96 extern "C" void LLVMInitializePowerPCTarget() {
97  // Register the targets
101 
108 }
109 
110 /// Return the datalayout string of a subtarget.
111 static std::string getDataLayoutString(const Triple &T) {
112  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
113  std::string Ret;
114 
115  // Most PPC* platforms are big endian, PPC64LE is little endian.
116  if (T.getArch() == Triple::ppc64le)
117  Ret = "e";
118  else
119  Ret = "E";
120 
122 
123  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
124  // pointers.
125  if (!is64Bit || T.getOS() == Triple::Lv2)
126  Ret += "-p:32:32";
127 
128  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
129  // documentation are wrong; these are correct (i.e. "what gcc does").
130  if (is64Bit || !T.isOSDarwin())
131  Ret += "-i64:64";
132  else
133  Ret += "-f64:32:64";
134 
135  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
136  if (is64Bit)
137  Ret += "-n32:64";
138  else
139  Ret += "-n32";
140 
141  return Ret;
142 }
143 
145  const Triple &TT) {
146  std::string FullFS = FS;
147 
148  // Make sure 64-bit features are available when CPUname is generic
149  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
150  if (!FullFS.empty())
151  FullFS = "+64bit," + FullFS;
152  else
153  FullFS = "+64bit";
154  }
155 
156  if (OL >= CodeGenOpt::Default) {
157  if (!FullFS.empty())
158  FullFS = "+crbits," + FullFS;
159  else
160  FullFS = "+crbits";
161  }
162 
163  if (OL != CodeGenOpt::None) {
164  if (!FullFS.empty())
165  FullFS = "+invariant-function-descriptors," + FullFS;
166  else
167  FullFS = "+invariant-function-descriptors";
168  }
169 
170  return FullFS;
171 }
172 
173 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
174  // If it isn't a Mach-O file then it's going to be a linux ELF
175  // object file.
176  if (TT.isOSDarwin())
177  return llvm::make_unique<TargetLoweringObjectFileMachO>();
178 
179  return llvm::make_unique<PPC64LinuxTargetObjectFile>();
180 }
181 
183  const TargetOptions &Options) {
184  if (TT.isOSDarwin())
185  report_fatal_error("Darwin is no longer supported for PowerPC");
186 
187  if (Options.MCOptions.getABIName().startswith("elfv1"))
189  else if (Options.MCOptions.getABIName().startswith("elfv2"))
191 
192  assert(Options.MCOptions.getABIName().empty() &&
193  "Unknown target-abi option!");
194 
195  if (TT.isMacOSX())
197 
198  switch (TT.getArch()) {
199  case Triple::ppc64le:
201  case Triple::ppc64:
203  default:
205  }
206 }
207 
210  if (RM.hasValue())
211  return *RM;
212 
213  // Darwin defaults to dynamic-no-pic.
214  if (TT.isOSDarwin())
215  return Reloc::DynamicNoPIC;
216 
217  // Non-darwin 64-bit platforms are PIC by default.
218  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
219  return Reloc::PIC_;
220 
221  // 32-bit is static by default.
222  return Reloc::Static;
223 }
224 
227  bool JIT) {
228  if (CM)
229  return *CM;
230  if (!TT.isOSDarwin() && !JIT &&
231  (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
232  return CodeModel::Medium;
233  return CodeModel::Small;
234 }
235 
236 // The FeatureString here is a little subtle. We are modifying the feature
237 // string with what are (currently) non-function specific overrides as it goes
238 // into the LLVMTargetMachine constructor and then using the stored value in the
239 // Subtarget constructor below it.
241  StringRef CPU, StringRef FS,
242  const TargetOptions &Options,
245  CodeGenOpt::Level OL, bool JIT)
246  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
247  computeFSAdditions(FS, OL, TT), Options,
248  getEffectiveRelocModel(TT, RM),
249  getEffectiveCodeModel(TT, CM, JIT), OL),
250  TLOF(createTLOF(getTargetTriple())),
251  TargetABI(computeTargetABI(TT, Options)) {
252  initAsmInfo();
253 }
254 
256 
257 const PPCSubtarget *
259  Attribute CPUAttr = F.getFnAttribute("target-cpu");
260  Attribute FSAttr = F.getFnAttribute("target-features");
261 
262  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
263  ? CPUAttr.getValueAsString().str()
264  : TargetCPU;
265  std::string FS = !FSAttr.hasAttribute(Attribute::None)
266  ? FSAttr.getValueAsString().str()
267  : TargetFS;
268 
269  // FIXME: This is related to the code below to reset the target options,
270  // we need to know whether or not the soft float flag is set on the
271  // function before we can generate a subtarget. We also need to use
272  // it as a key for the subtarget since that can be the only difference
273  // between two functions.
274  bool SoftFloat =
275  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
276  // If the soft float attribute is set on the function turn on the soft float
277  // subtarget feature.
278  if (SoftFloat)
279  FS += FS.empty() ? "-hard-float" : ",-hard-float";
280 
281  auto &I = SubtargetMap[CPU + FS];
282  if (!I) {
283  // This needs to be done before we create a new subtarget since any
284  // creation will depend on the TM and the code generation flags on the
285  // function that reside in TargetOptions.
287  I = llvm::make_unique<PPCSubtarget>(
288  TargetTriple, CPU,
289  // FIXME: It would be good to have the subtarget additions here
290  // not necessary. Anything that turns them on/off (overrides) ends
291  // up being put at the end of the feature string, but the defaults
292  // shouldn't require adding them. Fixing this means pulling Feature64Bit
293  // out of most of the target cpus in the .td file and making it set only
294  // as part of initialization via the TargetTriple.
296  }
297  return I.get();
298 }
299 
300 //===----------------------------------------------------------------------===//
301 // Pass Pipeline Configuration
302 //===----------------------------------------------------------------------===//
303 
304 namespace {
305 
306 /// PPC Code Generator Pass Configuration Options.
307 class PPCPassConfig : public TargetPassConfig {
308 public:
309  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
310  : TargetPassConfig(TM, PM) {
311  // At any optimization level above -O0 we use the Machine Scheduler and not
312  // the default Post RA List Scheduler.
313  if (TM.getOptLevel() != CodeGenOpt::None)
314  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
315  }
316 
317  PPCTargetMachine &getPPCTargetMachine() const {
318  return getTM<PPCTargetMachine>();
319  }
320 
321  void addIRPasses() override;
322  bool addPreISel() override;
323  bool addILPOpts() override;
324  bool addInstSelector() override;
325  void addMachineSSAOptimization() override;
326  void addPreRegAlloc() override;
327  void addPreSched2() override;
328  void addPreEmitPass() override;
329 };
330 
331 } // end anonymous namespace
332 
334  return new PPCPassConfig(*this, PM);
335 }
336 
337 void PPCPassConfig::addIRPasses() {
338  if (TM->getOptLevel() != CodeGenOpt::None)
339  addPass(createPPCBoolRetToIntPass());
340  addPass(createAtomicExpandPass());
341 
342  // For the BG/Q (or if explicitly requested), add explicit data prefetch
343  // intrinsics.
344  bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
346  if (EnablePrefetch.getNumOccurrences() > 0)
347  UsePrefetching = EnablePrefetch;
348  if (UsePrefetching)
349  addPass(createLoopDataPrefetchPass());
350 
351  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
352  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
353  // and lower a GEP with multiple indices to either arithmetic operations or
354  // multiple GEPs with single index.
356  // Call EarlyCSE pass to find and remove subexpressions in the lowered
357  // result.
358  addPass(createEarlyCSEPass());
359  // Do loop invariant code motion in case part of the lowered result is
360  // invariant.
361  addPass(createLICMPass());
362  }
363 
365 }
366 
367 bool PPCPassConfig::addPreISel() {
369  addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
370 
372  addPass(createPPCCTRLoops());
373 
374  return false;
375 }
376 
377 bool PPCPassConfig::addILPOpts() {
378  addPass(&EarlyIfConverterID);
379 
381  addPass(&MachineCombinerID);
382 
383  return true;
384 }
385 
386 bool PPCPassConfig::addInstSelector() {
387  // Install an instruction selector.
388  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
389 
390 #ifndef NDEBUG
392  addPass(createPPCCTRLoopsVerify());
393 #endif
394 
395  addPass(createPPCVSXCopyPass());
396  return false;
397 }
398 
399 void PPCPassConfig::addMachineSSAOptimization() {
400  // PPCBranchCoalescingPass need to be done before machine sinking
401  // since it merges empty blocks.
405  // For little endian, remove where possible the vector swap instructions
406  // introduced at code generation to normalize vector element order.
407  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
409  addPass(createPPCVSXSwapRemovalPass());
410  // Reduce the number of cr-logical ops.
413  // Target-specific peephole cleanups performed after instruction
414  // selection.
415  if (!DisableMIPeephole) {
416  addPass(createPPCMIPeepholePass());
418  }
419 }
420 
421 void PPCPassConfig::addPreRegAlloc() {
422  if (getOptLevel() != CodeGenOpt::None) {
426  }
427 
428  // FIXME: We probably don't need to run these for -fPIE.
429  if (getPPCTargetMachine().isPositionIndependent()) {
430  // FIXME: LiveVariables should not be necessary here!
431  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
432  // LiveVariables. This (unnecessary) dependency has been removed now,
433  // however a stage-2 clang build fails without LiveVariables computed here.
434  addPass(&LiveVariablesID, false);
435  addPass(createPPCTLSDynamicCallPass());
436  }
438  addPass(createPPCTOCRegDepsPass());
439 }
440 
441 void PPCPassConfig::addPreSched2() {
442  if (getOptLevel() != CodeGenOpt::None) {
443  addPass(&IfConverterID);
444 
445  // This optimization must happen after anything that might do store-to-load
446  // forwarding. Here we're after RA (and, thus, when spills are inserted)
447  // but before post-RA scheduling.
448  if (!DisableQPXLoadSplat)
449  addPass(createPPCQPXLoadSplatPass());
450  }
451 }
452 
453 void PPCPassConfig::addPreEmitPass() {
454  addPass(createPPCPreEmitPeepholePass());
455  addPass(createPPCExpandISELPass());
456 
457  if (getOptLevel() != CodeGenOpt::None)
458  addPass(createPPCEarlyReturnPass(), false);
459  // Must run branch selection immediately preceding the asm printer.
460  addPass(createPPCBranchSelectionPass(), false);
461 }
462 
465  return TargetTransformInfo(PPCTTIImpl(this, F));
466 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:446
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
void initializePPCTLSDynamicCallPass(PassRegistry &)
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:298
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializePPCMIPeepholePass(PassRegistry &)
F(f)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
char & PPCVSXFMAMutateID
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:157
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
FunctionPass * createLoopDataPrefetchPass()
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createPPCTOCRegDepsPass()
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
FunctionPass * createPPCCTRLoops()
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
Target-Independent Code Generator Pass Configuration Options.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
FunctionPass * createPPCReduceCRLogicalsPass()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
FunctionPass * createPPCBoolRetToIntPass()
Target & getThePPC64Target()
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const PPCSubtarget * getSubtargetImpl() const =delete
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
~PPCTargetMachine() override
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(false), cl::Hidden)
void initializePPCVSXFMAMutatePass(PassRegistry &)
Pass * createLICMPass()
Definition: LICM.cpp:248
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
Common code between 32-bit and 64-bit PowerPC targets.
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCExpandISELPass(PassRegistry &)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
std::string TargetCPU
Definition: TargetMachine.h:79
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
bool hasValue() const
Definition: Optional.h:183
void initializePPCPreEmitPeepholePass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
FunctionPass * createPPCQPXLoadSplatPass()
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
bool isPositionIndependent() const
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
std::string TargetFS
Definition: TargetMachine.h:80
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
FunctionPass * createPPCPreEmitPeepholePass()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1319
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
FunctionPass * createPPCExpandISELPass()