48 cl::desc(
"enable coalescing of duplicate branches for PPC"));
51 cl::desc(
"Disable CTR loops for PPC"));
55 cl::desc(
"Disable PPC loop preinc prep"));
63 cl::desc(
"Disable VSX Swap Removal for PPC"));
67 cl::desc(
"Disable QPX load splat simplification"));
71 cl::desc(
"Disable machine peepholes for PPC"));
75 cl::desc(
"Enable optimizations on complex GEPs"),
80 cl::desc(
"disable software prefetching on PPC"),
85 cl::desc(
"Add extra TOC register dependencies"),
90 cl::desc(
"Enable the machine combiner pass"),
95 cl::desc(
"Expand eligible cr-logical binary ops to branches"),
160 std::string FullFS = FS;
165 FullFS =
"+64bit," + FullFS;
172 FullFS =
"+crbits," + FullFS;
179 FullFS =
"+invariant-function-descriptors," + FullFS;
181 FullFS =
"+invariant-function-descriptors";
189 return std::make_unique<TargetLoweringObjectFileMachO>();
192 return std::make_unique<TargetLoweringObjectFileXCOFF>();
194 return std::make_unique<PPC64LinuxTargetObjectFile>();
208 "Unknown target-abi option!");
272 std::make_unique<PPCPreRASchedStrategy>(
C) :
273 std::make_unique<GenericScheduler>(C));
284 std::make_unique<PPCPostRASchedStrategy>(
C) :
285 std::make_unique<PostGenericScheduler>(C),
true);
333 FS += FS.
empty() ?
"-hard-float" :
",-hard-float";
335 auto &
I = SubtargetMap[CPU + FS];
341 I = std::make_unique<PPCSubtarget>(
372 return getTM<PPCTargetMachine>();
375 void addIRPasses()
override;
376 bool addPreISel()
override;
377 bool addILPOpts()
override;
378 bool addInstSelector()
override;
379 void addMachineSSAOptimization()
override;
380 void addPreRegAlloc()
override;
381 void addPreSched2()
override;
382 void addPreEmitPass()
override;
396 return new PPCPassConfig(*
this, PM);
399 void PPCPassConfig::addIRPasses() {
406 bool UsePrefetching =
TM->getTargetTriple().getVendor() ==
Triple::BGQ &&
429 bool PPCPassConfig::addPreISel() {
439 bool PPCPassConfig::addILPOpts() {
448 bool PPCPassConfig::addInstSelector() {
461 void PPCPassConfig::addMachineSSAOptimization() {
483 void PPCPassConfig::addPreRegAlloc() {
506 void PPCPassConfig::addPreSched2() {
518 void PPCPassConfig::addPreEmitPass() {
535 "Run PowerPC PreRA specific scheduler",
540 "Run PowerPC PostRA specific scheduler",
void initializePPCTOCRegDepsPass(PassRegistry &)
void initializePPCVSXCopyPass(PassRegistry &)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
void initializePPCTLSDynamicCallPass(PassRegistry &)
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
void initializePPCQPXLoadSplatPass(PassRegistry &)
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializePPCMIPeepholePass(PassRegistry &)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
MachineSchedRegistry provides a selection of available machine instruction schedulers.
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(true), cl::Hidden)
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createPPCTOCRegDepsPass()
void initializePPCBSelPass(PassRegistry &)
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
void initializePPCReduceCRLogicalsPass(PassRegistry &)
void initializePPCBranchCoalescingPass(PassRegistry &)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Target-Independent Code Generator Pass Configuration Options.
void initializePPCLoopPreIncPrepPass(PassRegistry &)
FunctionPass * createPPCReduceCRLogicalsPass()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass ...
static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static ScheduleDAGInstrs * createPPCMachineScheduler(MachineSchedContext *C)
FunctionPass * createPPCBoolRetToIntPass()
Target & getThePPC64Target()
void initializePPCVSXSwapRemovalPass(PassRegistry &)
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const PPCSubtarget * getSubtargetImpl() const =delete
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
~PPCTargetMachine() override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
void initializePPCVSXFMAMutatePass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
Common code between 32-bit and 64-bit PowerPC targets.
void initializePPCEarlyReturnPass(PassRegistry &)
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
bool isOSAIX() const
Tests whether the OS is AIX.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCExpandISELPass(PassRegistry &)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static ScheduleDAGInstrs * createPPCPostMachineScheduler(MachineSchedContext *C)
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
A ScheduleDAG for scheduling lists of MachineInstr.
void initializePPCPreEmitPeepholePass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
FunctionPass * createPPCQPXLoadSplatPass()
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isPositionIndependent() const
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
bool usePPCPostRASchedStrategy() const
FunctionPass * createPPCPreEmitPeepholePass()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
bool usePPCPreRASchedStrategy() const
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
FunctionPass * createAtomicExpandPass()
FunctionPass * createPPCExpandISELPass()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.