LLVM  9.0.0svn
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
25 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 
45 static cl::opt<bool>
46  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
47  cl::desc("enable coalescing of duplicate branches for PPC"));
48 static cl::
49 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
50  cl::desc("Disable CTR loops for PPC"));
51 
52 static cl::
53 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
54  cl::desc("Disable PPC loop preinc prep"));
55 
56 static cl::opt<bool>
57 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
58  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
59 
60 static cl::
61 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
62  cl::desc("Disable VSX Swap Removal for PPC"));
63 
64 static cl::
65 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
66  cl::desc("Disable QPX load splat simplification"));
67 
68 static cl::
69 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
70  cl::desc("Disable machine peepholes for PPC"));
71 
72 static cl::opt<bool>
73 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
74  cl::desc("Enable optimizations on complex GEPs"),
75  cl::init(true));
76 
77 static cl::opt<bool>
78 EnablePrefetch("enable-ppc-prefetching",
79  cl::desc("disable software prefetching on PPC"),
80  cl::init(false), cl::Hidden);
81 
82 static cl::opt<bool>
83 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
84  cl::desc("Add extra TOC register dependencies"),
85  cl::init(true), cl::Hidden);
86 
87 static cl::opt<bool>
88 EnableMachineCombinerPass("ppc-machine-combiner",
89  cl::desc("Enable the machine combiner pass"),
90  cl::init(true), cl::Hidden);
91 
92 static cl::opt<bool>
93  ReduceCRLogical("ppc-reduce-cr-logicals",
94  cl::desc("Expand eligible cr-logical binary ops to branches"),
95  cl::init(false), cl::Hidden);
96 extern "C" void LLVMInitializePowerPCTarget() {
97  // Register the targets
101 
104 #ifndef NDEBUG
106 #endif
122 }
123 
124 /// Return the datalayout string of a subtarget.
125 static std::string getDataLayoutString(const Triple &T) {
126  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
127  std::string Ret;
128 
129  // Most PPC* platforms are big endian, PPC64LE is little endian.
130  if (T.getArch() == Triple::ppc64le)
131  Ret = "e";
132  else
133  Ret = "E";
134 
136 
137  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
138  // pointers.
139  if (!is64Bit || T.getOS() == Triple::Lv2)
140  Ret += "-p:32:32";
141 
142  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
143  // documentation are wrong; these are correct (i.e. "what gcc does").
144  if (is64Bit || !T.isOSDarwin())
145  Ret += "-i64:64";
146  else
147  Ret += "-f64:32:64";
148 
149  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
150  if (is64Bit)
151  Ret += "-n32:64";
152  else
153  Ret += "-n32";
154 
155  return Ret;
156 }
157 
159  const Triple &TT) {
160  std::string FullFS = FS;
161 
162  // Make sure 64-bit features are available when CPUname is generic
163  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
164  if (!FullFS.empty())
165  FullFS = "+64bit," + FullFS;
166  else
167  FullFS = "+64bit";
168  }
169 
170  if (OL >= CodeGenOpt::Default) {
171  if (!FullFS.empty())
172  FullFS = "+crbits," + FullFS;
173  else
174  FullFS = "+crbits";
175  }
176 
177  if (OL != CodeGenOpt::None) {
178  if (!FullFS.empty())
179  FullFS = "+invariant-function-descriptors," + FullFS;
180  else
181  FullFS = "+invariant-function-descriptors";
182  }
183 
184  return FullFS;
185 }
186 
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188  // If it isn't a Mach-O file then it's going to be a linux ELF
189  // object file.
190  if (TT.isOSDarwin())
191  return llvm::make_unique<TargetLoweringObjectFileMachO>();
192 
193  return llvm::make_unique<PPC64LinuxTargetObjectFile>();
194 }
195 
197  const TargetOptions &Options) {
198  if (TT.isOSDarwin())
199  report_fatal_error("Darwin is no longer supported for PowerPC");
200 
201  if (Options.MCOptions.getABIName().startswith("elfv1"))
203  else if (Options.MCOptions.getABIName().startswith("elfv2"))
205 
206  assert(Options.MCOptions.getABIName().empty() &&
207  "Unknown target-abi option!");
208 
209  if (TT.isMacOSX())
211 
212  switch (TT.getArch()) {
213  case Triple::ppc64le:
215  case Triple::ppc64:
217  default:
219  }
220 }
221 
224  if (RM.hasValue())
225  return *RM;
226 
227  // Darwin defaults to dynamic-no-pic.
228  if (TT.isOSDarwin())
229  return Reloc::DynamicNoPIC;
230 
231  // Big Endian PPC is PIC by default.
232  if (TT.getArch() == Triple::ppc64)
233  return Reloc::PIC_;
234 
235  // Rest are static by default.
236  return Reloc::Static;
237 }
238 
241  bool JIT) {
242  if (CM) {
243  if (*CM == CodeModel::Tiny)
244  report_fatal_error("Target does not support the tiny CodeModel");
245  if (*CM == CodeModel::Kernel)
246  report_fatal_error("Target does not support the kernel CodeModel");
247  return *CM;
248  }
249  if (!TT.isOSDarwin() && !JIT &&
250  (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
251  return CodeModel::Medium;
252  return CodeModel::Small;
253 }
254 
255 
257  ScheduleDAGMILive *DAG =
258  new ScheduleDAGMILive(C, llvm::make_unique<PPCPreRASchedStrategy>(C));
259  // add DAG Mutations here.
261  return DAG;
262 }
263 
266  ScheduleDAGMI *DAG =
267  new ScheduleDAGMI(C, llvm::make_unique<PPCPostRASchedStrategy>(C), true);
268  // add DAG Mutations here.
269  return DAG;
270 }
271 
272 // The FeatureString here is a little subtle. We are modifying the feature
273 // string with what are (currently) non-function specific overrides as it goes
274 // into the LLVMTargetMachine constructor and then using the stored value in the
275 // Subtarget constructor below it.
277  StringRef CPU, StringRef FS,
278  const TargetOptions &Options,
281  CodeGenOpt::Level OL, bool JIT)
282  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
283  computeFSAdditions(FS, OL, TT), Options,
284  getEffectiveRelocModel(TT, RM),
285  getEffectivePPCCodeModel(TT, CM, JIT), OL),
286  TLOF(createTLOF(getTargetTriple())),
287  TargetABI(computeTargetABI(TT, Options)) {
288  initAsmInfo();
289 }
290 
292 
293 const PPCSubtarget *
295  Attribute CPUAttr = F.getFnAttribute("target-cpu");
296  Attribute FSAttr = F.getFnAttribute("target-features");
297 
298  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
299  ? CPUAttr.getValueAsString().str()
300  : TargetCPU;
301  std::string FS = !FSAttr.hasAttribute(Attribute::None)
302  ? FSAttr.getValueAsString().str()
303  : TargetFS;
304 
305  // FIXME: This is related to the code below to reset the target options,
306  // we need to know whether or not the soft float flag is set on the
307  // function before we can generate a subtarget. We also need to use
308  // it as a key for the subtarget since that can be the only difference
309  // between two functions.
310  bool SoftFloat =
311  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
312  // If the soft float attribute is set on the function turn on the soft float
313  // subtarget feature.
314  if (SoftFloat)
315  FS += FS.empty() ? "-hard-float" : ",-hard-float";
316 
317  auto &I = SubtargetMap[CPU + FS];
318  if (!I) {
319  // This needs to be done before we create a new subtarget since any
320  // creation will depend on the TM and the code generation flags on the
321  // function that reside in TargetOptions.
323  I = llvm::make_unique<PPCSubtarget>(
324  TargetTriple, CPU,
325  // FIXME: It would be good to have the subtarget additions here
326  // not necessary. Anything that turns them on/off (overrides) ends
327  // up being put at the end of the feature string, but the defaults
328  // shouldn't require adding them. Fixing this means pulling Feature64Bit
329  // out of most of the target cpus in the .td file and making it set only
330  // as part of initialization via the TargetTriple.
332  }
333  return I.get();
334 }
335 
336 //===----------------------------------------------------------------------===//
337 // Pass Pipeline Configuration
338 //===----------------------------------------------------------------------===//
339 
340 namespace {
341 
342 /// PPC Code Generator Pass Configuration Options.
343 class PPCPassConfig : public TargetPassConfig {
344 public:
345  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
346  : TargetPassConfig(TM, PM) {
347  // At any optimization level above -O0 we use the Machine Scheduler and not
348  // the default Post RA List Scheduler.
349  if (TM.getOptLevel() != CodeGenOpt::None)
350  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
351  }
352 
353  PPCTargetMachine &getPPCTargetMachine() const {
354  return getTM<PPCTargetMachine>();
355  }
356 
357  void addIRPasses() override;
358  bool addPreISel() override;
359  bool addILPOpts() override;
360  bool addInstSelector() override;
361  void addMachineSSAOptimization() override;
362  void addPreRegAlloc() override;
363  void addPreSched2() override;
364  void addPreEmitPass() override;
366  createMachineScheduler(MachineSchedContext *C) const override {
367  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
368  if (ST.usePPCPreRASchedStrategy())
369  return createPPCMachineScheduler(C);
370  return nullptr;
371  }
373  createPostMachineScheduler(MachineSchedContext *C) const override {
374  const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
375  if (ST.usePPCPostRASchedStrategy())
377  return nullptr;
378  }
379 };
380 
381 } // end anonymous namespace
382 
384  return new PPCPassConfig(*this, PM);
385 }
386 
387 void PPCPassConfig::addIRPasses() {
388  if (TM->getOptLevel() != CodeGenOpt::None)
389  addPass(createPPCBoolRetToIntPass());
390  addPass(createAtomicExpandPass());
391 
392  // For the BG/Q (or if explicitly requested), add explicit data prefetch
393  // intrinsics.
394  bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
396  if (EnablePrefetch.getNumOccurrences() > 0)
397  UsePrefetching = EnablePrefetch;
398  if (UsePrefetching)
399  addPass(createLoopDataPrefetchPass());
400 
401  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
402  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
403  // and lower a GEP with multiple indices to either arithmetic operations or
404  // multiple GEPs with single index.
406  // Call EarlyCSE pass to find and remove subexpressions in the lowered
407  // result.
408  addPass(createEarlyCSEPass());
409  // Do loop invariant code motion in case part of the lowered result is
410  // invariant.
411  addPass(createLICMPass());
412  }
413 
415 }
416 
417 bool PPCPassConfig::addPreISel() {
419  addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
420 
422  addPass(createPPCCTRLoops());
423 
424  return false;
425 }
426 
427 bool PPCPassConfig::addILPOpts() {
428  addPass(&EarlyIfConverterID);
429 
431  addPass(&MachineCombinerID);
432 
433  return true;
434 }
435 
436 bool PPCPassConfig::addInstSelector() {
437  // Install an instruction selector.
438  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
439 
440 #ifndef NDEBUG
442  addPass(createPPCCTRLoopsVerify());
443 #endif
444 
445  addPass(createPPCVSXCopyPass());
446  return false;
447 }
448 
449 void PPCPassConfig::addMachineSSAOptimization() {
450  // PPCBranchCoalescingPass need to be done before machine sinking
451  // since it merges empty blocks.
455  // For little endian, remove where possible the vector swap instructions
456  // introduced at code generation to normalize vector element order.
457  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
459  addPass(createPPCVSXSwapRemovalPass());
460  // Reduce the number of cr-logical ops.
463  // Target-specific peephole cleanups performed after instruction
464  // selection.
465  if (!DisableMIPeephole) {
466  addPass(createPPCMIPeepholePass());
468  }
469 }
470 
471 void PPCPassConfig::addPreRegAlloc() {
472  if (getOptLevel() != CodeGenOpt::None) {
476  }
477 
478  // FIXME: We probably don't need to run these for -fPIE.
479  if (getPPCTargetMachine().isPositionIndependent()) {
480  // FIXME: LiveVariables should not be necessary here!
481  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
482  // LiveVariables. This (unnecessary) dependency has been removed now,
483  // however a stage-2 clang build fails without LiveVariables computed here.
484  addPass(&LiveVariablesID, false);
485  addPass(createPPCTLSDynamicCallPass());
486  }
488  addPass(createPPCTOCRegDepsPass());
489 }
490 
491 void PPCPassConfig::addPreSched2() {
492  if (getOptLevel() != CodeGenOpt::None) {
493  addPass(&IfConverterID);
494 
495  // This optimization must happen after anything that might do store-to-load
496  // forwarding. Here we're after RA (and, thus, when spills are inserted)
497  // but before post-RA scheduling.
498  if (!DisableQPXLoadSplat)
499  addPass(createPPCQPXLoadSplatPass());
500  }
501 }
502 
503 void PPCPassConfig::addPreEmitPass() {
504  addPass(createPPCPreEmitPeepholePass());
505  addPass(createPPCExpandISELPass());
506 
507  if (getOptLevel() != CodeGenOpt::None)
508  addPass(createPPCEarlyReturnPass(), false);
509  // Must run branch selection immediately preceding the asm printer.
510  addPass(createPPCBranchSelectionPass(), false);
511 }
512 
515  return TargetTransformInfo(PPCTTIImpl(this, F));
516 }
517 
519 PPCPreRASchedRegistry("ppc-prera",
520  "Run PowerPC PreRA specific scheduler",
522 
524 PPCPostRASchedRegistry("ppc-postra",
525  "Run PowerPC PostRA specific scheduler",
void initializePPCTOCRegDepsPass(PassRegistry &)
void initializePPCVSXCopyPass(PassRegistry &)
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:476
static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:448
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
void initializePPCTLSDynamicCallPass(PassRegistry &)
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:300
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
void initializePPCQPXLoadSplatPass(PassRegistry &)
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializePPCMIPeepholePass(PassRegistry &)
F(f)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
MachineSchedRegistry provides a selection of available machine instruction schedulers.
char & PPCVSXFMAMutateID
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createLoopDataPrefetchPass()
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createPPCTOCRegDepsPass()
void initializePPCBSelPass(PassRegistry &)
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
FunctionPass * createPPCCTRLoops()
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
void initializePPCReduceCRLogicalsPass(PassRegistry &)
void initializePPCBranchCoalescingPass(PassRegistry &)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target-Independent Code Generator Pass Configuration Options.
void initializePPCLoopPreIncPrepPass(PassRegistry &)
FunctionPass * createPPCReduceCRLogicalsPass()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:291
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass ...
static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static ScheduleDAGInstrs * createPPCMachineScheduler(MachineSchedContext *C)
FunctionPass * createPPCBoolRetToIntPass()
Target & getThePPC64Target()
void initializePPCVSXSwapRemovalPass(PassRegistry &)
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const PPCSubtarget * getSubtargetImpl() const =delete
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
~PPCTargetMachine() override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(false), cl::Hidden)
void initializePPCVSXFMAMutatePass(PassRegistry &)
Pass * createLICMPass()
Definition: LICM.cpp:303
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
Common code between 32-bit and 64-bit PowerPC targets.
void initializePPCEarlyReturnPass(PassRegistry &)
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
void initializePPCCTRLoopsPass(PassRegistry &)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCExpandISELPass(PassRegistry &)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static ScheduleDAGInstrs * createPPCPostMachineScheduler(MachineSchedContext *C)
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
std::string TargetCPU
Definition: TargetMachine.h:85
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
void initializePPCPreEmitPeepholePass(PassRegistry &)
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
FunctionPass * createPPCQPXLoadSplatPass()
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
bool isPositionIndependent() const
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
std::string TargetFS
Definition: TargetMachine.h:86
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
bool usePPCPostRASchedStrategy() const
Definition: PPCSubtarget.h:274
FunctionPass * createPPCPreEmitPeepholePass()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1358
bool usePPCPreRASchedStrategy() const
Definition: PPCSubtarget.h:273
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
FunctionPass * createPPCExpandISELPass()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.