LLVM  9.0.0svn
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCSubtarget.h"
17 #include "PPCTargetObjectFile.h"
18 #include "PPCTargetTransformInfo.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Pass.h"
31 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include <cassert>
38 #include <memory>
39 #include <string>
40 
41 using namespace llvm;
42 
43 
44 static cl::opt<bool>
45  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
46  cl::desc("enable coalescing of duplicate branches for PPC"));
47 static cl::
48 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
49  cl::desc("Disable CTR loops for PPC"));
50 
51 static cl::
52 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
53  cl::desc("Disable PPC loop preinc prep"));
54 
55 static cl::opt<bool>
56 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
57  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
58 
59 static cl::
60 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
61  cl::desc("Disable VSX Swap Removal for PPC"));
62 
63 static cl::
64 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
65  cl::desc("Disable QPX load splat simplification"));
66 
67 static cl::
68 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
69  cl::desc("Disable machine peepholes for PPC"));
70 
71 static cl::opt<bool>
72 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
73  cl::desc("Enable optimizations on complex GEPs"),
74  cl::init(true));
75 
76 static cl::opt<bool>
77 EnablePrefetch("enable-ppc-prefetching",
78  cl::desc("disable software prefetching on PPC"),
79  cl::init(false), cl::Hidden);
80 
81 static cl::opt<bool>
82 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
83  cl::desc("Add extra TOC register dependencies"),
84  cl::init(true), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableMachineCombinerPass("ppc-machine-combiner",
88  cl::desc("Enable the machine combiner pass"),
89  cl::init(true), cl::Hidden);
90 
91 static cl::opt<bool>
92  ReduceCRLogical("ppc-reduce-cr-logicals",
93  cl::desc("Expand eligible cr-logical binary ops to branches"),
94  cl::init(false), cl::Hidden);
95 extern "C" void LLVMInitializePowerPCTarget() {
96  // Register the targets
100 
107 }
108 
109 /// Return the datalayout string of a subtarget.
110 static std::string getDataLayoutString(const Triple &T) {
111  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
112  std::string Ret;
113 
114  // Most PPC* platforms are big endian, PPC64LE is little endian.
115  if (T.getArch() == Triple::ppc64le)
116  Ret = "e";
117  else
118  Ret = "E";
119 
121 
122  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
123  // pointers.
124  if (!is64Bit || T.getOS() == Triple::Lv2)
125  Ret += "-p:32:32";
126 
127  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
128  // documentation are wrong; these are correct (i.e. "what gcc does").
129  if (is64Bit || !T.isOSDarwin())
130  Ret += "-i64:64";
131  else
132  Ret += "-f64:32:64";
133 
134  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
135  if (is64Bit)
136  Ret += "-n32:64";
137  else
138  Ret += "-n32";
139 
140  return Ret;
141 }
142 
144  const Triple &TT) {
145  std::string FullFS = FS;
146 
147  // Make sure 64-bit features are available when CPUname is generic
148  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
149  if (!FullFS.empty())
150  FullFS = "+64bit," + FullFS;
151  else
152  FullFS = "+64bit";
153  }
154 
155  if (OL >= CodeGenOpt::Default) {
156  if (!FullFS.empty())
157  FullFS = "+crbits," + FullFS;
158  else
159  FullFS = "+crbits";
160  }
161 
162  if (OL != CodeGenOpt::None) {
163  if (!FullFS.empty())
164  FullFS = "+invariant-function-descriptors," + FullFS;
165  else
166  FullFS = "+invariant-function-descriptors";
167  }
168 
169  return FullFS;
170 }
171 
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173  // If it isn't a Mach-O file then it's going to be a linux ELF
174  // object file.
175  if (TT.isOSDarwin())
176  return llvm::make_unique<TargetLoweringObjectFileMachO>();
177 
178  return llvm::make_unique<PPC64LinuxTargetObjectFile>();
179 }
180 
182  const TargetOptions &Options) {
183  if (TT.isOSDarwin())
184  report_fatal_error("Darwin is no longer supported for PowerPC");
185 
186  if (Options.MCOptions.getABIName().startswith("elfv1"))
188  else if (Options.MCOptions.getABIName().startswith("elfv2"))
190 
191  assert(Options.MCOptions.getABIName().empty() &&
192  "Unknown target-abi option!");
193 
194  if (TT.isMacOSX())
196 
197  switch (TT.getArch()) {
198  case Triple::ppc64le:
200  case Triple::ppc64:
202  default:
204  }
205 }
206 
209  if (RM.hasValue())
210  return *RM;
211 
212  // Darwin defaults to dynamic-no-pic.
213  if (TT.isOSDarwin())
214  return Reloc::DynamicNoPIC;
215 
216  // Big Endian PPC is PIC by default.
217  if (TT.getArch() == Triple::ppc64)
218  return Reloc::PIC_;
219 
220  // Rest are static by default.
221  return Reloc::Static;
222 }
223 
226  bool JIT) {
227  if (CM) {
228  if (*CM == CodeModel::Tiny)
229  report_fatal_error("Target does not support the tiny CodeModel");
230  if (*CM == CodeModel::Kernel)
231  report_fatal_error("Target does not support the kernel CodeModel");
232  return *CM;
233  }
234  if (!TT.isOSDarwin() && !JIT &&
235  (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
236  return CodeModel::Medium;
237  return CodeModel::Small;
238 }
239 
240 // The FeatureString here is a little subtle. We are modifying the feature
241 // string with what are (currently) non-function specific overrides as it goes
242 // into the LLVMTargetMachine constructor and then using the stored value in the
243 // Subtarget constructor below it.
245  StringRef CPU, StringRef FS,
246  const TargetOptions &Options,
249  CodeGenOpt::Level OL, bool JIT)
250  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
251  computeFSAdditions(FS, OL, TT), Options,
252  getEffectiveRelocModel(TT, RM),
253  getEffectivePPCCodeModel(TT, CM, JIT), OL),
254  TLOF(createTLOF(getTargetTriple())),
255  TargetABI(computeTargetABI(TT, Options)) {
256  initAsmInfo();
257 }
258 
260 
261 const PPCSubtarget *
263  Attribute CPUAttr = F.getFnAttribute("target-cpu");
264  Attribute FSAttr = F.getFnAttribute("target-features");
265 
266  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
267  ? CPUAttr.getValueAsString().str()
268  : TargetCPU;
269  std::string FS = !FSAttr.hasAttribute(Attribute::None)
270  ? FSAttr.getValueAsString().str()
271  : TargetFS;
272 
273  // FIXME: This is related to the code below to reset the target options,
274  // we need to know whether or not the soft float flag is set on the
275  // function before we can generate a subtarget. We also need to use
276  // it as a key for the subtarget since that can be the only difference
277  // between two functions.
278  bool SoftFloat =
279  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
280  // If the soft float attribute is set on the function turn on the soft float
281  // subtarget feature.
282  if (SoftFloat)
283  FS += FS.empty() ? "-hard-float" : ",-hard-float";
284 
285  auto &I = SubtargetMap[CPU + FS];
286  if (!I) {
287  // This needs to be done before we create a new subtarget since any
288  // creation will depend on the TM and the code generation flags on the
289  // function that reside in TargetOptions.
291  I = llvm::make_unique<PPCSubtarget>(
292  TargetTriple, CPU,
293  // FIXME: It would be good to have the subtarget additions here
294  // not necessary. Anything that turns them on/off (overrides) ends
295  // up being put at the end of the feature string, but the defaults
296  // shouldn't require adding them. Fixing this means pulling Feature64Bit
297  // out of most of the target cpus in the .td file and making it set only
298  // as part of initialization via the TargetTriple.
300  }
301  return I.get();
302 }
303 
304 //===----------------------------------------------------------------------===//
305 // Pass Pipeline Configuration
306 //===----------------------------------------------------------------------===//
307 
308 namespace {
309 
310 /// PPC Code Generator Pass Configuration Options.
311 class PPCPassConfig : public TargetPassConfig {
312 public:
313  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
314  : TargetPassConfig(TM, PM) {
315  // At any optimization level above -O0 we use the Machine Scheduler and not
316  // the default Post RA List Scheduler.
317  if (TM.getOptLevel() != CodeGenOpt::None)
318  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
319  }
320 
321  PPCTargetMachine &getPPCTargetMachine() const {
322  return getTM<PPCTargetMachine>();
323  }
324 
325  void addIRPasses() override;
326  bool addPreISel() override;
327  bool addILPOpts() override;
328  bool addInstSelector() override;
329  void addMachineSSAOptimization() override;
330  void addPreRegAlloc() override;
331  void addPreSched2() override;
332  void addPreEmitPass() override;
333 };
334 
335 } // end anonymous namespace
336 
338  return new PPCPassConfig(*this, PM);
339 }
340 
341 void PPCPassConfig::addIRPasses() {
342  if (TM->getOptLevel() != CodeGenOpt::None)
343  addPass(createPPCBoolRetToIntPass());
344  addPass(createAtomicExpandPass());
345 
346  // For the BG/Q (or if explicitly requested), add explicit data prefetch
347  // intrinsics.
348  bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
350  if (EnablePrefetch.getNumOccurrences() > 0)
351  UsePrefetching = EnablePrefetch;
352  if (UsePrefetching)
353  addPass(createLoopDataPrefetchPass());
354 
355  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
356  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
357  // and lower a GEP with multiple indices to either arithmetic operations or
358  // multiple GEPs with single index.
360  // Call EarlyCSE pass to find and remove subexpressions in the lowered
361  // result.
362  addPass(createEarlyCSEPass());
363  // Do loop invariant code motion in case part of the lowered result is
364  // invariant.
365  addPass(createLICMPass());
366  }
367 
369 }
370 
371 bool PPCPassConfig::addPreISel() {
373  addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
374 
376  addPass(createPPCCTRLoops());
377 
378  return false;
379 }
380 
381 bool PPCPassConfig::addILPOpts() {
382  addPass(&EarlyIfConverterID);
383 
385  addPass(&MachineCombinerID);
386 
387  return true;
388 }
389 
390 bool PPCPassConfig::addInstSelector() {
391  // Install an instruction selector.
392  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
393 
394 #ifndef NDEBUG
396  addPass(createPPCCTRLoopsVerify());
397 #endif
398 
399  addPass(createPPCVSXCopyPass());
400  return false;
401 }
402 
403 void PPCPassConfig::addMachineSSAOptimization() {
404  // PPCBranchCoalescingPass need to be done before machine sinking
405  // since it merges empty blocks.
409  // For little endian, remove where possible the vector swap instructions
410  // introduced at code generation to normalize vector element order.
411  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
413  addPass(createPPCVSXSwapRemovalPass());
414  // Reduce the number of cr-logical ops.
417  // Target-specific peephole cleanups performed after instruction
418  // selection.
419  if (!DisableMIPeephole) {
420  addPass(createPPCMIPeepholePass());
422  }
423 }
424 
425 void PPCPassConfig::addPreRegAlloc() {
426  if (getOptLevel() != CodeGenOpt::None) {
430  }
431 
432  // FIXME: We probably don't need to run these for -fPIE.
433  if (getPPCTargetMachine().isPositionIndependent()) {
434  // FIXME: LiveVariables should not be necessary here!
435  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
436  // LiveVariables. This (unnecessary) dependency has been removed now,
437  // however a stage-2 clang build fails without LiveVariables computed here.
438  addPass(&LiveVariablesID, false);
439  addPass(createPPCTLSDynamicCallPass());
440  }
442  addPass(createPPCTOCRegDepsPass());
443 }
444 
445 void PPCPassConfig::addPreSched2() {
446  if (getOptLevel() != CodeGenOpt::None) {
447  addPass(&IfConverterID);
448 
449  // This optimization must happen after anything that might do store-to-load
450  // forwarding. Here we're after RA (and, thus, when spills are inserted)
451  // but before post-RA scheduling.
452  if (!DisableQPXLoadSplat)
453  addPass(createPPCQPXLoadSplatPass());
454  }
455 }
456 
457 void PPCPassConfig::addPreEmitPass() {
458  addPass(createPPCPreEmitPeepholePass());
459  addPass(createPPCExpandISELPass());
460 
461  if (getOptLevel() != CodeGenOpt::None)
462  addPass(createPPCEarlyReturnPass(), false);
463  // Must run branch selection immediately preceding the asm printer.
464  addPass(createPPCBranchSelectionPass(), false);
465 }
466 
469  return TargetTransformInfo(PPCTTIImpl(this, F));
470 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
MCTargetOptions MCOptions
Machine level options.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:446
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:77
void initializePPCTLSDynamicCallPass(PassRegistry &)
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:298
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializePPCMIPeepholePass(PassRegistry &)
F(f)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
char & PPCVSXFMAMutateID
static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
FunctionPass * createLoopDataPrefetchPass()
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createPPCTOCRegDepsPass()
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
FunctionPass * createPPCCTRLoops()
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createPPCReduceCRLogicalsPass()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass ...
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
FunctionPass * createPPCBoolRetToIntPass()
Target & getThePPC64Target()
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const PPCSubtarget * getSubtargetImpl() const =delete
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
~PPCTargetMachine() override
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(false), cl::Hidden)
void initializePPCVSXFMAMutatePass(PassRegistry &)
Pass * createLICMPass()
Definition: LICM.cpp:294
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
Common code between 32-bit and 64-bit PowerPC targets.
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCExpandISELPass(PassRegistry &)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
std::string TargetCPU
Definition: TargetMachine.h:78
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
bool hasValue() const
Definition: Optional.h:166
void initializePPCPreEmitPeepholePass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
FunctionPass * createPPCQPXLoadSplatPass()
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
bool isPositionIndependent() const
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
std::string TargetFS
Definition: TargetMachine.h:79
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
FunctionPass * createPPCPreEmitPeepholePass()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1305
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
FunctionPass * createPPCExpandISELPass()