LLVM  7.0.0svn
PPCTargetMachine.cpp
Go to the documentation of this file.
1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
16 #include "PPC.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
25 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Support/CodeGen.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include <cassert>
38 #include <memory>
39 #include <string>
40 
41 using namespace llvm;
42 
43 
44 static cl::opt<bool>
45  EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
46  cl::desc("enable coalescing of duplicate branches for PPC"));
47 static cl::
48 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
49  cl::desc("Disable CTR loops for PPC"));
50 
51 static cl::
52 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
53  cl::desc("Disable PPC loop preinc prep"));
54 
55 static cl::opt<bool>
56 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
57  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
58 
59 static cl::
60 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
61  cl::desc("Disable VSX Swap Removal for PPC"));
62 
63 static cl::
64 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
65  cl::desc("Disable QPX load splat simplification"));
66 
67 static cl::
68 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
69  cl::desc("Disable machine peepholes for PPC"));
70 
71 static cl::opt<bool>
72 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
73  cl::desc("Enable optimizations on complex GEPs"),
74  cl::init(true));
75 
76 static cl::opt<bool>
77 EnablePrefetch("enable-ppc-prefetching",
78  cl::desc("disable software prefetching on PPC"),
79  cl::init(false), cl::Hidden);
80 
81 static cl::opt<bool>
82 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
83  cl::desc("Add extra TOC register dependencies"),
84  cl::init(true), cl::Hidden);
85 
86 static cl::opt<bool>
87 EnableMachineCombinerPass("ppc-machine-combiner",
88  cl::desc("Enable the machine combiner pass"),
89  cl::init(true), cl::Hidden);
90 
91 static cl::opt<bool>
92  ReduceCRLogical("ppc-reduce-cr-logicals",
93  cl::desc("Expand eligible cr-logical binary ops to branches"),
94  cl::init(false), cl::Hidden);
95 extern "C" void LLVMInitializePowerPCTarget() {
96  // Register the targets
100 
107 }
108 
109 /// Return the datalayout string of a subtarget.
110 static std::string getDataLayoutString(const Triple &T) {
111  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
112  std::string Ret;
113 
114  // Most PPC* platforms are big endian, PPC64LE is little endian.
115  if (T.getArch() == Triple::ppc64le)
116  Ret = "e";
117  else
118  Ret = "E";
119 
121 
122  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
123  // pointers.
124  if (!is64Bit || T.getOS() == Triple::Lv2)
125  Ret += "-p:32:32";
126 
127  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
128  // documentation are wrong; these are correct (i.e. "what gcc does").
129  if (is64Bit || !T.isOSDarwin())
130  Ret += "-i64:64";
131  else
132  Ret += "-f64:32:64";
133 
134  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
135  if (is64Bit)
136  Ret += "-n32:64";
137  else
138  Ret += "-n32";
139 
140  return Ret;
141 }
142 
144  const Triple &TT) {
145  std::string FullFS = FS;
146 
147  // Make sure 64-bit features are available when CPUname is generic
148  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
149  if (!FullFS.empty())
150  FullFS = "+64bit," + FullFS;
151  else
152  FullFS = "+64bit";
153  }
154 
155  if (OL >= CodeGenOpt::Default) {
156  if (!FullFS.empty())
157  FullFS = "+crbits," + FullFS;
158  else
159  FullFS = "+crbits";
160  }
161 
162  if (OL != CodeGenOpt::None) {
163  if (!FullFS.empty())
164  FullFS = "+invariant-function-descriptors," + FullFS;
165  else
166  FullFS = "+invariant-function-descriptors";
167  }
168 
169  return FullFS;
170 }
171 
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173  // If it isn't a Mach-O file then it's going to be a linux ELF
174  // object file.
175  if (TT.isOSDarwin())
176  return llvm::make_unique<TargetLoweringObjectFileMachO>();
177 
178  return llvm::make_unique<PPC64LinuxTargetObjectFile>();
179 }
180 
182  const TargetOptions &Options) {
183  if (Options.MCOptions.getABIName().startswith("elfv1"))
185  else if (Options.MCOptions.getABIName().startswith("elfv2"))
187 
188  assert(Options.MCOptions.getABIName().empty() &&
189  "Unknown target-abi option!");
190 
191  if (TT.isMacOSX())
193 
194  switch (TT.getArch()) {
195  case Triple::ppc64le:
197  case Triple::ppc64:
199  default:
201  }
202 }
203 
206  if (RM.hasValue())
207  return *RM;
208 
209  // Darwin defaults to dynamic-no-pic.
210  if (TT.isOSDarwin())
211  return Reloc::DynamicNoPIC;
212 
213  // Non-darwin 64-bit platforms are PIC by default.
214  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)
215  return Reloc::PIC_;
216 
217  // 32-bit is static by default.
218  return Reloc::Static;
219 }
220 
223  bool JIT) {
224  if (CM)
225  return *CM;
226  if (!TT.isOSDarwin() && !JIT &&
227  (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
228  return CodeModel::Medium;
229  return CodeModel::Small;
230 }
231 
232 // The FeatureString here is a little subtle. We are modifying the feature
233 // string with what are (currently) non-function specific overrides as it goes
234 // into the LLVMTargetMachine constructor and then using the stored value in the
235 // Subtarget constructor below it.
237  StringRef CPU, StringRef FS,
238  const TargetOptions &Options,
241  CodeGenOpt::Level OL, bool JIT)
242  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
243  computeFSAdditions(FS, OL, TT), Options,
244  getEffectiveRelocModel(TT, RM),
245  getEffectiveCodeModel(TT, CM, JIT), OL),
246  TLOF(createTLOF(getTargetTriple())),
247  TargetABI(computeTargetABI(TT, Options)) {
248  initAsmInfo();
249 }
250 
252 
253 const PPCSubtarget *
255  Attribute CPUAttr = F.getFnAttribute("target-cpu");
256  Attribute FSAttr = F.getFnAttribute("target-features");
257 
258  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
259  ? CPUAttr.getValueAsString().str()
260  : TargetCPU;
261  std::string FS = !FSAttr.hasAttribute(Attribute::None)
262  ? FSAttr.getValueAsString().str()
263  : TargetFS;
264 
265  // FIXME: This is related to the code below to reset the target options,
266  // we need to know whether or not the soft float flag is set on the
267  // function before we can generate a subtarget. We also need to use
268  // it as a key for the subtarget since that can be the only difference
269  // between two functions.
270  bool SoftFloat =
271  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
272  // If the soft float attribute is set on the function turn on the soft float
273  // subtarget feature.
274  if (SoftFloat)
275  FS += FS.empty() ? "-hard-float" : ",-hard-float";
276 
277  auto &I = SubtargetMap[CPU + FS];
278  if (!I) {
279  // This needs to be done before we create a new subtarget since any
280  // creation will depend on the TM and the code generation flags on the
281  // function that reside in TargetOptions.
283  I = llvm::make_unique<PPCSubtarget>(
284  TargetTriple, CPU,
285  // FIXME: It would be good to have the subtarget additions here
286  // not necessary. Anything that turns them on/off (overrides) ends
287  // up being put at the end of the feature string, but the defaults
288  // shouldn't require adding them. Fixing this means pulling Feature64Bit
289  // out of most of the target cpus in the .td file and making it set only
290  // as part of initialization via the TargetTriple.
292  }
293  return I.get();
294 }
295 
296 //===----------------------------------------------------------------------===//
297 // Pass Pipeline Configuration
298 //===----------------------------------------------------------------------===//
299 
300 namespace {
301 
302 /// PPC Code Generator Pass Configuration Options.
303 class PPCPassConfig : public TargetPassConfig {
304 public:
305  PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
306  : TargetPassConfig(TM, PM) {}
307 
308  PPCTargetMachine &getPPCTargetMachine() const {
309  return getTM<PPCTargetMachine>();
310  }
311 
312  void addIRPasses() override;
313  bool addPreISel() override;
314  bool addILPOpts() override;
315  bool addInstSelector() override;
316  void addMachineSSAOptimization() override;
317  void addPreRegAlloc() override;
318  void addPreSched2() override;
319  void addPreEmitPass() override;
320 };
321 
322 } // end anonymous namespace
323 
325  return new PPCPassConfig(*this, PM);
326 }
327 
328 void PPCPassConfig::addIRPasses() {
329  if (TM->getOptLevel() != CodeGenOpt::None)
330  addPass(createPPCBoolRetToIntPass());
331  addPass(createAtomicExpandPass());
332 
333  // For the BG/Q (or if explicitly requested), add explicit data prefetch
334  // intrinsics.
335  bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
337  if (EnablePrefetch.getNumOccurrences() > 0)
338  UsePrefetching = EnablePrefetch;
339  if (UsePrefetching)
340  addPass(createLoopDataPrefetchPass());
341 
342  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
343  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
344  // and lower a GEP with multiple indices to either arithmetic operations or
345  // multiple GEPs with single index.
347  // Call EarlyCSE pass to find and remove subexpressions in the lowered
348  // result.
349  addPass(createEarlyCSEPass());
350  // Do loop invariant code motion in case part of the lowered result is
351  // invariant.
352  addPass(createLICMPass());
353  }
354 
356 }
357 
358 bool PPCPassConfig::addPreISel() {
360  addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
361 
363  addPass(createPPCCTRLoops());
364 
365  return false;
366 }
367 
368 bool PPCPassConfig::addILPOpts() {
369  addPass(&EarlyIfConverterID);
370 
372  addPass(&MachineCombinerID);
373 
374  return true;
375 }
376 
377 bool PPCPassConfig::addInstSelector() {
378  // Install an instruction selector.
379  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
380 
381 #ifndef NDEBUG
383  addPass(createPPCCTRLoopsVerify());
384 #endif
385 
386  addPass(createPPCVSXCopyPass());
387  return false;
388 }
389 
390 void PPCPassConfig::addMachineSSAOptimization() {
391  // PPCBranchCoalescingPass need to be done before machine sinking
392  // since it merges empty blocks.
396  // For little endian, remove where possible the vector swap instructions
397  // introduced at code generation to normalize vector element order.
398  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
400  addPass(createPPCVSXSwapRemovalPass());
401  // Reduce the number of cr-logical ops.
404  // Target-specific peephole cleanups performed after instruction
405  // selection.
406  if (!DisableMIPeephole) {
407  addPass(createPPCMIPeepholePass());
409  }
410 }
411 
412 void PPCPassConfig::addPreRegAlloc() {
413  if (getOptLevel() != CodeGenOpt::None) {
417  }
418 
419  // FIXME: We probably don't need to run these for -fPIE.
420  if (getPPCTargetMachine().isPositionIndependent()) {
421  // FIXME: LiveVariables should not be necessary here!
422  // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
423  // LiveVariables. This (unnecessary) dependency has been removed now,
424  // however a stage-2 clang build fails without LiveVariables computed here.
425  addPass(&LiveVariablesID, false);
426  addPass(createPPCTLSDynamicCallPass());
427  }
429  addPass(createPPCTOCRegDepsPass());
430 }
431 
432 void PPCPassConfig::addPreSched2() {
433  if (getOptLevel() != CodeGenOpt::None) {
434  addPass(&IfConverterID);
435 
436  // This optimization must happen after anything that might do store-to-load
437  // forwarding. Here we're after RA (and, thus, when spills are inserted)
438  // but before post-RA scheduling.
439  if (!DisableQPXLoadSplat)
440  addPass(createPPCQPXLoadSplatPass());
441  }
442 }
443 
444 void PPCPassConfig::addPreEmitPass() {
445  addPass(createPPCPreEmitPeepholePass());
446  addPass(createPPCExpandISELPass());
447 
448  if (getOptLevel() != CodeGenOpt::None)
449  addPass(createPPCEarlyReturnPass(), false);
450  // Must run branch selection immediately preceding the asm printer.
451  addPass(createPPCBranchSelectionPass(), false);
452 }
453 
456  return TargetTransformInfo(PPCTTIImpl(this, F));
457 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
MCTargetOptions MCOptions
Machine level options.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:442
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
void initializePPCTLSDynamicCallPass(PassRegistry &)
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:294
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializePPCMIPeepholePass(PassRegistry &)
F(f)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
char & PPCVSXFMAMutateID
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:154
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
FunctionPass * createLoopDataPrefetchPass()
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createPPCTOCRegDepsPass()
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
FunctionPass * createPPCCTRLoops()
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
Target-Independent Code Generator Pass Configuration Options.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
FunctionPass * createPPCReduceCRLogicalsPass()
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
FunctionPass * createPPCBranchCoalescingPass()
createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
FunctionPass * createPPCBoolRetToIntPass()
Target & getThePPC64Target()
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const PPCSubtarget * getSubtargetImpl() const =delete
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
~PPCTargetMachine() override
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(false), cl::Hidden)
void initializePPCVSXFMAMutatePass(PassRegistry &)
Pass * createLICMPass()
Definition: LICM.cpp:237
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
Common code between 32-bit and 64-bit PowerPC targets.
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
void initializePPCExpandISELPass(PassRegistry &)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
std::string TargetCPU
Definition: TargetMachine.h:79
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
bool hasValue() const
Definition: Optional.h:185
void initializePPCPreEmitPeepholePass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
FunctionPass * createPPCQPXLoadSplatPass()
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
bool isPositionIndependent() const
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
#define I(x, y, z)
Definition: MD5.cpp:58
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
std::string TargetFS
Definition: TargetMachine.h:80
static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
FunctionPass * createPPCPreEmitPeepholePass()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1171
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()
FunctionPass * createPPCExpandISELPass()