LLVM  8.0.0svn
PPCTargetTransformInfo.cpp
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1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "PPCTargetTransformInfo.h"
13 #include "llvm/CodeGen/CostTable.h"
16 #include "llvm/Support/Debug.h"
17 using namespace llvm;
18 
19 #define DEBUG_TYPE "ppctti"
20 
21 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
22 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
23 
24 // This is currently only used for the data prefetch pass which is only enabled
25 // for BG/Q by default.
26 static cl::opt<unsigned>
27 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
28  cl::desc("The loop prefetch cache line size"));
29 
30 static cl::opt<bool>
31 EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false),
32  cl::desc("Enable using coldcc calling conv for cold "
33  "internal functions"));
34 
35 //===----------------------------------------------------------------------===//
36 //
37 // PPC cost model.
38 //
39 //===----------------------------------------------------------------------===//
40 
42 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
43  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
44  if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64)
45  return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ?
47  return TTI::PSK_Software;
48 }
49 
50 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
52  return BaseT::getIntImmCost(Imm, Ty);
53 
54  assert(Ty->isIntegerTy());
55 
56  unsigned BitSize = Ty->getPrimitiveSizeInBits();
57  if (BitSize == 0)
58  return ~0U;
59 
60  if (Imm == 0)
61  return TTI::TCC_Free;
62 
63  if (Imm.getBitWidth() <= 64) {
64  if (isInt<16>(Imm.getSExtValue()))
65  return TTI::TCC_Basic;
66 
67  if (isInt<32>(Imm.getSExtValue())) {
68  // A constant that can be materialized using lis.
69  if ((Imm.getZExtValue() & 0xFFFF) == 0)
70  return TTI::TCC_Basic;
71 
72  return 2 * TTI::TCC_Basic;
73  }
74  }
75 
76  return 4 * TTI::TCC_Basic;
77 }
78 
79 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
80  Type *Ty) {
82  return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
83 
84  assert(Ty->isIntegerTy());
85 
86  unsigned BitSize = Ty->getPrimitiveSizeInBits();
87  if (BitSize == 0)
88  return ~0U;
89 
90  switch (IID) {
91  default:
92  return TTI::TCC_Free;
93  case Intrinsic::sadd_with_overflow:
94  case Intrinsic::uadd_with_overflow:
95  case Intrinsic::ssub_with_overflow:
96  case Intrinsic::usub_with_overflow:
97  if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
98  return TTI::TCC_Free;
99  break;
100  case Intrinsic::experimental_stackmap:
101  if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
102  return TTI::TCC_Free;
103  break;
104  case Intrinsic::experimental_patchpoint_void:
105  case Intrinsic::experimental_patchpoint_i64:
106  if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
107  return TTI::TCC_Free;
108  break;
109  }
110  return PPCTTIImpl::getIntImmCost(Imm, Ty);
111 }
112 
113 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
114  Type *Ty) {
116  return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty);
117 
118  assert(Ty->isIntegerTy());
119 
120  unsigned BitSize = Ty->getPrimitiveSizeInBits();
121  if (BitSize == 0)
122  return ~0U;
123 
124  unsigned ImmIdx = ~0U;
125  bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
126  ZeroFree = false;
127  switch (Opcode) {
128  default:
129  return TTI::TCC_Free;
130  case Instruction::GetElementPtr:
131  // Always hoist the base address of a GetElementPtr. This prevents the
132  // creation of new constants for every base constant that gets constant
133  // folded with the offset.
134  if (Idx == 0)
135  return 2 * TTI::TCC_Basic;
136  return TTI::TCC_Free;
137  case Instruction::And:
138  RunFree = true; // (for the rotate-and-mask instructions)
140  case Instruction::Add:
141  case Instruction::Or:
142  case Instruction::Xor:
143  ShiftedFree = true;
145  case Instruction::Sub:
146  case Instruction::Mul:
147  case Instruction::Shl:
148  case Instruction::LShr:
149  case Instruction::AShr:
150  ImmIdx = 1;
151  break;
152  case Instruction::ICmp:
153  UnsignedFree = true;
154  ImmIdx = 1;
155  // Zero comparisons can use record-form instructions.
157  case Instruction::Select:
158  ZeroFree = true;
159  break;
160  case Instruction::PHI:
161  case Instruction::Call:
162  case Instruction::Ret:
163  case Instruction::Load:
164  case Instruction::Store:
165  break;
166  }
167 
168  if (ZeroFree && Imm == 0)
169  return TTI::TCC_Free;
170 
171  if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
172  if (isInt<16>(Imm.getSExtValue()))
173  return TTI::TCC_Free;
174 
175  if (RunFree) {
176  if (Imm.getBitWidth() <= 32 &&
177  (isShiftedMask_32(Imm.getZExtValue()) ||
179  return TTI::TCC_Free;
180 
181  if (ST->isPPC64() &&
182  (isShiftedMask_64(Imm.getZExtValue()) ||
184  return TTI::TCC_Free;
185  }
186 
187  if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
188  return TTI::TCC_Free;
189 
190  if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
191  return TTI::TCC_Free;
192  }
193 
194  return PPCTTIImpl::getIntImmCost(Imm, Ty);
195 }
196 
197 unsigned PPCTTIImpl::getUserCost(const User *U,
198  ArrayRef<const Value *> Operands) {
199  if (U->getType()->isVectorTy()) {
200  // Instructions that need to be split should cost more.
201  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, U->getType());
202  return LT.first * BaseT::getUserCost(U, Operands);
203  }
204 
205  return BaseT::getUserCost(U, Operands);
206 }
207 
210  if (ST->getDarwinDirective() == PPC::DIR_A2) {
211  // The A2 is in-order with a deep pipeline, and concatenation unrolling
212  // helps expose latency-hiding opportunities to the instruction scheduler.
213  UP.Partial = UP.Runtime = true;
214 
215  // We unroll a lot on the A2 (hundreds of instructions), and the benefits
216  // often outweigh the cost of a division to compute the trip count.
217  UP.AllowExpensiveTripCount = true;
218  }
219 
221 }
222 
223 // This function returns true to allow using coldcc calling convention.
224 // Returning true results in coldcc being used for functions which are cold at
225 // all call sites when the callers of the functions are not calling any other
226 // non coldcc functions.
228  return EnablePPCColdCC;
229 }
230 
231 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
232  // On the A2, always unroll aggressively. For QPX unaligned loads, we depend
233  // on combining the loads generated for consecutive accesses, and failure to
234  // do so is particularly expensive. This makes it much more likely (compared
235  // to only using concatenation unrolling).
236  if (ST->getDarwinDirective() == PPC::DIR_A2)
237  return true;
238 
239  return LoopHasReductions;
240 }
241 
243 PPCTTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const {
244  static const auto Options = []() {
246  Options.LoadSizes.push_back(8);
247  Options.LoadSizes.push_back(4);
248  Options.LoadSizes.push_back(2);
249  Options.LoadSizes.push_back(1);
250  return Options;
251  }();
252  return &Options;
253 }
254 
256  return true;
257 }
258 
259 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
260  if (Vector && !ST->hasAltivec() && !ST->hasQPX())
261  return 0;
262  return ST->hasVSX() ? 64 : 32;
263 }
264 
265 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const {
266  if (Vector) {
267  if (ST->hasQPX()) return 256;
268  if (ST->hasAltivec()) return 128;
269  return 0;
270  }
271 
272  if (ST->isPPC64())
273  return 64;
274  return 32;
275 
276 }
277 
279  // Check first if the user specified a custom line size.
280  if (CacheLineSize.getNumOccurrences() > 0)
281  return CacheLineSize;
282 
283  // On P7, P8 or P9 we have a cache line size of 128.
284  unsigned Directive = ST->getDarwinDirective();
285  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
286  Directive == PPC::DIR_PWR9)
287  return 128;
288 
289  // On other processors return a default of 64 bytes.
290  return 64;
291 }
292 
294  // This seems like a reasonable default for the BG/Q (this pass is enabled, by
295  // default, only on the BG/Q).
296  return 300;
297 }
298 
299 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
300  unsigned Directive = ST->getDarwinDirective();
301  // The 440 has no SIMD support, but floating-point instructions
302  // have a 5-cycle latency, so unroll by 5x for latency hiding.
303  if (Directive == PPC::DIR_440)
304  return 5;
305 
306  // The A2 has no SIMD support, but floating-point instructions
307  // have a 6-cycle latency, so unroll by 6x for latency hiding.
308  if (Directive == PPC::DIR_A2)
309  return 6;
310 
311  // FIXME: For lack of any better information, do no harm...
312  if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
313  return 1;
314 
315  // For P7 and P8, floating-point instructions have a 6-cycle latency and
316  // there are two execution units, so unroll by 12x for latency hiding.
317  // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
318  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
319  Directive == PPC::DIR_PWR9)
320  return 12;
321 
322  // For most things, modern systems have two execution units (and
323  // out-of-order execution).
324  return 2;
325 }
326 
328  unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
331  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
332 
333  // Fallback to the default implementation.
334  return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
335  Opd1PropInfo, Opd2PropInfo);
336 }
337 
339  Type *SubTp) {
340  // Legalize the type.
341  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
342 
343  // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
344  // (at least in the sense that there need only be one non-loop-invariant
345  // instruction). We need one such shuffle instruction for each actual
346  // register (this is not true for arbitrary shuffles, but is true for the
347  // structured types of shuffles covered by TTI::ShuffleKind).
348  return LT.first;
349 }
350 
351 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
352  const Instruction *I) {
353  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
354 
355  return BaseT::getCastInstrCost(Opcode, Dst, Src);
356 }
357 
358 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
359  const Instruction *I) {
360  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
361 }
362 
363 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
364  assert(Val->isVectorTy() && "This must be a vector type");
365 
366  int ISD = TLI->InstructionOpcodeToISD(Opcode);
367  assert(ISD && "Invalid opcode");
368 
369  if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
370  // Double-precision scalars are already located in index #0.
371  if (Index == 0)
372  return 0;
373 
374  return BaseT::getVectorInstrCost(Opcode, Val, Index);
375  } else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) {
376  // Floating point scalars are already located in index #0.
377  if (Index == 0)
378  return 0;
379 
380  return BaseT::getVectorInstrCost(Opcode, Val, Index);
381  }
382 
383  // Estimated cost of a load-hit-store delay. This was obtained
384  // experimentally as a minimum needed to prevent unprofitable
385  // vectorization for the paq8p benchmark. It may need to be
386  // raised further if other unprofitable cases remain.
387  unsigned LHSPenalty = 2;
388  if (ISD == ISD::INSERT_VECTOR_ELT)
389  LHSPenalty += 7;
390 
391  // Vector element insert/extract with Altivec is very expensive,
392  // because they require store and reload with the attendant
393  // processor stall for load-hit-store. Until VSX is available,
394  // these need to be estimated as very costly.
395  if (ISD == ISD::EXTRACT_VECTOR_ELT ||
396  ISD == ISD::INSERT_VECTOR_ELT)
397  return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index);
398 
399  return BaseT::getVectorInstrCost(Opcode, Val, Index);
400 }
401 
402 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
403  unsigned AddressSpace, const Instruction *I) {
404  // Legalize the type.
405  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
406  assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
407  "Invalid Opcode");
408 
409  int Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
410 
411  bool IsAltivecType = ST->hasAltivec() &&
412  (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
413  LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
414  bool IsVSXType = ST->hasVSX() &&
415  (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
416  bool IsQPXType = ST->hasQPX() &&
417  (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
418 
419  // VSX has 32b/64b load instructions. Legalization can handle loading of
420  // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
421  // PPCTargetLowering can't compute the cost appropriately. So here we
422  // explicitly check this case.
423  unsigned MemBytes = Src->getPrimitiveSizeInBits();
424  if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
425  (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
426  return 1;
427 
428  // Aligned loads and stores are easy.
429  unsigned SrcBytes = LT.second.getStoreSize();
430  if (!SrcBytes || !Alignment || Alignment >= SrcBytes)
431  return Cost;
432 
433  // If we can use the permutation-based load sequence, then this is also
434  // relatively cheap (not counting loop-invariant instructions): one load plus
435  // one permute (the last load in a series has extra cost, but we're
436  // neglecting that here). Note that on the P7, we could do unaligned loads
437  // for Altivec types using the VSX instructions, but that's more expensive
438  // than using the permutation-based load sequence. On the P8, that's no
439  // longer true.
440  if (Opcode == Instruction::Load &&
441  ((!ST->hasP8Vector() && IsAltivecType) || IsQPXType) &&
442  Alignment >= LT.second.getScalarType().getStoreSize())
443  return Cost + LT.first; // Add the cost of the permutations.
444 
445  // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the
446  // P7, unaligned vector loads are more expensive than the permutation-based
447  // load sequence, so that might be used instead, but regardless, the net cost
448  // is about the same (not counting loop-invariant instructions).
449  if (IsVSXType || (ST->hasVSX() && IsAltivecType))
450  return Cost;
451 
452  // Newer PPC supports unaligned memory access.
453  if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0))
454  return Cost;
455 
456  // PPC in general does not support unaligned loads and stores. They'll need
457  // to be decomposed based on the alignment factor.
458 
459  // Add the cost of each scalar load or store.
460  Cost += LT.first*(SrcBytes/Alignment-1);
461 
462  // For a vector type, there is also scalarization overhead (only for
463  // stores, loads are expanded using the vector-load + permutation sequence,
464  // which is much less expensive).
465  if (Src->isVectorTy() && Opcode == Instruction::Store)
466  for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
467  Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
468 
469  return Cost;
470 }
471 
472 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
473  unsigned Factor,
474  ArrayRef<unsigned> Indices,
475  unsigned Alignment,
476  unsigned AddressSpace,
477  bool IsMasked) {
478  if (IsMasked)
479  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
480  Alignment, AddressSpace, IsMasked);
481 
482  assert(isa<VectorType>(VecTy) &&
483  "Expect a vector type for interleaved memory op");
484 
485  // Legalize the type.
486  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy);
487 
488  // Firstly, the cost of load/store operation.
489  int Cost = getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace);
490 
491  // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
492  // (at least in the sense that there need only be one non-loop-invariant
493  // instruction). For each result vector, we need one shuffle per incoming
494  // vector (except that the first shuffle can take two incoming vectors
495  // because it does not need to take itself).
496  Cost += Factor*(LT.first-1);
497 
498  return Cost;
499 }
500 
void push_back(const T &Elt)
Definition: SmallVector.h:218
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:507
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool IsMasked=false)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1557
bool useColdCCForColdCall(Function &F)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Cost tables and simple lookup functions.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
The main scalar evolution driver.
bool hasVSX() const
Definition: PPCSubtarget.h:246
bool hasQPX() const
Definition: PPCSubtarget.h:245
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
F(f)
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1503
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
unsigned getUserCost(const User *U, ArrayRef< const Value *> Operands)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align=1, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation...
int getIntImmCost(const APInt &Imm, Type *Ty)
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:162
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
unsigned getMaxInterleaveFactor(unsigned VF)
static cl::opt< bool > DisablePPCConstHoist("disable-ppc-constant-hoisting", cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden)
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I)
Definition: BasicTTIImpl.h:705
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1569
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:567
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
PopcntSupportKind
Flags indicating the kind of support for population count.
static cl::opt< unsigned > CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), cl::desc("The loop prefetch cache line size"))
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return &#39;this&#39;.
Definition: Type.h:304
const TTI::MemCmpExpansionOptions * enableMemCmpExpansion(bool IsZeroCmp) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: BasicTTIImpl.h:363
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
unsigned getRegisterBitWidth(bool Vector) const
If not nullptr, enable inline expansion of memcmp.
static cl::opt< bool > EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), cl::desc("Enable using coldcc calling conv for cold " "internal functions"))
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:316
Expected to fold away in lowering.
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
unsigned getUserCost(const User *U, ArrayRef< const Value * > Operands)
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool IsMasked=false)
Definition: BasicTTIImpl.h:783
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:171
unsigned getNumberOfRegisters(bool Vector)
bool hasP8Vector() const
Definition: PPCSubtarget.h:247
OperandValueProperties
Additional properties of an operand&#39;s values.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:323
AddressSpace
Definition: NVPTXBaseInfo.h:22
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
bool enableAggressiveInterleaving(bool LoopHasReductions)
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:462
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Class for arbitrary precision integers.
Definition: APInt.h:70
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:752
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I=nullptr)
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:423
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:459
Parameters that control the generic loop unrolling transformation.
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasAltivec() const
Definition: PPCSubtarget.h:242
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:745
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical &#39;add&#39; instruction.
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:296
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I=nullptr)
constexpr bool isShiftedMask_32(uint32_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...
Definition: MathExtras.h:417
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
This file describes how to lower LLVM code to machine code.
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace, const Instruction *I=nullptr)
ShuffleKind
The various kinds of shuffle patterns for vector queries.