LLVM  7.0.0svn
R600ExpandSpecialInstrs.cpp
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1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "AMDGPU.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600RegisterInfo.h"
29 #include "llvm/Pass.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <iterator>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "r600-expand-special-instrs"
37 
38 namespace {
39 
40 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
41 private:
42  const R600InstrInfo *TII = nullptr;
43 
44  void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
45  unsigned Op);
46 
47 public:
48  static char ID;
49 
50  R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
51 
52  bool runOnMachineFunction(MachineFunction &MF) override;
53 
54  StringRef getPassName() const override {
55  return "R600 Expand special instructions pass";
56  }
57 };
58 
59 } // end anonymous namespace
60 
61 INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
62  "R600 Expand Special Instrs", false, false)
63 INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
65 
66 char R600ExpandSpecialInstrsPass::ID = 0;
67 
68 char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
69 
71  return new R600ExpandSpecialInstrsPass();
72 }
73 
74 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
75  const MachineInstr *OldMI, unsigned Op) {
76  int OpIdx = TII->getOperandIdx(*OldMI, Op);
77  if (OpIdx > -1) {
78  uint64_t Val = OldMI->getOperand(OpIdx).getImm();
79  TII->setImmOperand(*NewMI, Op, Val);
80  }
81 }
82 
83 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
85  TII = ST.getInstrInfo();
86 
87  const R600RegisterInfo &TRI = TII->getRegisterInfo();
88 
89  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
90  BB != BB_E; ++BB) {
91  MachineBasicBlock &MBB = *BB;
93  while (I != MBB.end()) {
94  MachineInstr &MI = *I;
95  I = std::next(I);
96 
97  // Expand LDS_*_RET instructions
98  if (TII->isLDSRetInstr(MI.getOpcode())) {
99  int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
100  assert(DstIdx != -1);
101  MachineOperand &DstOp = MI.getOperand(DstIdx);
102  MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
103  DstOp.getReg(), AMDGPU::OQAP);
104  DstOp.setReg(AMDGPU::OQAP);
105  int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
106  AMDGPU::OpName::pred_sel);
107  int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
108  AMDGPU::OpName::pred_sel);
109  // Copy the pred_sel bit
110  Mov->getOperand(MovPredSelIdx).setReg(
111  MI.getOperand(LDSPredSelIdx).getReg());
112  }
113 
114  switch (MI.getOpcode()) {
115  default: break;
116  // Expand PRED_X to one of the PRED_SET instructions.
117  case AMDGPU::PRED_X: {
118  uint64_t Flags = MI.getOperand(3).getImm();
119  // The native opcode used by PRED_X is stored as an immediate in the
120  // third operand.
121  MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
122  MI.getOperand(2).getImm(), // opcode
123  MI.getOperand(0).getReg(), // dst
124  MI.getOperand(1).getReg(), // src0
125  AMDGPU::ZERO); // src1
126  TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
127  if (Flags & MO_FLAG_PUSH) {
128  TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
129  } else {
130  TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
131  }
132  MI.eraseFromParent();
133  continue;
134  }
135  case AMDGPU::DOT_4: {
136  const R600RegisterInfo &TRI = TII->getRegisterInfo();
137 
138  unsigned DstReg = MI.getOperand(0).getReg();
139  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
140 
141  for (unsigned Chan = 0; Chan < 4; ++Chan) {
142  bool Mask = (Chan != TRI.getHWRegChan(DstReg));
143  unsigned SubDstReg =
144  AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
145  MachineInstr *BMI =
146  TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
147  if (Chan > 0) {
148  BMI->bundleWithPred();
149  }
150  if (Mask) {
151  TII->addFlag(*BMI, 0, MO_FLAG_MASK);
152  }
153  if (Chan != 3)
154  TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
155  unsigned Opcode = BMI->getOpcode();
156  // While not strictly necessary from hw point of view, we force
157  // all src operands of a dot4 inst to belong to the same slot.
158  unsigned Src0 = BMI->getOperand(
159  TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
160  .getReg();
161  unsigned Src1 = BMI->getOperand(
162  TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
163  .getReg();
164  (void) Src0;
165  (void) Src1;
166  if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
167  (TRI.getEncodingValue(Src1) & 0xff) < 127)
168  assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
169  }
170  MI.eraseFromParent();
171  continue;
172  }
173  }
174 
175  bool IsReduction = TII->isReductionOp(MI.getOpcode());
176  bool IsVector = TII->isVector(MI);
177  bool IsCube = TII->isCubeOp(MI.getOpcode());
178  if (!IsReduction && !IsVector && !IsCube) {
179  continue;
180  }
181 
182  // Expand the instruction
183  //
184  // Reduction instructions:
185  // T0_X = DP4 T1_XYZW, T2_XYZW
186  // becomes:
187  // TO_X = DP4 T1_X, T2_X
188  // TO_Y (write masked) = DP4 T1_Y, T2_Y
189  // TO_Z (write masked) = DP4 T1_Z, T2_Z
190  // TO_W (write masked) = DP4 T1_W, T2_W
191  //
192  // Vector instructions:
193  // T0_X = MULLO_INT T1_X, T2_X
194  // becomes:
195  // T0_X = MULLO_INT T1_X, T2_X
196  // T0_Y (write masked) = MULLO_INT T1_X, T2_X
197  // T0_Z (write masked) = MULLO_INT T1_X, T2_X
198  // T0_W (write masked) = MULLO_INT T1_X, T2_X
199  //
200  // Cube instructions:
201  // T0_XYZW = CUBE T1_XYZW
202  // becomes:
203  // TO_X = CUBE T1_Z, T1_Y
204  // T0_Y = CUBE T1_Z, T1_X
205  // T0_Z = CUBE T1_X, T1_Z
206  // T0_W = CUBE T1_Y, T1_Z
207  for (unsigned Chan = 0; Chan < 4; Chan++) {
208  unsigned DstReg = MI.getOperand(
209  TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
210  unsigned Src0 = MI.getOperand(
211  TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
212  unsigned Src1 = 0;
213 
214  // Determine the correct source registers
215  if (!IsCube) {
216  int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
217  if (Src1Idx != -1) {
218  Src1 = MI.getOperand(Src1Idx).getReg();
219  }
220  }
221  if (IsReduction) {
222  unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan);
223  Src0 = TRI.getSubReg(Src0, SubRegIndex);
224  Src1 = TRI.getSubReg(Src1, SubRegIndex);
225  } else if (IsCube) {
226  static const int CubeSrcSwz[] = {2, 2, 0, 1};
227  unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]);
228  unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
229  Src1 = TRI.getSubReg(Src0, SubRegIndex1);
230  Src0 = TRI.getSubReg(Src0, SubRegIndex0);
231  }
232 
233  // Determine the correct destination registers;
234  bool Mask = false;
235  bool NotLast = true;
236  if (IsCube) {
237  unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan);
238  DstReg = TRI.getSubReg(DstReg, SubRegIndex);
239  } else {
240  // Mask the write if the original instruction does not write to
241  // the current Channel.
242  Mask = (Chan != TRI.getHWRegChan(DstReg));
243  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
244  DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
245  }
246 
247  // Set the IsLast bit
248  NotLast = (Chan != 3 );
249 
250  // Add the new instruction
251  unsigned Opcode = MI.getOpcode();
252  switch (Opcode) {
253  case AMDGPU::CUBE_r600_pseudo:
254  Opcode = AMDGPU::CUBE_r600_real;
255  break;
256  case AMDGPU::CUBE_eg_pseudo:
257  Opcode = AMDGPU::CUBE_eg_real;
258  break;
259  default:
260  break;
261  }
262 
263  MachineInstr *NewMI =
264  TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
265 
266  if (Chan != 0)
267  NewMI->bundleWithPred();
268  if (Mask) {
269  TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
270  }
271  if (NotLast) {
272  TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
273  }
274  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
275  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
276  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs);
277  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs);
278  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg);
279  SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
280  }
281  MI.eraseFromParent();
282  }
283  }
284  return false;
285 }
void bundleWithPred()
Bundle this instruction with its predecessor.
static unsigned getSubRegFromChannel(unsigned Channel)
AMDGPU specific subclass of TargetSubtarget.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Interface definition for R600InstrInfo.
unsigned getReg() const
getReg - Returns the register number.
unsigned const TargetRegisterInfo * TRI
Interface definition for R600RegisterInfo.
INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE, "R600 Expand Special Instrs", false, false) INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
FunctionPass * createR600ExpandSpecialInstrsPass()
char & R600ExpandSpecialInstrsPassID
#define HW_REG_MASK
Defines for extracting register information from register encoding.
Definition: R600Defines.h:56
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const R600InstrInfo * getInstrInfo() const override
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
const R600RegisterInfo * getRegisterInfo() const override
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
#define DEBUG_TYPE
int64_t getImm() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register&#39;s channel.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:60
#define MO_FLAG_NOT_LAST
Definition: R600Defines.h:22
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
#define MO_FLAG_MASK
Definition: R600Defines.h:20
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
#define MO_FLAG_PUSH
Definition: R600Defines.h:21