LLVM  6.0.0svn
Macros | Functions | Variables
R600OptimizeVectorRegisters.cpp File Reference

This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities. More...

#include "AMDGPU.h"
#include "AMDGPUSubtarget.h"
#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <utility>
#include <vector>
Include dependency graph for R600OptimizeVectorRegisters.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "vec-merger"
 

Functions

static bool isImplicitlyDef (MachineRegisterInfo &MRI, unsigned Reg)
 
 INITIALIZE_PASS_BEGIN (R600VectorRegMerger, DEBUG_TYPE, "R600 Vector Reg Merger", false, false) INITIALIZE_PASS_END(R600VectorRegMerger
 
static unsigned getReassignedChan (const std::vector< std::pair< unsigned, unsigned >> &RemapChan, unsigned Chan)
 

Variables

 DEBUG_TYPE
 
R600 Vector Reg Merger
 
R600 Vector Reg false
 

Detailed Description

This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities.

For instance let's consider the following pseudo code : vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 ... vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3 (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3

is turned into : vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 ... vreg7<def> = INSERT_SUBREG vreg4, sub3 (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3

This allow regalloc to reduce register pressure for vector registers and to reduce MOV count.

Definition in file R600OptimizeVectorRegisters.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "vec-merger"

Definition at line 57 of file R600OptimizeVectorRegisters.cpp.

Referenced by isImplicitlyDef().

Function Documentation

◆ getReassignedChan()

static unsigned getReassignedChan ( const std::vector< std::pair< unsigned, unsigned >> &  RemapChan,
unsigned  Chan 
)
static

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( R600VectorRegMerger  ,
DEBUG_TYPE  ,
"R600 Vector Reg Merger ,
false  ,
false   
)

Referenced by isImplicitlyDef().

◆ isImplicitlyDef()

static bool isImplicitlyDef ( MachineRegisterInfo MRI,
unsigned  Reg 
)
static

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 149 of file R600OptimizeVectorRegisters.cpp.

◆ false

R600 Vector Reg false

Definition at line 149 of file R600OptimizeVectorRegisters.cpp.

◆ Merger

R600 Vector Reg Merger