LLVM  8.0.0svn
R600RegisterInfo.cpp
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1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// R600 implementation of the TargetRegisterInfo class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600InstrInfo.h"
21 
22 using namespace llvm;
23 
25  RCW.RegWeight = 0;
26  RCW.WeightLimit = 0;
27 }
28 
29 #define GET_REGINFO_TARGET_DESC
30 #include "R600GenRegisterInfo.inc"
31 
33  BitVector Reserved(getNumRegs());
34 
36  const R600InstrInfo *TII = ST.getInstrInfo();
37 
38  reserveRegisterTuples(Reserved, R600::ZERO);
39  reserveRegisterTuples(Reserved, R600::HALF);
40  reserveRegisterTuples(Reserved, R600::ONE);
41  reserveRegisterTuples(Reserved, R600::ONE_INT);
42  reserveRegisterTuples(Reserved, R600::NEG_HALF);
43  reserveRegisterTuples(Reserved, R600::NEG_ONE);
44  reserveRegisterTuples(Reserved, R600::PV_X);
45  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
46  reserveRegisterTuples(Reserved, R600::ALU_CONST);
47  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
48  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
49  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
50  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
51  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
52 
53  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
54  E = R600::R600_AddrRegClass.end(); I != E; ++I) {
55  reserveRegisterTuples(Reserved, *I);
56  }
57 
58  TII->reserveIndirectRegisters(Reserved, MF, *this);
59 
60  return Reserved;
61 }
62 
63 // Dummy to not crash RegisterClassInfo.
64 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
65 
67  const MachineFunction *) const {
68  return &CalleeSavedReg;
69 }
70 
72  return R600::NoRegister;
73 }
74 
75 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
76  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
77 }
78 
79 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
80  return GET_REG_INDEX(getEncodingValue(Reg));
81 }
82 
84  MVT VT) const {
85  switch(VT.SimpleTy) {
86  default:
87  case MVT::i32: return &R600::R600_TReg32RegClass;
88  }
89 }
90 
92  const TargetRegisterClass *RC) const {
93  return RCW;
94 }
95 
98 
99  switch (Reg) {
100  case R600::OQAP:
101  case R600::OQBP:
102  case R600::AR_X:
103  return false;
104  default:
105  return true;
106  }
107 }
108 
110  int SPAdj,
111  unsigned FIOperandNum,
112  RegScavenger *RS) const {
113  llvm_unreachable("Subroutines not supported yet");
114 }
115 
116 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
117  MCRegAliasIterator R(Reg, this, true);
118 
119  for (; R.isValid(); ++R)
120  Reserved.set(*R);
121 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
BitVector & set()
Definition: BitVector.h:398
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Interface definition for R600InstrInfo.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
Interface definition for R600RegisterInfo.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const HexagonInstrInfo * TII
#define HW_CHAN_SHIFT
Definition: R600Defines.h:57
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
SimpleValueType SimpleTy
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getHWRegIndex(unsigned Reg) const
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCRegAliasIterator enumerates all registers aliasing Reg.
const R600InstrInfo * getInstrInfo() const override
static const MCPhysReg CalleeSavedReg
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
The AMDGPU TargetMachine interface definition for hw codgen targets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register&#39;s channel.
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
Provides AMDGPU specific target descriptions.
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define GET_REG_INDEX(reg)
Definition: R600Defines.h:60
IRTranslator LLVM IR MI