LLVM  6.0.0svn
R600RegisterInfo.cpp
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1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 implementation of the TargetRegisterInfo class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "R600RegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "R600Defines.h"
18 #include "R600InstrInfo.h"
20 
21 using namespace llvm;
22 
24  RCW.RegWeight = 0;
25  RCW.WeightLimit = 0;
26 }
27 
29  BitVector Reserved(getNumRegs());
30 
32  const R600InstrInfo *TII = ST.getInstrInfo();
33 
34  Reserved.set(AMDGPU::ZERO);
35  Reserved.set(AMDGPU::HALF);
36  Reserved.set(AMDGPU::ONE);
37  Reserved.set(AMDGPU::ONE_INT);
38  Reserved.set(AMDGPU::NEG_HALF);
39  Reserved.set(AMDGPU::NEG_ONE);
40  Reserved.set(AMDGPU::PV_X);
41  Reserved.set(AMDGPU::ALU_LITERAL_X);
42  Reserved.set(AMDGPU::ALU_CONST);
43  Reserved.set(AMDGPU::PREDICATE_BIT);
44  Reserved.set(AMDGPU::PRED_SEL_OFF);
45  Reserved.set(AMDGPU::PRED_SEL_ZERO);
46  Reserved.set(AMDGPU::PRED_SEL_ONE);
47  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
48 
49  for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
50  E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
51  Reserved.set(*I);
52  }
53 
54  TII->reserveIndirectRegisters(Reserved, MF);
55 
56  return Reserved;
57 }
58 
59 // Dummy to not crash RegisterClassInfo.
60 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
61 
63  const MachineFunction *) const {
64  return &CalleeSavedReg;
65 }
66 
68  return AMDGPU::NoRegister;
69 }
70 
71 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
72  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
73 }
74 
75 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
76  return GET_REG_INDEX(getEncodingValue(Reg));
77 }
78 
80  MVT VT) const {
81  switch(VT.SimpleTy) {
82  default:
83  case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
84  }
85 }
86 
88  const TargetRegisterClass *RC) const {
89  return RCW;
90 }
91 
94 
95  switch (Reg) {
96  case AMDGPU::OQAP:
97  case AMDGPU::OQBP:
98  case AMDGPU::AR_X:
99  return false;
100  default:
101  return true;
102  }
103 }
104 
106  int SPAdj,
107  unsigned FIOperandNum,
108  RegScavenger *RS) const {
109  llvm_unreachable("Subroutines not supported yet");
110 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
BitVector & set()
Definition: BitVector.h:398
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:235
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Interface definition for R600InstrInfo.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Interface definition for R600RegisterInfo.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const HexagonInstrInfo * TII
#define HW_CHAN_SHIFT
Definition: R600Defines.h:57
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getHWRegIndex(unsigned Reg) const
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const R600InstrInfo * getInstrInfo() const override
static const MCPhysReg CalleeSavedReg
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
The AMDGPU TargetMachine interface definition for hw codgen targets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register&#39;s channel.
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define GET_REG_INDEX(reg)
Definition: R600Defines.h:60
IRTranslator LLVM IR MI