LLVM  8.0.0svn
R600RegisterInfo.h
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1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Interface definition for R600RegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
17 
18 #define GET_REGINFO_HEADER
19 #include "R600GenRegisterInfo.inc"
20 
21 namespace llvm {
22 
23 struct R600RegisterInfo final : public R600GenRegisterInfo {
25 
27 
28  BitVector getReservedRegs(const MachineFunction &MF) const override;
29  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
30  unsigned getFrameRegister(const MachineFunction &MF) const override;
31 
32  /// get the HW encoding for a register's channel.
33  unsigned getHWRegChan(unsigned reg) const;
34 
35  unsigned getHWRegIndex(unsigned Reg) const;
36 
37  /// get the register class of the specified type to use in the
38  /// CFGStructurizer
40 
41  const RegClassWeight &
42  getRegClassWeight(const TargetRegisterClass *RC) const override;
43 
44  // \returns true if \p Reg can be defined in one ALU clause and used in
45  // another.
46  bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
47 
49  unsigned FIOperandNum,
50  RegScavenger *RS = nullptr) const override;
51 
52  void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
53 };
54 
55 } // End namespace llvm
56 
57 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned Reg
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getHWRegIndex(unsigned Reg) const
Machine Value Type.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
IRTranslator LLVM IR MI