LLVM  9.0.0svn
R600RegisterInfo.h
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1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for R600RegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "R600GenRegisterInfo.inc"
19 
20 namespace llvm {
21 
22 struct R600RegisterInfo final : public R600GenRegisterInfo {
24 
26 
27  BitVector getReservedRegs(const MachineFunction &MF) const override;
28  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
29  unsigned getFrameRegister(const MachineFunction &MF) const override;
30 
31  /// get the HW encoding for a register's channel.
32  unsigned getHWRegChan(unsigned reg) const;
33 
34  unsigned getHWRegIndex(unsigned Reg) const;
35 
36  /// get the register class of the specified type to use in the
37  /// CFGStructurizer
39 
40  const RegClassWeight &
41  getRegClassWeight(const TargetRegisterClass *RC) const override;
42 
43  // \returns true if \p Reg can be defined in one ALU clause and used in
44  // another.
45  bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
46 
48  unsigned FIOperandNum,
49  RegScavenger *RS = nullptr) const override;
50 
51  void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
52 };
53 
54 } // End namespace llvm
55 
56 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getHWRegIndex(unsigned Reg) const
Machine Value Type.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
IRTranslator LLVM IR MI