LLVM  9.0.0svn
RDFRegisters.h
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1 //===- RDFRegisters.h -------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
10 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
11 
12 #include "llvm/ADT/BitVector.h"
13 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/MC/LaneBitmask.h"
16 #include <cassert>
17 #include <cstdint>
18 #include <map>
19 #include <set>
20 #include <vector>
21 
22 namespace llvm {
23 
24 class MachineFunction;
25 class raw_ostream;
26 
27 namespace rdf {
28 
30 
31  // Template class for a map translating uint32_t into arbitrary types.
32  // The map will act like an indexed set: upon insertion of a new object,
33  // it will automatically assign a new index to it. Index of 0 is treated
34  // as invalid and is never allocated.
35  template <typename T, unsigned N = 32>
36  struct IndexedSet {
37  IndexedSet() { Map.reserve(N); }
38 
39  T get(uint32_t Idx) const {
40  // Index Idx corresponds to Map[Idx-1].
41  assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
42  return Map[Idx-1];
43  }
44 
45  uint32_t insert(T Val) {
46  // Linear search.
47  auto F = llvm::find(Map, Val);
48  if (F != Map.end())
49  return F - Map.begin() + 1;
50  Map.push_back(Val);
51  return Map.size(); // Return actual_index + 1.
52  }
53 
54  uint32_t find(T Val) const {
55  auto F = llvm::find(Map, Val);
56  assert(F != Map.end());
57  return F - Map.begin() + 1;
58  }
59 
60  uint32_t size() const { return Map.size(); }
61 
62  using const_iterator = typename std::vector<T>::const_iterator;
63 
64  const_iterator begin() const { return Map.begin(); }
65  const_iterator end() const { return Map.end(); }
66 
67  private:
68  std::vector<T> Map;
69  };
70 
71  struct RegisterRef {
74 
75  RegisterRef() = default;
77  : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
78 
79  operator bool() const {
80  return Reg != 0 && Mask.any();
81  }
82 
83  bool operator== (const RegisterRef &RR) const {
84  return Reg == RR.Reg && Mask == RR.Mask;
85  }
86 
87  bool operator!= (const RegisterRef &RR) const {
88  return !operator==(RR);
89  }
90 
91  bool operator< (const RegisterRef &RR) const {
92  return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
93  }
94  };
95 
96 
99  const MachineFunction &mf);
100 
101  static bool isRegMaskId(RegisterId R) {
103  }
104 
106  return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
107  }
108 
110  return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
111  }
112 
113  RegisterRef normalize(RegisterRef RR) const;
114 
115  bool alias(RegisterRef RA, RegisterRef RB) const {
116  if (!isRegMaskId(RA.Reg))
117  return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
118  return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
119  }
120 
121  std::set<RegisterId> getAliasSet(RegisterId Reg) const;
122 
124  return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
125  }
126 
127  const BitVector &getMaskUnits(RegisterId MaskId) const {
128  return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
129  }
130 
131  RegisterRef mapTo(RegisterRef RR, unsigned R) const;
132  const TargetRegisterInfo &getTRI() const { return TRI; }
133 
134  private:
135  struct RegInfo {
136  const TargetRegisterClass *RegClass = nullptr;
137  };
138  struct UnitInfo {
139  RegisterId Reg = 0;
141  };
142  struct MaskInfo {
143  BitVector Units;
144  };
145 
146  const TargetRegisterInfo &TRI;
148  std::vector<RegInfo> RegInfos;
149  std::vector<UnitInfo> UnitInfos;
150  std::vector<MaskInfo> MaskInfos;
151 
152  bool aliasRR(RegisterRef RA, RegisterRef RB) const;
153  bool aliasRM(RegisterRef RR, RegisterRef RM) const;
154  bool aliasMM(RegisterRef RM, RegisterRef RN) const;
155  };
156 
157  struct RegisterAggr {
159  : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
160  RegisterAggr(const RegisterAggr &RG) = default;
161 
162  bool empty() const { return Units.none(); }
163  bool hasAliasOf(RegisterRef RR) const;
164  bool hasCoverOf(RegisterRef RR) const;
165 
167  const PhysicalRegisterInfo &PRI) {
168  return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
169  }
170 
172  RegisterAggr &insert(const RegisterAggr &RG);
174  RegisterAggr &intersect(const RegisterAggr &RG);
176  RegisterAggr &clear(const RegisterAggr &RG);
177 
178  RegisterRef intersectWith(RegisterRef RR) const;
179  RegisterRef clearIn(RegisterRef RR) const;
180  RegisterRef makeRegRef() const;
181 
182  void print(raw_ostream &OS) const;
183 
184  struct rr_iterator {
185  using MapType = std::map<RegisterId, LaneBitmask>;
186 
187  private:
188  MapType Masks;
189  MapType::iterator Pos;
190  unsigned Index;
191  const RegisterAggr *Owner;
192 
193  public:
194  rr_iterator(const RegisterAggr &RG, bool End);
195 
197  return RegisterRef(Pos->first, Pos->second);
198  }
199 
201  ++Pos;
202  ++Index;
203  return *this;
204  }
205 
206  bool operator==(const rr_iterator &I) const {
207  assert(Owner == I.Owner);
208  (void)Owner;
209  return Index == I.Index;
210  }
211 
212  bool operator!=(const rr_iterator &I) const {
213  return !(*this == I);
214  }
215  };
216 
218  return rr_iterator(*this, false);
219  }
220  rr_iterator rr_end() const {
221  return rr_iterator(*this, true);
222  }
223 
224  private:
225  BitVector Units;
226  const PhysicalRegisterInfo &PRI;
227  };
228 
229  // Optionally print the lane mask, if it is not ~0.
233  };
235 
236 } // end namespace rdf
237 
238 } // end namespace llvm
239 
240 #endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
bool hasCoverOf(RegisterRef RR) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
Definition: RDFGraph.cpp:51
A common definition of LaneBitmask for use in TableGen and CodeGen.
PrintLaneMaskOpt(LaneBitmask M)
Definition: RDFRegisters.h:231
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
bool operator!=(const rr_iterator &I) const
Definition: RDFRegisters.h:212
unsigned const TargetRegisterInfo * TRI
F(f)
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
Definition: RDFRegisters.h:76
rr_iterator rr_begin() const
Definition: RDFRegisters.h:217
SI optimize exec mask operations pre RA
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
const BitVector & getMaskUnits(RegisterId MaskId) const
Definition: RDFRegisters.h:127
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
uint32_t find(T Val) const
Definition: RDFRegisters.h:54
uint32_t size() const
Definition: RDFRegisters.h:60
const_iterator end() const
Definition: RDFRegisters.h:65
uint32_t insert(T Val)
Definition: RDFRegisters.h:45
std::map< RegisterId, LaneBitmask > MapType
Definition: RDFRegisters.h:185
#define P(N)
const TargetRegisterInfo & getTRI() const
Definition: RDFRegisters.h:132
rr_iterator rr_end() const
Definition: RDFRegisters.h:220
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
RegisterRef getRefForUnit(uint32_t U) const
Definition: RDFRegisters.h:123
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
RegisterAggr & insert(RegisterRef RR)
RegisterAggr(const PhysicalRegisterInfo &pri)
Definition: RDFRegisters.h:158
bool operator==(const rr_iterator &I) const
Definition: RDFRegisters.h:206
static void clear(coro::Shape &Shape)
Definition: Coroutines.cpp:211
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1968
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
RegisterId getRegMaskId(const uint32_t *RM) const
Definition: RDFRegisters.h:105
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
constexpr bool any() const
Definition: LaneBitmask.h:52
typename std::vector< const uint32_t * >::const_iterator const_iterator
Definition: RDFRegisters.h:62
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool alias(RegisterRef RA, RegisterRef RB) const
Definition: RDFRegisters.h:115
static bool isRegMaskId(RegisterId R)
Definition: RDFRegisters.h:101
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
Definition: RDFRegisters.h:166
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:343
const uint32_t * getRegMaskBits(RegisterId R) const
Definition: RDFRegisters.h:109
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1966
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
const_iterator begin() const
Definition: RDFRegisters.h:64