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RISCVAsmBackend.h
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1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
11 
14 #include "llvm/MC/MCAsmBackend.h"
17 
18 namespace llvm {
19 class MCAssembler;
20 class MCObjectTargetWriter;
21 class raw_ostream;
22 
23 class RISCVAsmBackend : public MCAsmBackend {
24  const MCSubtargetInfo &STI;
25  uint8_t OSABI;
26  bool Is64Bit;
27  bool ForceRelocs = false;
28 
29 public:
30  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
31  : MCAsmBackend(support::little), STI(STI), OSABI(OSABI),
32  Is64Bit(Is64Bit) {}
33  ~RISCVAsmBackend() override {}
34 
35  void setForceRelocs() { ForceRelocs = true; }
36 
37  // Generate diff expression relocations if the relax feature is enabled or had
38  // previously been enabled, otherwise it is safe for the assembler to
39  // calculate these internally.
40  bool requiresDiffExpressionRelocations() const override {
41  return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
42  }
43  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
45  uint64_t Value, bool IsResolved,
46  const MCSubtargetInfo *STI) const override;
47 
48  std::unique_ptr<MCObjectTargetWriter>
49  createObjectTargetWriter() const override;
50 
51  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
52  const MCValue &Target) override;
53 
54  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
55  const MCRelaxableFragment *DF,
56  const MCAsmLayout &Layout) const override {
57  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
58  }
59 
60  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
61  uint64_t Value,
62  const MCRelaxableFragment *DF,
63  const MCAsmLayout &Layout,
64  const bool WasForced) const override;
65 
66  unsigned getNumFixupKinds() const override {
68  }
69 
71  const static MCFixupKindInfo Infos[] = {
72  // This table *must* be in the order that the fixup_* kinds are defined in
73  // RISCVFixupKinds.h.
74  //
75  // name offset bits flags
76  { "fixup_riscv_hi20", 12, 20, 0 },
77  { "fixup_riscv_lo12_i", 20, 12, 0 },
78  { "fixup_riscv_lo12_s", 0, 32, 0 },
79  { "fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
80  { "fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel },
81  { "fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
82  { "fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
83  { "fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
84  { "fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel },
85  { "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
86  { "fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel },
87  { "fixup_riscv_relax", 0, 0, 0 }
88  };
89  static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
90  "Not all fixup kinds added to Infos array");
91 
92  if (Kind < FirstTargetFixupKind)
93  return MCAsmBackend::getFixupKindInfo(Kind);
94 
95  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
96  "Invalid kind!");
97  return Infos[Kind - FirstTargetFixupKind];
98  }
99 
100  bool mayNeedRelaxation(const MCInst &Inst,
101  const MCSubtargetInfo &STI) const override;
102  unsigned getRelaxedOpcode(unsigned Op) const;
103 
104  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
105  MCInst &Res) const override;
106 
107 
108  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
109 };
110 }
111 
112 #endif
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:73
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
const FeatureBitset & getFeatureBits() const
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
unsigned getRelaxedOpcode(unsigned Op) const
bool writeNopData(raw_ostream &OS, uint64_t Count) const override
Write an (optimal) nop sequence of Count bytes to the given output.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
PowerPC TLS Dynamic Call Fixup
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
Target - Wrapper for Target specific information.
bool requiresDiffExpressionRelocations() const override
Check whether the given target requires emitting differences of two symbols as a set of relocations...
Generic base class for all target subtargets.
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const override
Relax the instruction in the given fragment to the next wider instruction.
Target independent information on a fixup kind.
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.