28#define DEBUG_TYPE "riscv-disassembler"
34 std::unique_ptr<MCInstrInfo const>
const MCII;
46 void addSPOperands(
MCInst &
MI)
const;
53 return new RISCVDisassembler(STI, Ctx,
T.createMCInstrInfo());
69 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
81 if (Reg != RISCV::X1 && Reg != RISCV::X5)
177 if (RegNo >= 32 || RegNo & 1)
187 const void *Decoder) {
191 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
210 if (RegNo >= 32 || RegNo % 2)
213 const RISCVDisassembler *Dis =
214 static_cast<const RISCVDisassembler *
>(Decoder);
218 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
227 if (RegNo >= 32 || RegNo % 4)
230 const RISCVDisassembler *Dis =
231 static_cast<const RISCVDisassembler *
>(Decoder);
235 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
244 if (RegNo >= 32 || RegNo % 8)
247 const RISCVDisassembler *Dis =
248 static_cast<const RISCVDisassembler *
>(Decoder);
252 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
264 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
274 assert(isUInt<N>(Imm) &&
"Invalid immediate");
285 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
292 assert(isUInt<N>(Imm) &&
"Invalid immediate");
304 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
311 assert(isUInt<N>(Imm) &&
"Invalid immediate");
322 assert(isUInt<6>(Imm) &&
"Invalid immediate");
324 Imm = (SignExtend64<6>(Imm) & 0xfffff);
332 assert(isUInt<3>(Imm) &&
"Invalid immediate");
365 uint64_t Address,
const void *Decoder);
371 uint64_t Address,
const void *Decoder);
377#include "RISCVGenDisassemblerTables.inc"
406 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
408 decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
419 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
421 decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
458 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
463 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
464 Opcode == RISCV::TH_SWD);
474 uint64_t Address,
const void *Decoder) {
491 uint64_t Address,
const void *Decoder) {
498void RISCVDisassembler::addSPOperands(
MCInst &
MI)
const {
501 if (MCID.
operands()[i].RegClass == RISCV::SPRegClassID)
514#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
515 DESC, ADDITIONAL_OPERATION) \
517 if (FEATURE_CHECKS) { \
518 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
519 Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
520 if (Result != MCDisassembler::Fail) { \
521 ADDITIONAL_OPERATION; \
526#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
527 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
529#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
530 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
532#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
533 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
536 if ((Bytes[0] & 0x3) == 0x3) {
537 if (Bytes.
size() < 4) {
546 !STI.hasFeature(RISCV::Feature64Bit),
547 DecoderTableRV32Zdinx32,
548 "RV32Zdinx table (Double in Integer and rv32)");
550 !STI.hasFeature(RISCV::Feature64Bit),
551 DecoderTableRV32Zacas32,
552 "RV32Zacas table (Compare-And-Swap and rv32)");
554 "RVZfinx table (Float in Integer)");
556 DecoderTableXVentana32,
"Ventana custom opcode table");
558 "XTHeadBa custom opcode table");
560 "XTHeadBb custom opcode table");
562 "XTHeadBs custom opcode table");
564 DecoderTableXTHeadCondMov32,
565 "XTHeadCondMov custom opcode table");
567 "XTHeadCmo custom opcode table");
569 DecoderTableXTHeadFMemIdx32,
570 "XTHeadFMemIdx custom opcode table");
572 "XTHeadMac custom opcode table");
574 DecoderTableXTHeadMemIdx32,
575 "XTHeadMemIdx custom opcode table");
577 DecoderTableXTHeadMemPair32,
578 "XTHeadMemPair custom opcode table");
580 DecoderTableXTHeadSync32,
581 "XTHeadSync custom opcode table");
583 "XTHeadVdot custom opcode table");
585 "SiFive VCIX custom opcode table");
587 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
588 "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
590 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
591 "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
593 RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
594 "SiFive Matrix Multiplication Instruction opcode table");
596 RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
597 "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
599 DecoderTableXSiFivecdiscarddlone32,
600 "SiFive sf.cdiscard.d.l1 custom opcode table");
602 DecoderTableXSiFivecflushdlone32,
603 "SiFive sf.cflush.d.l1 custom opcode table");
605 "SiFive sf.cease custom opcode table");
607 DecoderTableXCVbitmanip32,
608 "CORE-V Bit Manipulation custom opcode table");
610 "CORE-V Event load custom opcode table");
612 "CORE-V MAC custom opcode table");
614 "CORE-V MEM custom opcode table");
616 "CORE-V ALU custom opcode table");
618 "CORE-V SIMD extensions custom opcode table");
620 "CORE-V Immediate Branching custom opcode table");
626 if (Bytes.
size() < 2) {
634 DecoderTableRISCV32Only_16,
635 "RISCV32Only_16 table (16-bit Instruction)");
637 "RVZicfiss table (Shadow Stack)");
639 "Zcmt table (16-bit Table Jump Instructions)");
641 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
642 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
644 "RISCV_C table (16-bit Instruction)");
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
uint32_t read32le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
Target & getTheRISCV64Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.