LLVM  6.0.0svn
RISCVDisassembler.cpp
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1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RISCVDisassembler class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/Support/Endian.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "riscv-disassembler"
27 
29 
30 namespace {
31 class RISCVDisassembler : public MCDisassembler {
32 
33 public:
34  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35  : MCDisassembler(STI, Ctx) {}
36 
37  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38  ArrayRef<uint8_t> Bytes, uint64_t Address,
39  raw_ostream &VStream,
40  raw_ostream &CStream) const override;
41 };
42 } // end anonymous namespace
43 
45  const MCSubtargetInfo &STI,
46  MCContext &Ctx) {
47  return new RISCVDisassembler(STI, Ctx);
48 }
49 
51  // Register the disassembler for each target.
56 }
57 
58 static const unsigned GPRDecoderTable[] = {
59  RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
60  RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
61  RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
62  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
63  RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
64  RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
65  RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
66  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
67 };
68 
69 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
70  uint64_t Address,
71  const void *Decoder) {
72  if (RegNo > sizeof(GPRDecoderTable)) {
73  return MCDisassembler::Fail;
74  }
75 
76  // We must define our own mapping from RegNo to register identifier.
77  // Accessing index RegNo in the register class will work in the case that
78  // registers were added in ascending order, but not in general.
79  unsigned Reg = GPRDecoderTable[RegNo];
82 }
83 
84 template <unsigned N>
85 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
86  int64_t Address, const void *Decoder) {
87  assert(isUInt<N>(Imm) && "Invalid immediate");
90 }
91 
92 template <unsigned N>
93 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
94  int64_t Address, const void *Decoder) {
95  assert(isUInt<N>(Imm) && "Invalid immediate");
96  // Sign-extend the number in the bottom N bits of Imm
97  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
99 }
100 
101 template <unsigned N>
102 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
103  int64_t Address,
104  const void *Decoder) {
105  assert(isUInt<N>(Imm) && "Invalid immediate");
106  // Sign-extend the number in the bottom N bits of Imm after accounting for
107  // the fact that the N bit immediate is stored in N-1 bits (the LSB is
108  // always zero)
109  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
111 }
112 
113 #include "RISCVGenDisassemblerTables.inc"
114 
115 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
116  ArrayRef<uint8_t> Bytes,
117  uint64_t Address,
118  raw_ostream &OS,
119  raw_ostream &CS) const {
120  // TODO: although assuming 4-byte instructions is sufficient for RV32 and
121  // RV64, this will need modification when supporting the compressed
122  // instruction set extension (RVC) which uses 16-bit instructions. Other
123  // instruction set extensions have the option of defining instructions up to
124  // 176 bits wide.
125  Size = 4;
126  if (Bytes.size() < 4) {
127  Size = 0;
128  return MCDisassembler::Fail;
129  }
130 
131  // Get the four bytes of the instruction.
132  uint32_t Inst = support::endian::read32le(Bytes.data());
133 
134  return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
135 }
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
DecodeStatus
Ternary decode status.
MCDisassembler::DecodeStatus DecodeStatus
Superclass for all disassemblers.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
Reg
All possible values of the reg field in the ModR/M byte.
void LLVMInitializeRISCVDisassembler()
Target & getTheRISCV32Target()
Context object for machine code objects.
Definition: MCContext.h:59
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
Target & getTheRISCV64Target()
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
const T * data() const
Definition: ArrayRef.h:146
static const unsigned GPRDecoderTable[]
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
uint32_t read32le(const void *P)
Definition: Endian.h:369
MCSubtargetInfo - Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123