LLVM  8.0.0svn
RISCVDisassembler.cpp
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1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RISCVDisassembler class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Utils/RISCVBaseInfo.h"
16 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "riscv-disassembler"
28 
30 
31 namespace {
32 class RISCVDisassembler : public MCDisassembler {
33 
34 public:
35  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36  : MCDisassembler(STI, Ctx) {}
37 
38  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39  ArrayRef<uint8_t> Bytes, uint64_t Address,
40  raw_ostream &VStream,
41  raw_ostream &CStream) const override;
42 };
43 } // end anonymous namespace
44 
46  const MCSubtargetInfo &STI,
47  MCContext &Ctx) {
48  return new RISCVDisassembler(STI, Ctx);
49 }
50 
52  // Register the disassembler for each target.
57 }
58 
59 static const unsigned GPRDecoderTable[] = {
60  RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
61  RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
62  RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
63  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
64  RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
65  RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
66  RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
67  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
68 };
69 
70 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
71  uint64_t Address,
72  const void *Decoder) {
73  if (RegNo > sizeof(GPRDecoderTable))
74  return MCDisassembler::Fail;
75 
76  // We must define our own mapping from RegNo to register identifier.
77  // Accessing index RegNo in the register class will work in the case that
78  // registers were added in ascending order, but not in general.
79  unsigned Reg = GPRDecoderTable[RegNo];
82 }
83 
84 static const unsigned FPR32DecoderTable[] = {
85  RISCV::F0_32, RISCV::F1_32, RISCV::F2_32, RISCV::F3_32,
86  RISCV::F4_32, RISCV::F5_32, RISCV::F6_32, RISCV::F7_32,
87  RISCV::F8_32, RISCV::F9_32, RISCV::F10_32, RISCV::F11_32,
88  RISCV::F12_32, RISCV::F13_32, RISCV::F14_32, RISCV::F15_32,
89  RISCV::F16_32, RISCV::F17_32, RISCV::F18_32, RISCV::F19_32,
90  RISCV::F20_32, RISCV::F21_32, RISCV::F22_32, RISCV::F23_32,
91  RISCV::F24_32, RISCV::F25_32, RISCV::F26_32, RISCV::F27_32,
92  RISCV::F28_32, RISCV::F29_32, RISCV::F30_32, RISCV::F31_32
93 };
94 
95 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
96  uint64_t Address,
97  const void *Decoder) {
98  if (RegNo > sizeof(FPR32DecoderTable))
99  return MCDisassembler::Fail;
100 
101  // We must define our own mapping from RegNo to register identifier.
102  // Accessing index RegNo in the register class will work in the case that
103  // registers were added in ascending order, but not in general.
104  unsigned Reg = FPR32DecoderTable[RegNo];
105  Inst.addOperand(MCOperand::createReg(Reg));
107 }
108 
109 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
110  uint64_t Address,
111  const void *Decoder) {
112  if (RegNo > 8) {
113  return MCDisassembler::Fail;
114  }
115  unsigned Reg = FPR32DecoderTable[RegNo + 8];
116  Inst.addOperand(MCOperand::createReg(Reg));
118 }
119 
120 static const unsigned FPR64DecoderTable[] = {
121  RISCV::F0_64, RISCV::F1_64, RISCV::F2_64, RISCV::F3_64,
122  RISCV::F4_64, RISCV::F5_64, RISCV::F6_64, RISCV::F7_64,
123  RISCV::F8_64, RISCV::F9_64, RISCV::F10_64, RISCV::F11_64,
124  RISCV::F12_64, RISCV::F13_64, RISCV::F14_64, RISCV::F15_64,
125  RISCV::F16_64, RISCV::F17_64, RISCV::F18_64, RISCV::F19_64,
126  RISCV::F20_64, RISCV::F21_64, RISCV::F22_64, RISCV::F23_64,
127  RISCV::F24_64, RISCV::F25_64, RISCV::F26_64, RISCV::F27_64,
128  RISCV::F28_64, RISCV::F29_64, RISCV::F30_64, RISCV::F31_64
129 };
130 
131 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
132  uint64_t Address,
133  const void *Decoder) {
134  if (RegNo > sizeof(FPR64DecoderTable))
135  return MCDisassembler::Fail;
136 
137  // We must define our own mapping from RegNo to register identifier.
138  // Accessing index RegNo in the register class will work in the case that
139  // registers were added in ascending order, but not in general.
140  unsigned Reg = FPR64DecoderTable[RegNo];
141  Inst.addOperand(MCOperand::createReg(Reg));
143 }
144 
145 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
146  uint64_t Address,
147  const void *Decoder) {
148  if (RegNo > 8) {
149  return MCDisassembler::Fail;
150  }
151  unsigned Reg = FPR64DecoderTable[RegNo + 8];
152  Inst.addOperand(MCOperand::createReg(Reg));
154 }
155 
156 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
157  uint64_t Address,
158  const void *Decoder) {
159  if (RegNo == 0) {
160  return MCDisassembler::Fail;
161  }
162 
163  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
164 }
165 
166 static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
167  uint64_t Address,
168  const void *Decoder) {
169  if (RegNo == 2) {
170  return MCDisassembler::Fail;
171  }
172 
173  return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
174 }
175 
176 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
177  uint64_t Address,
178  const void *Decoder) {
179  if (RegNo > 8)
180  return MCDisassembler::Fail;
181 
182  unsigned Reg = GPRDecoderTable[RegNo + 8];
183  Inst.addOperand(MCOperand::createReg(Reg));
185 }
186 
187 // Add implied SP operand for instructions *SP compressed instructions. The SP
188 // operand isn't explicitly encoded in the instruction.
189 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
190  if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
191  Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
192  Inst.getOpcode() == RISCV::C_FLWSP ||
193  Inst.getOpcode() == RISCV::C_FSWSP ||
194  Inst.getOpcode() == RISCV::C_FLDSP ||
195  Inst.getOpcode() == RISCV::C_FSDSP ||
196  Inst.getOpcode() == RISCV::C_ADDI4SPN) {
197  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
198  }
199  if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
200  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
201  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
202  }
203 }
204 
205 template <unsigned N>
206 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
207  int64_t Address, const void *Decoder) {
208  assert(isUInt<N>(Imm) && "Invalid immediate");
209  addImplySP(Inst, Address, Decoder);
210  Inst.addOperand(MCOperand::createImm(Imm));
212 }
213 
214 template <unsigned N>
215 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
216  int64_t Address,
217  const void *Decoder) {
218  if (Imm == 0)
219  return MCDisassembler::Fail;
220  return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
221 }
222 
223 template <unsigned N>
224 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
225  int64_t Address, const void *Decoder) {
226  assert(isUInt<N>(Imm) && "Invalid immediate");
227  addImplySP(Inst, Address, Decoder);
228  // Sign-extend the number in the bottom N bits of Imm
229  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
231 }
232 
233 template <unsigned N>
234 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
235  int64_t Address,
236  const void *Decoder) {
237  if (Imm == 0)
238  return MCDisassembler::Fail;
239  return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
240 }
241 
242 template <unsigned N>
243 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
244  int64_t Address,
245  const void *Decoder) {
246  assert(isUInt<N>(Imm) && "Invalid immediate");
247  // Sign-extend the number in the bottom N bits of Imm after accounting for
248  // the fact that the N bit immediate is stored in N-1 bits (the LSB is
249  // always zero)
250  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
252 }
253 
254 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
255  int64_t Address,
256  const void *Decoder) {
257  assert(isUInt<6>(Imm) && "Invalid immediate");
258  if (Imm > 31) {
259  Imm = (SignExtend64<6>(Imm) & 0xfffff);
260  }
261  Inst.addOperand(MCOperand::createImm(Imm));
263 }
264 
265 static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
266  int64_t Address,
267  const void *Decoder) {
268  assert(isUInt<3>(Imm) && "Invalid immediate");
270  return MCDisassembler::Fail;
271 
272  Inst.addOperand(MCOperand::createImm(Imm));
274 }
275 
276 #include "RISCVGenDisassemblerTables.inc"
277 
278 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
279  ArrayRef<uint8_t> Bytes,
280  uint64_t Address,
281  raw_ostream &OS,
282  raw_ostream &CS) const {
283  // TODO: This will need modification when supporting instruction set
284  // extensions with instructions > 32-bits (up to 176 bits wide).
285  uint32_t Insn;
286  DecodeStatus Result;
287 
288  // It's a 32 bit instruction if bit 0 and 1 are 1.
289  if ((Bytes[0] & 0x3) == 0x3) {
290  if (Bytes.size() < 4) {
291  Size = 0;
292  return MCDisassembler::Fail;
293  }
294  Insn = support::endian::read32le(Bytes.data());
295  LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
296  Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
297  Size = 4;
298  } else {
299  if (Bytes.size() < 2) {
300  Size = 0;
301  return MCDisassembler::Fail;
302  }
303  Insn = support::endian::read16le(Bytes.data());
304 
305  if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
306  LLVM_DEBUG(
307  dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
308  // Calling the auto-generated decoder function.
309  Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
310  this, STI);
311  if (Result != MCDisassembler::Fail) {
312  Size = 2;
313  return Result;
314  }
315  }
316 
317  LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
318  // Calling the auto-generated decoder function.
319  Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
320  Size = 2;
321  }
322 
323  return Result;
324 }
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool isValidRoundingMode(unsigned Mode)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
DecodeStatus
Ternary decode status.
MCDisassembler::DecodeStatus DecodeStatus
Superclass for all disassemblers.
unsigned Reg
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
uint16_t read16le(const void *P)
Definition: Endian.h:368
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
static const unsigned FPR32DecoderTable[]
void LLVMInitializeRISCVDisassembler()
Target & getTheRISCV32Target()
Context object for machine code objects.
Definition: MCContext.h:63
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static const unsigned FPR64DecoderTable[]
Target & getTheRISCV64Target()
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
const T * data() const
Definition: ArrayRef.h:146
static const unsigned GPRDecoderTable[]
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Target - Wrapper for Target specific information.
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder)
uint32_t read32le(const void *P)
Definition: Endian.h:369
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:47
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
unsigned getOpcode() const
Definition: MCInst.h:174
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
#define LLVM_DEBUG(X)
Definition: Debug.h:123
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)