LLVM  9.0.0svn
Macros | Functions | Variables
RISCVISelLowering.cpp File Reference
#include "RISCVISelLowering.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-lower"
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static void normaliseSetCC (SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
 
static unsigned getBranchOpcodeForIntCondCode (ISD::CondCode CC)
 
static SDValue getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static RISCVISD::NodeType getRISCVWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG)
 
static MachineBasicBlockemitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static MachineBasicBlockemitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static bool isSelectPseudo (MachineInstr &MI)
 
static MachineBasicBlockemitSelectPseudo (MachineInstr &MI, MachineBasicBlock *BB)
 
static bool CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static bool CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned XLen, AtomicRMWInst::BinOp BinOp)
 

Variables

static const MCPhysReg ArgGPRs []
 
static const MCPhysReg ArgFPR32s []
 
static const MCPhysReg ArgFPR64s []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 38 of file RISCVISelLowering.cpp.

Function Documentation

◆ CC_RISCV()

static bool CC_RISCV ( const DataLayout DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy 
)
static

◆ CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG 
)
static

◆ emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitSelectPseudo()

static MachineBasicBlock* emitSelectPseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr MI,
MachineBasicBlock BB 
)
static

◆ getBranchOpcodeForIntCondCode()

static unsigned getBranchOpcodeForIntCondCode ( ISD::CondCode  CC)
static

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  XLen,
AtomicRMWInst::BinOp  BinOp 
)
static

◆ getRISCVWOpcode()

static RISCVISD::NodeType getRISCVWOpcode ( unsigned  Opcode)
static

◆ getTargetNode() [1/3]

static SDValue getTargetNode ( GlobalAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

◆ getTargetNode() [2/3]

static SDValue getTargetNode ( BlockAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

◆ getTargetNode() [3/3]

static SDValue getTargetNode ( ConstantPoolSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 399 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::Depth, llvm::ConstantPoolSDNode::getAlignment(), llvm::TargetMachine::getCodeModel(), llvm::SelectionDAG::getConstant(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::RISCVRegisterInfo::getFrameRegister(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::ConstantPoolSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getRegClassFor(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstantPool(), llvm::TargetLoweringBase::getTargetMachine(), getTargetNode(), llvm::SDValue::getValueType(), llvm::RISCVMachineFunctionInfo::getVarArgsFrameIndex(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::Glue, llvm::MipsISD::Hi, llvm::TargetLowering::isPositionIndependent(), llvm::MipsISD::Lo, llvm::CodeModel::Medium, llvm::RISCVII::MO_HI, llvm::RISCVII::MO_LO, N, normaliseSetCC(), llvm::ISD::OR, Reg, llvm::report_fatal_error(), llvm::ISD::SELECT, llvm::RISCVISD::SELECT_CC, llvm::ISD::SETCC, llvm::MachineFrameInfo::setFrameAddressIsTaken(), llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::MachineFrameInfo::setReturnAddressIsTaken(), llvm::ISD::SHL, llvm::TargetMachine::shouldAssumeDSOLocal(), llvm::CodeModel::Small, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::TargetLowering::verifyReturnAddressArgumentIsConstant().

◆ isSelectPseudo()

static bool isSelectPseudo ( MachineInstr MI)
static

Definition at line 942 of file RISCVISelLowering.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by emitSelectPseudo().

◆ normaliseSetCC()

static void normaliseSetCC ( SDValue LHS,
SDValue RHS,
ISD::CondCode CC 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

Definition at line 1492 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineRegisterInfo::addLiveIn(), llvm::Address, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, Arg, llvm::Function::arg_empty(), ArgGPRs, assert(), llvm::RISCVISD::BuildPairF64, llvm::CallingConv::C, llvm::RISCVISD::CALL, Callee, CC_RISCV(), Context, convertLocVTToValVT(), convertValVTToLocVT(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::SelectionDAG::CreateStackTemporary(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SmallVectorBase::empty(), llvm::MVT::f64, false, llvm::CallingConv::Fast, llvm::CCValAssign::Full, G, llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::RISCVRegisterInfo::getCallPreservedMask(), llvm::TargetRegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getDataLayout(), llvm::CCState::getFirstUnallocated(), llvm::MachinePointerInfo::getFixedStack(), llvm::Function::getFnAttribute(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemcpy(), llvm::CCState::getNextStackOffset(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::Function::getReturnType(), llvm::SelectionDAG::getStore(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::Attribute::getValueAsString(), llvm::CCValAssign::getValVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::Glue, llvm::GlobalValue::hasExternalWeakLinkage(), llvm::Function::hasFnAttribute(), llvm::MipsISD::Hi, I, llvm::MVT::i32, llvm::CCValAssign::Indirect, llvm::ISD::ArgFlagsTy::isByVal(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::Type::isVoidTy(), llvm::MipsISD::Lo, llvm::makeArrayRef(), llvm::BitmaskEnumDetail::Mask(), llvm::RISCVII::MO_CALL, llvm::RISCVISD::MRET_FLAG, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), Reg, llvm::report_fatal_error(), llvm::RISCVISD::RET_FLAG, llvm::MachineFrameInfo::setHasTailCall(), llvm::RISCVMachineFunctionInfo::setVarArgsFrameIndex(), llvm::RISCVMachineFunctionInfo::setVarArgsSaveSize(), Size, llvm::SmallVectorBase::size(), llvm::ArrayRef< T >::size(), llvm::RISCVISD::SplitF64, llvm::RISCVISD::SRET_FLAG, llvm::SPII::Store, llvm::RISCVISD::TAIL, llvm::ISD::TokenFactor, TRI, unpackFromMemLoc(), unpackFromRegLoc(), and llvm::RISCVISD::URET_FLAG.

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

Variable Documentation

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
static
Initial value:
= {
RISCV::F10_32, RISCV::F11_32, RISCV::F12_32, RISCV::F13_32,
RISCV::F14_32, RISCV::F15_32, RISCV::F16_32, RISCV::F17_32
}

Definition at line 1121 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
static
Initial value:
= {
RISCV::F10_64, RISCV::F11_64, RISCV::F12_64, RISCV::F13_64,
RISCV::F14_64, RISCV::F15_64, RISCV::F16_64, RISCV::F17_64
}

Definition at line 1125 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
static
Initial value:
= {
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 1117 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), isSortedByValueNo(), and unpackF64OnRV32DSoftABI().