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RISCVISelLowering.cpp
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1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that RISCV uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RISCVISelLowering.h"
16 #include "RISCV.h"
17 #include "RISCVRegisterInfo.h"
18 #include "RISCVSubtarget.h"
19 #include "RISCVTargetMachine.h"
28 #include "llvm/IR/DiagnosticInfo.h"
30 #include "llvm/Support/Debug.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "riscv-lower"
37 
39  const RISCVSubtarget &STI)
40  : TargetLowering(TM), Subtarget(STI) {
41 
42  MVT XLenVT = Subtarget.getXLenVT();
43 
44  // Set up the register classes.
45  addRegisterClass(XLenVT, &RISCV::GPRRegClass);
46 
47  // Compute derived properties from the register classes.
49 
51 
52  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
53  setLoadExtAction(N, XLenVT, MVT::i1, Promote);
54 
55  // TODO: add all necessary setOperationAction calls.
60 
61  for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
63 
68 
75 
81 
85 
92 
95 
97 
98  // Function alignments (log2).
101 
102  // Effectively disable jump table generation.
104 }
105 
106 // Changes the condition code and swaps operands if necessary, so the SetCC
107 // operation matches one of the comparisons supported directly in the RISC-V
108 // ISA.
109 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
110  switch (CC) {
111  default:
112  break;
113  case ISD::SETGT:
114  case ISD::SETLE:
115  case ISD::SETUGT:
116  case ISD::SETULE:
118  std::swap(LHS, RHS);
119  break;
120  }
121 }
122 
123 // Return the RISC-V branch opcode that matches the given DAG integer
124 // condition code. The CondCode must be one of those supported by the RISC-V
125 // ISA (see normaliseSetCC).
127  switch (CC) {
128  default:
129  llvm_unreachable("Unsupported CondCode");
130  case ISD::SETEQ:
131  return RISCV::BEQ;
132  case ISD::SETNE:
133  return RISCV::BNE;
134  case ISD::SETLT:
135  return RISCV::BLT;
136  case ISD::SETGE:
137  return RISCV::BGE;
138  case ISD::SETULT:
139  return RISCV::BLTU;
140  case ISD::SETUGE:
141  return RISCV::BGEU;
142  }
143 }
144 
146  SelectionDAG &DAG) const {
147  switch (Op.getOpcode()) {
148  default:
149  report_fatal_error("unimplemented operand");
150  case ISD::GlobalAddress:
151  return lowerGlobalAddress(Op, DAG);
152  case ISD::BlockAddress:
153  return lowerBlockAddress(Op, DAG);
154  case ISD::SELECT:
155  return lowerSELECT(Op, DAG);
156  }
157 }
158 
159 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
160  SelectionDAG &DAG) const {
161  SDLoc DL(Op);
162  EVT Ty = Op.getValueType();
163  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
164  const GlobalValue *GV = N->getGlobal();
165  int64_t Offset = N->getOffset();
166 
167  if (isPositionIndependent() || Subtarget.is64Bit())
168  report_fatal_error("Unable to lowerGlobalAddress");
169 
170  SDValue GAHi =
171  DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_HI);
172  SDValue GALo =
173  DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_LO);
174  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
175  SDValue MNLo =
176  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
177  return MNLo;
178 }
179 
180 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
181  SelectionDAG &DAG) const {
182  SDLoc DL(Op);
183  EVT Ty = Op.getValueType();
184  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
185  const BlockAddress *BA = N->getBlockAddress();
186  int64_t Offset = N->getOffset();
187 
188  if (isPositionIndependent() || Subtarget.is64Bit())
189  report_fatal_error("Unable to lowerBlockAddress");
190 
191  SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI);
192  SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_LO);
193  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, BAHi), 0);
194  SDValue MNLo =
195  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, BALo), 0);
196  return MNLo;
197 }
198 
199 SDValue RISCVTargetLowering::lowerExternalSymbol(SDValue Op,
200  SelectionDAG &DAG) const {
201  SDLoc DL(Op);
202  EVT Ty = Op.getValueType();
203  ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
204  const char *Sym = N->getSymbol();
205 
206  // TODO: should also handle gp-relative loads.
207 
208  if (isPositionIndependent() || Subtarget.is64Bit())
209  report_fatal_error("Unable to lowerExternalSymbol");
210 
211  SDValue GAHi = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_HI);
212  SDValue GALo = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_LO);
213  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
214  SDValue MNLo =
215  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
216  return MNLo;
217 }
218 
219 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
220  SDValue CondV = Op.getOperand(0);
221  SDValue TrueV = Op.getOperand(1);
222  SDValue FalseV = Op.getOperand(2);
223  SDLoc DL(Op);
224  MVT XLenVT = Subtarget.getXLenVT();
225 
226  // If the result type is XLenVT and CondV is the output of a SETCC node
227  // which also operated on XLenVT inputs, then merge the SETCC node into the
228  // lowered RISCVISD::SELECT_CC to take advantage of the integer
229  // compare+branch instructions. i.e.:
230  // (select (setcc lhs, rhs, cc), truev, falsev)
231  // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
232  if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
233  CondV.getOperand(0).getSimpleValueType() == XLenVT) {
234  SDValue LHS = CondV.getOperand(0);
235  SDValue RHS = CondV.getOperand(1);
236  auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
237  ISD::CondCode CCVal = CC->get();
238 
239  normaliseSetCC(LHS, RHS, CCVal);
240 
241  SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
242  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
243  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
244  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
245  }
246 
247  // Otherwise:
248  // (select condv, truev, falsev)
249  // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
250  SDValue Zero = DAG.getConstant(0, DL, XLenVT);
251  SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
252 
253  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
254  SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
255 
256  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
257 }
258 
261  MachineBasicBlock *BB) const {
263  DebugLoc DL = MI.getDebugLoc();
264 
265  assert(MI.getOpcode() == RISCV::Select_GPR_Using_CC_GPR &&
266  "Unexpected instr type to insert");
267 
268  // To "insert" a SELECT instruction, we actually have to insert the triangle
269  // control-flow pattern. The incoming instruction knows the destination vreg
270  // to set, the condition code register to branch on, the true/false values to
271  // select between, and the condcode to use to select the appropriate branch.
272  //
273  // We produce the following control flow:
274  // HeadMBB
275  // | \
276  // | IfFalseMBB
277  // | /
278  // TailMBB
279  const BasicBlock *LLVM_BB = BB->getBasicBlock();
281 
282  MachineBasicBlock *HeadMBB = BB;
283  MachineFunction *F = BB->getParent();
284  MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
285  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
286 
287  F->insert(I, IfFalseMBB);
288  F->insert(I, TailMBB);
289  // Move all remaining instructions to TailMBB.
290  TailMBB->splice(TailMBB->begin(), HeadMBB,
291  std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
292  // Update machine-CFG edges by transferring all successors of the current
293  // block to the new block which will contain the Phi node for the select.
294  TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
295  // Set the successors for HeadMBB.
296  HeadMBB->addSuccessor(IfFalseMBB);
297  HeadMBB->addSuccessor(TailMBB);
298 
299  // Insert appropriate branch.
300  unsigned LHS = MI.getOperand(1).getReg();
301  unsigned RHS = MI.getOperand(2).getReg();
302  auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
303  unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
304 
305  BuildMI(HeadMBB, DL, TII.get(Opcode))
306  .addReg(LHS)
307  .addReg(RHS)
308  .addMBB(TailMBB);
309 
310  // IfFalseMBB just falls through to TailMBB.
311  IfFalseMBB->addSuccessor(TailMBB);
312 
313  // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
314  BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI),
315  MI.getOperand(0).getReg())
316  .addReg(MI.getOperand(4).getReg())
317  .addMBB(HeadMBB)
318  .addReg(MI.getOperand(5).getReg())
319  .addMBB(IfFalseMBB);
320 
321  MI.eraseFromParent(); // The pseudo instruction is gone now.
322  return TailMBB;
323 }
324 
325 // Calling Convention Implementation.
326 #include "RISCVGenCallingConv.inc"
327 
328 // Transform physical registers into virtual registers.
329 SDValue RISCVTargetLowering::LowerFormalArguments(
330  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
331  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
332  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
333 
334  switch (CallConv) {
335  default:
336  report_fatal_error("Unsupported calling convention");
337  case CallingConv::C:
338  case CallingConv::Fast:
339  break;
340  }
341 
343  MachineRegisterInfo &RegInfo = MF.getRegInfo();
344  MVT XLenVT = Subtarget.getXLenVT();
345 
346  if (IsVarArg)
347  report_fatal_error("VarArg not supported");
348 
349  // Assign locations to all of the incoming arguments.
351  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
352  CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV32);
353 
354  for (auto &VA : ArgLocs) {
355  if (!VA.isRegLoc())
356  report_fatal_error("Defined with too many args");
357 
358  // Arguments passed in registers.
359  EVT RegVT = VA.getLocVT();
360  if (RegVT != XLenVT) {
361  DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
362  << RegVT.getEVTString() << "\n");
363  report_fatal_error("unhandled argument type");
364  }
365  const unsigned VReg =
366  RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
367  RegInfo.addLiveIn(VA.getLocReg(), VReg);
368  SDValue ArgIn = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
369 
370  InVals.push_back(ArgIn);
371  }
372  return Chain;
373 }
374 
375 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
376 // and output parameter nodes.
377 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
378  SmallVectorImpl<SDValue> &InVals) const {
379  SelectionDAG &DAG = CLI.DAG;
380  SDLoc &DL = CLI.DL;
382  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
384  SDValue Chain = CLI.Chain;
385  SDValue Callee = CLI.Callee;
386  CLI.IsTailCall = false;
387  CallingConv::ID CallConv = CLI.CallConv;
388  bool IsVarArg = CLI.IsVarArg;
389  EVT PtrVT = getPointerTy(DAG.getDataLayout());
390 
391  if (IsVarArg) {
392  report_fatal_error("LowerCall with varargs not implemented");
393  }
394 
396 
397  // Analyze the operands of the call, assigning locations to each operand.
399  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
400  ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV32);
401 
402  // Get a count of how many bytes are to be pushed on the stack.
403  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
404 
405  for (auto &Arg : Outs) {
406  if (!Arg.Flags.isByVal())
407  continue;
408  report_fatal_error("Passing arguments byval not yet implemented");
409  }
410 
411  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
412 
413  // Copy argument values to their designated locations.
415  SDValue StackPtr;
416  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
417  CCValAssign &VA = ArgLocs[I];
418  SDValue ArgValue = OutVals[I];
419 
420  // Promote the value if needed.
421  // For now, only handle fully promoted arguments.
422  switch (VA.getLocInfo()) {
423  case CCValAssign::Full:
424  break;
425  default:
426  llvm_unreachable("Unknown loc info!");
427  }
428 
429  if (VA.isRegLoc()) {
430  // Queue up the argument copies and emit them at the end.
431  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
432  } else {
433  assert(VA.isMemLoc() && "Argument not register or memory");
434  report_fatal_error("Passing arguments via the stack not yet implemented");
435  }
436  }
437 
438  SDValue Glue;
439 
440  // Build a sequence of copy-to-reg nodes, chained and glued together.
441  for (auto &Reg : RegsToPass) {
442  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
443  Glue = Chain.getValue(1);
444  }
445 
446  if (isa<GlobalAddressSDNode>(Callee)) {
447  Callee = lowerGlobalAddress(Callee, DAG);
448  } else if (isa<ExternalSymbolSDNode>(Callee)) {
449  Callee = lowerExternalSymbol(Callee, DAG);
450  }
451 
452  // The first call operand is the chain and the second is the target address.
454  Ops.push_back(Chain);
455  Ops.push_back(Callee);
456 
457  // Add argument registers to the end of the list so that they are
458  // known live into the call.
459  for (auto &Reg : RegsToPass)
460  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
461 
462  // Add a register mask operand representing the call-preserved registers.
463  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
464  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
465  assert(Mask && "Missing call preserved mask for calling convention");
466  Ops.push_back(DAG.getRegisterMask(Mask));
467 
468  // Glue the call to the argument copies, if any.
469  if (Glue.getNode())
470  Ops.push_back(Glue);
471 
472  // Emit the call.
473  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
474  Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
475  Glue = Chain.getValue(1);
476 
477  // Mark the end of the call, which is glued to the call itself.
478  Chain = DAG.getCALLSEQ_END(Chain,
479  DAG.getConstant(NumBytes, DL, PtrVT, true),
480  DAG.getConstant(0, DL, PtrVT, true),
481  Glue, DL);
482  Glue = Chain.getValue(1);
483 
484  // Assign locations to each value returned by this call.
486  CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
487  RetCCInfo.AnalyzeCallResult(Ins, RetCC_RISCV32);
488 
489  // Copy all of the result registers out of their specified physreg.
490  for (auto &VA : RVLocs) {
491  // Copy the value out, gluing the copy to the end of the call sequence.
492  SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
493  VA.getLocVT(), Glue);
494  Chain = RetValue.getValue(1);
495  Glue = RetValue.getValue(2);
496 
497  InVals.push_back(Chain.getValue(0));
498  }
499 
500  return Chain;
501 }
502 
503 SDValue
504 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
505  bool IsVarArg,
507  const SmallVectorImpl<SDValue> &OutVals,
508  const SDLoc &DL, SelectionDAG &DAG) const {
509  if (IsVarArg) {
510  report_fatal_error("VarArg not supported");
511  }
512 
513  // Stores the assignment of the return value to a location.
515 
516  // Info about the registers and stack slot.
517  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
518  *DAG.getContext());
519 
520  CCInfo.AnalyzeReturn(Outs, RetCC_RISCV32);
521 
522  SDValue Flag;
523  SmallVector<SDValue, 4> RetOps(1, Chain);
524 
525  // Copy the result values into the output registers.
526  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
527  CCValAssign &VA = RVLocs[i];
528  assert(VA.isRegLoc() && "Can only return in registers!");
529 
530  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
531 
532  // Guarantee that all emitted copies are stuck together.
533  Flag = Chain.getValue(1);
534  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
535  }
536 
537  RetOps[0] = Chain; // Update chain.
538 
539  // Add the flag if we have it.
540  if (Flag.getNode()) {
541  RetOps.push_back(Flag);
542  }
543 
544  return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
545 }
546 
547 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
548  switch ((RISCVISD::NodeType)Opcode) {
550  break;
551  case RISCVISD::RET_FLAG:
552  return "RISCVISD::RET_FLAG";
553  case RISCVISD::CALL:
554  return "RISCVISD::CALL";
555  case RISCVISD::SELECT_CC:
556  return "RISCVISD::SELECT_CC";
557  }
558  return nullptr;
559 }
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const GlobalValue * getGlobal() const
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const RISCVRegisterInfo * getRegisterInfo() const override
static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC)
A debug info location.
Definition: DebugLoc.h:34
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
bool isMemLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
The address of a basic block.
Definition: Constants.h:813
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const HexagonInstrInfo * TII
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
const BlockAddress * getBlockAddress() const
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
SmallVector< ISD::OutputArg, 32 > Outs
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
virtual const TargetInstrInfo * getInstrInfo() const
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const char * getSymbol() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:120
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool isPositionIndependent() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
CCValAssign - Represent assignment of one arg/retval to a location.
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:382
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
bool is64Bit() const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:651
SmallVector< SDValue, 32 > OutVals
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getRegister(unsigned Reg, EVT VT)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:118
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
const SDValue & getOperand(unsigned i) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:600
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:355