LLVM  7.0.0svn
RISCVISelLowering.cpp
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1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that RISCV uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RISCVISelLowering.h"
16 #include "RISCV.h"
18 #include "RISCVRegisterInfo.h"
19 #include "RISCVSubtarget.h"
20 #include "RISCVTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
30 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/Support/Debug.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "riscv-lower"
39 
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 
43  const RISCVSubtarget &STI)
44  : TargetLowering(TM), Subtarget(STI) {
45 
46  MVT XLenVT = Subtarget.getXLenVT();
47 
48  // Set up the register classes.
49  addRegisterClass(XLenVT, &RISCV::GPRRegClass);
50 
51  if (Subtarget.hasStdExtF())
52  addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
53  if (Subtarget.hasStdExtD())
54  addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
55 
56  // Compute derived properties from the register classes.
58 
60 
61  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
62  setLoadExtAction(N, XLenVT, MVT::i1, Promote);
63 
64  // TODO: add all necessary setOperationAction calls.
66 
71 
74 
79 
80  for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
82 
83  if (!Subtarget.hasStdExtM()) {
91  }
92 
97 
101 
108 
109  ISD::CondCode FPCCToExtend[] = {
113 
114  if (Subtarget.hasStdExtF()) {
117  for (auto CC : FPCCToExtend)
122  }
123 
124  if (Subtarget.hasStdExtD()) {
127  for (auto CC : FPCCToExtend)
134  }
135 
139 
140  if (Subtarget.hasStdExtA())
142  else
144 
146 
147  // Function alignments (log2).
148  unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
149  setMinFunctionAlignment(FunctionAlignment);
150  setPrefFunctionAlignment(FunctionAlignment);
151 
152  // Effectively disable jump table generation.
154 }
155 
157  EVT VT) const {
158  if (!VT.isVector())
159  return getPointerTy(DL);
161 }
162 
164  const AddrMode &AM, Type *Ty,
165  unsigned AS,
166  Instruction *I) const {
167  // No global is ever allowed as a base.
168  if (AM.BaseGV)
169  return false;
170 
171  // Require a 12-bit signed offset.
172  if (!isInt<12>(AM.BaseOffs))
173  return false;
174 
175  switch (AM.Scale) {
176  case 0: // "r+i" or just "i", depending on HasBaseReg.
177  break;
178  case 1:
179  if (!AM.HasBaseReg) // allow "r+i".
180  break;
181  return false; // disallow "r+r" or "r+r+i".
182  default:
183  return false;
184  }
185 
186  return true;
187 }
188 
190  return isInt<12>(Imm);
191 }
192 
194  return isInt<12>(Imm);
195 }
196 
197 // On RV32, 64-bit integers are split into their high and low parts and held
198 // in two different registers, so the trunc is free since the low register can
199 // just be used.
200 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
201  if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
202  return false;
203  unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();
204  unsigned DestBits = DstTy->getPrimitiveSizeInBits();
205  return (SrcBits == 64 && DestBits == 32);
206 }
207 
208 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
209  if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
210  !SrcVT.isInteger() || !DstVT.isInteger())
211  return false;
212  unsigned SrcBits = SrcVT.getSizeInBits();
213  unsigned DestBits = DstVT.getSizeInBits();
214  return (SrcBits == 64 && DestBits == 32);
215 }
216 
218  // Zexts are free if they can be combined with a load.
219  if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
220  EVT MemVT = LD->getMemoryVT();
221  if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
222  (Subtarget.is64Bit() && MemVT == MVT::i32)) &&
223  (LD->getExtensionType() == ISD::NON_EXTLOAD ||
224  LD->getExtensionType() == ISD::ZEXTLOAD))
225  return true;
226  }
227 
228  return TargetLowering::isZExtFree(Val, VT2);
229 }
230 
231 // Changes the condition code and swaps operands if necessary, so the SetCC
232 // operation matches one of the comparisons supported directly in the RISC-V
233 // ISA.
234 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
235  switch (CC) {
236  default:
237  break;
238  case ISD::SETGT:
239  case ISD::SETLE:
240  case ISD::SETUGT:
241  case ISD::SETULE:
243  std::swap(LHS, RHS);
244  break;
245  }
246 }
247 
248 // Return the RISC-V branch opcode that matches the given DAG integer
249 // condition code. The CondCode must be one of those supported by the RISC-V
250 // ISA (see normaliseSetCC).
252  switch (CC) {
253  default:
254  llvm_unreachable("Unsupported CondCode");
255  case ISD::SETEQ:
256  return RISCV::BEQ;
257  case ISD::SETNE:
258  return RISCV::BNE;
259  case ISD::SETLT:
260  return RISCV::BLT;
261  case ISD::SETGE:
262  return RISCV::BGE;
263  case ISD::SETULT:
264  return RISCV::BLTU;
265  case ISD::SETUGE:
266  return RISCV::BGEU;
267  }
268 }
269 
271  SelectionDAG &DAG) const {
272  switch (Op.getOpcode()) {
273  default:
274  report_fatal_error("unimplemented operand");
275  case ISD::GlobalAddress:
276  return lowerGlobalAddress(Op, DAG);
277  case ISD::BlockAddress:
278  return lowerBlockAddress(Op, DAG);
279  case ISD::ConstantPool:
280  return lowerConstantPool(Op, DAG);
281  case ISD::SELECT:
282  return lowerSELECT(Op, DAG);
283  case ISD::VASTART:
284  return lowerVASTART(Op, DAG);
285  case ISD::FRAMEADDR:
286  return LowerFRAMEADDR(Op, DAG);
287  case ISD::RETURNADDR:
288  return LowerRETURNADDR(Op, DAG);
289  }
290 }
291 
292 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
293  SelectionDAG &DAG) const {
294  SDLoc DL(Op);
295  EVT Ty = Op.getValueType();
296  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
297  const GlobalValue *GV = N->getGlobal();
298  int64_t Offset = N->getOffset();
299  MVT XLenVT = Subtarget.getXLenVT();
300 
301  if (isPositionIndependent() || Subtarget.is64Bit())
302  report_fatal_error("Unable to lowerGlobalAddress");
303  // In order to maximise the opportunity for common subexpression elimination,
304  // emit a separate ADD node for the global address offset instead of folding
305  // it in the global address node. Later peephole optimisations may choose to
306  // fold it back in when profitable.
307  SDValue GAHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_HI);
308  SDValue GALo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_LO);
309  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
310  SDValue MNLo =
311  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
312  if (Offset != 0)
313  return DAG.getNode(ISD::ADD, DL, Ty, MNLo,
314  DAG.getConstant(Offset, DL, XLenVT));
315  return MNLo;
316 }
317 
318 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
319  SelectionDAG &DAG) const {
320  SDLoc DL(Op);
321  EVT Ty = Op.getValueType();
322  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
323  const BlockAddress *BA = N->getBlockAddress();
324  int64_t Offset = N->getOffset();
325 
326  if (isPositionIndependent() || Subtarget.is64Bit())
327  report_fatal_error("Unable to lowerBlockAddress");
328 
329  SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI);
330  SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_LO);
331  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, BAHi), 0);
332  SDValue MNLo =
333  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, BALo), 0);
334  return MNLo;
335 }
336 
337 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
338  SelectionDAG &DAG) const {
339  SDLoc DL(Op);
340  EVT Ty = Op.getValueType();
341  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
342  const Constant *CPA = N->getConstVal();
343  int64_t Offset = N->getOffset();
344  unsigned Alignment = N->getAlignment();
345 
346  if (!isPositionIndependent()) {
347  SDValue CPAHi =
348  DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_HI);
349  SDValue CPALo =
350  DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_LO);
351  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, CPAHi), 0);
352  SDValue MNLo =
353  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, CPALo), 0);
354  return MNLo;
355  } else {
356  report_fatal_error("Unable to lowerConstantPool");
357  }
358 }
359 
360 SDValue RISCVTargetLowering::lowerExternalSymbol(SDValue Op,
361  SelectionDAG &DAG) const {
362  SDLoc DL(Op);
363  EVT Ty = Op.getValueType();
364  ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
365  const char *Sym = N->getSymbol();
366 
367  // TODO: should also handle gp-relative loads.
368 
369  if (isPositionIndependent() || Subtarget.is64Bit())
370  report_fatal_error("Unable to lowerExternalSymbol");
371 
372  SDValue GAHi = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_HI);
373  SDValue GALo = DAG.getTargetExternalSymbol(Sym, Ty, RISCVII::MO_LO);
374  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
375  SDValue MNLo =
376  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
377  return MNLo;
378 }
379 
380 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
381  SDValue CondV = Op.getOperand(0);
382  SDValue TrueV = Op.getOperand(1);
383  SDValue FalseV = Op.getOperand(2);
384  SDLoc DL(Op);
385  MVT XLenVT = Subtarget.getXLenVT();
386 
387  // If the result type is XLenVT and CondV is the output of a SETCC node
388  // which also operated on XLenVT inputs, then merge the SETCC node into the
389  // lowered RISCVISD::SELECT_CC to take advantage of the integer
390  // compare+branch instructions. i.e.:
391  // (select (setcc lhs, rhs, cc), truev, falsev)
392  // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
393  if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
394  CondV.getOperand(0).getSimpleValueType() == XLenVT) {
395  SDValue LHS = CondV.getOperand(0);
396  SDValue RHS = CondV.getOperand(1);
397  auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
398  ISD::CondCode CCVal = CC->get();
399 
400  normaliseSetCC(LHS, RHS, CCVal);
401 
402  SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
403  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
404  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
405  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
406  }
407 
408  // Otherwise:
409  // (select condv, truev, falsev)
410  // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
411  SDValue Zero = DAG.getConstant(0, DL, XLenVT);
412  SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
413 
414  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
415  SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
416 
417  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
418 }
419 
420 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
423 
424  SDLoc DL(Op);
425  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
427 
428  // vastart just stores the address of the VarArgsFrameIndex slot into the
429  // memory location argument.
430  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
431  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
432  MachinePointerInfo(SV));
433 }
434 
435 SDValue RISCVTargetLowering::LowerFRAMEADDR(SDValue Op,
436  SelectionDAG &DAG) const {
437  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
439  MachineFrameInfo &MFI = MF.getFrameInfo();
440  MFI.setFrameAddressIsTaken(true);
441  unsigned FrameReg = RI.getFrameRegister(MF);
442  int XLenInBytes = Subtarget.getXLen() / 8;
443 
444  EVT VT = Op.getValueType();
445  SDLoc DL(Op);
446  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
447  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
448  while (Depth--) {
449  int Offset = -(XLenInBytes * 2);
450  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
451  DAG.getIntPtrConstant(Offset, DL));
452  FrameAddr =
453  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
454  }
455  return FrameAddr;
456 }
457 
458 SDValue RISCVTargetLowering::LowerRETURNADDR(SDValue Op,
459  SelectionDAG &DAG) const {
460  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
462  MachineFrameInfo &MFI = MF.getFrameInfo();
463  MFI.setReturnAddressIsTaken(true);
464  MVT XLenVT = Subtarget.getXLenVT();
465  int XLenInBytes = Subtarget.getXLen() / 8;
466 
468  return SDValue();
469 
470  EVT VT = Op.getValueType();
471  SDLoc DL(Op);
472  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
473  if (Depth) {
474  int Off = -XLenInBytes;
475  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
476  SDValue Offset = DAG.getConstant(Off, DL, VT);
477  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
478  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
480  }
481 
482  // Return the value of the return address register, marking it an implicit
483  // live-in.
484  unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
485  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
486 }
487 
489  MachineBasicBlock *BB) {
490  assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
491 
492  MachineFunction &MF = *BB->getParent();
493  DebugLoc DL = MI.getDebugLoc();
494  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
495  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
496  unsigned LoReg = MI.getOperand(0).getReg();
497  unsigned HiReg = MI.getOperand(1).getReg();
498  unsigned SrcReg = MI.getOperand(2).getReg();
499  const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
500  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
501 
502  TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
503  RI);
504  MachineMemOperand *MMO =
505  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
507  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
508  .addFrameIndex(FI)
509  .addImm(0)
510  .addMemOperand(MMO);
511  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
512  .addFrameIndex(FI)
513  .addImm(4)
514  .addMemOperand(MMO);
515  MI.eraseFromParent(); // The pseudo instruction is gone now.
516  return BB;
517 }
518 
520  MachineBasicBlock *BB) {
521  assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
522  "Unexpected instruction");
523 
524  MachineFunction &MF = *BB->getParent();
525  DebugLoc DL = MI.getDebugLoc();
526  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
527  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
528  unsigned DstReg = MI.getOperand(0).getReg();
529  unsigned LoReg = MI.getOperand(1).getReg();
530  unsigned HiReg = MI.getOperand(2).getReg();
531  const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
532  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
533 
534  MachineMemOperand *MMO =
535  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
537  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
538  .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
539  .addFrameIndex(FI)
540  .addImm(0)
541  .addMemOperand(MMO);
542  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
543  .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
544  .addFrameIndex(FI)
545  .addImm(4)
546  .addMemOperand(MMO);
547  TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI);
548  MI.eraseFromParent(); // The pseudo instruction is gone now.
549  return BB;
550 }
551 
554  MachineBasicBlock *BB) const {
555  switch (MI.getOpcode()) {
556  default:
557  llvm_unreachable("Unexpected instr type to insert");
558  case RISCV::Select_GPR_Using_CC_GPR:
559  case RISCV::Select_FPR32_Using_CC_GPR:
560  case RISCV::Select_FPR64_Using_CC_GPR:
561  break;
562  case RISCV::BuildPairF64Pseudo:
563  return emitBuildPairF64Pseudo(MI, BB);
564  case RISCV::SplitF64Pseudo:
565  return emitSplitF64Pseudo(MI, BB);
566  }
567 
568  // To "insert" a SELECT instruction, we actually have to insert the triangle
569  // control-flow pattern. The incoming instruction knows the destination vreg
570  // to set, the condition code register to branch on, the true/false values to
571  // select between, and the condcode to use to select the appropriate branch.
572  //
573  // We produce the following control flow:
574  // HeadMBB
575  // | \
576  // | IfFalseMBB
577  // | /
578  // TailMBB
580  const BasicBlock *LLVM_BB = BB->getBasicBlock();
581  DebugLoc DL = MI.getDebugLoc();
583 
584  MachineBasicBlock *HeadMBB = BB;
585  MachineFunction *F = BB->getParent();
586  MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
587  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
588 
589  F->insert(I, IfFalseMBB);
590  F->insert(I, TailMBB);
591  // Move all remaining instructions to TailMBB.
592  TailMBB->splice(TailMBB->begin(), HeadMBB,
593  std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
594  // Update machine-CFG edges by transferring all successors of the current
595  // block to the new block which will contain the Phi node for the select.
596  TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
597  // Set the successors for HeadMBB.
598  HeadMBB->addSuccessor(IfFalseMBB);
599  HeadMBB->addSuccessor(TailMBB);
600 
601  // Insert appropriate branch.
602  unsigned LHS = MI.getOperand(1).getReg();
603  unsigned RHS = MI.getOperand(2).getReg();
604  auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
605  unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
606 
607  BuildMI(HeadMBB, DL, TII.get(Opcode))
608  .addReg(LHS)
609  .addReg(RHS)
610  .addMBB(TailMBB);
611 
612  // IfFalseMBB just falls through to TailMBB.
613  IfFalseMBB->addSuccessor(TailMBB);
614 
615  // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
616  BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI),
617  MI.getOperand(0).getReg())
618  .addReg(MI.getOperand(4).getReg())
619  .addMBB(HeadMBB)
620  .addReg(MI.getOperand(5).getReg())
621  .addMBB(IfFalseMBB);
622 
623  MI.eraseFromParent(); // The pseudo instruction is gone now.
624  return TailMBB;
625 }
626 
627 // Calling Convention Implementation.
628 // The expectations for frontend ABI lowering vary from target to target.
629 // Ideally, an LLVM frontend would be able to avoid worrying about many ABI
630 // details, but this is a longer term goal. For now, we simply try to keep the
631 // role of the frontend as simple and well-defined as possible. The rules can
632 // be summarised as:
633 // * Never split up large scalar arguments. We handle them here.
634 // * If a hardfloat calling convention is being used, and the struct may be
635 // passed in a pair of registers (fp+fp, int+fp), and both registers are
636 // available, then pass as two separate arguments. If either the GPRs or FPRs
637 // are exhausted, then pass according to the rule below.
638 // * If a struct could never be passed in registers or directly in a stack
639 // slot (as it is larger than 2*XLEN and the floating point rules don't
640 // apply), then pass it using a pointer with the byval attribute.
641 // * If a struct is less than 2*XLEN, then coerce to either a two-element
642 // word-sized array or a 2*XLEN scalar (depending on alignment).
643 // * The frontend can determine whether a struct is returned by reference or
644 // not based on its size and fields. If it will be returned by reference, the
645 // frontend must modify the prototype so a pointer with the sret annotation is
646 // passed as the first argument. This is not necessary for large scalar
647 // returns.
648 // * Struct return values and varargs should be coerced to structs containing
649 // register-size fields in the same situations they would be for fixed
650 // arguments.
651 
652 static const MCPhysReg ArgGPRs[] = {
653  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
654  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
655 };
656 
657 // Pass a 2*XLEN argument that has been split into two XLEN values through
658 // registers or the stack as necessary.
659 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
660  ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
661  MVT ValVT2, MVT LocVT2,
662  ISD::ArgFlagsTy ArgFlags2) {
663  unsigned XLenInBytes = XLen / 8;
664  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
665  // At least one half can be passed via register.
666  State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
667  VA1.getLocVT(), CCValAssign::Full));
668  } else {
669  // Both halves must be passed on the stack, with proper alignment.
670  unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
671  State.addLoc(
673  State.AllocateStack(XLenInBytes, StackAlign),
674  VA1.getLocVT(), CCValAssign::Full));
676  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
678  return false;
679  }
680 
681  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
682  // The second half can also be passed via register.
683  State.addLoc(
684  CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
685  } else {
686  // The second half is passed via the stack, without additional alignment.
688  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
690  }
691 
692  return false;
693 }
694 
695 // Implements the RISC-V calling convention. Returns true upon failure.
696 static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
697  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
698  CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
699  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
700  assert(XLen == 32 || XLen == 64);
701  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
702  if (ValVT == MVT::f32) {
703  LocVT = MVT::i32;
704  LocInfo = CCValAssign::BCvt;
705  }
706 
707  // Any return value split in to more than two values can't be returned
708  // directly.
709  if (IsRet && ValNo > 1)
710  return true;
711 
712  // If this is a variadic argument, the RISC-V calling convention requires
713  // that it is assigned an 'even' or 'aligned' register if it has 8-byte
714  // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
715  // be used regardless of whether the original argument was split during
716  // legalisation or not. The argument will not be passed by registers if the
717  // original type is larger than 2*XLEN, so the register alignment rule does
718  // not apply.
719  unsigned TwoXLenInBytes = (2 * XLen) / 8;
720  if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
721  DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
722  unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
723  // Skip 'odd' register if necessary.
724  if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
725  State.AllocateReg(ArgGPRs);
726  }
727 
728  SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
729  SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
730  State.getPendingArgFlags();
731 
732  assert(PendingLocs.size() == PendingArgFlags.size() &&
733  "PendingLocs and PendingArgFlags out of sync");
734 
735  // Handle passing f64 on RV32D with a soft float ABI.
736  if (XLen == 32 && ValVT == MVT::f64) {
737  assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
738  "Can't lower f64 if it is split");
739  // Depending on available argument GPRS, f64 may be passed in a pair of
740  // GPRs, split between a GPR and the stack, or passed completely on the
741  // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
742  // cases.
743  unsigned Reg = State.AllocateReg(ArgGPRs);
744  LocVT = MVT::i32;
745  if (!Reg) {
746  unsigned StackOffset = State.AllocateStack(8, 8);
747  State.addLoc(
748  CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
749  return false;
750  }
751  if (!State.AllocateReg(ArgGPRs))
752  State.AllocateStack(4, 4);
753  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
754  return false;
755  }
756 
757  // Split arguments might be passed indirectly, so keep track of the pending
758  // values.
759  if (ArgFlags.isSplit() || !PendingLocs.empty()) {
760  LocVT = XLenVT;
761  LocInfo = CCValAssign::Indirect;
762  PendingLocs.push_back(
763  CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
764  PendingArgFlags.push_back(ArgFlags);
765  if (!ArgFlags.isSplitEnd()) {
766  return false;
767  }
768  }
769 
770  // If the split argument only had two elements, it should be passed directly
771  // in registers or on the stack.
772  if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
773  assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
774  // Apply the normal calling convention rules to the first half of the
775  // split argument.
776  CCValAssign VA = PendingLocs[0];
777  ISD::ArgFlagsTy AF = PendingArgFlags[0];
778  PendingLocs.clear();
779  PendingArgFlags.clear();
780  return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
781  ArgFlags);
782  }
783 
784  // Allocate to a register if possible, or else a stack slot.
785  unsigned Reg = State.AllocateReg(ArgGPRs);
786  unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
787 
788  // If we reach this point and PendingLocs is non-empty, we must be at the
789  // end of a split argument that must be passed indirectly.
790  if (!PendingLocs.empty()) {
791  assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
792  assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
793 
794  for (auto &It : PendingLocs) {
795  if (Reg)
796  It.convertToReg(Reg);
797  else
798  It.convertToMem(StackOffset);
799  State.addLoc(It);
800  }
801  PendingLocs.clear();
802  PendingArgFlags.clear();
803  return false;
804  }
805 
806  assert(LocVT == XLenVT && "Expected an XLenVT at this stage");
807 
808  if (Reg) {
809  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
810  } else {
811  State.addLoc(
812  CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
813  }
814  return false;
815 }
816 
817 void RISCVTargetLowering::analyzeInputArgs(
818  MachineFunction &MF, CCState &CCInfo,
819  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
820  unsigned NumArgs = Ins.size();
821  FunctionType *FType = MF.getFunction().getFunctionType();
822 
823  for (unsigned i = 0; i != NumArgs; ++i) {
824  MVT ArgVT = Ins[i].VT;
825  ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
826 
827  Type *ArgTy = nullptr;
828  if (IsRet)
829  ArgTy = FType->getReturnType();
830  else if (Ins[i].isOrigArg())
831  ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
832 
833  if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
834  ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
835  LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
836  << EVT(ArgVT).getEVTString() << '\n');
837  llvm_unreachable(nullptr);
838  }
839  }
840 }
841 
842 void RISCVTargetLowering::analyzeOutputArgs(
843  MachineFunction &MF, CCState &CCInfo,
844  const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
845  CallLoweringInfo *CLI) const {
846  unsigned NumArgs = Outs.size();
847 
848  for (unsigned i = 0; i != NumArgs; i++) {
849  MVT ArgVT = Outs[i].VT;
850  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
851  Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
852 
853  if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
854  ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
855  LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
856  << EVT(ArgVT).getEVTString() << "\n");
857  llvm_unreachable(nullptr);
858  }
859  }
860 }
861 
862 // The caller is responsible for loading the full value if the argument is
863 // passed with CCValAssign::Indirect.
865  const CCValAssign &VA, const SDLoc &DL) {
867  MachineRegisterInfo &RegInfo = MF.getRegInfo();
868  EVT LocVT = VA.getLocVT();
869  EVT ValVT = VA.getValVT();
870  SDValue Val;
871 
872  unsigned VReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
873  RegInfo.addLiveIn(VA.getLocReg(), VReg);
874  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
875 
876  switch (VA.getLocInfo()) {
877  default:
878  llvm_unreachable("Unexpected CCValAssign::LocInfo");
879  case CCValAssign::Full:
881  break;
882  case CCValAssign::BCvt:
883  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
884  break;
885  }
886  return Val;
887 }
888 
889 // The caller is responsible for loading the full value if the argument is
890 // passed with CCValAssign::Indirect.
892  const CCValAssign &VA, const SDLoc &DL) {
894  MachineFrameInfo &MFI = MF.getFrameInfo();
895  EVT LocVT = VA.getLocVT();
896  EVT ValVT = VA.getValVT();
898  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
899  VA.getLocMemOffset(), /*Immutable=*/true);
900  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
901  SDValue Val;
902 
903  ISD::LoadExtType ExtType;
904  switch (VA.getLocInfo()) {
905  default:
906  llvm_unreachable("Unexpected CCValAssign::LocInfo");
907  case CCValAssign::Full:
909  ExtType = ISD::NON_EXTLOAD;
910  break;
911  }
912  Val = DAG.getExtLoad(
913  ExtType, DL, LocVT, Chain, FIN,
915  return Val;
916 }
917 
919  const CCValAssign &VA, const SDLoc &DL) {
920  assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
921  "Unexpected VA");
923  MachineFrameInfo &MFI = MF.getFrameInfo();
924  MachineRegisterInfo &RegInfo = MF.getRegInfo();
925 
926  if (VA.isMemLoc()) {
927  // f64 is passed on the stack.
928  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
929  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
930  return DAG.getLoad(MVT::f64, DL, Chain, FIN,
932  }
933 
934  assert(VA.isRegLoc() && "Expected register VA assignment");
935 
936  unsigned LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
937  RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
938  SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
939  SDValue Hi;
940  if (VA.getLocReg() == RISCV::X17) {
941  // Second half of f64 is passed on the stack.
942  int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
943  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
944  Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
946  } else {
947  // Second half of f64 is passed in another GPR.
948  unsigned HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
949  RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
950  Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
951  }
952  return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
953 }
954 
955 // Transform physical registers into virtual registers.
956 SDValue RISCVTargetLowering::LowerFormalArguments(
957  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
958  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
959  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
960 
961  switch (CallConv) {
962  default:
963  report_fatal_error("Unsupported calling convention");
964  case CallingConv::C:
965  case CallingConv::Fast:
966  break;
967  }
968 
970  EVT PtrVT = getPointerTy(DAG.getDataLayout());
971  MVT XLenVT = Subtarget.getXLenVT();
972  unsigned XLenInBytes = Subtarget.getXLen() / 8;
973  // Used with vargs to acumulate store chains.
974  std::vector<SDValue> OutChains;
975 
976  // Assign locations to all of the incoming arguments.
978  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
979  analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
980 
981  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
982  CCValAssign &VA = ArgLocs[i];
983  assert(VA.getLocVT() == XLenVT && "Unhandled argument type");
984  SDValue ArgValue;
985  // Passing f64 on RV32D with a soft float ABI must be handled as a special
986  // case.
987  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
988  ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
989  else if (VA.isRegLoc())
990  ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);
991  else
992  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
993 
994  if (VA.getLocInfo() == CCValAssign::Indirect) {
995  // If the original argument was split and passed by reference (e.g. i128
996  // on RV32), we need to load all parts of it here (using the same
997  // address).
998  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
999  MachinePointerInfo()));
1000  unsigned ArgIndex = Ins[i].OrigArgIndex;
1001  assert(Ins[i].PartOffset == 0);
1002  while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1003  CCValAssign &PartVA = ArgLocs[i + 1];
1004  unsigned PartOffset = Ins[i + 1].PartOffset;
1005  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1006  DAG.getIntPtrConstant(PartOffset, DL));
1007  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1008  MachinePointerInfo()));
1009  ++i;
1010  }
1011  continue;
1012  }
1013  InVals.push_back(ArgValue);
1014  }
1015 
1016  if (IsVarArg) {
1018  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
1019  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1020  MachineFrameInfo &MFI = MF.getFrameInfo();
1021  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1023 
1024  // Offset of the first variable argument from stack pointer, and size of
1025  // the vararg save area. For now, the varargs save area is either zero or
1026  // large enough to hold a0-a7.
1027  int VaArgOffset, VarArgsSaveSize;
1028 
1029  // If all registers are allocated, then all varargs must be passed on the
1030  // stack and we don't need to save any argregs.
1031  if (ArgRegs.size() == Idx) {
1032  VaArgOffset = CCInfo.getNextStackOffset();
1033  VarArgsSaveSize = 0;
1034  } else {
1035  VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
1036  VaArgOffset = -VarArgsSaveSize;
1037  }
1038 
1039  // Record the frame index of the first variable argument
1040  // which is a value necessary to VASTART.
1041  int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1042  RVFI->setVarArgsFrameIndex(FI);
1043 
1044  // If saving an odd number of registers then create an extra stack slot to
1045  // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
1046  // offsets to even-numbered registered remain 2*XLEN-aligned.
1047  if (Idx % 2) {
1048  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes,
1049  true);
1050  VarArgsSaveSize += XLenInBytes;
1051  }
1052 
1053  // Copy the integer registers that may have been used for passing varargs
1054  // to the vararg save area.
1055  for (unsigned I = Idx; I < ArgRegs.size();
1056  ++I, VaArgOffset += XLenInBytes) {
1057  const unsigned Reg = RegInfo.createVirtualRegister(RC);
1058  RegInfo.addLiveIn(ArgRegs[I], Reg);
1059  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
1060  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1061  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1062  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
1064  cast<StoreSDNode>(Store.getNode())
1065  ->getMemOperand()
1066  ->setValue((Value *)nullptr);
1067  OutChains.push_back(Store);
1068  }
1069  RVFI->setVarArgsSaveSize(VarArgsSaveSize);
1070  }
1071 
1072  // All stores are grouped in one node to allow the matching between
1073  // the size of Ins and InVals. This only happens for vararg functions.
1074  if (!OutChains.empty()) {
1075  OutChains.push_back(Chain);
1076  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1077  }
1078 
1079  return Chain;
1080 }
1081 
1082 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1083 /// for tail call optimization.
1084 /// Note: This is modelled after ARM's IsEligibleForTailCallOptimization.
1085 bool RISCVTargetLowering::IsEligibleForTailCallOptimization(
1086  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
1087  const SmallVector<CCValAssign, 16> &ArgLocs) const {
1088 
1089  auto &Callee = CLI.Callee;
1090  auto CalleeCC = CLI.CallConv;
1091  auto IsVarArg = CLI.IsVarArg;
1092  auto &Outs = CLI.Outs;
1093  auto &Caller = MF.getFunction();
1094  auto CallerCC = Caller.getCallingConv();
1095 
1096  // Do not tail call opt functions with "disable-tail-calls" attribute.
1097  if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
1098  return false;
1099 
1100  // Exception-handling functions need a special set of instructions to
1101  // indicate a return to the hardware. Tail-calling another function would
1102  // probably break this.
1103  // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
1104  // should be expanded as new function attributes are introduced.
1105  if (Caller.hasFnAttribute("interrupt"))
1106  return false;
1107 
1108  // Do not tail call opt functions with varargs.
1109  if (IsVarArg)
1110  return false;
1111 
1112  // Do not tail call opt if the stack is used to pass parameters.
1113  if (CCInfo.getNextStackOffset() != 0)
1114  return false;
1115 
1116  // Do not tail call opt if any parameters need to be passed indirectly.
1117  // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
1118  // passed indirectly. So the address of the value will be passed in a
1119  // register, or if not available, then the address is put on the stack. In
1120  // order to pass indirectly, space on the stack often needs to be allocated
1121  // in order to store the value. In this case the CCInfo.getNextStackOffset()
1122  // != 0 check is not enough and we need to check if any CCValAssign ArgsLocs
1123  // are passed CCValAssign::Indirect.
1124  for (auto &VA : ArgLocs)
1125  if (VA.getLocInfo() == CCValAssign::Indirect)
1126  return false;
1127 
1128  // Do not tail call opt if either caller or callee uses struct return
1129  // semantics.
1130  auto IsCallerStructRet = Caller.hasStructRetAttr();
1131  auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
1132  if (IsCallerStructRet || IsCalleeStructRet)
1133  return false;
1134 
1135  // Externally-defined functions with weak linkage should not be
1136  // tail-called. The behaviour of branch instructions in this situation (as
1137  // used for tail calls) is implementation-defined, so we cannot rely on the
1138  // linker replacing the tail call with a return.
1139  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1140  const GlobalValue *GV = G->getGlobal();
1141  if (GV->hasExternalWeakLinkage())
1142  return false;
1143  }
1144 
1145  // The callee has to preserve all registers the caller needs to preserve.
1146  const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
1147  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1148  if (CalleeCC != CallerCC) {
1149  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1150  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1151  return false;
1152  }
1153 
1154  // Byval parameters hand the function a pointer directly into the stack area
1155  // we want to reuse during a tail call. Working around this *is* possible
1156  // but less efficient and uglier in LowerCall.
1157  for (auto &Arg : Outs)
1158  if (Arg.Flags.isByVal())
1159  return false;
1160 
1161  return true;
1162 }
1163 
1164 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
1165 // and output parameter nodes.
1166 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
1167  SmallVectorImpl<SDValue> &InVals) const {
1168  SelectionDAG &DAG = CLI.DAG;
1169  SDLoc &DL = CLI.DL;
1170  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1171  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1172  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1173  SDValue Chain = CLI.Chain;
1174  SDValue Callee = CLI.Callee;
1175  bool &IsTailCall = CLI.IsTailCall;
1176  CallingConv::ID CallConv = CLI.CallConv;
1177  bool IsVarArg = CLI.IsVarArg;
1178  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1179  MVT XLenVT = Subtarget.getXLenVT();
1180 
1181  MachineFunction &MF = DAG.getMachineFunction();
1182 
1183  // Analyze the operands of the call, assigning locations to each operand.
1185  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1186  analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
1187 
1188  // Check if it's really possible to do a tail call.
1189  if (IsTailCall)
1190  IsTailCall = IsEligibleForTailCallOptimization(ArgCCInfo, CLI, MF,
1191  ArgLocs);
1192 
1193  if (IsTailCall)
1194  ++NumTailCalls;
1195  else if (CLI.CS && CLI.CS.isMustTailCall())
1196  report_fatal_error("failed to perform tail call elimination on a call "
1197  "site marked musttail");
1198 
1199  // Get a count of how many bytes are to be pushed on the stack.
1200  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1201 
1202  // Create local copies for byval args
1203  SmallVector<SDValue, 8> ByValArgs;
1204  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1205  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1206  if (!Flags.isByVal())
1207  continue;
1208 
1209  SDValue Arg = OutVals[i];
1210  unsigned Size = Flags.getByValSize();
1211  unsigned Align = Flags.getByValAlign();
1212 
1213  int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false);
1214  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1215  SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
1216 
1217  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
1218  /*IsVolatile=*/false,
1219  /*AlwaysInline=*/false,
1220  IsTailCall, MachinePointerInfo(),
1221  MachinePointerInfo());
1222  ByValArgs.push_back(FIPtr);
1223  }
1224 
1225  if (!IsTailCall)
1226  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
1227 
1228  // Copy argument values to their designated locations.
1230  SmallVector<SDValue, 8> MemOpChains;
1231  SDValue StackPtr;
1232  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
1233  CCValAssign &VA = ArgLocs[i];
1234  SDValue ArgValue = OutVals[i];
1235  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1236 
1237  // Handle passing f64 on RV32D with a soft float ABI as a special case.
1238  bool IsF64OnRV32DSoftABI =
1239  VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
1240  if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
1241  SDValue SplitF64 = DAG.getNode(
1242  RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
1243  SDValue Lo = SplitF64.getValue(0);
1244  SDValue Hi = SplitF64.getValue(1);
1245 
1246  unsigned RegLo = VA.getLocReg();
1247  RegsToPass.push_back(std::make_pair(RegLo, Lo));
1248 
1249  if (RegLo == RISCV::X17) {
1250  // Second half of f64 is passed on the stack.
1251  // Work out the address of the stack slot.
1252  if (!StackPtr.getNode())
1253  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1254  // Emit the store.
1255  MemOpChains.push_back(
1256  DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
1257  } else {
1258  // Second half of f64 is passed in another GPR.
1259  unsigned RegHigh = RegLo + 1;
1260  RegsToPass.push_back(std::make_pair(RegHigh, Hi));
1261  }
1262  continue;
1263  }
1264 
1265  // IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way
1266  // as any other MemLoc.
1267 
1268  // Promote the value if needed.
1269  // For now, only handle fully promoted and indirect arguments.
1270  switch (VA.getLocInfo()) {
1271  case CCValAssign::Full:
1272  break;
1273  case CCValAssign::BCvt:
1274  ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), ArgValue);
1275  break;
1276  case CCValAssign::Indirect: {
1277  // Store the argument in a stack slot and pass its address.
1278  SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT);
1279  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1280  MemOpChains.push_back(
1281  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1283  // If the original argument was split (e.g. i128), we need
1284  // to store all parts of it here (and pass just one address).
1285  unsigned ArgIndex = Outs[i].OrigArgIndex;
1286  assert(Outs[i].PartOffset == 0);
1287  while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
1288  SDValue PartValue = OutVals[i + 1];
1289  unsigned PartOffset = Outs[i + 1].PartOffset;
1290  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1291  DAG.getIntPtrConstant(PartOffset, DL));
1292  MemOpChains.push_back(
1293  DAG.getStore(Chain, DL, PartValue, Address,
1295  ++i;
1296  }
1297  ArgValue = SpillSlot;
1298  break;
1299  }
1300  default:
1301  llvm_unreachable("Unknown loc info!");
1302  }
1303 
1304  // Use local copy if it is a byval arg.
1305  if (Flags.isByVal())
1306  ArgValue = ByValArgs[j++];
1307 
1308  if (VA.isRegLoc()) {
1309  // Queue up the argument copies and emit them at the end.
1310  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1311  } else {
1312  assert(VA.isMemLoc() && "Argument not register or memory");
1313  assert(!IsTailCall && "Tail call not allowed if stack is used "
1314  "for passing parameters");
1315 
1316  // Work out the address of the stack slot.
1317  if (!StackPtr.getNode())
1318  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1319  SDValue Address =
1320  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1321  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
1322 
1323  // Emit the store.
1324  MemOpChains.push_back(
1325  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1326  }
1327  }
1328 
1329  // Join the stores, which are independent of one another.
1330  if (!MemOpChains.empty())
1331  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1332 
1333  SDValue Glue;
1334 
1335  // Build a sequence of copy-to-reg nodes, chained and glued together.
1336  for (auto &Reg : RegsToPass) {
1337  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
1338  Glue = Chain.getValue(1);
1339  }
1340 
1341  // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
1342  // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
1343  // split it and then direct call can be matched by PseudoCALL.
1344  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
1345  Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0);
1346  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1347  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0);
1348  }
1349 
1350  // The first call operand is the chain and the second is the target address.
1352  Ops.push_back(Chain);
1353  Ops.push_back(Callee);
1354 
1355  // Add argument registers to the end of the list so that they are
1356  // known live into the call.
1357  for (auto &Reg : RegsToPass)
1358  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1359 
1360  if (!IsTailCall) {
1361  // Add a register mask operand representing the call-preserved registers.
1362  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1363  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1364  assert(Mask && "Missing call preserved mask for calling convention");
1365  Ops.push_back(DAG.getRegisterMask(Mask));
1366  }
1367 
1368  // Glue the call to the argument copies, if any.
1369  if (Glue.getNode())
1370  Ops.push_back(Glue);
1371 
1372  // Emit the call.
1373  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1374 
1375  if (IsTailCall) {
1377  return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
1378  }
1379 
1380  Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
1381  Glue = Chain.getValue(1);
1382 
1383  // Mark the end of the call, which is glued to the call itself.
1384  Chain = DAG.getCALLSEQ_END(Chain,
1385  DAG.getConstant(NumBytes, DL, PtrVT, true),
1386  DAG.getConstant(0, DL, PtrVT, true),
1387  Glue, DL);
1388  Glue = Chain.getValue(1);
1389 
1390  // Assign locations to each value returned by this call.
1392  CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
1393  analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true);
1394 
1395  // Copy all of the result registers out of their specified physreg.
1396  for (auto &VA : RVLocs) {
1397  // Copy the value out
1398  SDValue RetValue =
1399  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
1400  // Glue the RetValue to the end of the call sequence
1401  Chain = RetValue.getValue(1);
1402  Glue = RetValue.getValue(2);
1403  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
1404  assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment");
1405  SDValue RetValue2 =
1406  DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue);
1407  Chain = RetValue2.getValue(1);
1408  Glue = RetValue2.getValue(2);
1409  RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
1410  RetValue2);
1411  }
1412 
1413  switch (VA.getLocInfo()) {
1414  default:
1415  llvm_unreachable("Unknown loc info!");
1416  case CCValAssign::Full:
1417  break;
1418  case CCValAssign::BCvt:
1419  RetValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), RetValue);
1420  break;
1421  }
1422 
1423  InVals.push_back(RetValue);
1424  }
1425 
1426  return Chain;
1427 }
1428 
1429 bool RISCVTargetLowering::CanLowerReturn(
1430  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
1431  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1433  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
1434  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1435  MVT VT = Outs[i].VT;
1436  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
1437  if (CC_RISCV(MF.getDataLayout(), i, VT, VT, CCValAssign::Full, ArgFlags,
1438  CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
1439  return false;
1440  }
1441  return true;
1442 }
1443 
1445  const CCValAssign &VA, const SDLoc &DL) {
1446  EVT LocVT = VA.getLocVT();
1447 
1448  switch (VA.getLocInfo()) {
1449  default:
1450  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1451  case CCValAssign::Full:
1452  break;
1453  case CCValAssign::BCvt:
1454  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
1455  break;
1456  }
1457  return Val;
1458 }
1459 
1460 SDValue
1461 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1462  bool IsVarArg,
1463  const SmallVectorImpl<ISD::OutputArg> &Outs,
1464  const SmallVectorImpl<SDValue> &OutVals,
1465  const SDLoc &DL, SelectionDAG &DAG) const {
1466  // Stores the assignment of the return value to a location.
1468 
1469  // Info about the registers and stack slot.
1470  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
1471  *DAG.getContext());
1472 
1473  analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
1474  nullptr);
1475 
1476  SDValue Glue;
1477  SmallVector<SDValue, 4> RetOps(1, Chain);
1478 
1479  // Copy the result values into the output registers.
1480  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
1481  SDValue Val = OutVals[i];
1482  CCValAssign &VA = RVLocs[i];
1483  assert(VA.isRegLoc() && "Can only return in registers!");
1484 
1485  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
1486  // Handle returning f64 on RV32D with a soft float ABI.
1487  assert(VA.isRegLoc() && "Expected return via registers");
1489  DAG.getVTList(MVT::i32, MVT::i32), Val);
1490  SDValue Lo = SplitF64.getValue(0);
1491  SDValue Hi = SplitF64.getValue(1);
1492  unsigned RegLo = VA.getLocReg();
1493  unsigned RegHi = RegLo + 1;
1494  Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
1495  Glue = Chain.getValue(1);
1496  RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
1497  Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
1498  Glue = Chain.getValue(1);
1499  RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
1500  } else {
1501  // Handle a 'normal' return.
1502  Val = packIntoRegLoc(DAG, Val, VA, DL);
1503  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
1504 
1505  // Guarantee that all emitted copies are stuck together.
1506  Glue = Chain.getValue(1);
1507  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1508  }
1509  }
1510 
1511  RetOps[0] = Chain; // Update chain.
1512 
1513  // Add the glue node if we have it.
1514  if (Glue.getNode()) {
1515  RetOps.push_back(Glue);
1516  }
1517 
1518  return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
1519 }
1520 
1521 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
1522  switch ((RISCVISD::NodeType)Opcode) {
1524  break;
1525  case RISCVISD::RET_FLAG:
1526  return "RISCVISD::RET_FLAG";
1527  case RISCVISD::CALL:
1528  return "RISCVISD::CALL";
1529  case RISCVISD::SELECT_CC:
1530  return "RISCVISD::SELECT_CC";
1532  return "RISCVISD::BuildPairF64";
1533  case RISCVISD::SplitF64:
1534  return "RISCVISD::SplitF64";
1535  case RISCVISD::TAIL:
1536  return "RISCVISD::TAIL";
1537  }
1538  return nullptr;
1539 }
1540 
1541 std::pair<unsigned, const TargetRegisterClass *>
1543  StringRef Constraint,
1544  MVT VT) const {
1545  // First, see if this is a constraint that directly corresponds to a
1546  // RISCV register class.
1547  if (Constraint.size() == 1) {
1548  switch (Constraint[0]) {
1549  case 'r':
1550  return std::make_pair(0U, &RISCV::GPRRegClass);
1551  default:
1552  break;
1553  }
1554  }
1555 
1556  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1557 }
1558 
1560  Instruction *Inst,
1561  AtomicOrdering Ord) const {
1562  if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
1563  return Builder.CreateFence(Ord);
1564  if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
1565  return Builder.CreateFence(AtomicOrdering::Release);
1566  return nullptr;
1567 }
1568 
1570  Instruction *Inst,
1571  AtomicOrdering Ord) const {
1572  if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
1573  return Builder.CreateFence(AtomicOrdering::Acquire);
1574  return nullptr;
1575 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:539
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:563
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const GlobalValue * getGlobal() const
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:611
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:135
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:660
unsigned Reg
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const RISCVRegisterInfo * getRegisterInfo() const override
unsigned getValNo() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:436
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:426
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:826
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getXLen() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:731
static MachineBasicBlock * emitSplitF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:398
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
const BlockAddress * getBlockAddress() const
LocInfo getLocInfo() const
static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:656
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
SmallVectorImpl< CCValAssign > & getPendingLocs()
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool hasStdExtA() const
static MachineBasicBlock * emitBuildPairF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:911
virtual const TargetInstrInfo * getInstrInfo() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const char * getSymbol() const
unsigned getByValSize() const
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
TargetInstrInfo - Interface to description of machine instruction set.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
unsigned getOrigAlign() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool hasStdExtF() const
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:689
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:886
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:837
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
bool hasStdExtM() const
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
Definition: DataLayout.cpp:764
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:680
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
The memory access writes data.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReleaseOrStronger(AtomicOrdering ao)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:634
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
static const MCPhysReg ArgGPRs[]
bool hasStdExtD() const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:96
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:383
Type * getReturnType() const
Definition: DerivedTypes.h:124
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:674
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:150
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getByValAlign() const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
bool is64Bit() const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:599
Representation of each machine instruction.
Definition: MachineInstr.h:60
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:685
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:668
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1353
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:700
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:62
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:456
static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
bool hasStdExtC() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:413
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
#define LLVM_DEBUG(X)
Definition: Debug.h:119
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static SDValue packIntoRegLoc(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Function Alias Analysis false
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:584