LLVM  8.0.0svn
RISCVISelLowering.cpp
Go to the documentation of this file.
1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that RISCV uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RISCVISelLowering.h"
16 #include "RISCV.h"
18 #include "RISCVRegisterInfo.h"
19 #include "RISCVSubtarget.h"
20 #include "RISCVTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
30 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/Support/Debug.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "riscv-lower"
39 
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 
43  const RISCVSubtarget &STI)
44  : TargetLowering(TM), Subtarget(STI) {
45 
46  MVT XLenVT = Subtarget.getXLenVT();
47 
48  // Set up the register classes.
49  addRegisterClass(XLenVT, &RISCV::GPRRegClass);
50 
51  if (Subtarget.hasStdExtF())
52  addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
53  if (Subtarget.hasStdExtD())
54  addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
55 
56  // Compute derived properties from the register classes.
58 
60 
61  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
62  setLoadExtAction(N, XLenVT, MVT::i1, Promote);
63 
64  // TODO: add all necessary setOperationAction calls.
66 
71 
74 
79 
80  for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
82 
83  if (!Subtarget.hasStdExtM()) {
91  }
92 
97 
101 
108 
109  ISD::CondCode FPCCToExtend[] = {
113 
114  ISD::NodeType FPOpToExtend[] = {
116 
117  if (Subtarget.hasStdExtF()) {
120  for (auto CC : FPCCToExtend)
125  for (auto Op : FPOpToExtend)
127  }
128 
129  if (Subtarget.hasStdExtD()) {
132  for (auto CC : FPCCToExtend)
139  for (auto Op : FPOpToExtend)
141  }
142 
146 
147  if (Subtarget.hasStdExtA()) {
150  } else {
152  }
153 
155 
156  // Function alignments (log2).
157  unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
158  setMinFunctionAlignment(FunctionAlignment);
159  setPrefFunctionAlignment(FunctionAlignment);
160 
161  // Effectively disable jump table generation.
163 }
164 
166  EVT VT) const {
167  if (!VT.isVector())
168  return getPointerTy(DL);
170 }
171 
173  const CallInst &I,
174  MachineFunction &MF,
175  unsigned Intrinsic) const {
176  switch (Intrinsic) {
177  default:
178  return false;
179  case Intrinsic::riscv_masked_atomicrmw_xchg_i32:
180  case Intrinsic::riscv_masked_atomicrmw_add_i32:
181  case Intrinsic::riscv_masked_atomicrmw_sub_i32:
182  case Intrinsic::riscv_masked_atomicrmw_nand_i32:
183  case Intrinsic::riscv_masked_atomicrmw_max_i32:
184  case Intrinsic::riscv_masked_atomicrmw_min_i32:
185  case Intrinsic::riscv_masked_atomicrmw_umax_i32:
186  case Intrinsic::riscv_masked_atomicrmw_umin_i32:
187  case Intrinsic::riscv_masked_cmpxchg_i32:
188  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
190  Info.memVT = MVT::getVT(PtrTy->getElementType());
191  Info.ptrVal = I.getArgOperand(0);
192  Info.offset = 0;
193  Info.align = 4;
196  return true;
197  }
198 }
199 
201  const AddrMode &AM, Type *Ty,
202  unsigned AS,
203  Instruction *I) const {
204  // No global is ever allowed as a base.
205  if (AM.BaseGV)
206  return false;
207 
208  // Require a 12-bit signed offset.
209  if (!isInt<12>(AM.BaseOffs))
210  return false;
211 
212  switch (AM.Scale) {
213  case 0: // "r+i" or just "i", depending on HasBaseReg.
214  break;
215  case 1:
216  if (!AM.HasBaseReg) // allow "r+i".
217  break;
218  return false; // disallow "r+r" or "r+r+i".
219  default:
220  return false;
221  }
222 
223  return true;
224 }
225 
227  return isInt<12>(Imm);
228 }
229 
231  return isInt<12>(Imm);
232 }
233 
234 // On RV32, 64-bit integers are split into their high and low parts and held
235 // in two different registers, so the trunc is free since the low register can
236 // just be used.
237 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
238  if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
239  return false;
240  unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();
241  unsigned DestBits = DstTy->getPrimitiveSizeInBits();
242  return (SrcBits == 64 && DestBits == 32);
243 }
244 
245 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
246  if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
247  !SrcVT.isInteger() || !DstVT.isInteger())
248  return false;
249  unsigned SrcBits = SrcVT.getSizeInBits();
250  unsigned DestBits = DstVT.getSizeInBits();
251  return (SrcBits == 64 && DestBits == 32);
252 }
253 
255  // Zexts are free if they can be combined with a load.
256  if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
257  EVT MemVT = LD->getMemoryVT();
258  if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
259  (Subtarget.is64Bit() && MemVT == MVT::i32)) &&
260  (LD->getExtensionType() == ISD::NON_EXTLOAD ||
261  LD->getExtensionType() == ISD::ZEXTLOAD))
262  return true;
263  }
264 
265  return TargetLowering::isZExtFree(Val, VT2);
266 }
267 
269  return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
270 }
271 
272 // Changes the condition code and swaps operands if necessary, so the SetCC
273 // operation matches one of the comparisons supported directly in the RISC-V
274 // ISA.
275 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
276  switch (CC) {
277  default:
278  break;
279  case ISD::SETGT:
280  case ISD::SETLE:
281  case ISD::SETUGT:
282  case ISD::SETULE:
284  std::swap(LHS, RHS);
285  break;
286  }
287 }
288 
289 // Return the RISC-V branch opcode that matches the given DAG integer
290 // condition code. The CondCode must be one of those supported by the RISC-V
291 // ISA (see normaliseSetCC).
293  switch (CC) {
294  default:
295  llvm_unreachable("Unsupported CondCode");
296  case ISD::SETEQ:
297  return RISCV::BEQ;
298  case ISD::SETNE:
299  return RISCV::BNE;
300  case ISD::SETLT:
301  return RISCV::BLT;
302  case ISD::SETGE:
303  return RISCV::BGE;
304  case ISD::SETULT:
305  return RISCV::BLTU;
306  case ISD::SETUGE:
307  return RISCV::BGEU;
308  }
309 }
310 
312  SelectionDAG &DAG) const {
313  switch (Op.getOpcode()) {
314  default:
315  report_fatal_error("unimplemented operand");
316  case ISD::GlobalAddress:
317  return lowerGlobalAddress(Op, DAG);
318  case ISD::BlockAddress:
319  return lowerBlockAddress(Op, DAG);
320  case ISD::ConstantPool:
321  return lowerConstantPool(Op, DAG);
322  case ISD::SELECT:
323  return lowerSELECT(Op, DAG);
324  case ISD::VASTART:
325  return lowerVASTART(Op, DAG);
326  case ISD::FRAMEADDR:
327  return lowerFRAMEADDR(Op, DAG);
328  case ISD::RETURNADDR:
329  return lowerRETURNADDR(Op, DAG);
330  }
331 }
332 
333 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
334  SelectionDAG &DAG) const {
335  SDLoc DL(Op);
336  EVT Ty = Op.getValueType();
337  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
338  const GlobalValue *GV = N->getGlobal();
339  int64_t Offset = N->getOffset();
340  MVT XLenVT = Subtarget.getXLenVT();
341 
342  if (isPositionIndependent())
343  report_fatal_error("Unable to lowerGlobalAddress");
344  // In order to maximise the opportunity for common subexpression elimination,
345  // emit a separate ADD node for the global address offset instead of folding
346  // it in the global address node. Later peephole optimisations may choose to
347  // fold it back in when profitable.
348  SDValue GAHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_HI);
349  SDValue GALo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_LO);
350  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
351  SDValue MNLo =
352  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
353  if (Offset != 0)
354  return DAG.getNode(ISD::ADD, DL, Ty, MNLo,
355  DAG.getConstant(Offset, DL, XLenVT));
356  return MNLo;
357 }
358 
359 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
360  SelectionDAG &DAG) const {
361  SDLoc DL(Op);
362  EVT Ty = Op.getValueType();
363  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
364  const BlockAddress *BA = N->getBlockAddress();
365  int64_t Offset = N->getOffset();
366 
367  if (isPositionIndependent())
368  report_fatal_error("Unable to lowerBlockAddress");
369 
370  SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI);
371  SDValue BALo = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_LO);
372  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, BAHi), 0);
373  SDValue MNLo =
374  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, BALo), 0);
375  return MNLo;
376 }
377 
378 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
379  SelectionDAG &DAG) const {
380  SDLoc DL(Op);
381  EVT Ty = Op.getValueType();
382  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
383  const Constant *CPA = N->getConstVal();
384  int64_t Offset = N->getOffset();
385  unsigned Alignment = N->getAlignment();
386 
387  if (!isPositionIndependent()) {
388  SDValue CPAHi =
389  DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_HI);
390  SDValue CPALo =
391  DAG.getTargetConstantPool(CPA, Ty, Alignment, Offset, RISCVII::MO_LO);
392  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, CPAHi), 0);
393  SDValue MNLo =
394  SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, CPALo), 0);
395  return MNLo;
396  } else {
397  report_fatal_error("Unable to lowerConstantPool");
398  }
399 }
400 
401 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
402  SDValue CondV = Op.getOperand(0);
403  SDValue TrueV = Op.getOperand(1);
404  SDValue FalseV = Op.getOperand(2);
405  SDLoc DL(Op);
406  MVT XLenVT = Subtarget.getXLenVT();
407 
408  // If the result type is XLenVT and CondV is the output of a SETCC node
409  // which also operated on XLenVT inputs, then merge the SETCC node into the
410  // lowered RISCVISD::SELECT_CC to take advantage of the integer
411  // compare+branch instructions. i.e.:
412  // (select (setcc lhs, rhs, cc), truev, falsev)
413  // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
414  if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
415  CondV.getOperand(0).getSimpleValueType() == XLenVT) {
416  SDValue LHS = CondV.getOperand(0);
417  SDValue RHS = CondV.getOperand(1);
418  auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
419  ISD::CondCode CCVal = CC->get();
420 
421  normaliseSetCC(LHS, RHS, CCVal);
422 
423  SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
424  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
425  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
426  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
427  }
428 
429  // Otherwise:
430  // (select condv, truev, falsev)
431  // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
432  SDValue Zero = DAG.getConstant(0, DL, XLenVT);
433  SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
434 
435  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
436  SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
437 
438  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
439 }
440 
441 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
444 
445  SDLoc DL(Op);
446  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
448 
449  // vastart just stores the address of the VarArgsFrameIndex slot into the
450  // memory location argument.
451  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
452  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
453  MachinePointerInfo(SV));
454 }
455 
456 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
457  SelectionDAG &DAG) const {
458  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
460  MachineFrameInfo &MFI = MF.getFrameInfo();
461  MFI.setFrameAddressIsTaken(true);
462  unsigned FrameReg = RI.getFrameRegister(MF);
463  int XLenInBytes = Subtarget.getXLen() / 8;
464 
465  EVT VT = Op.getValueType();
466  SDLoc DL(Op);
467  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
468  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
469  while (Depth--) {
470  int Offset = -(XLenInBytes * 2);
471  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
472  DAG.getIntPtrConstant(Offset, DL));
473  FrameAddr =
474  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
475  }
476  return FrameAddr;
477 }
478 
479 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
480  SelectionDAG &DAG) const {
481  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
483  MachineFrameInfo &MFI = MF.getFrameInfo();
484  MFI.setReturnAddressIsTaken(true);
485  MVT XLenVT = Subtarget.getXLenVT();
486  int XLenInBytes = Subtarget.getXLen() / 8;
487 
489  return SDValue();
490 
491  EVT VT = Op.getValueType();
492  SDLoc DL(Op);
493  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
494  if (Depth) {
495  int Off = -XLenInBytes;
496  SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
497  SDValue Offset = DAG.getConstant(Off, DL, VT);
498  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
499  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
501  }
502 
503  // Return the value of the return address register, marking it an implicit
504  // live-in.
505  unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
506  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
507 }
508 
510  DAGCombinerInfo &DCI) const {
511  switch (N->getOpcode()) {
512  default:
513  break;
514  case RISCVISD::SplitF64: {
515  // If the input to SplitF64 is just BuildPairF64 then the operation is
516  // redundant. Instead, use BuildPairF64's operands directly.
517  SDValue Op0 = N->getOperand(0);
518  if (Op0->getOpcode() != RISCVISD::BuildPairF64)
519  break;
520  return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
521  }
522  }
523 
524  return SDValue();
525 }
526 
528  MachineBasicBlock *BB) {
529  assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
530 
531  MachineFunction &MF = *BB->getParent();
532  DebugLoc DL = MI.getDebugLoc();
533  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
534  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
535  unsigned LoReg = MI.getOperand(0).getReg();
536  unsigned HiReg = MI.getOperand(1).getReg();
537  unsigned SrcReg = MI.getOperand(2).getReg();
538  const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
539  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
540 
541  TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
542  RI);
543  MachineMemOperand *MMO =
544  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
546  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
547  .addFrameIndex(FI)
548  .addImm(0)
549  .addMemOperand(MMO);
550  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
551  .addFrameIndex(FI)
552  .addImm(4)
553  .addMemOperand(MMO);
554  MI.eraseFromParent(); // The pseudo instruction is gone now.
555  return BB;
556 }
557 
559  MachineBasicBlock *BB) {
560  assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
561  "Unexpected instruction");
562 
563  MachineFunction &MF = *BB->getParent();
564  DebugLoc DL = MI.getDebugLoc();
565  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
566  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
567  unsigned DstReg = MI.getOperand(0).getReg();
568  unsigned LoReg = MI.getOperand(1).getReg();
569  unsigned HiReg = MI.getOperand(2).getReg();
570  const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
571  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
572 
573  MachineMemOperand *MMO =
574  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
576  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
577  .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
578  .addFrameIndex(FI)
579  .addImm(0)
580  .addMemOperand(MMO);
581  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
582  .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
583  .addFrameIndex(FI)
584  .addImm(4)
585  .addMemOperand(MMO);
586  TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI);
587  MI.eraseFromParent(); // The pseudo instruction is gone now.
588  return BB;
589 }
590 
593  MachineBasicBlock *BB) const {
594  switch (MI.getOpcode()) {
595  default:
596  llvm_unreachable("Unexpected instr type to insert");
597  case RISCV::Select_GPR_Using_CC_GPR:
598  case RISCV::Select_FPR32_Using_CC_GPR:
599  case RISCV::Select_FPR64_Using_CC_GPR:
600  break;
601  case RISCV::BuildPairF64Pseudo:
602  return emitBuildPairF64Pseudo(MI, BB);
603  case RISCV::SplitF64Pseudo:
604  return emitSplitF64Pseudo(MI, BB);
605  }
606 
607  // To "insert" a SELECT instruction, we actually have to insert the triangle
608  // control-flow pattern. The incoming instruction knows the destination vreg
609  // to set, the condition code register to branch on, the true/false values to
610  // select between, and the condcode to use to select the appropriate branch.
611  //
612  // We produce the following control flow:
613  // HeadMBB
614  // | \
615  // | IfFalseMBB
616  // | /
617  // TailMBB
619  const BasicBlock *LLVM_BB = BB->getBasicBlock();
620  DebugLoc DL = MI.getDebugLoc();
622 
623  MachineBasicBlock *HeadMBB = BB;
624  MachineFunction *F = BB->getParent();
625  MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
626  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
627 
628  F->insert(I, IfFalseMBB);
629  F->insert(I, TailMBB);
630  // Move all remaining instructions to TailMBB.
631  TailMBB->splice(TailMBB->begin(), HeadMBB,
632  std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end());
633  // Update machine-CFG edges by transferring all successors of the current
634  // block to the new block which will contain the Phi node for the select.
635  TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
636  // Set the successors for HeadMBB.
637  HeadMBB->addSuccessor(IfFalseMBB);
638  HeadMBB->addSuccessor(TailMBB);
639 
640  // Insert appropriate branch.
641  unsigned LHS = MI.getOperand(1).getReg();
642  unsigned RHS = MI.getOperand(2).getReg();
643  auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
644  unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
645 
646  BuildMI(HeadMBB, DL, TII.get(Opcode))
647  .addReg(LHS)
648  .addReg(RHS)
649  .addMBB(TailMBB);
650 
651  // IfFalseMBB just falls through to TailMBB.
652  IfFalseMBB->addSuccessor(TailMBB);
653 
654  // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
655  BuildMI(*TailMBB, TailMBB->begin(), DL, TII.get(RISCV::PHI),
656  MI.getOperand(0).getReg())
657  .addReg(MI.getOperand(4).getReg())
658  .addMBB(HeadMBB)
659  .addReg(MI.getOperand(5).getReg())
660  .addMBB(IfFalseMBB);
661 
662  MI.eraseFromParent(); // The pseudo instruction is gone now.
663  return TailMBB;
664 }
665 
666 // Calling Convention Implementation.
667 // The expectations for frontend ABI lowering vary from target to target.
668 // Ideally, an LLVM frontend would be able to avoid worrying about many ABI
669 // details, but this is a longer term goal. For now, we simply try to keep the
670 // role of the frontend as simple and well-defined as possible. The rules can
671 // be summarised as:
672 // * Never split up large scalar arguments. We handle them here.
673 // * If a hardfloat calling convention is being used, and the struct may be
674 // passed in a pair of registers (fp+fp, int+fp), and both registers are
675 // available, then pass as two separate arguments. If either the GPRs or FPRs
676 // are exhausted, then pass according to the rule below.
677 // * If a struct could never be passed in registers or directly in a stack
678 // slot (as it is larger than 2*XLEN and the floating point rules don't
679 // apply), then pass it using a pointer with the byval attribute.
680 // * If a struct is less than 2*XLEN, then coerce to either a two-element
681 // word-sized array or a 2*XLEN scalar (depending on alignment).
682 // * The frontend can determine whether a struct is returned by reference or
683 // not based on its size and fields. If it will be returned by reference, the
684 // frontend must modify the prototype so a pointer with the sret annotation is
685 // passed as the first argument. This is not necessary for large scalar
686 // returns.
687 // * Struct return values and varargs should be coerced to structs containing
688 // register-size fields in the same situations they would be for fixed
689 // arguments.
690 
691 static const MCPhysReg ArgGPRs[] = {
692  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
693  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
694 };
695 
696 // Pass a 2*XLEN argument that has been split into two XLEN values through
697 // registers or the stack as necessary.
698 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
699  ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
700  MVT ValVT2, MVT LocVT2,
701  ISD::ArgFlagsTy ArgFlags2) {
702  unsigned XLenInBytes = XLen / 8;
703  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
704  // At least one half can be passed via register.
705  State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
706  VA1.getLocVT(), CCValAssign::Full));
707  } else {
708  // Both halves must be passed on the stack, with proper alignment.
709  unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
710  State.addLoc(
712  State.AllocateStack(XLenInBytes, StackAlign),
713  VA1.getLocVT(), CCValAssign::Full));
715  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
717  return false;
718  }
719 
720  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
721  // The second half can also be passed via register.
722  State.addLoc(
723  CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
724  } else {
725  // The second half is passed via the stack, without additional alignment.
727  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
729  }
730 
731  return false;
732 }
733 
734 // Implements the RISC-V calling convention. Returns true upon failure.
735 static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
736  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
737  CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
738  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
739  assert(XLen == 32 || XLen == 64);
740  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
741  if (ValVT == MVT::f32) {
742  LocVT = MVT::i32;
743  LocInfo = CCValAssign::BCvt;
744  }
745 
746  // Any return value split in to more than two values can't be returned
747  // directly.
748  if (IsRet && ValNo > 1)
749  return true;
750 
751  // If this is a variadic argument, the RISC-V calling convention requires
752  // that it is assigned an 'even' or 'aligned' register if it has 8-byte
753  // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
754  // be used regardless of whether the original argument was split during
755  // legalisation or not. The argument will not be passed by registers if the
756  // original type is larger than 2*XLEN, so the register alignment rule does
757  // not apply.
758  unsigned TwoXLenInBytes = (2 * XLen) / 8;
759  if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
760  DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
761  unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
762  // Skip 'odd' register if necessary.
763  if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
764  State.AllocateReg(ArgGPRs);
765  }
766 
767  SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
768  SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
769  State.getPendingArgFlags();
770 
771  assert(PendingLocs.size() == PendingArgFlags.size() &&
772  "PendingLocs and PendingArgFlags out of sync");
773 
774  // Handle passing f64 on RV32D with a soft float ABI.
775  if (XLen == 32 && ValVT == MVT::f64) {
776  assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
777  "Can't lower f64 if it is split");
778  // Depending on available argument GPRS, f64 may be passed in a pair of
779  // GPRs, split between a GPR and the stack, or passed completely on the
780  // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
781  // cases.
782  unsigned Reg = State.AllocateReg(ArgGPRs);
783  LocVT = MVT::i32;
784  if (!Reg) {
785  unsigned StackOffset = State.AllocateStack(8, 8);
786  State.addLoc(
787  CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
788  return false;
789  }
790  if (!State.AllocateReg(ArgGPRs))
791  State.AllocateStack(4, 4);
792  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
793  return false;
794  }
795 
796  // Split arguments might be passed indirectly, so keep track of the pending
797  // values.
798  if (ArgFlags.isSplit() || !PendingLocs.empty()) {
799  LocVT = XLenVT;
800  LocInfo = CCValAssign::Indirect;
801  PendingLocs.push_back(
802  CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
803  PendingArgFlags.push_back(ArgFlags);
804  if (!ArgFlags.isSplitEnd()) {
805  return false;
806  }
807  }
808 
809  // If the split argument only had two elements, it should be passed directly
810  // in registers or on the stack.
811  if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
812  assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
813  // Apply the normal calling convention rules to the first half of the
814  // split argument.
815  CCValAssign VA = PendingLocs[0];
816  ISD::ArgFlagsTy AF = PendingArgFlags[0];
817  PendingLocs.clear();
818  PendingArgFlags.clear();
819  return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
820  ArgFlags);
821  }
822 
823  // Allocate to a register if possible, or else a stack slot.
824  unsigned Reg = State.AllocateReg(ArgGPRs);
825  unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
826 
827  // If we reach this point and PendingLocs is non-empty, we must be at the
828  // end of a split argument that must be passed indirectly.
829  if (!PendingLocs.empty()) {
830  assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
831  assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
832 
833  for (auto &It : PendingLocs) {
834  if (Reg)
835  It.convertToReg(Reg);
836  else
837  It.convertToMem(StackOffset);
838  State.addLoc(It);
839  }
840  PendingLocs.clear();
841  PendingArgFlags.clear();
842  return false;
843  }
844 
845  assert(LocVT == XLenVT && "Expected an XLenVT at this stage");
846 
847  if (Reg) {
848  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
849  return false;
850  }
851 
852  if (ValVT == MVT::f32) {
853  LocVT = MVT::f32;
854  LocInfo = CCValAssign::Full;
855  }
856  State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
857  return false;
858 }
859 
860 void RISCVTargetLowering::analyzeInputArgs(
861  MachineFunction &MF, CCState &CCInfo,
862  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
863  unsigned NumArgs = Ins.size();
864  FunctionType *FType = MF.getFunction().getFunctionType();
865 
866  for (unsigned i = 0; i != NumArgs; ++i) {
867  MVT ArgVT = Ins[i].VT;
868  ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
869 
870  Type *ArgTy = nullptr;
871  if (IsRet)
872  ArgTy = FType->getReturnType();
873  else if (Ins[i].isOrigArg())
874  ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
875 
876  if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
877  ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
878  LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
879  << EVT(ArgVT).getEVTString() << '\n');
880  llvm_unreachable(nullptr);
881  }
882  }
883 }
884 
885 void RISCVTargetLowering::analyzeOutputArgs(
886  MachineFunction &MF, CCState &CCInfo,
887  const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
888  CallLoweringInfo *CLI) const {
889  unsigned NumArgs = Outs.size();
890 
891  for (unsigned i = 0; i != NumArgs; i++) {
892  MVT ArgVT = Outs[i].VT;
893  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
894  Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
895 
896  if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full,
897  ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
898  LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
899  << EVT(ArgVT).getEVTString() << "\n");
900  llvm_unreachable(nullptr);
901  }
902  }
903 }
904 
905 // Convert Val to a ValVT. Should not be called for CCValAssign::Indirect
906 // values.
908  const CCValAssign &VA, const SDLoc &DL) {
909  switch (VA.getLocInfo()) {
910  default:
911  llvm_unreachable("Unexpected CCValAssign::LocInfo");
912  case CCValAssign::Full:
913  break;
914  case CCValAssign::BCvt:
915  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
916  break;
917  }
918  return Val;
919 }
920 
921 // The caller is responsible for loading the full value if the argument is
922 // passed with CCValAssign::Indirect.
924  const CCValAssign &VA, const SDLoc &DL) {
926  MachineRegisterInfo &RegInfo = MF.getRegInfo();
927  EVT LocVT = VA.getLocVT();
928  SDValue Val;
929 
930  unsigned VReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
931  RegInfo.addLiveIn(VA.getLocReg(), VReg);
932  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
933 
934  if (VA.getLocInfo() == CCValAssign::Indirect)
935  return Val;
936 
937  return convertLocVTToValVT(DAG, Val, VA, DL);
938 }
939 
941  const CCValAssign &VA, const SDLoc &DL) {
942  EVT LocVT = VA.getLocVT();
943 
944  switch (VA.getLocInfo()) {
945  default:
946  llvm_unreachable("Unexpected CCValAssign::LocInfo");
947  case CCValAssign::Full:
948  break;
949  case CCValAssign::BCvt:
950  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
951  break;
952  }
953  return Val;
954 }
955 
956 // The caller is responsible for loading the full value if the argument is
957 // passed with CCValAssign::Indirect.
959  const CCValAssign &VA, const SDLoc &DL) {
961  MachineFrameInfo &MFI = MF.getFrameInfo();
962  EVT LocVT = VA.getLocVT();
963  EVT ValVT = VA.getValVT();
965  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
966  VA.getLocMemOffset(), /*Immutable=*/true);
967  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
968  SDValue Val;
969 
971  switch (VA.getLocInfo()) {
972  default:
973  llvm_unreachable("Unexpected CCValAssign::LocInfo");
974  case CCValAssign::Full:
976  ExtType = ISD::NON_EXTLOAD;
977  break;
978  }
979  Val = DAG.getExtLoad(
980  ExtType, DL, LocVT, Chain, FIN,
982  return Val;
983 }
984 
986  const CCValAssign &VA, const SDLoc &DL) {
987  assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
988  "Unexpected VA");
990  MachineFrameInfo &MFI = MF.getFrameInfo();
991  MachineRegisterInfo &RegInfo = MF.getRegInfo();
992 
993  if (VA.isMemLoc()) {
994  // f64 is passed on the stack.
995  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
996  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
997  return DAG.getLoad(MVT::f64, DL, Chain, FIN,
999  }
1000 
1001  assert(VA.isRegLoc() && "Expected register VA assignment");
1002 
1003  unsigned LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1004  RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
1005  SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
1006  SDValue Hi;
1007  if (VA.getLocReg() == RISCV::X17) {
1008  // Second half of f64 is passed on the stack.
1009  int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
1010  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1011  Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
1013  } else {
1014  // Second half of f64 is passed in another GPR.
1015  unsigned HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1016  RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
1017  Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
1018  }
1019  return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1020 }
1021 
1022 // Transform physical registers into virtual registers.
1023 SDValue RISCVTargetLowering::LowerFormalArguments(
1024  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1025  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1026  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1027 
1028  switch (CallConv) {
1029  default:
1030  report_fatal_error("Unsupported calling convention");
1031  case CallingConv::C:
1032  case CallingConv::Fast:
1033  break;
1034  }
1035 
1036  MachineFunction &MF = DAG.getMachineFunction();
1037 
1038  const Function &Func = MF.getFunction();
1039  if (Func.hasFnAttribute("interrupt")) {
1040  if (!Func.arg_empty())
1042  "Functions with the interrupt attribute cannot have arguments!");
1043 
1044  StringRef Kind =
1045  MF.getFunction().getFnAttribute("interrupt").getValueAsString();
1046 
1047  if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
1049  "Function interrupt attribute argument not supported!");
1050  }
1051 
1052  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1053  MVT XLenVT = Subtarget.getXLenVT();
1054  unsigned XLenInBytes = Subtarget.getXLen() / 8;
1055  // Used with vargs to acumulate store chains.
1056  std::vector<SDValue> OutChains;
1057 
1058  // Assign locations to all of the incoming arguments.
1060  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1061  analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
1062 
1063  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1064  CCValAssign &VA = ArgLocs[i];
1065  SDValue ArgValue;
1066  // Passing f64 on RV32D with a soft float ABI must be handled as a special
1067  // case.
1068  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
1069  ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
1070  else if (VA.isRegLoc())
1071  ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);
1072  else
1073  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
1074 
1075  if (VA.getLocInfo() == CCValAssign::Indirect) {
1076  // If the original argument was split and passed by reference (e.g. i128
1077  // on RV32), we need to load all parts of it here (using the same
1078  // address).
1079  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1080  MachinePointerInfo()));
1081  unsigned ArgIndex = Ins[i].OrigArgIndex;
1082  assert(Ins[i].PartOffset == 0);
1083  while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1084  CCValAssign &PartVA = ArgLocs[i + 1];
1085  unsigned PartOffset = Ins[i + 1].PartOffset;
1086  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1087  DAG.getIntPtrConstant(PartOffset, DL));
1088  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1089  MachinePointerInfo()));
1090  ++i;
1091  }
1092  continue;
1093  }
1094  InVals.push_back(ArgValue);
1095  }
1096 
1097  if (IsVarArg) {
1099  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
1100  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1101  MachineFrameInfo &MFI = MF.getFrameInfo();
1102  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1104 
1105  // Offset of the first variable argument from stack pointer, and size of
1106  // the vararg save area. For now, the varargs save area is either zero or
1107  // large enough to hold a0-a7.
1108  int VaArgOffset, VarArgsSaveSize;
1109 
1110  // If all registers are allocated, then all varargs must be passed on the
1111  // stack and we don't need to save any argregs.
1112  if (ArgRegs.size() == Idx) {
1113  VaArgOffset = CCInfo.getNextStackOffset();
1114  VarArgsSaveSize = 0;
1115  } else {
1116  VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
1117  VaArgOffset = -VarArgsSaveSize;
1118  }
1119 
1120  // Record the frame index of the first variable argument
1121  // which is a value necessary to VASTART.
1122  int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1123  RVFI->setVarArgsFrameIndex(FI);
1124 
1125  // If saving an odd number of registers then create an extra stack slot to
1126  // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
1127  // offsets to even-numbered registered remain 2*XLEN-aligned.
1128  if (Idx % 2) {
1129  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes,
1130  true);
1131  VarArgsSaveSize += XLenInBytes;
1132  }
1133 
1134  // Copy the integer registers that may have been used for passing varargs
1135  // to the vararg save area.
1136  for (unsigned I = Idx; I < ArgRegs.size();
1137  ++I, VaArgOffset += XLenInBytes) {
1138  const unsigned Reg = RegInfo.createVirtualRegister(RC);
1139  RegInfo.addLiveIn(ArgRegs[I], Reg);
1140  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
1141  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1142  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1143  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
1145  cast<StoreSDNode>(Store.getNode())
1146  ->getMemOperand()
1147  ->setValue((Value *)nullptr);
1148  OutChains.push_back(Store);
1149  }
1150  RVFI->setVarArgsSaveSize(VarArgsSaveSize);
1151  }
1152 
1153  // All stores are grouped in one node to allow the matching between
1154  // the size of Ins and InVals. This only happens for vararg functions.
1155  if (!OutChains.empty()) {
1156  OutChains.push_back(Chain);
1157  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1158  }
1159 
1160  return Chain;
1161 }
1162 
1163 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1164 /// for tail call optimization.
1165 /// Note: This is modelled after ARM's IsEligibleForTailCallOptimization.
1166 bool RISCVTargetLowering::IsEligibleForTailCallOptimization(
1167  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
1168  const SmallVector<CCValAssign, 16> &ArgLocs) const {
1169 
1170  auto &Callee = CLI.Callee;
1171  auto CalleeCC = CLI.CallConv;
1172  auto IsVarArg = CLI.IsVarArg;
1173  auto &Outs = CLI.Outs;
1174  auto &Caller = MF.getFunction();
1175  auto CallerCC = Caller.getCallingConv();
1176 
1177  // Do not tail call opt functions with "disable-tail-calls" attribute.
1178  if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
1179  return false;
1180 
1181  // Exception-handling functions need a special set of instructions to
1182  // indicate a return to the hardware. Tail-calling another function would
1183  // probably break this.
1184  // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
1185  // should be expanded as new function attributes are introduced.
1186  if (Caller.hasFnAttribute("interrupt"))
1187  return false;
1188 
1189  // Do not tail call opt functions with varargs.
1190  if (IsVarArg)
1191  return false;
1192 
1193  // Do not tail call opt if the stack is used to pass parameters.
1194  if (CCInfo.getNextStackOffset() != 0)
1195  return false;
1196 
1197  // Do not tail call opt if any parameters need to be passed indirectly.
1198  // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
1199  // passed indirectly. So the address of the value will be passed in a
1200  // register, or if not available, then the address is put on the stack. In
1201  // order to pass indirectly, space on the stack often needs to be allocated
1202  // in order to store the value. In this case the CCInfo.getNextStackOffset()
1203  // != 0 check is not enough and we need to check if any CCValAssign ArgsLocs
1204  // are passed CCValAssign::Indirect.
1205  for (auto &VA : ArgLocs)
1206  if (VA.getLocInfo() == CCValAssign::Indirect)
1207  return false;
1208 
1209  // Do not tail call opt if either caller or callee uses struct return
1210  // semantics.
1211  auto IsCallerStructRet = Caller.hasStructRetAttr();
1212  auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
1213  if (IsCallerStructRet || IsCalleeStructRet)
1214  return false;
1215 
1216  // Externally-defined functions with weak linkage should not be
1217  // tail-called. The behaviour of branch instructions in this situation (as
1218  // used for tail calls) is implementation-defined, so we cannot rely on the
1219  // linker replacing the tail call with a return.
1220  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1221  const GlobalValue *GV = G->getGlobal();
1222  if (GV->hasExternalWeakLinkage())
1223  return false;
1224  }
1225 
1226  // The callee has to preserve all registers the caller needs to preserve.
1227  const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
1228  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1229  if (CalleeCC != CallerCC) {
1230  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1231  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1232  return false;
1233  }
1234 
1235  // Byval parameters hand the function a pointer directly into the stack area
1236  // we want to reuse during a tail call. Working around this *is* possible
1237  // but less efficient and uglier in LowerCall.
1238  for (auto &Arg : Outs)
1239  if (Arg.Flags.isByVal())
1240  return false;
1241 
1242  return true;
1243 }
1244 
1245 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
1246 // and output parameter nodes.
1247 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
1248  SmallVectorImpl<SDValue> &InVals) const {
1249  SelectionDAG &DAG = CLI.DAG;
1250  SDLoc &DL = CLI.DL;
1251  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1252  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1253  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1254  SDValue Chain = CLI.Chain;
1255  SDValue Callee = CLI.Callee;
1256  bool &IsTailCall = CLI.IsTailCall;
1257  CallingConv::ID CallConv = CLI.CallConv;
1258  bool IsVarArg = CLI.IsVarArg;
1259  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1260  MVT XLenVT = Subtarget.getXLenVT();
1261 
1262  MachineFunction &MF = DAG.getMachineFunction();
1263 
1264  // Analyze the operands of the call, assigning locations to each operand.
1266  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1267  analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
1268 
1269  // Check if it's really possible to do a tail call.
1270  if (IsTailCall)
1271  IsTailCall = IsEligibleForTailCallOptimization(ArgCCInfo, CLI, MF,
1272  ArgLocs);
1273 
1274  if (IsTailCall)
1275  ++NumTailCalls;
1276  else if (CLI.CS && CLI.CS.isMustTailCall())
1277  report_fatal_error("failed to perform tail call elimination on a call "
1278  "site marked musttail");
1279 
1280  // Get a count of how many bytes are to be pushed on the stack.
1281  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1282 
1283  // Create local copies for byval args
1284  SmallVector<SDValue, 8> ByValArgs;
1285  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1286  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1287  if (!Flags.isByVal())
1288  continue;
1289 
1290  SDValue Arg = OutVals[i];
1291  unsigned Size = Flags.getByValSize();
1292  unsigned Align = Flags.getByValAlign();
1293 
1294  int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false);
1295  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1296  SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
1297 
1298  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
1299  /*IsVolatile=*/false,
1300  /*AlwaysInline=*/false,
1301  IsTailCall, MachinePointerInfo(),
1302  MachinePointerInfo());
1303  ByValArgs.push_back(FIPtr);
1304  }
1305 
1306  if (!IsTailCall)
1307  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
1308 
1309  // Copy argument values to their designated locations.
1311  SmallVector<SDValue, 8> MemOpChains;
1312  SDValue StackPtr;
1313  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
1314  CCValAssign &VA = ArgLocs[i];
1315  SDValue ArgValue = OutVals[i];
1316  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1317 
1318  // Handle passing f64 on RV32D with a soft float ABI as a special case.
1319  bool IsF64OnRV32DSoftABI =
1320  VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
1321  if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
1322  SDValue SplitF64 = DAG.getNode(
1323  RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
1324  SDValue Lo = SplitF64.getValue(0);
1325  SDValue Hi = SplitF64.getValue(1);
1326 
1327  unsigned RegLo = VA.getLocReg();
1328  RegsToPass.push_back(std::make_pair(RegLo, Lo));
1329 
1330  if (RegLo == RISCV::X17) {
1331  // Second half of f64 is passed on the stack.
1332  // Work out the address of the stack slot.
1333  if (!StackPtr.getNode())
1334  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1335  // Emit the store.
1336  MemOpChains.push_back(
1337  DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
1338  } else {
1339  // Second half of f64 is passed in another GPR.
1340  unsigned RegHigh = RegLo + 1;
1341  RegsToPass.push_back(std::make_pair(RegHigh, Hi));
1342  }
1343  continue;
1344  }
1345 
1346  // IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way
1347  // as any other MemLoc.
1348 
1349  // Promote the value if needed.
1350  // For now, only handle fully promoted and indirect arguments.
1351  if (VA.getLocInfo() == CCValAssign::Indirect) {
1352  // Store the argument in a stack slot and pass its address.
1353  SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT);
1354  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1355  MemOpChains.push_back(
1356  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1358  // If the original argument was split (e.g. i128), we need
1359  // to store all parts of it here (and pass just one address).
1360  unsigned ArgIndex = Outs[i].OrigArgIndex;
1361  assert(Outs[i].PartOffset == 0);
1362  while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
1363  SDValue PartValue = OutVals[i + 1];
1364  unsigned PartOffset = Outs[i + 1].PartOffset;
1365  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1366  DAG.getIntPtrConstant(PartOffset, DL));
1367  MemOpChains.push_back(
1368  DAG.getStore(Chain, DL, PartValue, Address,
1370  ++i;
1371  }
1372  ArgValue = SpillSlot;
1373  } else {
1374  ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
1375  }
1376 
1377  // Use local copy if it is a byval arg.
1378  if (Flags.isByVal())
1379  ArgValue = ByValArgs[j++];
1380 
1381  if (VA.isRegLoc()) {
1382  // Queue up the argument copies and emit them at the end.
1383  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1384  } else {
1385  assert(VA.isMemLoc() && "Argument not register or memory");
1386  assert(!IsTailCall && "Tail call not allowed if stack is used "
1387  "for passing parameters");
1388 
1389  // Work out the address of the stack slot.
1390  if (!StackPtr.getNode())
1391  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1392  SDValue Address =
1393  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1394  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
1395 
1396  // Emit the store.
1397  MemOpChains.push_back(
1398  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1399  }
1400  }
1401 
1402  // Join the stores, which are independent of one another.
1403  if (!MemOpChains.empty())
1404  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1405 
1406  SDValue Glue;
1407 
1408  // Build a sequence of copy-to-reg nodes, chained and glued together.
1409  for (auto &Reg : RegsToPass) {
1410  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
1411  Glue = Chain.getValue(1);
1412  }
1413 
1414  // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
1415  // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
1416  // split it and then direct call can be matched by PseudoCALL.
1417  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
1418  Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0);
1419  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1420  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0);
1421  }
1422 
1423  // The first call operand is the chain and the second is the target address.
1425  Ops.push_back(Chain);
1426  Ops.push_back(Callee);
1427 
1428  // Add argument registers to the end of the list so that they are
1429  // known live into the call.
1430  for (auto &Reg : RegsToPass)
1431  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1432 
1433  if (!IsTailCall) {
1434  // Add a register mask operand representing the call-preserved registers.
1435  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1436  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1437  assert(Mask && "Missing call preserved mask for calling convention");
1438  Ops.push_back(DAG.getRegisterMask(Mask));
1439  }
1440 
1441  // Glue the call to the argument copies, if any.
1442  if (Glue.getNode())
1443  Ops.push_back(Glue);
1444 
1445  // Emit the call.
1446  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1447 
1448  if (IsTailCall) {
1450  return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
1451  }
1452 
1453  Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
1454  Glue = Chain.getValue(1);
1455 
1456  // Mark the end of the call, which is glued to the call itself.
1457  Chain = DAG.getCALLSEQ_END(Chain,
1458  DAG.getConstant(NumBytes, DL, PtrVT, true),
1459  DAG.getConstant(0, DL, PtrVT, true),
1460  Glue, DL);
1461  Glue = Chain.getValue(1);
1462 
1463  // Assign locations to each value returned by this call.
1465  CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
1466  analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true);
1467 
1468  // Copy all of the result registers out of their specified physreg.
1469  for (auto &VA : RVLocs) {
1470  // Copy the value out
1471  SDValue RetValue =
1472  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
1473  // Glue the RetValue to the end of the call sequence
1474  Chain = RetValue.getValue(1);
1475  Glue = RetValue.getValue(2);
1476 
1477  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
1478  assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment");
1479  SDValue RetValue2 =
1480  DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue);
1481  Chain = RetValue2.getValue(1);
1482  Glue = RetValue2.getValue(2);
1483  RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
1484  RetValue2);
1485  }
1486 
1487  RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
1488 
1489  InVals.push_back(RetValue);
1490  }
1491 
1492  return Chain;
1493 }
1494 
1495 bool RISCVTargetLowering::CanLowerReturn(
1496  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
1497  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1499  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
1500  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1501  MVT VT = Outs[i].VT;
1502  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
1503  if (CC_RISCV(MF.getDataLayout(), i, VT, VT, CCValAssign::Full, ArgFlags,
1504  CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
1505  return false;
1506  }
1507  return true;
1508 }
1509 
1510 SDValue
1511 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1512  bool IsVarArg,
1513  const SmallVectorImpl<ISD::OutputArg> &Outs,
1514  const SmallVectorImpl<SDValue> &OutVals,
1515  const SDLoc &DL, SelectionDAG &DAG) const {
1516  // Stores the assignment of the return value to a location.
1518 
1519  // Info about the registers and stack slot.
1520  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
1521  *DAG.getContext());
1522 
1523  analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
1524  nullptr);
1525 
1526  SDValue Glue;
1527  SmallVector<SDValue, 4> RetOps(1, Chain);
1528 
1529  // Copy the result values into the output registers.
1530  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
1531  SDValue Val = OutVals[i];
1532  CCValAssign &VA = RVLocs[i];
1533  assert(VA.isRegLoc() && "Can only return in registers!");
1534 
1535  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
1536  // Handle returning f64 on RV32D with a soft float ABI.
1537  assert(VA.isRegLoc() && "Expected return via registers");
1539  DAG.getVTList(MVT::i32, MVT::i32), Val);
1540  SDValue Lo = SplitF64.getValue(0);
1541  SDValue Hi = SplitF64.getValue(1);
1542  unsigned RegLo = VA.getLocReg();
1543  unsigned RegHi = RegLo + 1;
1544  Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
1545  Glue = Chain.getValue(1);
1546  RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
1547  Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
1548  Glue = Chain.getValue(1);
1549  RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
1550  } else {
1551  // Handle a 'normal' return.
1552  Val = convertValVTToLocVT(DAG, Val, VA, DL);
1553  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
1554 
1555  // Guarantee that all emitted copies are stuck together.
1556  Glue = Chain.getValue(1);
1557  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1558  }
1559  }
1560 
1561  RetOps[0] = Chain; // Update chain.
1562 
1563  // Add the glue node if we have it.
1564  if (Glue.getNode()) {
1565  RetOps.push_back(Glue);
1566  }
1567 
1568  // Interrupt service routines use different return instructions.
1569  const Function &Func = DAG.getMachineFunction().getFunction();
1570  if (Func.hasFnAttribute("interrupt")) {
1571  if (!Func.getReturnType()->isVoidTy())
1573  "Functions with the interrupt attribute must have void return type!");
1574 
1575  MachineFunction &MF = DAG.getMachineFunction();
1576  StringRef Kind =
1577  MF.getFunction().getFnAttribute("interrupt").getValueAsString();
1578 
1579  unsigned RetOpc;
1580  if (Kind == "user")
1581  RetOpc = RISCVISD::URET_FLAG;
1582  else if (Kind == "supervisor")
1583  RetOpc = RISCVISD::SRET_FLAG;
1584  else
1585  RetOpc = RISCVISD::MRET_FLAG;
1586 
1587  return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
1588  }
1589 
1590  return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
1591 }
1592 
1593 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
1594  switch ((RISCVISD::NodeType)Opcode) {
1596  break;
1597  case RISCVISD::RET_FLAG:
1598  return "RISCVISD::RET_FLAG";
1599  case RISCVISD::URET_FLAG:
1600  return "RISCVISD::URET_FLAG";
1601  case RISCVISD::SRET_FLAG:
1602  return "RISCVISD::SRET_FLAG";
1603  case RISCVISD::MRET_FLAG:
1604  return "RISCVISD::MRET_FLAG";
1605  case RISCVISD::CALL:
1606  return "RISCVISD::CALL";
1607  case RISCVISD::SELECT_CC:
1608  return "RISCVISD::SELECT_CC";
1610  return "RISCVISD::BuildPairF64";
1611  case RISCVISD::SplitF64:
1612  return "RISCVISD::SplitF64";
1613  case RISCVISD::TAIL:
1614  return "RISCVISD::TAIL";
1615  }
1616  return nullptr;
1617 }
1618 
1619 std::pair<unsigned, const TargetRegisterClass *>
1621  StringRef Constraint,
1622  MVT VT) const {
1623  // First, see if this is a constraint that directly corresponds to a
1624  // RISCV register class.
1625  if (Constraint.size() == 1) {
1626  switch (Constraint[0]) {
1627  case 'r':
1628  return std::make_pair(0U, &RISCV::GPRRegClass);
1629  default:
1630  break;
1631  }
1632  }
1633 
1634  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1635 }
1636 
1638  Instruction *Inst,
1639  AtomicOrdering Ord) const {
1640  if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
1641  return Builder.CreateFence(Ord);
1642  if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
1643  return Builder.CreateFence(AtomicOrdering::Release);
1644  return nullptr;
1645 }
1646 
1648  Instruction *Inst,
1649  AtomicOrdering Ord) const {
1650  if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
1651  return Builder.CreateFence(AtomicOrdering::Acquire);
1652  return nullptr;
1653 }
1654 
1656 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1657  unsigned Size = AI->getType()->getPrimitiveSizeInBits();
1658  if (Size == 8 || Size == 16)
1661 }
1662 
1663 static Intrinsic::ID
1665  switch (BinOp) {
1666  default:
1667  llvm_unreachable("Unexpected AtomicRMW BinOp");
1668  case AtomicRMWInst::Xchg:
1669  return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
1670  case AtomicRMWInst::Add:
1671  return Intrinsic::riscv_masked_atomicrmw_add_i32;
1672  case AtomicRMWInst::Sub:
1673  return Intrinsic::riscv_masked_atomicrmw_sub_i32;
1674  case AtomicRMWInst::Nand:
1675  return Intrinsic::riscv_masked_atomicrmw_nand_i32;
1676  case AtomicRMWInst::Max:
1677  return Intrinsic::riscv_masked_atomicrmw_max_i32;
1678  case AtomicRMWInst::Min:
1679  return Intrinsic::riscv_masked_atomicrmw_min_i32;
1680  case AtomicRMWInst::UMax:
1681  return Intrinsic::riscv_masked_atomicrmw_umax_i32;
1682  case AtomicRMWInst::UMin:
1683  return Intrinsic::riscv_masked_atomicrmw_umin_i32;
1684  }
1685 }
1686 
1687 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
1688  IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
1689  Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
1690  Value *Ordering = Builder.getInt32(static_cast<uint32_t>(AI->getOrdering()));
1691  Type *Tys[] = {AlignedAddr->getType()};
1692  Function *LrwOpScwLoop = Intrinsic::getDeclaration(
1693  AI->getModule(),
1695 
1696  // Must pass the shift amount needed to sign extend the loaded value prior
1697  // to performing a signed comparison for min/max. ShiftAmt is the number of
1698  // bits to shift the value into position. Pass XLen-ShiftAmt-ValWidth, which
1699  // is the number of bits to left+right shift the value in order to
1700  // sign-extend.
1701  if (AI->getOperation() == AtomicRMWInst::Min ||
1702  AI->getOperation() == AtomicRMWInst::Max) {
1703  const DataLayout &DL = AI->getModule()->getDataLayout();
1704  unsigned ValWidth =
1706  Value *SextShamt = Builder.CreateSub(
1707  Builder.getInt32(Subtarget.getXLen() - ValWidth), ShiftAmt);
1708  return Builder.CreateCall(LrwOpScwLoop,
1709  {AlignedAddr, Incr, Mask, SextShamt, Ordering});
1710  }
1711 
1712  return Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
1713 }
1714 
1716 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
1717  AtomicCmpXchgInst *CI) const {
1718  unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
1719  if (Size == 8 || Size == 16)
1722 }
1723 
1724 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
1725  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1726  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1727  Value *Ordering = Builder.getInt32(static_cast<uint32_t>(Ord));
1728  Type *Tys[] = {AlignedAddr->getType()};
1729  Function *MaskedCmpXchg = Intrinsic::getDeclaration(
1730  CI->getModule(), Intrinsic::riscv_masked_cmpxchg_i32, Tys);
1731  return Builder.CreateCall(MaskedCmpXchg,
1732  {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
1733 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:571
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
uint64_t getTypeStoreSizeInBits(Type *Ty) const
Returns the maximum number of bits that may be overwritten by storing the specified type; always a mu...
Definition: DataLayout.h:419
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:594
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
const GlobalValue * getGlobal() const
*p = old <signed v ? old : v
Definition: Instructions.h:711
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:833
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:650
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:135
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:699
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const RISCVRegisterInfo * getRegisterInfo() const override
*p = old <unsigned v ? old : v
Definition: Instructions.h:715
*p = old >unsigned v ? old : v
Definition: Instructions.h:713
unsigned getValNo() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:321
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:437
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
*p = old >signed v ? old : v
Definition: Instructions.h:709
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:435
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
bool isMemLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1079
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:456
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:840
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:365
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:451
unsigned getXLen() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
BinOp getOperation() const
Definition: Instructions.h:734
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:743
static MachineBasicBlock * emitSplitF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:398
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
const BlockAddress * getBlockAddress() const
LocInfo getLocInfo() const
static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:695
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
BinOp
This enumeration lists the possible modifications atomicrmw can make.
Definition: Instructions.h:693
bool arg_empty() const
Definition: Function.h:699
SmallVectorImpl< CCValAssign > & getPendingLocs()
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool hasStdExtA() const
static MachineBasicBlock * emitBuildPairF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
Value * CreateSub(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:991
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
virtual const TargetInstrInfo * getInstrInfo() const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
amdgpu Simplify well known AMD library false Value * Callee
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1021
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Class to represent pointers.
Definition: DerivedTypes.h:467
unsigned getByValSize() const
unsigned getKillRegState(bool B)
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
TargetInstrInfo - Interface to description of machine instruction set.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:169
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
unsigned getOrigAlign() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool hasStdExtF() const
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:728
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:934
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:821
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
bool hasStdExtM() const
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
Definition: DataLayout.cpp:764
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:281
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:719
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
size_t size() const
Definition: SmallVector.h:53
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
Definition: Instructions.h:763
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
The memory access writes data.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReleaseOrStronger(AtomicOrdering ao)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:636
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
Value * getValOperand()
Definition: Instructions.h:789
static const MCPhysReg ArgGPRs[]
bool hasStdExtD() const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1038
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:96
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:413
Type * getReturnType() const
Definition: DerivedTypes.h:124
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:307
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:676
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:164
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:56
unsigned getByValAlign() const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:420
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
bool is64Bit() const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:638
Representation of each machine instruction.
Definition: MachineInstr.h:64
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:724
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:670
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1365
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:702
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:486
static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
uint32_t Size
Definition: Profile.cpp:47
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp32(AtomicRMWInst::BinOp BinOp)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:608
SDValue getValue(unsigned R) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
const unsigned Kind
bool hasStdExtC() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:443
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
#define LLVM_DEBUG(X)
Definition: Debug.h:123
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Function Alias Analysis false
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
Type * getElementType() const
Definition: DerivedTypes.h:486
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:619
CallInst * CreateCall(Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:1883
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:380
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:623