LLVM  10.0.0svn
RISCVInstrInfo.h
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1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
15 
16 #include "RISCVRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "RISCVGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class RISCVSubtarget;
25 
27 
28 public:
30 
31  unsigned isLoadFromStackSlot(const MachineInstr &MI,
32  int &FrameIndex) const override;
33  unsigned isStoreToStackSlot(const MachineInstr &MI,
34  int &FrameIndex) const override;
35 
37  const DebugLoc &DL, unsigned DstReg, unsigned SrcReg,
38  bool KillSrc) const override;
39 
41  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
42  bool IsKill, int FrameIndex,
43  const TargetRegisterClass *RC,
44  const TargetRegisterInfo *TRI) const override;
45 
47  MachineBasicBlock::iterator MBBI, unsigned DstReg,
48  int FrameIndex, const TargetRegisterClass *RC,
49  const TargetRegisterInfo *TRI) const override;
50 
51  // Materializes the given integer Val into DstReg.
53  const DebugLoc &DL, Register DstReg, uint64_t Val,
55 
56  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
57 
59  MachineBasicBlock *&FBB,
61  bool AllowModify) const override;
62 
65  const DebugLoc &dl,
66  int *BytesAdded = nullptr) const override;
67 
69  MachineBasicBlock &NewDestBB,
70  const DebugLoc &DL, int64_t BrOffset,
71  RegScavenger *RS = nullptr) const override;
72 
73  unsigned removeBranch(MachineBasicBlock &MBB,
74  int *BytesRemoved = nullptr) const override;
75 
76  bool
78 
79  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
80 
81  bool isBranchOffsetInRange(unsigned BranchOpc,
82  int64_t BrOffset) const override;
83 
84  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
85 
86  bool verifyInstruction(const MachineInstr &MI,
87  StringRef &ErrInfo) const override;
88 
89 protected:
91 };
92 }
93 #endif
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isAsCheapAsAMove(const MachineInstr &MI) const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, bool KillSrc) const override
RISCVInstrInfo(RISCVSubtarget &STI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const RISCVSubtarget & STI
Representation of each machine instruction.
Definition: MachineInstr.h:64
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Wrapper class representing virtual and physical registers.
Definition: Register.h:19