24#define DEBUG_TYPE "riscv-merge-base-offset"
25#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
51 MachineFunctionProperties::Property::IsSSA);
65char RISCVMergeBaseOffsetOpt::ID = 0;
87 if (
Hi.getOpcode() != RISCV::LUI &&
Hi.getOpcode() != RISCV::AUIPC)
91 unsigned ExpectedFlags =
100 Register HiDestReg =
Hi.getOperand(0).getReg();
101 if (!
MRI->hasOneUse(HiDestReg))
104 Lo = &*
MRI->use_instr_begin(HiDestReg);
105 if (
Lo->getOpcode() != RISCV::ADDI)
109 if (
Hi.getOpcode() == RISCV::LUI) {
115 assert(
Hi.getOpcode() == RISCV::AUIPC);
127 }
else if (HiOp1.
isCPI()) {
143 if (
Hi.getOpcode() != RISCV::AUIPC)
146 MRI->constrainRegClass(
Lo.getOperand(0).getReg(),
147 MRI->getRegClass(
Tail.getOperand(0).getReg()));
148 MRI->replaceRegWith(
Tail.getOperand(0).getReg(),
Lo.getOperand(0).getReg());
149 Tail.eraseFromParent();
151 <<
" " <<
Hi <<
" " <<
Lo;);
178 assert((TailAdd.
getOpcode() == RISCV::ADD) &&
"Expected ADD instruction!");
184 if (!
Reg.isVirtual() || !
MRI->hasOneUse(Reg))
188 if (OffsetTail.
getOpcode() == RISCV::ADDI ||
189 OffsetTail.
getOpcode() == RISCV::ADDIW) {
196 int64_t OffLo = AddiImmOp.
getImm();
199 if (AddiReg == RISCV::X0) {
201 foldOffset(
Hi,
Lo, TailAdd, OffLo);
208 if (OffsetLui.
getOpcode() != RISCV::LUI ||
212 int64_t
Offset = SignExtend64<32>(LuiImmOp.
getImm() << 12);
215 if (!
ST->is64Bit() || OffsetTail.
getOpcode() == RISCV::ADDIW)
221 <<
" " << OffsetLui);
226 }
else if (OffsetTail.
getOpcode() == RISCV::LUI) {
254 TailShXAdd.
getOpcode() == RISCV::SH2ADD ||
255 TailShXAdd.
getOpcode() == RISCV::SH3ADD) &&
256 "Expected SHXADD instruction!");
269 if (OffsetTail.
getOpcode() != RISCV::ADDI)
282 case RISCV::SH1ADD: ShAmt = 1;
break;
283 case RISCV::SH2ADD: ShAmt = 2;
break;
284 case RISCV::SH3ADD: ShAmt = 3;
break;
295bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(
MachineInstr &
Hi,
302 if (!
MRI->hasOneUse(DestReg))
307 switch (
Tail.getOpcode()) {
309 LLVM_DEBUG(
dbgs() <<
"Don't know how to get offset from this instr:"
318 if (
MRI->hasOneUse(TailDestReg)) {
320 if (TailTail.
getOpcode() == RISCV::ADDI) {
324 Tail.eraseFromParent();
342 return foldLargeOffset(
Hi,
Lo,
Tail, DestReg);
349 return foldShiftedOffset(
Hi,
Lo,
Tail, DestReg);
371 std::optional<int64_t> CommonOffset;
373 InlineAsmMemoryOpIndexesMap;
375 switch (
UseMI.getOpcode()) {
396 if (
UseMI.getOperand(1).isFI())
402 "Expected base address use");
405 if (CommonOffset &&
Offset != CommonOffset)
410 case RISCV::INLINEASM:
411 case RISCV::INLINEASM_BR: {
415 I <
UseMI.getNumOperands();
I += 1 + NumOps) {
418 if (!FlagsMO.
isImm())
422 NumOps =
Flags.getNumOperandRegisters();
425 if (NumOps != 2 || !
Flags.isMemKind())
430 if (
Flags.getMemoryConstraintID() == InlineAsm::ConstraintCode::A)
438 if (!OffsetMO.
isImm())
443 if (CommonOffset &&
Offset != CommonOffset)
448 InlineAsmMemoryOpIndexesMap.
insert(
449 std::make_pair(&
UseMI, InlineAsmMemoryOpIndexes));
459 int64_t NewOffset =
Hi.getOperand(1).getOffset() + *CommonOffset;
462 NewOffset = SignExtend64<32>(NewOffset);
464 if (!isInt<32>(NewOffset))
467 Hi.getOperand(1).setOffset(NewOffset);
469 if (
Hi.getOpcode() != RISCV::AUIPC)
475 if (
UseMI.getOpcode() == RISCV::INLINEASM ||
476 UseMI.getOpcode() == RISCV::INLINEASM_BR) {
477 auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&
UseMI];
478 for (
unsigned I : InlineAsmMemoryOpIndexes) {
499 UseMI.removeOperand(2);
500 UseMI.addOperand(ImmOp);
504 MRI->replaceRegWith(
Lo.getOperand(0).getReg(),
Hi.getOperand(0).getReg());
505 Lo.eraseFromParent();
509bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(
MachineFunction &Fn) {
515 bool MadeChange =
false;
521 if (!detectFoldable(
Hi,
Lo))
523 MadeChange |= detectAndFoldOffset(
Hi, *
Lo);
524 MadeChange |= foldIntoMemoryOps(
Hi, *
Lo);
533 return new RISCVMergeBaseOffsetOpt();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_MERGE_BASE_OFFSET_NAME
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
support::ulittle16_t & Lo
support::ulittle16_t & Hi
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
FunctionPass class - This class is used to implement most global optimizations.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
const BlockAddress * getBlockAddress() const
void setOffset(int64_t Offset)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.