LLVM  10.0.0svn
RISCVSubtarget.cpp
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1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "riscv-subtarget"
25 
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "RISCVGenSubtargetInfo.inc"
29 
30 void RISCVSubtarget::anchor() {}
31 
32 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
33  const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
34  // Determine default and user-specified characteristics
35  bool Is64Bit = TT.isArch64Bit();
36  std::string CPUName = CPU;
37  if (CPUName.empty())
38  CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
39  ParseSubtargetFeatures(CPUName, FS);
40  if (Is64Bit) {
41  XLenVT = MVT::i64;
42  XLen = 64;
43  }
44 
45  TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
46  RISCVFeatures::validate(TT, getFeatureBits());
47  return *this;
48 }
49 
51  StringRef ABIName, const TargetMachine &TM)
52  : RISCVGenSubtargetInfo(TT, CPU, FS),
53  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
54  InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {
56  Legalizer.reset(new RISCVLegalizerInfo(*this));
57 
58  auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
59  RegBankInfo.reset(RBI);
61  *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
62 }
63 
65  return CallLoweringInfo.get();
66 }
67 
69  return InstSelector.get();
70 }
71 
73  return Legalizer.get();
74 }
75 
77  return RegBankInfo.get();
78 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const RegisterBankInfo * getRegBankInfo() const override
const RISCVRegisterInfo * getRegisterInfo() const override
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
std::unique_ptr< InstructionSelector > InstSelector
This class provides the information for the target register banks.
const LegalizerInfo * getLegalizerInfo() const override
Holds all the information related to register banks.
std::unique_ptr< RegisterBankInfo > RegBankInfo
InstructionSelector * getInstructionSelector() const override
This file describes how to lower LLVM calls to machine code calls.
const RISCVTargetLowering * getTargetLowering() const override
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
const CallLowering * getCallLowering() const override
Provides the logic to select generic machine instructions.
std::unique_ptr< CallLowering > CallLoweringInfo
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName, const TargetMachine &TM)
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
This class provides the information for the target register banks.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
This file declares the targeting of the RegisterBankInfo class for RISCV.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
This file declares the targeting of the Machinelegalizer class for RISCV.