LLVM 19.0.0git
Functions | Variables
RISCVTargetMachine.cpp File Reference
#include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/Scalar.h"
#include <optional>

Go to the source code of this file.

Functions

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget ()
 
static StringRef computeDataLayout (const Triple &TT, const TargetOptions &Options)
 
static Reloc::Model getEffectiveRelocModel (const Triple &TT, std::optional< Reloc::Model > RM)
 

Variables

static cl::opt< boolEnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
 
static cl::opt< cl::boolOrDefaultEnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
 
static cl::opt< boolEnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
 
static cl::opt< unsignedRVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
 
static cl::opt< int > RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
 
static cl::opt< boolEnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnableRISCVDeadRegisterElimination ("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
 
static cl::opt< boolEnableSinkFold ("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnableLoopDataPrefetch ("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
 
static cl::opt< boolEnableSplitRegAlloc ("riscv-split-regalloc", cl::Hidden, cl::desc("Enable Split RegisterAlloc for RVV"), cl::init(true))
 
static cl::opt< boolEnableMISchedLoadClustering ("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false))
 

Function Documentation

◆ computeDataLayout()

static StringRef computeDataLayout ( const Triple TT,
const TargetOptions Options 
)
static

Definition at line 131 of file RISCVTargetMachine.cpp.

References assert(), and Options.

◆ getEffectiveRelocModel()

static Reloc::Model getEffectiveRelocModel ( const Triple TT,
std::optional< Reloc::Model RM 
)
static

Definition at line 148 of file RISCVTargetMachine.cpp.

References llvm::Reloc::Static.

◆ LLVMInitializeRISCVTarget()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget ( )

Variable Documentation

◆ EnableGlobalMerge

cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")) ( "riscv-enable-global-merge"  ,
cl::Hidden  ,
cl::desc("Enable the global merge pass")   
)
static

◆ EnableLoopDataPrefetch

cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true)) ( "riscv-enable-loop-data-prefetch"  ,
cl::Hidden  ,
cl::desc("Enable the loop data prefetch pass")  ,
cl::init(true  
)
static

◆ EnableMachineCombiner

cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) ( "riscv-enable-machine-combiner"  ,
cl::desc("Enable the machine combiner pass")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableMISchedLoadClustering

cl::opt< bool > EnableMISchedLoadClustering("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)) ( "riscv-misched-load-clustering"  ,
cl::Hidden  ,
cl::desc("Enable load clustering in the machine scheduler")  ,
cl::init(false)   
)
static

◆ EnableRedundantCopyElimination

cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) ( "riscv-enable-copyelim"  ,
cl::desc("Enable the redundant copy elimination pass")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableRISCVCopyPropagation

cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) ( "riscv-enable-copy-propagation"  ,
cl::desc("Enable the copy propagation with RISC-V copy instr")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableRISCVDeadRegisterElimination

cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true)) ( "riscv-enable-dead-defs"  ,
cl::Hidden  ,
cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0")  ,
cl::init(true  
)
static

◆ EnableSinkFold

cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden) ( "riscv-enable-sink-fold"  ,
cl::desc("Enable sinking and folding of instruction copies")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableSplitRegAlloc

cl::opt< bool > EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden, cl::desc("Enable Split RegisterAlloc for RVV"), cl::init(true)) ( "riscv-split-regalloc"  ,
cl::Hidden  ,
cl::desc("Enable Split RegisterAlloc for RVV")  ,
cl::init(true  
)
static

◆ RVVVectorBitsMaxOpt

cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) ( "riscv-v-vector-bits-max"  ,
cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed.")  ,
cl::init(0)  ,
cl::Hidden   
)
static

◆ RVVVectorBitsMinOpt

cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) ( "riscv-v-vector-bits-min"  ,
cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors.")  ,
cl::init(-1)  ,
cl::Hidden   
)
static