LLVM  6.0.0svn
Macros | Functions | Variables
RegAllocGreedy.cpp File Reference
#include "AllocationOrder.h"
#include "InterferenceCache.h"
#include "LiveDebugVariables.h"
#include "RegAllocBase.h"
#include "SpillPlacement.h"
#include "Spiller.h"
#include "SplitKit.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/OptimizationDiagnosticInfo.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveIntervalUnion.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <memory>
#include <queue>
#include <tuple>
#include <utility>

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "regalloc"
 

Functions

 STATISTIC (NumGlobalSplits, "Number of split global live ranges")
 
 STATISTIC (NumLocalSplits, "Number of split local live ranges")
 
 STATISTIC (NumEvicted, "Number of interferences evicted")
 
 INITIALIZE_PASS_BEGIN (RAGreedy, "greedy", "Greedy Register Allocator", false, false) INITIALIZE_PASS_END(RAGreedy
 
static unsigned getNumAllocatableRegsForConstraints (const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI)
 Get the number of allocatable registers that match the constraints of Reg on MI and that are also in SuperRC. More...
 

Variables

static cl::opt< SplitEditor::ComplementSpillModeSplitSpillMode ("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")), cl::init(SplitEditor::SM_Speed))
 
static cl::opt< unsignedLastChanceRecoloringMaxDepth ("lcr-max-depth", cl::Hidden, cl::desc("Last chance recoloring max depth"), cl::init(5))
 
static cl::opt< unsignedLastChanceRecoloringMaxInterference ("lcr-max-interf", cl::Hidden, cl::desc("Last chance recoloring maximum number of considered" " interference at a time"), cl::init(8))
 
static cl::opt< boolExhaustiveSearch ("exhaustive-register-search", cl::NotHidden, cl::desc("Exhaustive Search for registers bypassing the depth " "and interference cutoffs of last chance recoloring"))
 
static cl::opt< boolEnableLocalReassignment ("enable-local-reassign", cl::Hidden, cl::desc("Local reassignment can yield better allocation decisions, but " "may be compile time intensive"), cl::init(false))
 
static cl::opt< boolEnableDeferredSpilling ("enable-deferred-spilling", cl::Hidden, cl::desc("Instead of spilling a variable right away, defer the actual " "code insertion to the end of the allocation. That way the " "allocator might still find a suitable coloring for this " "variable because of other evicted variables."), cl::init(false))
 
static cl::opt< unsignedCSRFirstTimeCost ("regalloc-csr-first-time-cost", cl::desc("Cost for first time use of callee-saved register."), cl::init(0), cl::Hidden)
 
static RegisterRegAlloc greedyRegAlloc ("greedy", "greedy register allocator", createGreedyRegisterAllocator)
 
 greedy
 
Greedy Register Allocator
 
Greedy Register false
 
const float Hysteresis = (2007 / 2048.0f)
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "regalloc"

Definition at line 82 of file RegAllocGreedy.cpp.

Referenced by getNumAllocatableRegsForConstraints().

Function Documentation

◆ getNumAllocatableRegsForConstraints()

static unsigned getNumAllocatableRegsForConstraints ( const MachineInstr MI,
unsigned  Reg,
const TargetRegisterClass SuperRC,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI,
const RegisterClassInfo RCI 
)
static

Get the number of allocatable registers that match the constraints of Reg on MI and that are also in SuperRC.

Definition at line 1613 of file RegAllocGreedy.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ArrayRef< T >::begin(), llvm::LiveRangeEdit::begin(), llvm::calculateSpillWeightsAndHints(), llvm::IndexedMap< T, ToIndexT >::clear(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::clear(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::clear(), llvm::SmallVectorImpl< T >::clear(), llvm::LiveIntervalUnion::Query::collectInterferingVRegs(), llvm::createInlineSpiller(), CSRFirstTimeCost, llvm::dbgs(), DEBUG, DEBUG_TYPE, llvm::Depth, E, llvm::MachineOptimizationRemarkEmitter::emit(), llvm::LLVMContext::emitError(), llvm::SmallVectorBase::empty(), llvm::LiveRangeEdit::empty(), llvm::LiveRange::empty(), EnableDeferredSpilling, EnableLocalReassignment, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::ArrayRef< T >::end(), llvm::LiveRangeEdit::end(), llvm::WebAssembly::End, llvm::LiveRange::end(), ExhaustiveSearch, llvm::LiveRange::find(), llvm::ArrayRef< T >::front(), llvm::LiveRangeEdit::get(), llvm::SlotIndex::getBaseIndex(), llvm::MachineBlockFrequencyInfo::getBlockFreq(), llvm::SpillPlacement::getBlockFrequency(), llvm::SlotIndex::getBoundaryIndex(), llvm::Function::getContext(), llvm::TargetRegisterInfo::getCSRFirstUseCost(), llvm::MachineBlockFrequencyInfo::getEntryFreq(), llvm::MachineFunction::getFrameInfo(), llvm::BlockFrequency::getFrequency(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::SlotIndexes::getInstructionFromIndex(), llvm::TargetRegisterInfo::getLargestLegalSuperClass(), llvm::MachineLoopInfo::getLoopFor(), llvm::MachineFunction::getName(), llvm::RegisterClassInfo::getNumAllocatableRegs(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), llvm::SlotIndex::getRegSlot(), llvm::MachineFunction::getSubtarget(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), llvm::AArch64CC::HI, llvm::huge_valf, I, llvm::LiveRegMatrix::IK_VirtReg, llvm::RegAllocBase::init(), llvm::InterferenceCache::init(), llvm::SmallSet< T, N, C >::insert(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::SlotIndex::InstrDist, llvm::LiveIntervalUnion::Query::interferingVRegs(), llvm::SlotIndex::isEarlierInstr(), llvm::TargetInstrInfo::isLoadFromStackSlot(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::SlotIndex::isSameInstr(), llvm::LiveInterval::isSpillable(), llvm::MachineFrameInfo::isSpillSlotObjectIndex(), llvm::TargetInstrInfo::isStoreToStackSlot(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::TargetRegisterInfo::isVirtualRegister(), LastChanceRecoloringMaxDepth, LastChanceRecoloringMaxInterference, List, Matrix, llvm::max(), MI, MRI, llvm::AllocationOrder::next(), llvm::NoCand, llvm::normalizeSpillWeight(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::PrintReg(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::LiveInterval::reg, llvm::LiveRangeEdit::regs(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::remove(), llvm::IndexedMap< T, ToIndexT >::resize(), llvm::SmallVectorImpl< T >::resize(), llvm::AllocationOrder::rewind(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ArrayRef< T >::size(), llvm::SplitEditor::SM_Size, fuzzer::SplitBefore(), llvm::LiveDebugVariables::splitRegister(), llvm::IntervalMap< KeyT, ValT, N, Traits >::const_iterator::start(), llvm::IntervalMap< KeyT, ValT, N, Traits >::const_iterator::stop(), T, llvm::TimePassesIsEnabled, llvm::IntervalMap< KeyT, ValT, N, Traits >::const_iterator::valid(), llvm::IntervalMap< KeyT, ValT, N, Traits >::const_iterator::value(), and llvm::MachineFunction::verify().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( RAGreedy  ,
"greedy"  ,
"Greedy Register Allocator ,
false  ,
false   
)

◆ STATISTIC() [1/3]

STATISTIC ( NumGlobalSplits  ,
"Number of split global live ranges"   
)

◆ STATISTIC() [2/3]

STATISTIC ( NumLocalSplits  ,
"Number of split local live ranges"   
)

◆ STATISTIC() [3/3]

STATISTIC ( NumEvicted  ,
"Number of interferences evicted"   
)

Variable Documentation

◆ Allocator

Greedy Register Allocator

Definition at line 490 of file RegAllocGreedy.cpp.

◆ CSRFirstTimeCost

cl::opt<unsigned> CSRFirstTimeCost("regalloc-csr-first-time-cost", cl::desc("Cost for first time use of callee-saved register."), cl::init(0), cl::Hidden)
static

◆ EnableDeferredSpilling

cl::opt<bool> EnableDeferredSpilling("enable-deferred-spilling", cl::Hidden, cl::desc("Instead of spilling a variable right away, defer the actual " "code insertion to the end of the allocation. That way the " "allocator might still find a suitable coloring for this " "variable because of other evicted variables."), cl::init(false))
static

◆ EnableLocalReassignment

cl::opt<bool> EnableLocalReassignment("enable-local-reassign", cl::Hidden, cl::desc("Local reassignment can yield better allocation decisions, but " "may be compile time intensive"), cl::init(false))
static

◆ ExhaustiveSearch

cl::opt<bool> ExhaustiveSearch("exhaustive-register-search", cl::NotHidden, cl::desc("Exhaustive Search for registers bypassing the depth " "and interference cutoffs of last chance recoloring"))
static

◆ false

Greedy Register false

Definition at line 490 of file RegAllocGreedy.cpp.

◆ greedy

greedy

Definition at line 490 of file RegAllocGreedy.cpp.

◆ greedyRegAlloc

RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator)
static

◆ Hysteresis

const float Hysteresis = (2007 / 2048.0f)

Definition at line 507 of file RegAllocGreedy.cpp.

◆ LastChanceRecoloringMaxDepth

cl::opt<unsigned> LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden, cl::desc("Last chance recoloring max depth"), cl::init(5))
static

◆ LastChanceRecoloringMaxInterference

cl::opt<unsigned> LastChanceRecoloringMaxInterference("lcr-max-interf", cl::Hidden, cl::desc("Last chance recoloring maximum number of considered" " interference at a time"), cl::init(8))
static

◆ SplitSpillMode

cl::opt<SplitEditor::ComplementSpillMode> SplitSpillMode("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")), cl::init(SplitEditor::SM_Speed))
static