LLVM  7.0.0svn
RegisterBankInfo.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBankInfo class.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
28 
29 #include <algorithm> // For std::max.
30 
31 #define DEBUG_TYPE "registerbankinfo"
32 
33 using namespace llvm;
34 
35 STATISTIC(NumPartialMappingsCreated,
36  "Number of partial mappings dynamically created");
37 STATISTIC(NumPartialMappingsAccessed,
38  "Number of partial mappings dynamically accessed");
39 STATISTIC(NumValueMappingsCreated,
40  "Number of value mappings dynamically created");
41 STATISTIC(NumValueMappingsAccessed,
42  "Number of value mappings dynamically accessed");
43 STATISTIC(NumOperandsMappingsCreated,
44  "Number of operands mappings dynamically created");
45 STATISTIC(NumOperandsMappingsAccessed,
46  "Number of operands mappings dynamically accessed");
47 STATISTIC(NumInstructionMappingsCreated,
48  "Number of instruction mappings dynamically created");
49 STATISTIC(NumInstructionMappingsAccessed,
50  "Number of instruction mappings dynamically accessed");
51 
52 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
53 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
54 
55 //------------------------------------------------------------------------------
56 // RegisterBankInfo implementation.
57 //------------------------------------------------------------------------------
59  unsigned NumRegBanks)
60  : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
61 #ifndef NDEBUG
62  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
63  assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
64  assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
65  }
66 #endif // NDEBUG
67 }
68 
69 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
70 #ifndef NDEBUG
71  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
72  const RegisterBank &RegBank = getRegBank(Idx);
73  assert(Idx == RegBank.getID() &&
74  "ID does not match the index in the array");
75  DEBUG(dbgs() << "Verify " << RegBank << '\n');
76  assert(RegBank.verify(TRI) && "RegBank is invalid");
77  }
78 #endif // NDEBUG
79  return true;
80 }
81 
82 const RegisterBank *
84  const TargetRegisterInfo &TRI) const {
87 
88  assert(Reg && "NoRegister does not have a register bank");
89  const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
90  if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
91  return RB;
92  if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
93  return &getRegBankFromRegClass(*RC);
94  return nullptr;
95 }
96 
97 const TargetRegisterClass &
99  const TargetRegisterInfo &TRI) const {
101  "Reg must be a physreg");
102  const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
103  if (RegRCIt != PhysRegMinimalRCs.end())
104  return *RegRCIt->second;
105  const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
106  PhysRegMinimalRCs[Reg] = PhysRC;
107  return *PhysRC;
108 }
109 
111  const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
112  const TargetRegisterInfo &TRI) const {
113  // The mapping of the registers may be available via the
114  // register class constraints.
115  const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
116 
117  if (!RC)
118  return nullptr;
119 
120  const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
121  // Sanity check that the target properly implemented getRegBankFromRegClass.
122  assert(RegBank.covers(*RC) &&
123  "The mapping of the register bank does not make sense");
124  return &RegBank;
125 }
126 
128  unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
129 
130  // If the register already has a class, fallback to MRI::constrainRegClass.
131  auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
132  if (RegClassOrBank.is<const TargetRegisterClass *>())
133  return MRI.constrainRegClass(Reg, &RC);
134 
135  const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
136  // Otherwise, all we can do is ensure the bank covers the class, and set it.
137  if (RB && !RB->covers(RC))
138  return nullptr;
139 
140  // If nothing was set or the class is simply compatible, set it.
141  MRI.setRegClass(Reg, &RC);
142  return &RC;
143 }
144 
145 /// Check whether or not \p MI should be treated like a copy
146 /// for the mappings.
147 /// Copy like instruction are special for mapping because
148 /// they don't have actual register constraints. Moreover,
149 /// they sometimes have register classes assigned and we can
150 /// just use that instead of failing to provide a generic mapping.
151 static bool isCopyLike(const MachineInstr &MI) {
152  return MI.isCopy() || MI.isPHI() ||
153  MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
154 }
155 
158  // For copies we want to walk over the operands and try to find one
159  // that has a register bank since the instruction itself will not get
160  // us any constraint.
161  bool IsCopyLike = isCopyLike(MI);
162  // For copy like instruction, only the mapping of the definition
163  // is important. The rest is not constrained.
164  unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
165 
166  const MachineFunction &MF = *MI.getMF();
167  const TargetSubtargetInfo &STI = MF.getSubtarget();
168  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
169  const MachineRegisterInfo &MRI = MF.getRegInfo();
170  // We may need to query the instruction encoding to guess the mapping.
171  const TargetInstrInfo &TII = *STI.getInstrInfo();
172 
173  // Before doing anything complicated check if the mapping is not
174  // directly available.
175  bool CompleteMapping = true;
176 
177  SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
178  for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
179  ++OpIdx) {
180  const MachineOperand &MO = MI.getOperand(OpIdx);
181  if (!MO.isReg())
182  continue;
183  unsigned Reg = MO.getReg();
184  if (!Reg)
185  continue;
186  // The register bank of Reg is just a side effect of the current
187  // excution and in particular, there is no reason to believe this
188  // is the best default mapping for the current instruction. Keep
189  // it as an alternative register bank if we cannot figure out
190  // something.
191  const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
192  // For copy-like instruction, we want to reuse the register bank
193  // that is already set on Reg, if any, since those instructions do
194  // not have any constraints.
195  const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
196  if (!CurRegBank) {
197  // If this is a target specific instruction, we can deduce
198  // the register bank from the encoding constraints.
199  CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
200  if (!CurRegBank) {
201  // All our attempts failed, give up.
202  CompleteMapping = false;
203 
204  if (!IsCopyLike)
205  // MI does not carry enough information to guess the mapping.
207  continue;
208  }
209  }
210  const ValueMapping *ValMapping =
211  &getValueMapping(0, getSizeInBits(Reg, MRI, TRI), *CurRegBank);
212  if (IsCopyLike) {
213  OperandsMapping[0] = ValMapping;
214  CompleteMapping = true;
215  break;
216  }
217  OperandsMapping[OpIdx] = ValMapping;
218  }
219 
220  if (IsCopyLike && !CompleteMapping)
221  // No way to deduce the type from what we have.
223 
224  assert(CompleteMapping && "Setting an uncomplete mapping");
225  return getInstructionMapping(
226  DefaultMappingID, /*Cost*/ 1,
227  /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
228  NumOperandsForMapping);
229 }
230 
231 /// Hashing function for PartialMapping.
232 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
233  const RegisterBank *RegBank) {
234  return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
235 }
236 
237 /// Overloaded version of hash_value for a PartialMapping.
238 hash_code
240  return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
241  PartMapping.RegBank);
242 }
243 
245 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
246  const RegisterBank &RegBank) const {
247  ++NumPartialMappingsAccessed;
248 
249  hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
250  const auto &It = MapOfPartialMappings.find(Hash);
251  if (It != MapOfPartialMappings.end())
252  return *It->second;
253 
254  ++NumPartialMappingsCreated;
255 
256  auto &PartMapping = MapOfPartialMappings[Hash];
257  PartMapping = llvm::make_unique<PartialMapping>(StartIdx, Length, RegBank);
258  return *PartMapping;
259 }
260 
262 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
263  const RegisterBank &RegBank) const {
264  return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
265 }
266 
267 static hash_code
269  unsigned NumBreakDowns) {
270  if (LLVM_LIKELY(NumBreakDowns == 1))
271  return hash_value(*BreakDown);
272  SmallVector<size_t, 8> Hashes(NumBreakDowns);
273  for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
274  Hashes.push_back(hash_value(BreakDown[Idx]));
275  return hash_combine_range(Hashes.begin(), Hashes.end());
276 }
277 
280  unsigned NumBreakDowns) const {
281  ++NumValueMappingsAccessed;
282 
283  hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
284  const auto &It = MapOfValueMappings.find(Hash);
285  if (It != MapOfValueMappings.end())
286  return *It->second;
287 
288  ++NumValueMappingsCreated;
289 
290  auto &ValMapping = MapOfValueMappings[Hash];
291  ValMapping = llvm::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
292  return *ValMapping;
293 }
294 
295 template <typename Iterator>
297 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
298 
299  ++NumOperandsMappingsAccessed;
300 
301  // The addresses of the value mapping are unique.
302  // Therefore, we can use them directly to hash the operand mapping.
303  hash_code Hash = hash_combine_range(Begin, End);
304  auto &Res = MapOfOperandsMappings[Hash];
305  if (Res)
306  return Res.get();
307 
308  ++NumOperandsMappingsCreated;
309 
310  // Create the array of ValueMapping.
311  // Note: this array will not hash to this instance of operands
312  // mapping, because we use the pointer of the ValueMapping
313  // to hash and we expect them to uniquely identify an instance
314  // of value mapping.
315  Res = llvm::make_unique<ValueMapping[]>(std::distance(Begin, End));
316  unsigned Idx = 0;
317  for (Iterator It = Begin; It != End; ++It, ++Idx) {
318  const ValueMapping *ValMap = *It;
319  if (!ValMap)
320  continue;
321  Res[Idx] = *ValMap;
322  }
323  return Res.get();
324 }
325 
328  const {
329  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
330 }
331 
333  std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
334  const {
335  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
336 }
337 
338 static hash_code
339 hashInstructionMapping(unsigned ID, unsigned Cost,
340  const RegisterBankInfo::ValueMapping *OperandsMapping,
341  unsigned NumOperands) {
342  return hash_combine(ID, Cost, OperandsMapping, NumOperands);
343 }
344 
346 RegisterBankInfo::getInstructionMappingImpl(
347  bool IsInvalid, unsigned ID, unsigned Cost,
348  const RegisterBankInfo::ValueMapping *OperandsMapping,
349  unsigned NumOperands) const {
350  assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
351  OperandsMapping == nullptr && NumOperands == 0) ||
352  !IsInvalid) &&
353  "Mismatch argument for invalid input");
354  ++NumInstructionMappingsAccessed;
355 
356  hash_code Hash =
357  hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
358  const auto &It = MapOfInstructionMappings.find(Hash);
359  if (It != MapOfInstructionMappings.end())
360  return *It->second;
361 
362  ++NumInstructionMappingsCreated;
363 
364  auto &InstrMapping = MapOfInstructionMappings[Hash];
365  if (IsInvalid)
366  InstrMapping = llvm::make_unique<InstructionMapping>();
367  else
368  InstrMapping = llvm::make_unique<InstructionMapping>(
369  ID, Cost, OperandsMapping, NumOperands);
370  return *InstrMapping;
371 }
372 
376  if (Mapping.isValid())
377  return Mapping;
378  llvm_unreachable("The target must implement this");
379 }
380 
382 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
383  InstructionMappings PossibleMappings;
384  // Put the default mapping first.
385  PossibleMappings.push_back(&getInstrMapping(MI));
386  // Then the alternative mapping, if any.
388  for (const InstructionMapping *AltMapping : AltMappings)
389  PossibleMappings.push_back(AltMapping);
390 #ifndef NDEBUG
391  for (const InstructionMapping *Mapping : PossibleMappings)
392  assert(Mapping->verify(MI) && "Mapping is invalid");
393 #endif
394  return PossibleMappings;
395 }
396 
399  // No alternative for MI.
400  return InstructionMappings();
401 }
402 
404  MachineInstr &MI = OpdMapper.getMI();
405  MachineRegisterInfo &MRI = OpdMapper.getMRI();
406  DEBUG(dbgs() << "Applying default-like mapping\n");
407  for (unsigned OpIdx = 0,
408  EndIdx = OpdMapper.getInstrMapping().getNumOperands();
409  OpIdx != EndIdx; ++OpIdx) {
410  DEBUG(dbgs() << "OpIdx " << OpIdx);
411  MachineOperand &MO = MI.getOperand(OpIdx);
412  if (!MO.isReg()) {
413  DEBUG(dbgs() << " is not a register, nothing to be done\n");
414  continue;
415  }
416  if (!MO.getReg()) {
417  DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
418  continue;
419  }
420  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
421  0 &&
422  "Invalid mapping");
423  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
424  1 &&
425  "This mapping is too complex for this function");
427  OpdMapper.getVRegs(OpIdx);
428  if (NewRegs.begin() == NewRegs.end()) {
429  DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
430  continue;
431  }
432  unsigned OrigReg = MO.getReg();
433  unsigned NewReg = *NewRegs.begin();
434  DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
435  MO.setReg(NewReg);
436  DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
437 
438  // The OperandsMapper creates plain scalar, we may have to fix that.
439  // Check if the types match and if not, fix that.
440  LLT OrigTy = MRI.getType(OrigReg);
441  LLT NewTy = MRI.getType(NewReg);
442  if (OrigTy != NewTy) {
443  // The default mapping is not supposed to change the size of
444  // the storage. However, right now we don't necessarily bump all
445  // the types to storage size. For instance, we can consider
446  // s16 G_AND legal whereas the storage size is going to be 32.
447  assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
448  "Types with difference size cannot be handled by the default "
449  "mapping");
450  DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
451  << OrigTy);
452  MRI.setType(NewReg, OrigTy);
453  }
454  DEBUG(dbgs() << '\n');
455  }
456 }
457 
458 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
459  const MachineRegisterInfo &MRI,
460  const TargetRegisterInfo &TRI) const {
461  const TargetRegisterClass *RC = nullptr;
463  // The size is not directly available for physical registers.
464  // Instead, we need to access a register class that contains Reg and
465  // get the size of that register class.
466  RC = &getMinimalPhysRegClass(Reg, TRI);
467  } else {
468  LLT Ty = MRI.getType(Reg);
469  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
470  // If Reg is not a generic register, query the register class to
471  // get its size.
472  if (RegSize)
473  return RegSize;
474  // Since Reg is not a generic register, it must have a register class.
475  RC = MRI.getRegClass(Reg);
476  }
477  assert(RC && "Unable to deduce the register class");
478  return TRI.getRegSizeInBits(*RC);
479 }
480 
481 //------------------------------------------------------------------------------
482 // Helper classes implementation.
483 //------------------------------------------------------------------------------
484 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
486  print(dbgs());
487  dbgs() << '\n';
488 }
489 #endif
490 
492  assert(RegBank && "Register bank not set");
493  assert(Length && "Empty mapping");
494  assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
495  // Check if the minimum width fits into RegBank.
496  assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
497  return true;
498 }
499 
501  OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
502  if (RegBank)
503  OS << *RegBank;
504  else
505  OS << "nullptr";
506 }
507 
508 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
509  assert(NumBreakDowns && "Value mapped nowhere?!");
510  unsigned OrigValueBitWidth = 0;
511  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
512  // Check that each register bank is big enough to hold the partial value:
513  // this check is done by PartialMapping::verify
514  assert(PartMap.verify() && "Partial mapping is invalid");
515  // The original value should completely be mapped.
516  // Thus the maximum accessed index + 1 is the size of the original value.
517  OrigValueBitWidth =
518  std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
519  }
520  assert(OrigValueBitWidth >= MeaningfulBitWidth &&
521  "Meaningful bits not covered by the mapping");
522  APInt ValueMask(OrigValueBitWidth, 0);
523  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
524  // Check that the union of the partial mappings covers the whole value,
525  // without overlaps.
526  // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
527  APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
528  PartMap.getHighBitIdx() + 1);
529  ValueMask ^= PartMapMask;
530  assert((ValueMask & PartMapMask) == PartMapMask &&
531  "Some partial mappings overlap");
532  }
533  assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
534  return true;
535 }
536 
537 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
539  print(dbgs());
540  dbgs() << '\n';
541 }
542 #endif
543 
545  OS << "#BreakDown: " << NumBreakDowns << " ";
546  bool IsFirst = true;
547  for (const PartialMapping &PartMap : *this) {
548  if (!IsFirst)
549  OS << ", ";
550  OS << '[' << PartMap << ']';
551  IsFirst = false;
552  }
553 }
554 
556  const MachineInstr &MI) const {
557  // Check that all the register operands are properly mapped.
558  // Check the constructor invariant.
559  // For PHI, we only care about mapping the definition.
560  assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
561  "NumOperands must match, see constructor");
562  assert(MI.getParent() && MI.getMF() &&
563  "MI must be connected to a MachineFunction");
564  const MachineFunction &MF = *MI.getMF();
565  const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
566  (void)RBI;
567 
568  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
569  const MachineOperand &MO = MI.getOperand(Idx);
570  if (!MO.isReg()) {
571  assert(!getOperandMapping(Idx).isValid() &&
572  "We should not care about non-reg mapping");
573  continue;
574  }
575  unsigned Reg = MO.getReg();
576  if (!Reg)
577  continue;
578  assert(getOperandMapping(Idx).isValid() &&
579  "We must have a mapping for reg operands");
580  const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
581  (void)MOMapping;
582  // Register size in bits.
583  // This size must match what the mapping expects.
584  assert(MOMapping.verify(RBI->getSizeInBits(
585  Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
586  "Value mapping is invalid");
587  }
588  return true;
589 }
590 
591 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
593  print(dbgs());
594  dbgs() << '\n';
595 }
596 #endif
597 
599  OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
600 
601  for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
602  const ValueMapping &ValMapping = getOperandMapping(OpIdx);
603  if (OpIdx)
604  OS << ", ";
605  OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
606  }
607 }
608 
609 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
610 
612  MachineInstr &MI, const InstructionMapping &InstrMapping,
613  MachineRegisterInfo &MRI)
614  : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
615  unsigned NumOpds = InstrMapping.getNumOperands();
616  OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
617  assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
618 }
619 
621 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
622  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
623  unsigned NumPartialVal =
624  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
625  int StartIdx = OpToNewVRegIdx[OpIdx];
626 
627  if (StartIdx == OperandsMapper::DontKnowIdx) {
628  // This is the first time we try to access OpIdx.
629  // Create the cells that will hold all the partial values at the
630  // end of the list of NewVReg.
631  StartIdx = NewVRegs.size();
632  OpToNewVRegIdx[OpIdx] = StartIdx;
633  for (unsigned i = 0; i < NumPartialVal; ++i)
634  NewVRegs.push_back(0);
635  }
637  getNewVRegsEnd(StartIdx, NumPartialVal);
638 
639  return make_range(&NewVRegs[StartIdx], End);
640 }
641 
643 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
644  unsigned NumVal) const {
645  return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
646 }
648 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
649  unsigned NumVal) {
650  assert((NewVRegs.size() == StartIdx + NumVal ||
651  NewVRegs.size() > StartIdx + NumVal) &&
652  "NewVRegs too small to contain all the partial mapping");
653  return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
654  : &NewVRegs[StartIdx + NumVal];
655 }
656 
658  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
660  getVRegsMem(OpIdx);
661  const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
662  const PartialMapping *PartMap = ValMapping.begin();
663  for (unsigned &NewVReg : NewVRegsForOpIdx) {
664  assert(PartMap != ValMapping.end() && "Out-of-bound access");
665  assert(NewVReg == 0 && "Register has already been created");
666  // The new registers are always bound to scalar with the right size.
667  // The actual type has to be set when the target does the mapping
668  // of the instruction.
669  // The rationale is that this generic code cannot guess how the
670  // target plans to split the input type.
671  NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
672  MRI.setRegBank(NewVReg, *PartMap->RegBank);
673  ++PartMap;
674  }
675 }
676 
678  unsigned PartialMapIdx,
679  unsigned NewVReg) {
680  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
681  assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
682  PartialMapIdx &&
683  "Out-of-bound access for partial mapping");
684  // Make sure the memory is initialized for that operand.
685  (void)getVRegsMem(OpIdx);
686  assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
687  "This value is already set");
688  NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
689 }
690 
693  bool ForDebug) const {
694  (void)ForDebug;
695  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
696  int StartIdx = OpToNewVRegIdx[OpIdx];
697 
698  if (StartIdx == OperandsMapper::DontKnowIdx)
699  return make_range(NewVRegs.end(), NewVRegs.end());
700 
701  unsigned PartMapSize =
702  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
704  getNewVRegsEnd(StartIdx, PartMapSize);
706  make_range(&NewVRegs[StartIdx], End);
707 #ifndef NDEBUG
708  for (unsigned VReg : Res)
709  assert((VReg || ForDebug) && "Some registers are uninitialized");
710 #endif
711  return Res;
712 }
713 
714 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
716  print(dbgs(), true);
717  dbgs() << '\n';
718 }
719 #endif
720 
722  bool ForDebug) const {
723  unsigned NumOpds = getInstrMapping().getNumOperands();
724  if (ForDebug) {
725  OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
726  // Print out the internal state of the index table.
727  OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
728  bool IsFirst = true;
729  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
730  if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
731  if (!IsFirst)
732  OS << ", ";
733  OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
734  IsFirst = false;
735  }
736  }
737  OS << '\n';
738  } else
739  OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
740 
741  OS << "Operand Mapping: ";
742  // If we have a function, we can pretty print the name of the registers.
743  // Otherwise we will print the raw numbers.
744  const TargetRegisterInfo *TRI =
745  getMI().getParent() && getMI().getMF()
747  : nullptr;
748  bool IsFirst = true;
749  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
750  if (OpToNewVRegIdx[Idx] == DontKnowIdx)
751  continue;
752  if (!IsFirst)
753  OS << ", ";
754  IsFirst = false;
755  OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
756  bool IsFirstNewVReg = true;
757  for (unsigned VReg : getVRegs(Idx)) {
758  if (!IsFirstNewVReg)
759  OS << ", ";
760  IsFirstNewVReg = false;
761  OS << printReg(VReg, TRI);
762  }
763  OS << "])";
764  }
765 }
unsigned NumRegBanks
Total number of register banks.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank ** RegBanks
Hold the set of supported register banks.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void print(raw_ostream &OS) const
Print this on OS;.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:175
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void dump() const
Print this on dbgs() stream.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
STATISTIC(NumFunctions, "Total number of functions")
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
bool isPHI() const
Definition: MachineInstr.h:829
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
void dump() const
Print this partial mapping on dbgs() stream.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Reg
All possible values of the reg field in the ModR/M byte.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
void dump() const
Print this operands mapper on dbgs() stream.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4428
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:389
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
static bool isCopyLike(const MachineInstr &MI)
Check whether or not MI should be treated like a copy for the mappings.
bool isValid() const
static const unsigned End
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:142
bool isCopy() const
Definition: MachineInstr.h:860
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping * end() const
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
void print(raw_ostream &OS) const
Print this on OS;.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
A range adaptor for a pair of iterators.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:602
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:480
An opaque object representing a hash code.
Definition: Hashing.h:72
const PartialMapping * begin() const
Iterators through the PartialMappings.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:600
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
RegisterBankInfo()
This constructor is meaningless.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
ppc ctr loops verify
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void dump() const
Print this on dbgs() stream.
unsigned getNumOperands() const
Get the number of operands.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
void resize(size_type N)
Definition: SmallVector.h:353