LLVM  9.0.0svn
RegisterBankInfo.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the RegisterBankInfo class.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
28 
29 #include <algorithm> // For std::max.
30 
31 #define DEBUG_TYPE "registerbankinfo"
32 
33 using namespace llvm;
34 
35 STATISTIC(NumPartialMappingsCreated,
36  "Number of partial mappings dynamically created");
37 STATISTIC(NumPartialMappingsAccessed,
38  "Number of partial mappings dynamically accessed");
39 STATISTIC(NumValueMappingsCreated,
40  "Number of value mappings dynamically created");
41 STATISTIC(NumValueMappingsAccessed,
42  "Number of value mappings dynamically accessed");
43 STATISTIC(NumOperandsMappingsCreated,
44  "Number of operands mappings dynamically created");
45 STATISTIC(NumOperandsMappingsAccessed,
46  "Number of operands mappings dynamically accessed");
47 STATISTIC(NumInstructionMappingsCreated,
48  "Number of instruction mappings dynamically created");
49 STATISTIC(NumInstructionMappingsAccessed,
50  "Number of instruction mappings dynamically accessed");
51 
52 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
53 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
54 
55 //------------------------------------------------------------------------------
56 // RegisterBankInfo implementation.
57 //------------------------------------------------------------------------------
59  unsigned NumRegBanks)
60  : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
61 #ifndef NDEBUG
62  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
63  assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
64  assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
65  }
66 #endif // NDEBUG
67 }
68 
70 #ifndef NDEBUG
71  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
72  const RegisterBank &RegBank = getRegBank(Idx);
73  assert(Idx == RegBank.getID() &&
74  "ID does not match the index in the array");
75  LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
76  assert(RegBank.verify(TRI) && "RegBank is invalid");
77  }
78 #endif // NDEBUG
79  return true;
80 }
81 
82 const RegisterBank *
84  const TargetRegisterInfo &TRI) const {
87 
88  assert(Reg && "NoRegister does not have a register bank");
89  const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
90  if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
91  return RB;
92  if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
93  return &getRegBankFromRegClass(*RC);
94  return nullptr;
95 }
96 
97 const TargetRegisterClass &
99  const TargetRegisterInfo &TRI) const {
101  "Reg must be a physreg");
102  const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
103  if (RegRCIt != PhysRegMinimalRCs.end())
104  return *RegRCIt->second;
105  const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
106  PhysRegMinimalRCs[Reg] = PhysRC;
107  return *PhysRC;
108 }
109 
111  const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
112  const TargetRegisterInfo &TRI) const {
113  // The mapping of the registers may be available via the
114  // register class constraints.
115  const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
116 
117  if (!RC)
118  return nullptr;
119 
120  const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
121  // Sanity check that the target properly implemented getRegBankFromRegClass.
122  assert(RegBank.covers(*RC) &&
123  "The mapping of the register bank does not make sense");
124  return &RegBank;
125 }
126 
128  unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
129 
130  // If the register already has a class, fallback to MRI::constrainRegClass.
131  auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
132  if (RegClassOrBank.is<const TargetRegisterClass *>())
133  return MRI.constrainRegClass(Reg, &RC);
134 
135  const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
136  // Otherwise, all we can do is ensure the bank covers the class, and set it.
137  if (RB && !RB->covers(RC))
138  return nullptr;
139 
140  // If nothing was set or the class is simply compatible, set it.
141  MRI.setRegClass(Reg, &RC);
142  return &RC;
143 }
144 
145 /// Check whether or not \p MI should be treated like a copy
146 /// for the mappings.
147 /// Copy like instruction are special for mapping because
148 /// they don't have actual register constraints. Moreover,
149 /// they sometimes have register classes assigned and we can
150 /// just use that instead of failing to provide a generic mapping.
151 static bool isCopyLike(const MachineInstr &MI) {
152  return MI.isCopy() || MI.isPHI() ||
153  MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
154 }
155 
158  // For copies we want to walk over the operands and try to find one
159  // that has a register bank since the instruction itself will not get
160  // us any constraint.
161  bool IsCopyLike = isCopyLike(MI);
162  // For copy like instruction, only the mapping of the definition
163  // is important. The rest is not constrained.
164  unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
165 
166  const MachineFunction &MF = *MI.getMF();
167  const TargetSubtargetInfo &STI = MF.getSubtarget();
168  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
169  const MachineRegisterInfo &MRI = MF.getRegInfo();
170  // We may need to query the instruction encoding to guess the mapping.
171  const TargetInstrInfo &TII = *STI.getInstrInfo();
172 
173  // Before doing anything complicated check if the mapping is not
174  // directly available.
175  bool CompleteMapping = true;
176 
177  SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
178  for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
179  ++OpIdx) {
180  const MachineOperand &MO = MI.getOperand(OpIdx);
181  if (!MO.isReg())
182  continue;
183  unsigned Reg = MO.getReg();
184  if (!Reg)
185  continue;
186  // The register bank of Reg is just a side effect of the current
187  // excution and in particular, there is no reason to believe this
188  // is the best default mapping for the current instruction. Keep
189  // it as an alternative register bank if we cannot figure out
190  // something.
191  const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
192  // For copy-like instruction, we want to reuse the register bank
193  // that is already set on Reg, if any, since those instructions do
194  // not have any constraints.
195  const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
196  if (!CurRegBank) {
197  // If this is a target specific instruction, we can deduce
198  // the register bank from the encoding constraints.
199  CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
200  if (!CurRegBank) {
201  // All our attempts failed, give up.
202  CompleteMapping = false;
203 
204  if (!IsCopyLike)
205  // MI does not carry enough information to guess the mapping.
207  continue;
208  }
209  }
210 
211  unsigned Size = getSizeInBits(Reg, MRI, TRI);
212  const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank);
213  if (IsCopyLike) {
214  if (!OperandsMapping[0]) {
215  if (MI.isRegSequence()) {
216  // For reg_sequence, the result size does not match the input.
217  unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
218  MRI, TRI);
219  OperandsMapping[0] = &getValueMapping(0, ResultSize, *CurRegBank);
220  } else {
221  OperandsMapping[0] = ValMapping;
222  }
223 
224  CompleteMapping = true;
225  }
226 
227  break;
228  }
229  OperandsMapping[OpIdx] = ValMapping;
230  }
231 
232  if (IsCopyLike && !CompleteMapping)
233  // No way to deduce the type from what we have.
235 
236  assert(CompleteMapping && "Setting an uncomplete mapping");
237  return getInstructionMapping(
238  DefaultMappingID, /*Cost*/ 1,
239  /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
240  NumOperandsForMapping);
241 }
242 
243 /// Hashing function for PartialMapping.
244 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
245  const RegisterBank *RegBank) {
246  return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
247 }
248 
249 /// Overloaded version of hash_value for a PartialMapping.
250 hash_code
252  return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
253  PartMapping.RegBank);
254 }
255 
257 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
258  const RegisterBank &RegBank) const {
259  ++NumPartialMappingsAccessed;
260 
261  hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
262  const auto &It = MapOfPartialMappings.find(Hash);
263  if (It != MapOfPartialMappings.end())
264  return *It->second;
265 
266  ++NumPartialMappingsCreated;
267 
268  auto &PartMapping = MapOfPartialMappings[Hash];
269  PartMapping = llvm::make_unique<PartialMapping>(StartIdx, Length, RegBank);
270  return *PartMapping;
271 }
272 
274 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
275  const RegisterBank &RegBank) const {
276  return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
277 }
278 
279 static hash_code
281  unsigned NumBreakDowns) {
282  if (LLVM_LIKELY(NumBreakDowns == 1))
283  return hash_value(*BreakDown);
284  SmallVector<size_t, 8> Hashes(NumBreakDowns);
285  for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
286  Hashes.push_back(hash_value(BreakDown[Idx]));
287  return hash_combine_range(Hashes.begin(), Hashes.end());
288 }
289 
292  unsigned NumBreakDowns) const {
293  ++NumValueMappingsAccessed;
294 
295  hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
296  const auto &It = MapOfValueMappings.find(Hash);
297  if (It != MapOfValueMappings.end())
298  return *It->second;
299 
300  ++NumValueMappingsCreated;
301 
302  auto &ValMapping = MapOfValueMappings[Hash];
303  ValMapping = llvm::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
304  return *ValMapping;
305 }
306 
307 template <typename Iterator>
309 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
310 
311  ++NumOperandsMappingsAccessed;
312 
313  // The addresses of the value mapping are unique.
314  // Therefore, we can use them directly to hash the operand mapping.
315  hash_code Hash = hash_combine_range(Begin, End);
316  auto &Res = MapOfOperandsMappings[Hash];
317  if (Res)
318  return Res.get();
319 
320  ++NumOperandsMappingsCreated;
321 
322  // Create the array of ValueMapping.
323  // Note: this array will not hash to this instance of operands
324  // mapping, because we use the pointer of the ValueMapping
325  // to hash and we expect them to uniquely identify an instance
326  // of value mapping.
327  Res = llvm::make_unique<ValueMapping[]>(std::distance(Begin, End));
328  unsigned Idx = 0;
329  for (Iterator It = Begin; It != End; ++It, ++Idx) {
330  const ValueMapping *ValMap = *It;
331  if (!ValMap)
332  continue;
333  Res[Idx] = *ValMap;
334  }
335  return Res.get();
336 }
337 
340  const {
341  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
342 }
343 
345  std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
346  const {
347  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
348 }
349 
350 static hash_code
351 hashInstructionMapping(unsigned ID, unsigned Cost,
352  const RegisterBankInfo::ValueMapping *OperandsMapping,
353  unsigned NumOperands) {
354  return hash_combine(ID, Cost, OperandsMapping, NumOperands);
355 }
356 
358 RegisterBankInfo::getInstructionMappingImpl(
359  bool IsInvalid, unsigned ID, unsigned Cost,
360  const RegisterBankInfo::ValueMapping *OperandsMapping,
361  unsigned NumOperands) const {
362  assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
363  OperandsMapping == nullptr && NumOperands == 0) ||
364  !IsInvalid) &&
365  "Mismatch argument for invalid input");
366  ++NumInstructionMappingsAccessed;
367 
368  hash_code Hash =
369  hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
370  const auto &It = MapOfInstructionMappings.find(Hash);
371  if (It != MapOfInstructionMappings.end())
372  return *It->second;
373 
374  ++NumInstructionMappingsCreated;
375 
376  auto &InstrMapping = MapOfInstructionMappings[Hash];
377  if (IsInvalid)
378  InstrMapping = llvm::make_unique<InstructionMapping>();
379  else
380  InstrMapping = llvm::make_unique<InstructionMapping>(
381  ID, Cost, OperandsMapping, NumOperands);
382  return *InstrMapping;
383 }
384 
388  if (Mapping.isValid())
389  return Mapping;
390  llvm_unreachable("The target must implement this");
391 }
392 
394 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
395  InstructionMappings PossibleMappings;
396  // Put the default mapping first.
397  PossibleMappings.push_back(&getInstrMapping(MI));
398  // Then the alternative mapping, if any.
400  for (const InstructionMapping *AltMapping : AltMappings)
401  PossibleMappings.push_back(AltMapping);
402 #ifndef NDEBUG
403  for (const InstructionMapping *Mapping : PossibleMappings)
404  assert(Mapping->verify(MI) && "Mapping is invalid");
405 #endif
406  return PossibleMappings;
407 }
408 
411  // No alternative for MI.
412  return InstructionMappings();
413 }
414 
416  MachineInstr &MI = OpdMapper.getMI();
417  MachineRegisterInfo &MRI = OpdMapper.getMRI();
418  LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");
419  for (unsigned OpIdx = 0,
420  EndIdx = OpdMapper.getInstrMapping().getNumOperands();
421  OpIdx != EndIdx; ++OpIdx) {
422  LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx);
423  MachineOperand &MO = MI.getOperand(OpIdx);
424  if (!MO.isReg()) {
425  LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");
426  continue;
427  }
428  if (!MO.getReg()) {
429  LLVM_DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
430  continue;
431  }
432  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
433  0 &&
434  "Invalid mapping");
435  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
436  1 &&
437  "This mapping is too complex for this function");
439  OpdMapper.getVRegs(OpIdx);
440  if (empty(NewRegs)) {
441  LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
442  continue;
443  }
444  unsigned OrigReg = MO.getReg();
445  unsigned NewReg = *NewRegs.begin();
446  LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
447  MO.setReg(NewReg);
448  LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
449 
450  // The OperandsMapper creates plain scalar, we may have to fix that.
451  // Check if the types match and if not, fix that.
452  LLT OrigTy = MRI.getType(OrigReg);
453  LLT NewTy = MRI.getType(NewReg);
454  if (OrigTy != NewTy) {
455  // The default mapping is not supposed to change the size of
456  // the storage. However, right now we don't necessarily bump all
457  // the types to storage size. For instance, we can consider
458  // s16 G_AND legal whereas the storage size is going to be 32.
459  assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
460  "Types with difference size cannot be handled by the default "
461  "mapping");
462  LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
463  << OrigTy);
464  MRI.setType(NewReg, OrigTy);
465  }
466  LLVM_DEBUG(dbgs() << '\n');
467  }
468 }
469 
470 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
471  const MachineRegisterInfo &MRI,
472  const TargetRegisterInfo &TRI) const {
474  // The size is not directly available for physical registers.
475  // Instead, we need to access a register class that contains Reg and
476  // get the size of that register class.
477  // Because this is expensive, we'll cache the register class by calling
478  auto *RC = &getMinimalPhysRegClass(Reg, TRI);
479  assert(RC && "Expecting Register class");
480  return TRI.getRegSizeInBits(*RC);
481  }
482  return TRI.getRegSizeInBits(Reg, MRI);
483 }
484 
485 //------------------------------------------------------------------------------
486 // Helper classes implementation.
487 //------------------------------------------------------------------------------
488 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
490  print(dbgs());
491  dbgs() << '\n';
492 }
493 #endif
494 
496  assert(RegBank && "Register bank not set");
497  assert(Length && "Empty mapping");
498  assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
499  // Check if the minimum width fits into RegBank.
500  assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
501  return true;
502 }
503 
505  OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
506  if (RegBank)
507  OS << *RegBank;
508  else
509  OS << "nullptr";
510 }
511 
513  if (NumBreakDowns < 2)
514  return true;
515 
516  const PartialMapping *First = begin();
517  for (const PartialMapping *Part = First + 1; Part != end(); ++Part) {
518  if (Part->Length != First->Length || Part->RegBank != First->RegBank)
519  return false;
520  }
521 
522  return true;
523 }
524 
525 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
526  assert(NumBreakDowns && "Value mapped nowhere?!");
527  unsigned OrigValueBitWidth = 0;
528  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
529  // Check that each register bank is big enough to hold the partial value:
530  // this check is done by PartialMapping::verify
531  assert(PartMap.verify() && "Partial mapping is invalid");
532  // The original value should completely be mapped.
533  // Thus the maximum accessed index + 1 is the size of the original value.
534  OrigValueBitWidth =
535  std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
536  }
537  assert(OrigValueBitWidth >= MeaningfulBitWidth &&
538  "Meaningful bits not covered by the mapping");
539  APInt ValueMask(OrigValueBitWidth, 0);
540  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
541  // Check that the union of the partial mappings covers the whole value,
542  // without overlaps.
543  // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
544  APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
545  PartMap.getHighBitIdx() + 1);
546  ValueMask ^= PartMapMask;
547  assert((ValueMask & PartMapMask) == PartMapMask &&
548  "Some partial mappings overlap");
549  }
550  assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
551  return true;
552 }
553 
554 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
556  print(dbgs());
557  dbgs() << '\n';
558 }
559 #endif
560 
562  OS << "#BreakDown: " << NumBreakDowns << " ";
563  bool IsFirst = true;
564  for (const PartialMapping &PartMap : *this) {
565  if (!IsFirst)
566  OS << ", ";
567  OS << '[' << PartMap << ']';
568  IsFirst = false;
569  }
570 }
571 
573  const MachineInstr &MI) const {
574  // Check that all the register operands are properly mapped.
575  // Check the constructor invariant.
576  // For PHI, we only care about mapping the definition.
577  assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
578  "NumOperands must match, see constructor");
579  assert(MI.getParent() && MI.getMF() &&
580  "MI must be connected to a MachineFunction");
581  const MachineFunction &MF = *MI.getMF();
582  const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
583  (void)RBI;
584 
585  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
586  const MachineOperand &MO = MI.getOperand(Idx);
587  if (!MO.isReg()) {
588  assert(!getOperandMapping(Idx).isValid() &&
589  "We should not care about non-reg mapping");
590  continue;
591  }
592  unsigned Reg = MO.getReg();
593  if (!Reg)
594  continue;
595  assert(getOperandMapping(Idx).isValid() &&
596  "We must have a mapping for reg operands");
597  const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
598  (void)MOMapping;
599  // Register size in bits.
600  // This size must match what the mapping expects.
601  assert(MOMapping.verify(RBI->getSizeInBits(
602  Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
603  "Value mapping is invalid");
604  }
605  return true;
606 }
607 
608 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
610  print(dbgs());
611  dbgs() << '\n';
612 }
613 #endif
614 
616  OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
617 
618  for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
619  const ValueMapping &ValMapping = getOperandMapping(OpIdx);
620  if (OpIdx)
621  OS << ", ";
622  OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
623  }
624 }
625 
626 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
627 
629  MachineInstr &MI, const InstructionMapping &InstrMapping,
630  MachineRegisterInfo &MRI)
631  : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
632  unsigned NumOpds = InstrMapping.getNumOperands();
633  OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
634  assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
635 }
636 
638 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
639  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
640  unsigned NumPartialVal =
641  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
642  int StartIdx = OpToNewVRegIdx[OpIdx];
643 
644  if (StartIdx == OperandsMapper::DontKnowIdx) {
645  // This is the first time we try to access OpIdx.
646  // Create the cells that will hold all the partial values at the
647  // end of the list of NewVReg.
648  StartIdx = NewVRegs.size();
649  OpToNewVRegIdx[OpIdx] = StartIdx;
650  for (unsigned i = 0; i < NumPartialVal; ++i)
651  NewVRegs.push_back(0);
652  }
654  getNewVRegsEnd(StartIdx, NumPartialVal);
655 
656  return make_range(&NewVRegs[StartIdx], End);
657 }
658 
660 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
661  unsigned NumVal) const {
662  return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
663 }
665 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
666  unsigned NumVal) {
667  assert((NewVRegs.size() == StartIdx + NumVal ||
668  NewVRegs.size() > StartIdx + NumVal) &&
669  "NewVRegs too small to contain all the partial mapping");
670  return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
671  : &NewVRegs[StartIdx + NumVal];
672 }
673 
675  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
677  getVRegsMem(OpIdx);
678  const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
679  const PartialMapping *PartMap = ValMapping.begin();
680  for (unsigned &NewVReg : NewVRegsForOpIdx) {
681  assert(PartMap != ValMapping.end() && "Out-of-bound access");
682  assert(NewVReg == 0 && "Register has already been created");
683  // The new registers are always bound to scalar with the right size.
684  // The actual type has to be set when the target does the mapping
685  // of the instruction.
686  // The rationale is that this generic code cannot guess how the
687  // target plans to split the input type.
688  NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
689  MRI.setRegBank(NewVReg, *PartMap->RegBank);
690  ++PartMap;
691  }
692 }
693 
695  unsigned PartialMapIdx,
696  unsigned NewVReg) {
697  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
698  assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
699  PartialMapIdx &&
700  "Out-of-bound access for partial mapping");
701  // Make sure the memory is initialized for that operand.
702  (void)getVRegsMem(OpIdx);
703  assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
704  "This value is already set");
705  NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
706 }
707 
710  bool ForDebug) const {
711  (void)ForDebug;
712  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
713  int StartIdx = OpToNewVRegIdx[OpIdx];
714 
715  if (StartIdx == OperandsMapper::DontKnowIdx)
716  return make_range(NewVRegs.end(), NewVRegs.end());
717 
718  unsigned PartMapSize =
719  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
721  getNewVRegsEnd(StartIdx, PartMapSize);
723  make_range(&NewVRegs[StartIdx], End);
724 #ifndef NDEBUG
725  for (unsigned VReg : Res)
726  assert((VReg || ForDebug) && "Some registers are uninitialized");
727 #endif
728  return Res;
729 }
730 
731 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
733  print(dbgs(), true);
734  dbgs() << '\n';
735 }
736 #endif
737 
739  bool ForDebug) const {
740  unsigned NumOpds = getInstrMapping().getNumOperands();
741  if (ForDebug) {
742  OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
743  // Print out the internal state of the index table.
744  OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
745  bool IsFirst = true;
746  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
747  if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
748  if (!IsFirst)
749  OS << ", ";
750  OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
751  IsFirst = false;
752  }
753  }
754  OS << '\n';
755  } else
756  OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
757 
758  OS << "Operand Mapping: ";
759  // If we have a function, we can pretty print the name of the registers.
760  // Otherwise we will print the raw numbers.
761  const TargetRegisterInfo *TRI =
762  getMI().getParent() && getMI().getMF()
764  : nullptr;
765  bool IsFirst = true;
766  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
767  if (OpToNewVRegIdx[Idx] == DontKnowIdx)
768  continue;
769  if (!IsFirst)
770  OS << ", ";
771  IsFirst = false;
772  OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
773  bool IsFirstNewVReg = true;
774  for (unsigned VReg : getVRegs(Idx)) {
775  if (!IsFirstNewVReg)
776  OS << ", ";
777  IsFirstNewVReg = false;
778  OS << printReg(VReg, TRI);
779  }
780  OS << "])";
781  }
782 }
unsigned NumRegBanks
Total number of register banks.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank ** RegBanks
Hold the set of supported register banks.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void print(raw_ostream &OS) const
Print this on OS;.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:473
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:190
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void dump() const
Print this on dbgs() stream.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
bool isRegSequence() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool isPHI() const
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
void dump() const
Print this partial mapping on dbgs() stream.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
void dump() const
Print this operands mapper on dbgs() stream.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4433
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
static bool isCopyLike(const MachineInstr &MI)
Check whether or not MI should be treated like a copy for the mappings.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:141
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping * end() const
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
void print(raw_ostream &OS) const
Print this on OS;.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
A range adaptor for a pair of iterators.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:600
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:478
An opaque object representing a hash code.
Definition: Hashing.h:71
const PartialMapping * begin() const
Iterators through the PartialMappings.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:606
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
uint32_t Size
Definition: Profile.cpp:46
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
RegisterBankInfo()
This constructor is meaningless.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
ppc ctr loops verify
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void dump() const
Print this on dbgs() stream.
unsigned getNumOperands() const
Get the number of operands.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:86
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
void resize(size_type N)
Definition: SmallVector.h:344