LLVM  6.0.0svn
RegisterBankInfo.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBankInfo class.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Debug.h"
29 
30 #include <algorithm> // For std::max.
31 
32 #define DEBUG_TYPE "registerbankinfo"
33 
34 using namespace llvm;
35 
36 STATISTIC(NumPartialMappingsCreated,
37  "Number of partial mappings dynamically created");
38 STATISTIC(NumPartialMappingsAccessed,
39  "Number of partial mappings dynamically accessed");
40 STATISTIC(NumValueMappingsCreated,
41  "Number of value mappings dynamically created");
42 STATISTIC(NumValueMappingsAccessed,
43  "Number of value mappings dynamically accessed");
44 STATISTIC(NumOperandsMappingsCreated,
45  "Number of operands mappings dynamically created");
46 STATISTIC(NumOperandsMappingsAccessed,
47  "Number of operands mappings dynamically accessed");
48 STATISTIC(NumInstructionMappingsCreated,
49  "Number of instruction mappings dynamically created");
50 STATISTIC(NumInstructionMappingsAccessed,
51  "Number of instruction mappings dynamically accessed");
52 
53 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
54 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
55 
56 //------------------------------------------------------------------------------
57 // RegisterBankInfo implementation.
58 //------------------------------------------------------------------------------
60  unsigned NumRegBanks)
61  : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
62 #ifndef NDEBUG
63  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
64  assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
65  assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
66  }
67 #endif // NDEBUG
68 }
69 
70 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
71 #ifndef NDEBUG
72  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
73  const RegisterBank &RegBank = getRegBank(Idx);
74  assert(Idx == RegBank.getID() &&
75  "ID does not match the index in the array");
76  DEBUG(dbgs() << "Verify " << RegBank << '\n');
77  assert(RegBank.verify(TRI) && "RegBank is invalid");
78  }
79 #endif // NDEBUG
80  return true;
81 }
82 
83 const RegisterBank *
85  const TargetRegisterInfo &TRI) const {
88 
89  assert(Reg && "NoRegister does not have a register bank");
90  const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
91  if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
92  return RB;
93  if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
94  return &getRegBankFromRegClass(*RC);
95  return nullptr;
96 }
97 
98 const TargetRegisterClass &
100  const TargetRegisterInfo &TRI) const {
102  "Reg must be a physreg");
103  const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
104  if (RegRCIt != PhysRegMinimalRCs.end())
105  return *RegRCIt->second;
106  const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
107  PhysRegMinimalRCs[Reg] = PhysRC;
108  return *PhysRC;
109 }
110 
112  const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
113  const TargetRegisterInfo &TRI) const {
114  // The mapping of the registers may be available via the
115  // register class constraints.
116  const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
117 
118  if (!RC)
119  return nullptr;
120 
121  const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
122  // Sanity check that the target properly implemented getRegBankFromRegClass.
123  assert(RegBank.covers(*RC) &&
124  "The mapping of the register bank does not make sense");
125  return &RegBank;
126 }
127 
129  unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
130 
131  // If the register already has a class, fallback to MRI::constrainRegClass.
132  auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
133  if (RegClassOrBank.is<const TargetRegisterClass *>())
134  return MRI.constrainRegClass(Reg, &RC);
135 
136  const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
137  // Otherwise, all we can do is ensure the bank covers the class, and set it.
138  if (RB && !RB->covers(RC))
139  return nullptr;
140 
141  // If nothing was set or the class is simply compatible, set it.
142  MRI.setRegClass(Reg, &RC);
143  return &RC;
144 }
145 
146 /// Check whether or not \p MI should be treated like a copy
147 /// for the mappings.
148 /// Copy like instruction are special for mapping because
149 /// they don't have actual register constraints. Moreover,
150 /// they sometimes have register classes assigned and we can
151 /// just use that instead of failing to provide a generic mapping.
152 static bool isCopyLike(const MachineInstr &MI) {
153  return MI.isCopy() || MI.isPHI() ||
154  MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
155 }
156 
159  // For copies we want to walk over the operands and try to find one
160  // that has a register bank since the instruction itself will not get
161  // us any constraint.
162  bool IsCopyLike = isCopyLike(MI);
163  // For copy like instruction, only the mapping of the definition
164  // is important. The rest is not constrained.
165  unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
166 
167  const MachineFunction &MF = *MI.getMF();
168  const TargetSubtargetInfo &STI = MF.getSubtarget();
169  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
170  const MachineRegisterInfo &MRI = MF.getRegInfo();
171  // We may need to query the instruction encoding to guess the mapping.
172  const TargetInstrInfo &TII = *STI.getInstrInfo();
173 
174  // Before doing anything complicated check if the mapping is not
175  // directly available.
176  bool CompleteMapping = true;
177 
178  SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
179  for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
180  ++OpIdx) {
181  const MachineOperand &MO = MI.getOperand(OpIdx);
182  if (!MO.isReg())
183  continue;
184  unsigned Reg = MO.getReg();
185  if (!Reg)
186  continue;
187  // The register bank of Reg is just a side effect of the current
188  // excution and in particular, there is no reason to believe this
189  // is the best default mapping for the current instruction. Keep
190  // it as an alternative register bank if we cannot figure out
191  // something.
192  const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
193  // For copy-like instruction, we want to reuse the register bank
194  // that is already set on Reg, if any, since those instructions do
195  // not have any constraints.
196  const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
197  if (!CurRegBank) {
198  // If this is a target specific instruction, we can deduce
199  // the register bank from the encoding constraints.
200  CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
201  if (!CurRegBank) {
202  // All our attempts failed, give up.
203  CompleteMapping = false;
204 
205  if (!IsCopyLike)
206  // MI does not carry enough information to guess the mapping.
208  continue;
209  }
210  }
211  const ValueMapping *ValMapping =
212  &getValueMapping(0, getSizeInBits(Reg, MRI, TRI), *CurRegBank);
213  if (IsCopyLike) {
214  OperandsMapping[0] = ValMapping;
215  CompleteMapping = true;
216  break;
217  }
218  OperandsMapping[OpIdx] = ValMapping;
219  }
220 
221  if (IsCopyLike && !CompleteMapping)
222  // No way to deduce the type from what we have.
224 
225  assert(CompleteMapping && "Setting an uncomplete mapping");
226  return getInstructionMapping(
227  DefaultMappingID, /*Cost*/ 1,
228  /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
229  NumOperandsForMapping);
230 }
231 
232 /// Hashing function for PartialMapping.
233 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
234  const RegisterBank *RegBank) {
235  return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
236 }
237 
238 /// Overloaded version of hash_value for a PartialMapping.
239 hash_code
241  return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
242  PartMapping.RegBank);
243 }
244 
246 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
247  const RegisterBank &RegBank) const {
248  ++NumPartialMappingsAccessed;
249 
250  hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
251  const auto &It = MapOfPartialMappings.find(Hash);
252  if (It != MapOfPartialMappings.end())
253  return *It->second;
254 
255  ++NumPartialMappingsCreated;
256 
257  auto &PartMapping = MapOfPartialMappings[Hash];
258  PartMapping = llvm::make_unique<PartialMapping>(StartIdx, Length, RegBank);
259  return *PartMapping;
260 }
261 
263 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
264  const RegisterBank &RegBank) const {
265  return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
266 }
267 
268 static hash_code
270  unsigned NumBreakDowns) {
271  if (LLVM_LIKELY(NumBreakDowns == 1))
272  return hash_value(*BreakDown);
273  SmallVector<size_t, 8> Hashes(NumBreakDowns);
274  for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
275  Hashes.push_back(hash_value(BreakDown[Idx]));
276  return hash_combine_range(Hashes.begin(), Hashes.end());
277 }
278 
281  unsigned NumBreakDowns) const {
282  ++NumValueMappingsAccessed;
283 
284  hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
285  const auto &It = MapOfValueMappings.find(Hash);
286  if (It != MapOfValueMappings.end())
287  return *It->second;
288 
289  ++NumValueMappingsCreated;
290 
291  auto &ValMapping = MapOfValueMappings[Hash];
292  ValMapping = llvm::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
293  return *ValMapping;
294 }
295 
296 template <typename Iterator>
298 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
299 
300  ++NumOperandsMappingsAccessed;
301 
302  // The addresses of the value mapping are unique.
303  // Therefore, we can use them directly to hash the operand mapping.
304  hash_code Hash = hash_combine_range(Begin, End);
305  auto &Res = MapOfOperandsMappings[Hash];
306  if (Res)
307  return Res.get();
308 
309  ++NumOperandsMappingsCreated;
310 
311  // Create the array of ValueMapping.
312  // Note: this array will not hash to this instance of operands
313  // mapping, because we use the pointer of the ValueMapping
314  // to hash and we expect them to uniquely identify an instance
315  // of value mapping.
316  Res = llvm::make_unique<ValueMapping[]>(std::distance(Begin, End));
317  unsigned Idx = 0;
318  for (Iterator It = Begin; It != End; ++It, ++Idx) {
319  const ValueMapping *ValMap = *It;
320  if (!ValMap)
321  continue;
322  Res[Idx] = *ValMap;
323  }
324  return Res.get();
325 }
326 
329  const {
330  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
331 }
332 
334  std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
335  const {
336  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
337 }
338 
339 static hash_code
340 hashInstructionMapping(unsigned ID, unsigned Cost,
341  const RegisterBankInfo::ValueMapping *OperandsMapping,
342  unsigned NumOperands) {
343  return hash_combine(ID, Cost, OperandsMapping, NumOperands);
344 }
345 
347 RegisterBankInfo::getInstructionMappingImpl(
348  bool IsInvalid, unsigned ID, unsigned Cost,
349  const RegisterBankInfo::ValueMapping *OperandsMapping,
350  unsigned NumOperands) const {
351  assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
352  OperandsMapping == nullptr && NumOperands == 0) ||
353  !IsInvalid) &&
354  "Mismatch argument for invalid input");
355  ++NumInstructionMappingsAccessed;
356 
357  hash_code Hash =
358  hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
359  const auto &It = MapOfInstructionMappings.find(Hash);
360  if (It != MapOfInstructionMappings.end())
361  return *It->second;
362 
363  ++NumInstructionMappingsCreated;
364 
365  auto &InstrMapping = MapOfInstructionMappings[Hash];
366  if (IsInvalid)
367  InstrMapping = llvm::make_unique<InstructionMapping>();
368  else
369  InstrMapping = llvm::make_unique<InstructionMapping>(
370  ID, Cost, OperandsMapping, NumOperands);
371  return *InstrMapping;
372 }
373 
377  if (Mapping.isValid())
378  return Mapping;
379  llvm_unreachable("The target must implement this");
380 }
381 
383 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
384  InstructionMappings PossibleMappings;
385  // Put the default mapping first.
386  PossibleMappings.push_back(&getInstrMapping(MI));
387  // Then the alternative mapping, if any.
389  for (const InstructionMapping *AltMapping : AltMappings)
390  PossibleMappings.push_back(AltMapping);
391 #ifndef NDEBUG
392  for (const InstructionMapping *Mapping : PossibleMappings)
393  assert(Mapping->verify(MI) && "Mapping is invalid");
394 #endif
395  return PossibleMappings;
396 }
397 
400  // No alternative for MI.
401  return InstructionMappings();
402 }
403 
405  MachineInstr &MI = OpdMapper.getMI();
406  MachineRegisterInfo &MRI = OpdMapper.getMRI();
407  DEBUG(dbgs() << "Applying default-like mapping\n");
408  for (unsigned OpIdx = 0,
409  EndIdx = OpdMapper.getInstrMapping().getNumOperands();
410  OpIdx != EndIdx; ++OpIdx) {
411  DEBUG(dbgs() << "OpIdx " << OpIdx);
412  MachineOperand &MO = MI.getOperand(OpIdx);
413  if (!MO.isReg()) {
414  DEBUG(dbgs() << " is not a register, nothing to be done\n");
415  continue;
416  }
417  if (!MO.getReg()) {
418  DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
419  continue;
420  }
421  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
422  0 &&
423  "Invalid mapping");
424  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
425  1 &&
426  "This mapping is too complex for this function");
428  OpdMapper.getVRegs(OpIdx);
429  if (NewRegs.begin() == NewRegs.end()) {
430  DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
431  continue;
432  }
433  unsigned OrigReg = MO.getReg();
434  unsigned NewReg = *NewRegs.begin();
435  DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr));
436  MO.setReg(NewReg);
437  DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr));
438 
439  // The OperandsMapper creates plain scalar, we may have to fix that.
440  // Check if the types match and if not, fix that.
441  LLT OrigTy = MRI.getType(OrigReg);
442  LLT NewTy = MRI.getType(NewReg);
443  if (OrigTy != NewTy) {
444  // The default mapping is not supposed to change the size of
445  // the storage. However, right now we don't necessarily bump all
446  // the types to storage size. For instance, we can consider
447  // s16 G_AND legal whereas the storage size is going to be 32.
448  assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
449  "Types with difference size cannot be handled by the default "
450  "mapping");
451  DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
452  << OrigTy);
453  MRI.setType(NewReg, OrigTy);
454  }
455  DEBUG(dbgs() << '\n');
456  }
457 }
458 
459 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
460  const MachineRegisterInfo &MRI,
461  const TargetRegisterInfo &TRI) const {
462  const TargetRegisterClass *RC = nullptr;
464  // The size is not directly available for physical registers.
465  // Instead, we need to access a register class that contains Reg and
466  // get the size of that register class.
467  RC = &getMinimalPhysRegClass(Reg, TRI);
468  } else {
469  LLT Ty = MRI.getType(Reg);
470  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
471  // If Reg is not a generic register, query the register class to
472  // get its size.
473  if (RegSize)
474  return RegSize;
475  // Since Reg is not a generic register, it must have a register class.
476  RC = MRI.getRegClass(Reg);
477  }
478  assert(RC && "Unable to deduce the register class");
479  return TRI.getRegSizeInBits(*RC);
480 }
481 
482 //------------------------------------------------------------------------------
483 // Helper classes implementation.
484 //------------------------------------------------------------------------------
485 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
487  print(dbgs());
488  dbgs() << '\n';
489 }
490 #endif
491 
493  assert(RegBank && "Register bank not set");
494  assert(Length && "Empty mapping");
495  assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
496  // Check if the minimum width fits into RegBank.
497  assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
498  return true;
499 }
500 
502  OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
503  if (RegBank)
504  OS << *RegBank;
505  else
506  OS << "nullptr";
507 }
508 
509 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
510  assert(NumBreakDowns && "Value mapped nowhere?!");
511  unsigned OrigValueBitWidth = 0;
512  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
513  // Check that each register bank is big enough to hold the partial value:
514  // this check is done by PartialMapping::verify
515  assert(PartMap.verify() && "Partial mapping is invalid");
516  // The original value should completely be mapped.
517  // Thus the maximum accessed index + 1 is the size of the original value.
518  OrigValueBitWidth =
519  std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
520  }
521  assert(OrigValueBitWidth >= MeaningfulBitWidth &&
522  "Meaningful bits not covered by the mapping");
523  APInt ValueMask(OrigValueBitWidth, 0);
524  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
525  // Check that the union of the partial mappings covers the whole value,
526  // without overlaps.
527  // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
528  APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
529  PartMap.getHighBitIdx() + 1);
530  ValueMask ^= PartMapMask;
531  assert((ValueMask & PartMapMask) == PartMapMask &&
532  "Some partial mappings overlap");
533  }
534  assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
535  return true;
536 }
537 
538 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
540  print(dbgs());
541  dbgs() << '\n';
542 }
543 #endif
544 
546  OS << "#BreakDown: " << NumBreakDowns << " ";
547  bool IsFirst = true;
548  for (const PartialMapping &PartMap : *this) {
549  if (!IsFirst)
550  OS << ", ";
551  OS << '[' << PartMap << ']';
552  IsFirst = false;
553  }
554 }
555 
557  const MachineInstr &MI) const {
558  // Check that all the register operands are properly mapped.
559  // Check the constructor invariant.
560  // For PHI, we only care about mapping the definition.
561  assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
562  "NumOperands must match, see constructor");
563  assert(MI.getParent() && MI.getMF() &&
564  "MI must be connected to a MachineFunction");
565  const MachineFunction &MF = *MI.getMF();
566  const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
567  (void)RBI;
568 
569  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
570  const MachineOperand &MO = MI.getOperand(Idx);
571  if (!MO.isReg()) {
572  assert(!getOperandMapping(Idx).isValid() &&
573  "We should not care about non-reg mapping");
574  continue;
575  }
576  unsigned Reg = MO.getReg();
577  if (!Reg)
578  continue;
579  assert(getOperandMapping(Idx).isValid() &&
580  "We must have a mapping for reg operands");
581  const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
582  (void)MOMapping;
583  // Register size in bits.
584  // This size must match what the mapping expects.
585  assert(MOMapping.verify(RBI->getSizeInBits(
586  Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
587  "Value mapping is invalid");
588  }
589  return true;
590 }
591 
592 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
594  print(dbgs());
595  dbgs() << '\n';
596 }
597 #endif
598 
600  OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
601 
602  for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
603  const ValueMapping &ValMapping = getOperandMapping(OpIdx);
604  if (OpIdx)
605  OS << ", ";
606  OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
607  }
608 }
609 
610 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
611 
613  MachineInstr &MI, const InstructionMapping &InstrMapping,
614  MachineRegisterInfo &MRI)
615  : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
616  unsigned NumOpds = InstrMapping.getNumOperands();
617  OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
618  assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
619 }
620 
622 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
623  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
624  unsigned NumPartialVal =
625  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
626  int StartIdx = OpToNewVRegIdx[OpIdx];
627 
628  if (StartIdx == OperandsMapper::DontKnowIdx) {
629  // This is the first time we try to access OpIdx.
630  // Create the cells that will hold all the partial values at the
631  // end of the list of NewVReg.
632  StartIdx = NewVRegs.size();
633  OpToNewVRegIdx[OpIdx] = StartIdx;
634  for (unsigned i = 0; i < NumPartialVal; ++i)
635  NewVRegs.push_back(0);
636  }
638  getNewVRegsEnd(StartIdx, NumPartialVal);
639 
640  return make_range(&NewVRegs[StartIdx], End);
641 }
642 
644 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
645  unsigned NumVal) const {
646  return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
647 }
649 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
650  unsigned NumVal) {
651  assert((NewVRegs.size() == StartIdx + NumVal ||
652  NewVRegs.size() > StartIdx + NumVal) &&
653  "NewVRegs too small to contain all the partial mapping");
654  return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
655  : &NewVRegs[StartIdx + NumVal];
656 }
657 
659  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
661  getVRegsMem(OpIdx);
662  const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
663  const PartialMapping *PartMap = ValMapping.begin();
664  for (unsigned &NewVReg : NewVRegsForOpIdx) {
665  assert(PartMap != ValMapping.end() && "Out-of-bound access");
666  assert(NewVReg == 0 && "Register has already been created");
667  // The new registers are always bound to scalar with the right size.
668  // The actual type has to be set when the target does the mapping
669  // of the instruction.
670  // The rationale is that this generic code cannot guess how the
671  // target plans to split the input type.
672  NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
673  MRI.setRegBank(NewVReg, *PartMap->RegBank);
674  ++PartMap;
675  }
676 }
677 
679  unsigned PartialMapIdx,
680  unsigned NewVReg) {
681  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
682  assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
683  PartialMapIdx &&
684  "Out-of-bound access for partial mapping");
685  // Make sure the memory is initialized for that operand.
686  (void)getVRegsMem(OpIdx);
687  assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
688  "This value is already set");
689  NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
690 }
691 
694  bool ForDebug) const {
695  (void)ForDebug;
696  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
697  int StartIdx = OpToNewVRegIdx[OpIdx];
698 
699  if (StartIdx == OperandsMapper::DontKnowIdx)
700  return make_range(NewVRegs.end(), NewVRegs.end());
701 
702  unsigned PartMapSize =
703  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
705  getNewVRegsEnd(StartIdx, PartMapSize);
707  make_range(&NewVRegs[StartIdx], End);
708 #ifndef NDEBUG
709  for (unsigned VReg : Res)
710  assert((VReg || ForDebug) && "Some registers are uninitialized");
711 #endif
712  return Res;
713 }
714 
715 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
717  print(dbgs(), true);
718  dbgs() << '\n';
719 }
720 #endif
721 
723  bool ForDebug) const {
724  unsigned NumOpds = getInstrMapping().getNumOperands();
725  if (ForDebug) {
726  OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
727  // Print out the internal state of the index table.
728  OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
729  bool IsFirst = true;
730  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
731  if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
732  if (!IsFirst)
733  OS << ", ";
734  OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
735  IsFirst = false;
736  }
737  }
738  OS << '\n';
739  } else
740  OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
741 
742  OS << "Operand Mapping: ";
743  // If we have a function, we can pretty print the name of the registers.
744  // Otherwise we will print the raw numbers.
745  const TargetRegisterInfo *TRI =
746  getMI().getParent() && getMI().getMF()
748  : nullptr;
749  bool IsFirst = true;
750  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
751  if (OpToNewVRegIdx[Idx] == DontKnowIdx)
752  continue;
753  if (!IsFirst)
754  OS << ", ";
755  IsFirst = false;
756  OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
757  bool IsFirstNewVReg = true;
758  for (unsigned VReg : getVRegs(Idx)) {
759  if (!IsFirstNewVReg)
760  OS << ", ";
761  IsFirstNewVReg = false;
762  OS << PrintReg(VReg, TRI);
763  }
764  OS << "])";
765  }
766 }
unsigned NumRegBanks
Total number of register banks.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank ** RegBanks
Hold the set of supported register banks.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void print(raw_ostream &OS) const
Print this on OS;.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:449
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:175
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void dump() const
Print this on dbgs() stream.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
STATISTIC(NumFunctions, "Total number of functions")
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
bool isPHI() const
Definition: MachineInstr.h:826
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
void dump() const
Print this partial mapping on dbgs() stream.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Reg
All possible values of the reg field in the ModR/M byte.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
void dump() const
Print this operands mapper on dbgs() stream.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4428
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:389
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
static bool isCopyLike(const MachineInstr &MI)
Check whether or not MI should be treated like a copy for the mappings.
bool isValid() const
static const unsigned End
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:142
bool isCopy() const
Definition: MachineInstr.h:857
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping * end() const
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
void print(raw_ostream &OS) const
Print this on OS;.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
A range adaptor for a pair of iterators.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:602
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:480
An opaque object representing a hash code.
Definition: Hashing.h:72
const PartialMapping * begin() const
Iterators through the PartialMappings.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:600
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
RegisterBankInfo()
This constructor is meaningless.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
ppc ctr loops verify
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void dump() const
Print this on dbgs() stream.
unsigned getNumOperands() const
Get the number of operands.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
void resize(size_type N)
Definition: SmallVector.h:355