LLVM  7.0.0svn
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RegisterBankInfo.h File Reference
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Hashing.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
#include <initializer_list>
#include <memory>
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Classes

class  llvm::RegisterBankInfo
 Holds all the information related to register banks. More...
 
struct  llvm::RegisterBankInfo::PartialMapping
 Helper struct that represents how a value is partially mapped into a register. More...
 
struct  llvm::RegisterBankInfo::ValueMapping
 Helper struct that represents how a value is mapped through different register banks. More...
 
class  llvm::RegisterBankInfo::InstructionMapping
 Helper class that represents how the value of an instruction may be mapped and what is the related cost of such mapping. More...
 
class  llvm::RegisterBankInfo::OperandsMapper
 Helper class used to get/create the virtual registers that will be used to replace the MachineOperand when applying a mapping. More...
 
struct  PartialMapping
 Helper struct that represents how a value is partially mapped into a register. More...
 
struct  ValueMapping
 Helper struct that represents how a value is mapped through different register banks. More...
 
class  InstructionMapping
 Helper class that represents how the value of an instruction may be mapped and what is the related cost of such mapping. More...
 
class  OperandsMapper
 Helper class used to get/create the virtual registers that will be used to replace the MachineOperand when applying a mapping. More...
 

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Typedefs

using InstructionMappings = SmallVector< const InstructionMapping *, 4 >
 Convenient type to represent the alternatives for mapping an instruction. More...
 

Functions

class llvm::RegisterBankInfo llvm::ScalarAddx2 (0x00FF, GPR)
 
 RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. More...
 
 RegisterBankInfo ()
 This constructor is meaningless. More...
 
RegisterBank & getRegBank (unsigned ID)
 Get the register bank identified by ID. More...
 
const TargetRegisterClass & getMinimalPhysRegClass (unsigned Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg. More...
 
const InstructionMappinggetInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI. More...
 
const PartialMappinggetPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments. More...
 
const RegisterBank * getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. More...
 
static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping. More...
 
virtual void applyMappingImpl (const OperandsMapper &OpdMapper) const
 See ::applyMapping. More...
 
virtual ~RegisterBankInfo ()=default
 
const RegisterBank * getRegBank (unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg. More...
 
unsigned getNumRegBanks () const
 Get the total number of register banks. More...
 
virtual const RegisterBank & getRegBankFromRegClass (const TargetRegisterClass &RC) const
 Get a register bank that covers RC. More...
 
virtual unsigned copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. More...
 
static const TargetRegisterClass * constrainGenericRegister (unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC. More...
 
virtual const InstructionMappinggetInstrMapping (const MachineInstr &MI) const
 Get the mapping of the different operands of MI on the register bank. More...
 
virtual InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const
 Get the alternative mappings for MI. More...
 
class llvm::RegisterBankInfo *void llvm::applyMapping (const OperandsMapper &OpdMapper) const
 Apply OpdMapper.getInstrMapping() to OpdMapper.getMI(). More...
 
unsigned llvm::getSizeInBits (unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the size in bits of Reg. More...
 
bool llvm::verify (const TargetRegisterInfo &TRI) const
 Check that information hold by this instance make sense for the given TRI. More...
 
raw_ostream & operator<< (raw_ostream &OS, const RegisterBankInfo::PartialMapping &PartMapping)
 
raw_ostream & operator<< (raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping)
 
raw_ostream & operator<< (raw_ostream &OS, const RegisterBankInfo::InstructionMapping &InstrMapping)
 
raw_ostream & operator<< (raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper)
 
hash_code hash_value (const RegisterBankInfo::PartialMapping &PartMapping)
 Hashing function for PartialMapping. More...
 
Methods to get a uniquely generated ValueMapping.
const ValueMappinggetValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping. More...
 
const ValueMappinggetValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments. More...
 
Methods to get a uniquely generated array of ValueMapping.
template<typename Iterator >
const ValueMappinggetOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End. More...
 
const ValueMappinggetOperandsMapping (const SmallVectorImpl< const ValueMapping *> &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. More...
 
const ValueMappinggetOperandsMapping (std::initializer_list< const ValueMapping *> OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments. More...
 
Methods to get a uniquely generated InstructionMapping.
const InstructionMappinggetInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping. More...
 
const InstructionMappinggetInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping. More...
 

Variables

class llvm::RegisterBankInfo llvm::ScalarAddx2
 
RegisterBank ** RegBanks
 Hold the set of supported register banks. More...
 
unsigned NumRegBanks
 Total number of register banks. More...
 
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map. More...
 
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive. More...
 
static const unsigned DefaultMappingID
 Identifier used when the related instruction mapping instance is generated by target independent code. More...
 
static const unsigned InvalidMappingID
 Identifier used when the related instruction mapping instance is generated by the default constructor. More...
 
 VectorAdd
 Get the possible mapping for MI. More...
 
class llvm::RegisterBankInfo llvm::GPR
 

Typedef Documentation

◆ InstructionMappings

using InstructionMappings = SmallVector<const InstructionMapping *, 4>

Convenient type to represent the alternatives for mapping an instruction.

Todo:
When we move to TableGen this should be an array ref.

Definition at line 988 of file RegisterBankInfo.h.

Function Documentation

◆ applyDefaultMapping()

static void ScalarAddx2::applyDefaultMapping ( const OperandsMapper OpdMapper)
static

Helper method to apply something that is like the default mapping.

Basically, that means that OpdMapper.getMI() is left untouched aside from the reassignment of the register operand that have been remapped.

The type of all the new registers that have been created by the mapper are properly remapped to the type of the original registers they replace. In other words, the semantic of the instruction does not change, only the register banks.

If the mapping of one of the operand spans several registers, this method will abort as this is not like a default mapping anymore.

Precondition
For OpIdx in {0..OpdMapper.getMI().getNumOperands()) the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.

◆ applyMappingImpl()

virtual void ScalarAddx2::applyMappingImpl ( const OperandsMapper OpdMapper) const
virtual

See ::applyMapping.

Definition at line 1280 of file RegisterBankInfo.h.

◆ constrainGenericRegister()

static const TargetRegisterClass* ScalarAddx2::constrainGenericRegister ( unsigned  Reg,
const TargetRegisterClass &  RC,
MachineRegisterInfo &  MRI 
)
static

Constrain the (possibly generic) virtual register Reg to RC.

Precondition
Reg is a virtual register that either has a bank or a class.
Returns
The constrained register class, or nullptr if there is none.
Note
This is a generic variant of MachineRegisterInfo::constrainRegClass
Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel purpose, including non-select passes of GlobalISel

◆ copyCost()

virtual unsigned ScalarAddx2::copyCost ( const RegisterBank &  A,
const RegisterBank &  B,
unsigned  Size 
) const
virtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note
Since this is a copy, both registers have the same size.

Definition at line 1326 of file RegisterBankInfo.h.

◆ getInstrAlternativeMappings()

virtual InstructionMappings ScalarAddx2::getInstrAlternativeMappings ( const MachineInstr &  MI) const
virtual

Get the alternative mappings for MI.

Alternative in the sense different from getInstrMapping.

◆ getInstrMapping()

virtual const InstructionMapping& ScalarAddx2::getInstrMapping ( const MachineInstr &  MI) const
virtual

Get the mapping of the different operands of MI on the register bank.

This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, if MI is a vector add, the mapping should not be a scalarization of the add.

Postcondition
returnedVal.verify(MI).
Note
If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

◆ getInstrMappingImpl()

const InstructionMapping& ScalarAddx2::getInstrMappingImpl ( const MachineInstr &  MI) const
protected

Try to get the mapping of MI.

See getInstrMapping for more details on what a mapping represents.

Unlike getInstrMapping the returned InstructionMapping may be invalid (isValid() == false). This means that the target independent code is not smart enough to get the mapping of MI and thus, the target has to provide the information for MI.

This implementation is able to get the mapping of:

  • Target specific instructions by looking at the encoding constraints.
  • Any instruction if all the register operands have already been assigned a register, a register class, or a register bank.
  • Copies and phis if at least one of the operands has been assigned a register, a register class, or a register bank. In other words, this method will likely fail to find a mapping for any generic opcode that has not been lowered by target specific code.

◆ getInstructionMapping()

const InstructionMapping& ScalarAddx2::getInstructionMapping ( unsigned  ID,
unsigned  Cost,
const ValueMapping OperandsMapping,
unsigned  NumOperands 
) const

Method to get a uniquely generated InstructionMapping.

Definition at line 1238 of file RegisterBankInfo.h.

◆ getInvalidInstructionMapping()

const InstructionMapping& ScalarAddx2::getInvalidInstructionMapping ( ) const

Method to get a uniquely generated invalid InstructionMapping.

Definition at line 1246 of file RegisterBankInfo.h.

◆ getMinimalPhysRegClass()

const TargetRegisterClass& ScalarAddx2::getMinimalPhysRegClass ( unsigned  Reg,
const TargetRegisterInfo &  TRI 
) const
protected

Get the MinimalPhysRegClass for Reg.

Precondition
Reg is a physical register.

Referenced by llvm::TargetRegisterInfo::legalclasstypes_end().

◆ getNumRegBanks()

unsigned ScalarAddx2::getNumRegBanks ( ) const

Get the total number of register banks.

Definition at line 1301 of file RegisterBankInfo.h.

◆ getOperandsMapping() [1/3]

template<typename Iterator >
const ValueMapping* ScalarAddx2::getOperandsMapping ( Iterator  Begin,
Iterator  End 
) const
protected

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

Elements that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

Precondition
The pointers on ValueMapping between Begin and End must uniquely identify a ValueMapping. Otherwise, there is no guarantee that the return instance will be unique, i.e., another OperandsMapping could have the same content.

◆ getOperandsMapping() [2/3]

const ValueMapping* ScalarAddx2::getOperandsMapping ( const SmallVectorImpl< const ValueMapping *> &  OpdsMapping) const
protected

Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.

Elements of OpdsMapping that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

◆ getOperandsMapping() [3/3]

const ValueMapping* ScalarAddx2::getOperandsMapping ( std::initializer_list< const ValueMapping *>  OpdsMapping) const
protected

Get the uniquely generated array of ValueMapping for the given arguments.

Arguments that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

◆ getPartialMapping()

const PartialMapping& ScalarAddx2::getPartialMapping ( unsigned  StartIdx,
unsigned  Length,
const RegisterBank &  RegBank 
) const
protected

Get the uniquely generated PartialMapping for the given arguments.

◆ getRegBank() [1/2]

const RegisterBank & getRegBank ( unsigned  ID)
protected

Get the register bank identified by ID.

Definition at line 1144 of file RegisterBankInfo.h.

◆ getRegBank() [2/2]

const RegisterBank* ScalarAddx2::getRegBank ( unsigned  Reg,
const MachineRegisterInfo &  MRI,
const TargetRegisterInfo &  TRI 
) const

Get the register bank of Reg.

If Reg has not been assigned a register, a register class, or a register bank, then this returns nullptr.

Precondition
Reg != 0 (NoRegister)

◆ getRegBankFromConstraints()

const RegisterBank* ScalarAddx2::getRegBankFromConstraints ( const MachineInstr &  MI,
unsigned  OpIdx,
const TargetInstrInfo &  TII,
const TargetRegisterInfo &  TRI 
) const

Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.

Returns
A register bank that covers the register class of the related encoding constraints or nullptr if MI did not provide enough information to deduce it.

◆ getRegBankFromRegClass()

virtual const RegisterBank& ScalarAddx2::getRegBankFromRegClass ( const TargetRegisterClass &  RC) const
virtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo:
This should be TableGen'ed.

Definition at line 1316 of file RegisterBankInfo.h.

◆ getValueMapping() [1/2]

const ValueMapping& ScalarAddx2::getValueMapping ( unsigned  StartIdx,
unsigned  Length,
const RegisterBank &  RegBank 
) const
protected

◆ getValueMapping() [2/2]

const ValueMapping& ScalarAddx2::getValueMapping ( const PartialMapping BreakDown,
unsigned  NumBreakDowns 
) const
protected

Get the ValueMapping for the given arguments.

◆ hash_value()

hash_code hash_value ( const RegisterBankInfo::PartialMapping &  PartMapping)

Hashing function for PartialMapping.

It is required for the hashing of ValueMapping.

Referenced by llvm::hashing::detail::get_hashable_data().

◆ operator<<() [1/4]

raw_ostream& operator<< ( raw_ostream &  OS,
const RegisterBankInfo::PartialMapping &  PartMapping 
)
inline

Definition at line 726 of file RegisterBankInfo.h.

◆ operator<<() [2/4]

raw_ostream& operator<< ( raw_ostream &  OS,
const RegisterBankInfo::ValueMapping &  ValMapping 
)
inline

Definition at line 733 of file RegisterBankInfo.h.

◆ operator<<() [3/4]

raw_ostream& operator<< ( raw_ostream &  OS,
const RegisterBankInfo::InstructionMapping &  InstrMapping 
)
inline

Definition at line 739 of file RegisterBankInfo.h.

◆ operator<<() [4/4]

raw_ostream& operator<< ( raw_ostream &  OS,
const RegisterBankInfo::OperandsMapper &  OpdMapper 
)
inline

Definition at line 746 of file RegisterBankInfo.h.

References llvm::hash_value().

◆ RegisterBankInfo() [1/2]

ScalarAddx2::RegisterBankInfo ( RegisterBank **  RegBanks,
unsigned  NumRegBanks 
)
protected

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

◆ RegisterBankInfo() [2/2]

ScalarAddx2::RegisterBankInfo ( )
protected

This constructor is meaningless.

It just provides a default constructor that can be used at link time when GlobalISel is not built. That way, targets can still inherit from this class without doing crazy gymnastic to avoid link time failures.

Note
That works because the constructor is inlined.

Definition at line 1139 of file RegisterBankInfo.h.

◆ ~RegisterBankInfo()

virtual ScalarAddx2::~RegisterBankInfo ( )
virtualdefault

Variable Documentation

◆ DefaultMappingID

const unsigned DefaultMappingID
static

Identifier used when the related instruction mapping instance is generated by target independent code.

Make sure not to use that identifier to avoid possible collision.

Definition at line 1349 of file RegisterBankInfo.h.

◆ InvalidMappingID

const unsigned InvalidMappingID
static

Identifier used when the related instruction mapping instance is generated by the default constructor.

Make sure not to use that identifier.

Definition at line 1354 of file RegisterBankInfo.h.

◆ MapOfInstructionMappings

DenseMap<unsigned, std::unique_ptr<const InstructionMapping> > MapOfInstructionMappings
mutableprotected

Keep dynamically allocated InstructionMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 1123 of file RegisterBankInfo.h.

◆ MapOfOperandsMappings

DenseMap<unsigned, std::unique_ptr<ValueMapping[]> > MapOfOperandsMappings
mutableprotected

Keep dynamically allocated array of ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 1118 of file RegisterBankInfo.h.

◆ MapOfPartialMappings

DenseMap<unsigned, std::unique_ptr<const PartialMapping> > MapOfPartialMappings
mutableprotected

Keep dynamically allocated PartialMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 1108 of file RegisterBankInfo.h.

◆ MapOfValueMappings

DenseMap<unsigned, std::unique_ptr<const ValueMapping> > MapOfValueMappings
mutableprotected

Keep dynamically allocated ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 1113 of file RegisterBankInfo.h.

◆ NumRegBanks

unsigned NumRegBanks
protected

Total number of register banks.

Definition at line 1103 of file RegisterBankInfo.h.

◆ PhysRegMinimalRCs

DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs
mutableprotected

Getting the minimal register class of a physreg is expensive.

Cache this information as we get it.

Definition at line 1127 of file RegisterBankInfo.h.

◆ RegBanks

RegisterBank** RegBanks
protected

Hold the set of supported register banks.

Definition at line 1100 of file RegisterBankInfo.h.

◆ VectorAdd

VectorAdd

Get the possible mapping for MI.

A mapping defines where the different operands may live and at what cost. For instance, let us consider: v0(16) = G_ADD <2 x i8> v1, v2 The possible mapping could be:

{/*ID

Definition at line 1392 of file RegisterBankInfo.h.