LLVM  7.0.0svn
RegisterBank.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/Config/llvm-config.h"
16 
17 #define DEBUG_TYPE "registerbank"
18 
19 using namespace llvm;
20 
21 const unsigned RegisterBank::InvalidID = UINT_MAX;
22 
24  unsigned ID, const char *Name, unsigned Size,
25  const uint32_t *CoveredClasses, unsigned NumRegClasses)
26  : ID(ID), Name(Name), Size(Size) {
27  ContainedRegClasses.resize(NumRegClasses);
28  ContainedRegClasses.setBitsInMask(CoveredClasses);
29 }
30 
32  assert(isValid() && "Invalid register bank");
33  for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
34  const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
35 
36  if (!covers(RC))
37  continue;
38  // Verify that the register bank covers all the sub classes of the
39  // classes it covers.
40 
41  // Use a different (slow in that case) method than
42  // RegisterBankInfo to find the subclasses of RC, to make sure
43  // both agree on the covers.
44  for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
45  const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
46 
47  if (!RC.hasSubClassEq(&SubRC))
48  continue;
49 
50  // Verify that the Size of the register bank is big enough to cover
51  // all the register classes it covers.
52  assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
53  "Size is not big enough for all the subclasses!");
54  assert(covers(SubRC) && "Not all subclasses are covered");
55  }
56  }
57  return true;
58 }
59 
61  assert(isValid() && "RB hasn't been initialized yet");
62  return ContainedRegClasses.test(RC.getID());
63 }
64 
65 bool RegisterBank::isValid() const {
66  return ID != InvalidID && Name != nullptr && Size != 0 &&
67  // A register bank that does not cover anything is useless.
68  !ContainedRegClasses.empty();
69 }
70 
71 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
72  // There must be only one instance of a given register bank alive
73  // for the whole compilation.
74  // The RegisterBankInfo is supposed to enforce that.
75  assert((OtherRB.getID() != getID() || &OtherRB == this) &&
76  "ID does not uniquely identify a RegisterBank");
77  return &OtherRB == this;
78 }
79 
80 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
82  print(dbgs(), /* IsForDebug */ true, TRI);
83 }
84 #endif
85 
86 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
87  const TargetRegisterInfo *TRI) const {
88  OS << getName();
89  if (!IsForDebug)
90  return;
91  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
92  << "isValid:" << isValid() << '\n'
93  << "Number of Covered register classes: " << ContainedRegClasses.count()
94  << '\n';
95  // Print all the subclasses if we can.
96  // This register classes may not be properly initialized yet.
97  if (!TRI || ContainedRegClasses.empty())
98  return;
99  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
100  "TRI does not match the initialization process?");
101  bool IsFirst = true;
102  OS << "Covered register classes:\n";
103  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
104  const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
105 
106  if (!covers(RC))
107  continue;
108 
109  if (!IsFirst)
110  OS << ", ";
111  OS << TRI->getRegClassName(&RC);
112  IsFirst = false;
113  }
114 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:167
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
bool test(unsigned Idx) const
Definition: BitVector.h:502
unsigned const TargetRegisterInfo * TRI
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:452
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
unsigned getID() const
Return the register class ID number.
unsigned getNumRegClasses() const
RegisterBank(unsigned ID, const char *Name, unsigned Size, const uint32_t *CoveredClasses, unsigned NumRegClasses)
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
bool isValid() const
Check whether this instance is ready to be used.
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
This class implements the register bank concept.
Definition: RegisterBank.h:29
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:55
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:759
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48