LLVM  9.0.0svn
RegisterBank.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the RegisterBank class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/Config/llvm-config.h"
15 
16 #define DEBUG_TYPE "registerbank"
17 
18 using namespace llvm;
19 
20 const unsigned RegisterBank::InvalidID = UINT_MAX;
21 
23  unsigned ID, const char *Name, unsigned Size,
24  const uint32_t *CoveredClasses, unsigned NumRegClasses)
25  : ID(ID), Name(Name), Size(Size) {
26  ContainedRegClasses.resize(NumRegClasses);
27  ContainedRegClasses.setBitsInMask(CoveredClasses);
28 }
29 
31  assert(isValid() && "Invalid register bank");
32  for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
33  const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
34 
35  if (!covers(RC))
36  continue;
37  // Verify that the register bank covers all the sub classes of the
38  // classes it covers.
39 
40  // Use a different (slow in that case) method than
41  // RegisterBankInfo to find the subclasses of RC, to make sure
42  // both agree on the covers.
43  for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
44  const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
45 
46  if (!RC.hasSubClassEq(&SubRC))
47  continue;
48 
49  // Verify that the Size of the register bank is big enough to cover
50  // all the register classes it covers.
51  assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
52  "Size is not big enough for all the subclasses!");
53  assert(covers(SubRC) && "Not all subclasses are covered");
54  }
55  }
56  return true;
57 }
58 
60  assert(isValid() && "RB hasn't been initialized yet");
61  return ContainedRegClasses.test(RC.getID());
62 }
63 
64 bool RegisterBank::isValid() const {
65  return ID != InvalidID && Name != nullptr && Size != 0 &&
66  // A register bank that does not cover anything is useless.
67  !ContainedRegClasses.empty();
68 }
69 
70 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
71  // There must be only one instance of a given register bank alive
72  // for the whole compilation.
73  // The RegisterBankInfo is supposed to enforce that.
74  assert((OtherRB.getID() != getID() || &OtherRB == this) &&
75  "ID does not uniquely identify a RegisterBank");
76  return &OtherRB == this;
77 }
78 
79 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
81  print(dbgs(), /* IsForDebug */ true, TRI);
82 }
83 #endif
84 
85 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
86  const TargetRegisterInfo *TRI) const {
87  OS << getName();
88  if (!IsForDebug)
89  return;
90  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
91  << "isValid:" << isValid() << '\n'
92  << "Number of Covered register classes: " << ContainedRegClasses.count()
93  << '\n';
94  // Print all the subclasses if we can.
95  // This register classes may not be properly initialized yet.
96  if (!TRI || ContainedRegClasses.empty())
97  return;
98  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
99  "TRI does not match the initialization process?");
100  bool IsFirst = true;
101  OS << "Covered register classes:\n";
102  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
103  const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
104 
105  if (!covers(RC))
106  continue;
107 
108  if (!IsFirst)
109  OS << ", ";
110  OS << TRI->getRegClassName(&RC);
111  IsFirst = false;
112  }
113 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:371
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:473
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:166
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
bool test(unsigned Idx) const
Definition: BitVector.h:501
unsigned const TargetRegisterInfo * TRI
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
unsigned getID() const
Return the register class ID number.
unsigned getNumRegClasses() const
RegisterBank(unsigned ID, const char *Name, unsigned Size, const uint32_t *CoveredClasses, unsigned NumRegClasses)
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
bool isValid() const
Check whether this instance is ready to be used.
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
This class implements the register bank concept.
Definition: RegisterBank.h:28
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
uint32_t Size
Definition: Profile.cpp:46
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47