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RuntimeDyldMachOAArch64.h
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1 //===-- RuntimeDyldMachOAArch64.h -- MachO/AArch64 specific code. -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDMACHOAARCH64_H
11 #define LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDMACHOAARCH64_H
12 
13 #include "../RuntimeDyldMachO.h"
14 #include "llvm/Support/Endian.h"
15 
16 #define DEBUG_TYPE "dyld"
17 
18 namespace llvm {
19 
21  : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOAArch64> {
22 public:
23 
24  typedef uint64_t TargetPtrT;
25 
28  : RuntimeDyldMachOCRTPBase(MM, Resolver) {}
29 
30  unsigned getMaxStubSize() override { return 8; }
31 
32  unsigned getStubAlignment() override { return 8; }
33 
34  /// Extract the addend encoded in the instruction / memory location.
35  int64_t decodeAddend(const RelocationEntry &RE) const {
37  uint8_t *LocalAddress = Section.getAddressWithOffset(RE.Offset);
38  unsigned NumBytes = 1 << RE.Size;
39  int64_t Addend = 0;
40  // Verify that the relocation has the correct size and alignment.
41  switch (RE.RelType) {
42  default:
43  llvm_unreachable("Unsupported relocation type!");
45  assert((NumBytes == 4 || NumBytes == 8) && "Invalid relocation size.");
46  break;
52  assert(NumBytes == 4 && "Invalid relocation size.");
53  assert((((uintptr_t)LocalAddress & 0x3) == 0) &&
54  "Instruction address is not aligned to 4 bytes.");
55  break;
56  }
57 
58  switch (RE.RelType) {
59  default:
60  llvm_unreachable("Unsupported relocation type!");
62  // This could be an unaligned memory location.
63  if (NumBytes == 4)
64  Addend = *reinterpret_cast<support::ulittle32_t *>(LocalAddress);
65  else
66  Addend = *reinterpret_cast<support::ulittle64_t *>(LocalAddress);
67  break;
69  // Verify that the relocation points to the expected branch instruction.
70  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
71  assert((*p & 0xFC000000) == 0x14000000 && "Expected branch instruction.");
72 
73  // Get the 26 bit addend encoded in the branch instruction and sign-extend
74  // to 64 bit. The lower 2 bits are always zeros and are therefore implicit
75  // (<< 2).
76  Addend = (*p & 0x03FFFFFF) << 2;
77  Addend = SignExtend64(Addend, 28);
78  break;
79  }
82  // Verify that the relocation points to the expected adrp instruction.
83  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
84  assert((*p & 0x9F000000) == 0x90000000 && "Expected adrp instruction.");
85 
86  // Get the 21 bit addend encoded in the adrp instruction and sign-extend
87  // to 64 bit. The lower 12 bits (4096 byte page) are always zeros and are
88  // therefore implicit (<< 12).
89  Addend = ((*p & 0x60000000) >> 29) | ((*p & 0x01FFFFE0) >> 3) << 12;
90  Addend = SignExtend64(Addend, 33);
91  break;
92  }
94  // Verify that the relocation points to one of the expected load / store
95  // instructions.
96  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
97  (void)p;
98  assert((*p & 0x3B000000) == 0x39000000 &&
99  "Only expected load / store instructions.");
101  }
103  // Verify that the relocation points to one of the expected load / store
104  // or add / sub instructions.
105  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
106  assert((((*p & 0x3B000000) == 0x39000000) ||
107  ((*p & 0x11C00000) == 0x11000000) ) &&
108  "Expected load / store or add/sub instruction.");
109 
110  // Get the 12 bit addend encoded in the instruction.
111  Addend = (*p & 0x003FFC00) >> 10;
112 
113  // Check which instruction we are decoding to obtain the implicit shift
114  // factor of the instruction.
115  int ImplicitShift = 0;
116  if ((*p & 0x3B000000) == 0x39000000) { // << load / store
117  // For load / store instructions the size is encoded in bits 31:30.
118  ImplicitShift = ((*p >> 30) & 0x3);
119  if (ImplicitShift == 0) {
120  // Check if this a vector op to get the correct shift value.
121  if ((*p & 0x04800000) == 0x04800000)
122  ImplicitShift = 4;
123  }
124  }
125  // Compensate for implicit shift.
126  Addend <<= ImplicitShift;
127  break;
128  }
129  }
130  return Addend;
131  }
132 
133  /// Extract the addend encoded in the instruction.
134  void encodeAddend(uint8_t *LocalAddress, unsigned NumBytes,
135  MachO::RelocationInfoType RelType, int64_t Addend) const {
136  // Verify that the relocation has the correct alignment.
137  switch (RelType) {
138  default:
139  llvm_unreachable("Unsupported relocation type!");
141  assert((NumBytes == 4 || NumBytes == 8) && "Invalid relocation size.");
142  break;
148  assert(NumBytes == 4 && "Invalid relocation size.");
149  assert((((uintptr_t)LocalAddress & 0x3) == 0) &&
150  "Instruction address is not aligned to 4 bytes.");
151  break;
152  }
153 
154  switch (RelType) {
155  default:
156  llvm_unreachable("Unsupported relocation type!");
158  // This could be an unaligned memory location.
159  if (NumBytes == 4)
160  *reinterpret_cast<support::ulittle32_t *>(LocalAddress) = Addend;
161  else
162  *reinterpret_cast<support::ulittle64_t *>(LocalAddress) = Addend;
163  break;
165  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
166  // Verify that the relocation points to the expected branch instruction.
167  assert((*p & 0xFC000000) == 0x14000000 && "Expected branch instruction.");
168 
169  // Verify addend value.
170  assert((Addend & 0x3) == 0 && "Branch target is not aligned");
171  assert(isInt<28>(Addend) && "Branch target is out of range.");
172 
173  // Encode the addend as 26 bit immediate in the branch instruction.
174  *p = (*p & 0xFC000000) | ((uint32_t)(Addend >> 2) & 0x03FFFFFF);
175  break;
176  }
179  // Verify that the relocation points to the expected adrp instruction.
180  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
181  assert((*p & 0x9F000000) == 0x90000000 && "Expected adrp instruction.");
182 
183  // Check that the addend fits into 21 bits (+ 12 lower bits).
184  assert((Addend & 0xFFF) == 0 && "ADRP target is not page aligned.");
185  assert(isInt<33>(Addend) && "Invalid page reloc value.");
186 
187  // Encode the addend into the instruction.
188  uint32_t ImmLoValue = ((uint64_t)Addend << 17) & 0x60000000;
189  uint32_t ImmHiValue = ((uint64_t)Addend >> 9) & 0x00FFFFE0;
190  *p = (*p & 0x9F00001F) | ImmHiValue | ImmLoValue;
191  break;
192  }
194  // Verify that the relocation points to one of the expected load / store
195  // instructions.
196  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
197  assert((*p & 0x3B000000) == 0x39000000 &&
198  "Only expected load / store instructions.");
199  (void)p;
201  }
203  // Verify that the relocation points to one of the expected load / store
204  // or add / sub instructions.
205  auto *p = reinterpret_cast<support::aligned_ulittle32_t *>(LocalAddress);
206  assert((((*p & 0x3B000000) == 0x39000000) ||
207  ((*p & 0x11C00000) == 0x11000000) ) &&
208  "Expected load / store or add/sub instruction.");
209 
210  // Check which instruction we are decoding to obtain the implicit shift
211  // factor of the instruction and verify alignment.
212  int ImplicitShift = 0;
213  if ((*p & 0x3B000000) == 0x39000000) { // << load / store
214  // For load / store instructions the size is encoded in bits 31:30.
215  ImplicitShift = ((*p >> 30) & 0x3);
216  switch (ImplicitShift) {
217  case 0:
218  // Check if this a vector op to get the correct shift value.
219  if ((*p & 0x04800000) == 0x04800000) {
220  ImplicitShift = 4;
221  assert(((Addend & 0xF) == 0) &&
222  "128-bit LDR/STR not 16-byte aligned.");
223  }
224  break;
225  case 1:
226  assert(((Addend & 0x1) == 0) && "16-bit LDR/STR not 2-byte aligned.");
227  break;
228  case 2:
229  assert(((Addend & 0x3) == 0) && "32-bit LDR/STR not 4-byte aligned.");
230  break;
231  case 3:
232  assert(((Addend & 0x7) == 0) && "64-bit LDR/STR not 8-byte aligned.");
233  break;
234  }
235  }
236  // Compensate for implicit shift.
237  Addend >>= ImplicitShift;
238  assert(isUInt<12>(Addend) && "Addend cannot be encoded.");
239 
240  // Encode the addend into the instruction.
241  *p = (*p & 0xFFC003FF) | ((uint32_t)(Addend << 10) & 0x003FFC00);
242  break;
243  }
244  }
245  }
246 
248  processRelocationRef(unsigned SectionID, relocation_iterator RelI,
249  const ObjectFile &BaseObjT,
250  ObjSectionToIDMap &ObjSectionToID,
251  StubMap &Stubs) override {
252  const MachOObjectFile &Obj =
253  static_cast<const MachOObjectFile &>(BaseObjT);
255  Obj.getRelocation(RelI->getRawDataRefImpl());
256 
257  if (Obj.isRelocationScattered(RelInfo))
258  return make_error<RuntimeDyldError>("Scattered relocations not supported "
259  "for MachO AArch64");
260 
261  // ARM64 has an ARM64_RELOC_ADDEND relocation type that carries an explicit
262  // addend for the following relocation. If found: (1) store the associated
263  // addend, (2) consume the next relocation, and (3) use the stored addend to
264  // override the addend.
265  int64_t ExplicitAddend = 0;
266  if (Obj.getAnyRelocationType(RelInfo) == MachO::ARM64_RELOC_ADDEND) {
267  assert(!Obj.getPlainRelocationExternal(RelInfo));
268  assert(!Obj.getAnyRelocationPCRel(RelInfo));
269  assert(Obj.getAnyRelocationLength(RelInfo) == 2);
270  int64_t RawAddend = Obj.getPlainRelocationSymbolNum(RelInfo);
271  // Sign-extend the 24-bit to 64-bit.
272  ExplicitAddend = SignExtend64(RawAddend, 24);
273  ++RelI;
274  RelInfo = Obj.getRelocation(RelI->getRawDataRefImpl());
275  }
276 
278  return processSubtractRelocation(SectionID, RelI, Obj, ObjSectionToID);
279 
280  RelocationEntry RE(getRelocationEntry(SectionID, Obj, RelI));
281  RE.Addend = decodeAddend(RE);
282 
283  assert((ExplicitAddend == 0 || RE.Addend == 0) && "Relocation has "\
284  "ARM64_RELOC_ADDEND and embedded addend in the instruction.");
285  if (ExplicitAddend)
286  RE.Addend = ExplicitAddend;
287 
289  if (auto ValueOrErr = getRelocationValueRef(Obj, RelI, RE, ObjSectionToID))
290  Value = *ValueOrErr;
291  else
292  return ValueOrErr.takeError();
293 
294  bool IsExtern = Obj.getPlainRelocationExternal(RelInfo);
295  if (!IsExtern && RE.IsPCRel)
296  makeValueAddendPCRel(Value, RelI, 1 << RE.Size);
297 
298  RE.Addend = Value.Offset;
299 
302  processGOTRelocation(RE, Value, Stubs);
303  else {
304  if (Value.SymbolName)
306  else
308  }
309 
310  return ++RelI;
311  }
312 
313  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
314  DEBUG(dumpRelocationToResolve(RE, Value));
315 
316  const SectionEntry &Section = Sections[RE.SectionID];
317  uint8_t *LocalAddress = Section.getAddressWithOffset(RE.Offset);
318  MachO::RelocationInfoType RelType =
319  static_cast<MachO::RelocationInfoType>(RE.RelType);
320 
321  switch (RelType) {
322  default:
323  llvm_unreachable("Invalid relocation type!");
325  assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_UNSIGNED not supported");
326  // Mask in the target value a byte at a time (we don't have an alignment
327  // guarantee for the target address, so this is safest).
328  if (RE.Size < 2)
329  llvm_unreachable("Invalid size for ARM64_RELOC_UNSIGNED");
330 
331  encodeAddend(LocalAddress, 1 << RE.Size, RelType, Value + RE.Addend);
332  break;
333  }
335  assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_BRANCH26 not supported");
336  // Check if branch is in range.
337  uint64_t FinalAddress = Section.getLoadAddressWithOffset(RE.Offset);
338  int64_t PCRelVal = Value - FinalAddress + RE.Addend;
339  encodeAddend(LocalAddress, /*Size=*/4, RelType, PCRelVal);
340  break;
341  }
344  assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_PAGE21 not supported");
345  // Adjust for PC-relative relocation and offset.
346  uint64_t FinalAddress = Section.getLoadAddressWithOffset(RE.Offset);
347  int64_t PCRelVal =
348  ((Value + RE.Addend) & (-4096)) - (FinalAddress & (-4096));
349  encodeAddend(LocalAddress, /*Size=*/4, RelType, PCRelVal);
350  break;
351  }
354  assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_PAGEOFF21 not supported");
355  // Add the offset from the symbol.
356  Value += RE.Addend;
357  // Mask out the page address and only use the lower 12 bits.
358  Value &= 0xFFF;
359  encodeAddend(LocalAddress, /*Size=*/4, RelType, Value);
360  break;
361  }
363  uint64_t SectionABase = Sections[RE.Sections.SectionA].getLoadAddress();
364  uint64_t SectionBBase = Sections[RE.Sections.SectionB].getLoadAddress();
365  assert((Value == SectionABase || Value == SectionBBase) &&
366  "Unexpected SUBTRACTOR relocation value.");
367  Value = SectionABase - SectionBBase + RE.Addend;
368  writeBytesUnaligned(Value, LocalAddress, 1 << RE.Size);
369  break;
370  }
374  llvm_unreachable("Relocation type not yet implemented!");
376  llvm_unreachable("ARM64_RELOC_ADDEND should have been handeled by "
377  "processRelocationRef!");
378  }
379  }
380 
381  Error finalizeSection(const ObjectFile &Obj, unsigned SectionID,
382  const SectionRef &Section) {
383  return Error::success();
384  }
385 
386 private:
387  void processGOTRelocation(const RelocationEntry &RE,
388  RelocationValueRef &Value, StubMap &Stubs) {
389  assert(RE.Size == 2);
391  StubMap::const_iterator i = Stubs.find(Value);
392  int64_t Offset;
393  if (i != Stubs.end())
394  Offset = static_cast<int64_t>(i->second);
395  else {
396  // FIXME: There must be a better way to do this then to check and fix the
397  // alignment every time!!!
398  uintptr_t BaseAddress = uintptr_t(Section.getAddress());
399  uintptr_t StubAlignment = getStubAlignment();
400  uintptr_t StubAddress =
401  (BaseAddress + Section.getStubOffset() + StubAlignment - 1) &
402  -StubAlignment;
403  unsigned StubOffset = StubAddress - BaseAddress;
404  Stubs[Value] = StubOffset;
405  assert(((StubAddress % getStubAlignment()) == 0) &&
406  "GOT entry not aligned");
407  RelocationEntry GOTRE(RE.SectionID, StubOffset,
409  /*IsPCRel=*/false, /*Size=*/3);
410  if (Value.SymbolName)
411  addRelocationForSymbol(GOTRE, Value.SymbolName);
412  else
413  addRelocationForSection(GOTRE, Value.SectionID);
415  Offset = static_cast<int64_t>(StubOffset);
416  }
417  RelocationEntry TargetRE(RE.SectionID, RE.Offset, RE.RelType, Offset,
418  RE.IsPCRel, RE.Size);
419  addRelocationForSection(TargetRE, RE.SectionID);
420  }
421 
423  processSubtractRelocation(unsigned SectionID, relocation_iterator RelI,
424  const ObjectFile &BaseObjT,
425  ObjSectionToIDMap &ObjSectionToID) {
426  const MachOObjectFile &Obj =
427  static_cast<const MachOObjectFile&>(BaseObjT);
429  Obj.getRelocation(RelI->getRawDataRefImpl());
430 
431  unsigned Size = Obj.getAnyRelocationLength(RE);
432  uint64_t Offset = RelI->getOffset();
433  uint8_t *LocalAddress = Sections[SectionID].getAddressWithOffset(Offset);
434  unsigned NumBytes = 1 << Size;
435 
436  Expected<StringRef> SubtrahendNameOrErr = RelI->getSymbol()->getName();
437  if (!SubtrahendNameOrErr)
438  return SubtrahendNameOrErr.takeError();
439  auto SubtrahendI = GlobalSymbolTable.find(*SubtrahendNameOrErr);
440  unsigned SectionBID = SubtrahendI->second.getSectionID();
441  uint64_t SectionBOffset = SubtrahendI->second.getOffset();
442  int64_t Addend =
443  SignExtend64(readBytesUnaligned(LocalAddress, NumBytes), NumBytes * 8);
444 
445  ++RelI;
446  Expected<StringRef> MinuendNameOrErr = RelI->getSymbol()->getName();
447  if (!MinuendNameOrErr)
448  return MinuendNameOrErr.takeError();
449  auto MinuendI = GlobalSymbolTable.find(*MinuendNameOrErr);
450  unsigned SectionAID = MinuendI->second.getSectionID();
451  uint64_t SectionAOffset = MinuendI->second.getOffset();
452 
453  RelocationEntry R(SectionID, Offset, MachO::ARM64_RELOC_SUBTRACTOR, (uint64_t)Addend,
454  SectionAID, SectionAOffset, SectionBID, SectionBOffset,
455  false, Size);
456 
457  addRelocationForSection(R, SectionAID);
458 
459  return ++RelI;
460  }
461 
462 };
463 }
464 
465 #undef DEBUG_TYPE
466 
467 #endif
RelocationEntry - used to represent relocations internally in the dynamic linker. ...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getAnyRelocationPCRel(const MachO::any_relocation_info &RE) const
uint64_t readBytesUnaligned(uint8_t *Src, unsigned Size) const
Endian-aware read Read the least significant Size bytes from Src.
uint64_t getLoadAddressWithOffset(unsigned OffsetBytes) const
Return the load address of this section with an offset.
Expected< relocation_iterator > processRelocationRef(unsigned SectionID, relocation_iterator RelI, const ObjectFile &BaseObjT, ObjSectionToIDMap &ObjSectionToID, StubMap &Stubs) override
Parses one or more object file relocations (some object files use relocation pairs) and stores it to ...
bool getPlainRelocationExternal(const MachO::any_relocation_info &RE) const
iterator find(StringRef Key)
Definition: StringMap.h:337
void dumpRelocationToResolve(const RelocationEntry &RE, uint64_t Value) const
Dump information about the relocation entry (RE) and resolved value.
This class is the base class for all object file types.
Definition: ObjectFile.h:189
uint8_t * getAddress() const
Error takeError()
Take ownership of the stored error.
Definition: Error.h:537
void writeBytesUnaligned(uint64_t Value, uint8_t *Dst, unsigned Size) const
Endian-aware write.
bool IsPCRel
True if this is a PCRel relocation (MachO specific).
unsigned SectionID
SectionID - the section this relocation points to.
std::map< RelocationValueRef, uintptr_t > StubMap
Tagged union holding either a T or a Error.
Definition: CachePruning.h:23
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override
A object file specific relocation resolver.
unsigned getAnyRelocationType(const MachO::any_relocation_info &RE) const
RuntimeDyldMachOTarget - Templated base class for generic MachO linker algorithms and data structures...
Expected< RelocationValueRef > getRelocationValueRef(const ObjectFile &BaseTObj, const relocation_iterator &RI, const RelocationEntry &RE, ObjSectionToIDMap &ObjSectionToID)
Construct a RelocationValueRef representing the relocation target.
void addRelocationForSymbol(const RelocationEntry &RE, StringRef SymbolName)
Error finalizeSection(const ObjectFile &Obj, unsigned SectionID, const SectionRef &Section)
RelocationEntry getRelocationEntry(unsigned SectionID, const ObjectFile &BaseTObj, const relocation_iterator &RI) const
Given a relocation_iterator for a non-scattered relocation, construct a RelocationEntry and fill in t...
void addRelocationForSection(const RelocationEntry &RE, unsigned SectionID)
MachO::any_relocation_info getRelocation(DataRefImpl Rel) const
Symbol resolution.
Definition: JITSymbol.h:260
void encodeAddend(uint8_t *LocalAddress, unsigned NumBytes, MachO::RelocationInfoType RelType, int64_t Addend) const
Extract the addend encoded in the instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isRelocationScattered(const MachO::any_relocation_info &RE) const
static ErrorSuccess success()
Create a success value.
Definition: Error.h:313
Represents base address of the CU.
Definition: DWARFUnit.h:163
RuntimeDyldMachOAArch64(RuntimeDyld::MemoryManager &MM, JITSymbolResolver &Resolver)
int64_t Addend
Addend - the relocation addend encoded in the instruction itself.
uint32_t RelType
RelType - relocation type.
JITSymbolResolver & Resolver
uintptr_t getStubOffset() const
unsigned getAnyRelocationLength(const MachO::any_relocation_info &RE) const
uint64_t Offset
Offset - offset into the section.
std::map< SectionRef, unsigned > ObjSectionToIDMap
unsigned getPlainRelocationSymbolNum(const MachO::any_relocation_info &RE) const
uint8_t * getAddressWithOffset(unsigned OffsetBytes) const
Return the address of this section with an offset.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:741
SectionEntry - represents a section emitted into memory by the dynamic linker.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RelocationInfoType
Definition: MachO.h:392
LLVM Value Representation.
Definition: Value.h:73
int64_t decodeAddend(const RelocationEntry &RE) const
Extract the addend encoded in the instruction / memory location.
RTDyldSymbolTable GlobalSymbolTable
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
unsigned Size
The size of this relocation (MachO specific).
#define DEBUG(X)
Definition: Debug.h:118
void advanceStubOffset(unsigned StubSize)
void makeValueAddendPCRel(RelocationValueRef &Value, const relocation_iterator &RI, unsigned OffsetToNextPC)
Make the RelocationValueRef addend PC-relative.
This is a value type class that represents a single section in the list of sections in the object fil...
Definition: ObjectFile.h:80