LLVM  6.0.0svn
SIFixSGPRCopies.cpp
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1 //===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Copies from VGPR to SGPR registers are illegal and the register coalescer
12 /// will sometimes generate these illegal copies in situations like this:
13 ///
14 /// Register Class <vsrc> is the union of <vgpr> and <sgpr>
15 ///
16 /// BB0:
17 /// %vreg0 <sgpr> = SCALAR_INST
18 /// %vreg1 <vsrc> = COPY %vreg0 <sgpr>
19 /// ...
20 /// BRANCH %cond BB1, BB2
21 /// BB1:
22 /// %vreg2 <vgpr> = VECTOR_INST
23 /// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
24 /// BB2:
25 /// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
26 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
27 ///
28 ///
29 /// The coalescer will begin at BB0 and eliminate its copy, then the resulting
30 /// code will look like this:
31 ///
32 /// BB0:
33 /// %vreg0 <sgpr> = SCALAR_INST
34 /// ...
35 /// BRANCH %cond BB1, BB2
36 /// BB1:
37 /// %vreg2 <vgpr> = VECTOR_INST
38 /// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
39 /// BB2:
40 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
41 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
42 ///
43 /// Now that the result of the PHI instruction is an SGPR, the register
44 /// allocator is now forced to constrain the register class of %vreg3 to
45 /// <sgpr> so we end up with final code like this:
46 ///
47 /// BB0:
48 /// %vreg0 <sgpr> = SCALAR_INST
49 /// ...
50 /// BRANCH %cond BB1, BB2
51 /// BB1:
52 /// %vreg2 <vgpr> = VECTOR_INST
53 /// %vreg3 <sgpr> = COPY %vreg2 <vgpr>
54 /// BB2:
55 /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
56 /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
57 ///
58 /// Now this code contains an illegal copy from a VGPR to an SGPR.
59 ///
60 /// In order to avoid this problem, this pass searches for PHI instructions
61 /// which define a <vsrc> register and constrains its definition class to
62 /// <vgpr> if the user of the PHI's definition register is a vector instruction.
63 /// If the PHI's definition class is constrained to <vgpr> then the coalescer
64 /// will be unable to perform the COPY removal from the above example which
65 /// ultimately led to the creation of an illegal COPY.
66 //===----------------------------------------------------------------------===//
67 
68 #include "AMDGPU.h"
69 #include "AMDGPUSubtarget.h"
70 #include "SIInstrInfo.h"
71 #include "SIRegisterInfo.h"
72 #include "llvm/ADT/DenseSet.h"
73 #include "llvm/ADT/STLExtras.h"
74 #include "llvm/ADT/SmallSet.h"
75 #include "llvm/ADT/SmallVector.h"
85 #include "llvm/Pass.h"
86 #include "llvm/Support/CodeGen.h"
88 #include "llvm/Support/Debug.h"
91 #include <cassert>
92 #include <cstdint>
93 #include <iterator>
94 #include <list>
95 #include <map>
96 #include <tuple>
97 #include <utility>
98 
99 using namespace llvm;
100 
101 #define DEBUG_TYPE "si-fix-sgpr-copies"
102 
104  "amdgpu-enable-merge-m0",
105  cl::desc("Merge and hoist M0 initializations"),
106  cl::init(false));
107 
108 namespace {
109 
110 class SIFixSGPRCopies : public MachineFunctionPass {
112 
113 public:
114  static char ID;
115 
116  SIFixSGPRCopies() : MachineFunctionPass(ID) {}
117 
118  bool runOnMachineFunction(MachineFunction &MF) override;
119 
120  StringRef getPassName() const override { return "SI Fix SGPR copies"; }
121 
122  void getAnalysisUsage(AnalysisUsage &AU) const override {
125  AU.setPreservesCFG();
127  }
128 };
129 
130 } // end anonymous namespace
131 
132 INITIALIZE_PASS_BEGIN(SIFixSGPRCopies, DEBUG_TYPE,
133  "SI Fix SGPR copies", false, false)
136  "SI Fix SGPR copies", false, false)
137 
138 char SIFixSGPRCopies::ID = 0;
139 
140 char &llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID;
141 
143  return new SIFixSGPRCopies();
144 }
145 
146 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
148  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
149  if (!MI.getOperand(i).isReg() ||
151  continue;
152 
153  if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
154  return true;
155  }
156  return false;
157 }
158 
159 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
161  const SIRegisterInfo &TRI,
162  const MachineRegisterInfo &MRI) {
163  unsigned DstReg = Copy.getOperand(0).getReg();
164  unsigned SrcReg = Copy.getOperand(1).getReg();
165 
166  const TargetRegisterClass *SrcRC =
168  MRI.getRegClass(SrcReg) :
169  TRI.getPhysRegClass(SrcReg);
170 
171  // We don't really care about the subregister here.
172  // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
173 
174  const TargetRegisterClass *DstRC =
176  MRI.getRegClass(DstReg) :
177  TRI.getPhysRegClass(DstReg);
178 
179  return std::make_pair(SrcRC, DstRC);
180 }
181 
182 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
183  const TargetRegisterClass *DstRC,
184  const SIRegisterInfo &TRI) {
185  return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
186 }
187 
188 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
189  const TargetRegisterClass *DstRC,
190  const SIRegisterInfo &TRI) {
191  return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
192 }
193 
195  const SIRegisterInfo *TRI,
196  const SIInstrInfo *TII) {
198  auto &Src = MI.getOperand(1);
199  unsigned DstReg = MI.getOperand(0).getReg();
200  unsigned SrcReg = Src.getReg();
203  return false;
204 
205  for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
206  const auto *UseMI = MO.getParent();
207  if (UseMI == &MI)
208  continue;
209  if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
210  UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
211  !TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
212  return false;
213  }
214  // Change VGPR to SGPR destination.
215  MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
216  return true;
217 }
218 
219 // Distribute an SGPR->VGPR copy of a REG_SEQUENCE into a VGPR REG_SEQUENCE.
220 //
221 // SGPRx = ...
222 // SGPRy = REG_SEQUENCE SGPRx, sub0 ...
223 // VGPRz = COPY SGPRy
224 //
225 // ==>
226 //
227 // VGPRx = COPY SGPRx
228 // VGPRz = REG_SEQUENCE VGPRx, sub0
229 //
230 // This exposes immediate folding opportunities when materializing 64-bit
231 // immediates.
233  const SIRegisterInfo *TRI,
234  const SIInstrInfo *TII,
236  assert(MI.isRegSequence());
237 
238  unsigned DstReg = MI.getOperand(0).getReg();
239  if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
240  return false;
241 
242  if (!MRI.hasOneUse(DstReg))
243  return false;
244 
245  MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
246  if (!CopyUse.isCopy())
247  return false;
248 
249  // It is illegal to have vreg inputs to a physreg defining reg_sequence.
251  return false;
252 
253  const TargetRegisterClass *SrcRC, *DstRC;
254  std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
255 
256  if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
257  return false;
258 
259  if (tryChangeVGPRtoSGPRinCopy(CopyUse, TRI, TII))
260  return true;
261 
262  // TODO: Could have multiple extracts?
263  unsigned SubReg = CopyUse.getOperand(1).getSubReg();
264  if (SubReg != AMDGPU::NoSubRegister)
265  return false;
266 
267  MRI.setRegClass(DstReg, DstRC);
268 
269  // SGPRx = ...
270  // SGPRy = REG_SEQUENCE SGPRx, sub0 ...
271  // VGPRz = COPY SGPRy
272 
273  // =>
274  // VGPRx = COPY SGPRx
275  // VGPRz = REG_SEQUENCE VGPRx, sub0
276 
277  MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
278 
279  for (unsigned I = 1, N = MI.getNumOperands(); I != N; I += 2) {
280  unsigned SrcReg = MI.getOperand(I).getReg();
281  unsigned SrcSubReg = MI.getOperand(I).getSubReg();
282 
283  const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
284  assert(TRI->isSGPRClass(SrcRC) &&
285  "Expected SGPR REG_SEQUENCE to only have SGPR inputs");
286 
287  SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg);
288  const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC);
289 
290  unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC);
291 
292  BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
293  TmpReg)
294  .add(MI.getOperand(I));
295 
296  MI.getOperand(I).setReg(TmpReg);
297  }
298 
299  CopyUse.eraseFromParent();
300  return true;
301 }
302 
303 static bool phiHasVGPROperands(const MachineInstr &PHI,
304  const MachineRegisterInfo &MRI,
305  const SIRegisterInfo *TRI,
306  const SIInstrInfo *TII) {
307  for (unsigned i = 1; i < PHI.getNumOperands(); i += 2) {
308  unsigned Reg = PHI.getOperand(i).getReg();
309  if (TRI->hasVGPRs(MRI.getRegClass(Reg)))
310  return true;
311  }
312  return false;
313 }
314 
315 static bool phiHasBreakDef(const MachineInstr &PHI,
316  const MachineRegisterInfo &MRI,
317  SmallSet<unsigned, 8> &Visited) {
318  for (unsigned i = 1; i < PHI.getNumOperands(); i += 2) {
319  unsigned Reg = PHI.getOperand(i).getReg();
320  if (Visited.count(Reg))
321  continue;
322 
323  Visited.insert(Reg);
324 
325  MachineInstr *DefInstr = MRI.getVRegDef(Reg);
326  switch (DefInstr->getOpcode()) {
327  default:
328  break;
329  case AMDGPU::SI_BREAK:
330  case AMDGPU::SI_IF_BREAK:
331  case AMDGPU::SI_ELSE_BREAK:
332  return true;
333  case AMDGPU::PHI:
334  if (phiHasBreakDef(*DefInstr, MRI, Visited))
335  return true;
336  }
337  }
338  return false;
339 }
340 
342  const TargetRegisterInfo &TRI) {
344  E = MBB.end(); I != E; ++I) {
345  if (I->modifiesRegister(AMDGPU::EXEC, &TRI))
346  return true;
347  }
348  return false;
349 }
350 
351 static bool isSafeToFoldImmIntoCopy(const MachineInstr *Copy,
352  const MachineInstr *MoveImm,
353  const SIInstrInfo *TII,
354  unsigned &SMovOp,
355  int64_t &Imm) {
356  if (Copy->getOpcode() != AMDGPU::COPY)
357  return false;
358 
359  if (!MoveImm->isMoveImmediate())
360  return false;
361 
362  const MachineOperand *ImmOp =
363  TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0);
364  if (!ImmOp->isImm())
365  return false;
366 
367  // FIXME: Handle copies with sub-regs.
368  if (Copy->getOperand(0).getSubReg())
369  return false;
370 
371  switch (MoveImm->getOpcode()) {
372  default:
373  return false;
374  case AMDGPU::V_MOV_B32_e32:
375  SMovOp = AMDGPU::S_MOV_B32;
376  break;
377  case AMDGPU::V_MOV_B64_PSEUDO:
378  SMovOp = AMDGPU::S_MOV_B64;
379  break;
380  }
381  Imm = ImmOp->getImm();
382  return true;
383 }
384 
385 template <class UnaryPredicate>
387  const MachineBasicBlock *CutOff,
388  UnaryPredicate Predicate) {
389  if (MBB == CutOff)
390  return false;
391 
394  MBB->pred_end());
395 
396  while (!Worklist.empty()) {
397  MachineBasicBlock *MBB = Worklist.pop_back_val();
398 
399  if (!Visited.insert(MBB).second)
400  continue;
401  if (MBB == CutOff)
402  continue;
403  if (Predicate(MBB))
404  return true;
405 
406  Worklist.append(MBB->pred_begin(), MBB->pred_end());
407  }
408 
409  return false;
410 }
411 
413  const TargetRegisterInfo *TRI) {
414  return searchPredecessors(MBB, nullptr, [TRI](MachineBasicBlock *MBB) {
415  return hasTerminatorThatModifiesExec(*MBB, *TRI); });
416 }
417 
418 // Checks if there is potential path From instruction To instruction.
419 // If CutOff is specified and it sits in between of that path we ignore
420 // a higher portion of the path and report it is not reachable.
421 static bool isReachable(const MachineInstr *From,
422  const MachineInstr *To,
423  const MachineBasicBlock *CutOff,
424  MachineDominatorTree &MDT) {
425  // If either From block dominates To block or instructions are in the same
426  // block and From is higher.
427  if (MDT.dominates(From, To))
428  return true;
429 
430  const MachineBasicBlock *MBBFrom = From->getParent();
431  const MachineBasicBlock *MBBTo = To->getParent();
432  if (MBBFrom == MBBTo)
433  return false;
434 
435  // Instructions are in different blocks, do predecessor search.
436  // We should almost never get here since we do not usually produce M0 stores
437  // other than -1.
438  return searchPredecessors(MBBTo, CutOff, [MBBFrom]
439  (const MachineBasicBlock *MBB) { return MBB == MBBFrom; });
440 }
441 
442 // Hoist and merge identical SGPR initializations into a common predecessor.
443 // This is intended to combine M0 initializations, but can work with any
444 // SGPR. A VGPR cannot be processed since we cannot guarantee vector
445 // executioon.
446 static bool hoistAndMergeSGPRInits(unsigned Reg,
447  const MachineRegisterInfo &MRI,
448  MachineDominatorTree &MDT) {
449  // List of inits by immediate value.
450  using InitListMap = std::map<unsigned, std::list<MachineInstr *>>;
451  InitListMap Inits;
452  // List of clobbering instructions.
454  bool Changed = false;
455 
456  for (auto &MI : MRI.def_instructions(Reg)) {
457  MachineOperand *Imm = nullptr;
458  for (auto &MO: MI.operands()) {
459  if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
460  (!MO.isImm() && !MO.isReg()) || (MO.isImm() && Imm)) {
461  Imm = nullptr;
462  break;
463  } else if (MO.isImm())
464  Imm = &MO;
465  }
466  if (Imm)
467  Inits[Imm->getImm()].push_front(&MI);
468  else
469  Clobbers.push_back(&MI);
470  }
471 
472  for (auto &Init : Inits) {
473  auto &Defs = Init.second;
474 
475  for (auto I1 = Defs.begin(), E = Defs.end(); I1 != E; ) {
476  MachineInstr *MI1 = *I1;
477 
478  for (auto I2 = std::next(I1); I2 != E; ) {
479  MachineInstr *MI2 = *I2;
480 
481  // Check any possible interference
482  auto intereferes = [&](MachineBasicBlock::iterator From,
483  MachineBasicBlock::iterator To) -> bool {
484 
485  assert(MDT.dominates(&*To, &*From));
486 
487  auto interferes = [&MDT, From, To](MachineInstr* &Clobber) -> bool {
488  const MachineBasicBlock *MBBFrom = From->getParent();
489  const MachineBasicBlock *MBBTo = To->getParent();
490  bool MayClobberFrom = isReachable(Clobber, &*From, MBBTo, MDT);
491  bool MayClobberTo = isReachable(Clobber, &*To, MBBTo, MDT);
492  if (!MayClobberFrom && !MayClobberTo)
493  return false;
494  if ((MayClobberFrom && !MayClobberTo) ||
495  (!MayClobberFrom && MayClobberTo))
496  return true;
497  // Both can clobber, this is not an interference only if both are
498  // dominated by Clobber and belong to the same block or if Clobber
499  // properly dominates To, given that To >> From, so it dominates
500  // both and located in a common dominator.
501  return !((MBBFrom == MBBTo &&
502  MDT.dominates(Clobber, &*From) &&
503  MDT.dominates(Clobber, &*To)) ||
504  MDT.properlyDominates(Clobber->getParent(), MBBTo));
505  };
506 
507  return (llvm::any_of(Clobbers, interferes)) ||
508  (llvm::any_of(Inits, [&](InitListMap::value_type &C) {
509  return C.first != Init.first &&
510  llvm::any_of(C.second, interferes);
511  }));
512  };
513 
514  if (MDT.dominates(MI1, MI2)) {
515  if (!intereferes(MI2, MI1)) {
516  DEBUG(dbgs() << "Erasing from BB#" << MI2->getParent()->getNumber()
517  << " " << *MI2);
518  MI2->eraseFromParent();
519  Defs.erase(I2++);
520  Changed = true;
521  continue;
522  }
523  } else if (MDT.dominates(MI2, MI1)) {
524  if (!intereferes(MI1, MI2)) {
525  DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber()
526  << " " << *MI1);
527  MI1->eraseFromParent();
528  Defs.erase(I1++);
529  Changed = true;
530  break;
531  }
532  } else {
533  auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(),
534  MI2->getParent());
535  if (!MBB) {
536  ++I2;
537  continue;
538  }
539 
540  MachineBasicBlock::iterator I = MBB->getFirstNonPHI();
541  if (!intereferes(MI1, I) && !intereferes(MI2, I)) {
542  DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber()
543  << " " << *MI1 << "and moving from BB#"
544  << MI2->getParent()->getNumber() << " to BB#"
545  << I->getParent()->getNumber() << " " << *MI2);
546  I->getParent()->splice(I, MI2->getParent(), MI2);
547  MI1->eraseFromParent();
548  Defs.erase(I1++);
549  Changed = true;
550  break;
551  }
552  }
553  ++I2;
554  }
555  ++I1;
556  }
557  }
558 
559  if (Changed)
560  MRI.clearKillFlags(Reg);
561 
562  return Changed;
563 }
564 
565 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
566  const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
568  const SIRegisterInfo *TRI = ST.getRegisterInfo();
569  const SIInstrInfo *TII = ST.getInstrInfo();
570  MDT = &getAnalysis<MachineDominatorTree>();
571 
573 
574  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
575  BI != BE; ++BI) {
576  MachineBasicBlock &MBB = *BI;
577  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
578  I != E; ++I) {
579  MachineInstr &MI = *I;
580 
581  switch (MI.getOpcode()) {
582  default:
583  continue;
584  case AMDGPU::COPY:
585  case AMDGPU::WQM:
586  case AMDGPU::WWM: {
587  // If the destination register is a physical register there isn't really
588  // much we can do to fix this.
590  continue;
591 
592  const TargetRegisterClass *SrcRC, *DstRC;
593  std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
594  if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
595  unsigned SrcReg = MI.getOperand(1).getReg();
597  TII->moveToVALU(MI);
598  break;
599  }
600 
601  MachineInstr *DefMI = MRI.getVRegDef(SrcReg);
602  unsigned SMovOp;
603  int64_t Imm;
604  // If we are just copying an immediate, we can replace the copy with
605  // s_mov_b32.
606  if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) {
607  MI.getOperand(1).ChangeToImmediate(Imm);
609  MI.setDesc(TII->get(SMovOp));
610  break;
611  }
612  TII->moveToVALU(MI);
613  } else if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
614  tryChangeVGPRtoSGPRinCopy(MI, TRI, TII);
615  }
616 
617  break;
618  }
619  case AMDGPU::PHI: {
620  unsigned Reg = MI.getOperand(0).getReg();
621  if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
622  break;
623 
624  // We don't need to fix the PHI if the common dominator of the
625  // two incoming blocks terminates with a uniform branch.
626  bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII);
627  if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) {
628  MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB();
629  MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB();
630 
631  if (!predsHasDivergentTerminator(MBB0, TRI) &&
632  !predsHasDivergentTerminator(MBB1, TRI)) {
633  DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n');
634  break;
635  }
636  }
637 
638  // If a PHI node defines an SGPR and any of its operands are VGPRs,
639  // then we need to move it to the VALU.
640  //
641  // Also, if a PHI node defines an SGPR and has all SGPR operands
642  // we must move it to the VALU, because the SGPR operands will
643  // all end up being assigned the same register, which means
644  // there is a potential for a conflict if different threads take
645  // different control flow paths.
646  //
647  // For Example:
648  //
649  // sgpr0 = def;
650  // ...
651  // sgpr1 = def;
652  // ...
653  // sgpr2 = PHI sgpr0, sgpr1
654  // use sgpr2;
655  //
656  // Will Become:
657  //
658  // sgpr2 = def;
659  // ...
660  // sgpr2 = def;
661  // ...
662  // use sgpr2
663  //
664  // The one exception to this rule is when one of the operands
665  // is defined by a SI_BREAK, SI_IF_BREAK, or SI_ELSE_BREAK
666  // instruction. In this case, there we know the program will
667  // never enter the second block (the loop) without entering
668  // the first block (where the condition is computed), so there
669  // is no chance for values to be over-written.
670 
671  SmallSet<unsigned, 8> Visited;
672  if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) {
673  DEBUG(dbgs() << "Fixing PHI: " << MI);
674  TII->moveToVALU(MI);
675  }
676  break;
677  }
678  case AMDGPU::REG_SEQUENCE:
679  if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
680  !hasVGPROperands(MI, TRI)) {
681  foldVGPRCopyIntoRegSequence(MI, TRI, TII, MRI);
682  continue;
683  }
684 
685  DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
686 
687  TII->moveToVALU(MI);
688  break;
689  case AMDGPU::INSERT_SUBREG: {
690  const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
691  DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
692  Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
693  Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
694  if (TRI->isSGPRClass(DstRC) &&
695  (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
696  DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
697  TII->moveToVALU(MI);
698  }
699  break;
700  }
701  }
702  }
703  }
704 
706  hoistAndMergeSGPRInits(AMDGPU::M0, MRI, *MDT);
707 
708  return true;
709 }
uint64_t CallInst * C
Interface definition for SIRegisterInfo.
static cl::opt< bool > EnableM0Merge("amdgpu-enable-merge-m0", cl::desc("Merge and hoist M0 initializations"), cl::init(false))
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
AMDGPU specific subclass of TargetSubtarget.
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
static bool isSafeToFoldImmIntoCopy(const MachineInstr *Copy, const MachineInstr *MoveImm, const SIInstrInfo *TII, unsigned &SMovOp, int64_t &Imm)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Implements a dense probed hash-table based set.
Definition: DenseSet.h:221
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:384
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
const SIInstrInfo * getInstrInfo() const override
unsigned getSubReg() const
bool isRegSequence() const
Definition: MachineInstr.h:849
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:525
static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI)
static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool isSGPRClass(const TargetRegisterClass *RC) const
static bool hoistAndMergeSGPRInits(unsigned Reg, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT)
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
SI Fix SGPR copies
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
INITIALIZE_PASS_BEGIN(SIFixSGPRCopies, DEBUG_TYPE, "SI Fix SGPR copies", false, false) INITIALIZE_PASS_END(SIFixSGPRCopies
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI)
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasVGPRs(const TargetRegisterClass *RC) const
Represent the analysis usage information of a pass.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:774
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
bool isCopy() const
Definition: MachineInstr.h:857
Falkor HW Prefetch Fix
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
static bool phiHasBreakDef(const MachineInstr &PHI, const MachineRegisterInfo &MRI, SmallSet< unsigned, 8 > &Visited)
Iterator for intrusive lists based on ilist_node.
static std::pair< const TargetRegisterClass *, const TargetRegisterClass * > getCopyRegClasses(const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI)
#define DEBUG_TYPE
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool searchPredecessors(const MachineBasicBlock *MBB, const MachineBasicBlock *CutOff, UnaryPredicate Predicate)
const SIRegisterInfo * getRegisterInfo() const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
bool properlyDominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:285
int64_t getImm() const
static bool hasTerminatorThatModifiesExec(const MachineBasicBlock &MBB, const TargetRegisterInfo &TRI)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
FunctionPass * createSIFixSGPRCopiesPass()
static bool phiHasVGPROperands(const MachineInstr &PHI, const MachineRegisterInfo &MRI, const SIRegisterInfo *TRI, const SIInstrInfo *TII)
static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Interface definition for SIInstrInfo.
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
char & SIFixSGPRCopiesID
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static bool predsHasDivergentTerminator(MachineBasicBlock *MBB, const TargetRegisterInfo *TRI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void moveToVALU(MachineInstr &MI) const
Replace this instruction&#39;s opcode with the equivalent VALU opcode.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the &#39;base&#39; register class for this register.
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static bool isReachable(const MachineInstr *From, const MachineInstr *To, const MachineBasicBlock *CutOff, MachineDominatorTree &MDT)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65