LLVM  9.0.0svn
SIInsertSkips.cpp
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1 //===-- SIInsertSkips.cpp - Use predicates for control flow ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass inserts branches on the 0 exec mask over divergent branches
11 /// branches when it's expected that jumping over the untaken control flow will
12 /// be cheaper than having every workitem no-op through it.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/DebugLoc.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/Pass.h"
35 #include <cassert>
36 #include <cstdint>
37 #include <iterator>
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "si-insert-skips"
42 
44  "amdgpu-skip-threshold",
45  cl::desc("Number of instructions before jumping over divergent control flow"),
46  cl::init(12), cl::Hidden);
47 
48 namespace {
49 
50 class SIInsertSkips : public MachineFunctionPass {
51 private:
52  const SIRegisterInfo *TRI = nullptr;
53  const SIInstrInfo *TII = nullptr;
54  unsigned SkipThreshold = 0;
55 
56  bool shouldSkip(const MachineBasicBlock &From,
57  const MachineBasicBlock &To) const;
58 
59  bool skipIfDead(MachineInstr &MI, MachineBasicBlock &NextBB);
60 
61  void kill(MachineInstr &MI);
62 
63  MachineBasicBlock *insertSkipBlock(MachineBasicBlock &MBB,
65 
66  bool skipMaskBranch(MachineInstr &MI, MachineBasicBlock &MBB);
67 
68  bool optimizeVccBranch(MachineInstr &MI) const;
69 
70 public:
71  static char ID;
72 
73  SIInsertSkips() : MachineFunctionPass(ID) {}
74 
75  bool runOnMachineFunction(MachineFunction &MF) override;
76 
77  StringRef getPassName() const override {
78  return "SI insert s_cbranch_execz instructions";
79  }
80 
81  void getAnalysisUsage(AnalysisUsage &AU) const override {
83  }
84 };
85 
86 } // end anonymous namespace
87 
88 char SIInsertSkips::ID = 0;
89 
90 INITIALIZE_PASS(SIInsertSkips, DEBUG_TYPE,
91  "SI insert s_cbranch_execz instructions", false, false)
92 
93 char &llvm::SIInsertSkipsPassID = SIInsertSkips::ID;
94 
95 static bool opcodeEmitsNoInsts(unsigned Opc) {
96  switch (Opc) {
97  case TargetOpcode::IMPLICIT_DEF:
98  case TargetOpcode::KILL:
99  case TargetOpcode::BUNDLE:
100  case TargetOpcode::CFI_INSTRUCTION:
102  case TargetOpcode::GC_LABEL:
103  case TargetOpcode::DBG_VALUE:
104  return true;
105  default:
106  return false;
107  }
108 }
109 
110 bool SIInsertSkips::shouldSkip(const MachineBasicBlock &From,
111  const MachineBasicBlock &To) const {
112  if (From.succ_empty())
113  return false;
114 
115  unsigned NumInstr = 0;
116  const MachineFunction *MF = From.getParent();
117 
118  for (MachineFunction::const_iterator MBBI(&From), ToI(&To), End = MF->end();
119  MBBI != End && MBBI != ToI; ++MBBI) {
120  const MachineBasicBlock &MBB = *MBBI;
121 
122  for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
123  NumInstr < SkipThreshold && I != E; ++I) {
124  if (opcodeEmitsNoInsts(I->getOpcode()))
125  continue;
126 
127  // FIXME: Since this is required for correctness, this should be inserted
128  // during SILowerControlFlow.
129 
130  // When a uniform loop is inside non-uniform control flow, the branch
131  // leaving the loop might be an S_CBRANCH_VCCNZ, which is never taken
132  // when EXEC = 0. We should skip the loop lest it becomes infinite.
133  if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
134  I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
135  return true;
136 
137  if (TII->hasUnwantedEffectsWhenEXECEmpty(*I))
138  return true;
139 
140  ++NumInstr;
141  if (NumInstr >= SkipThreshold)
142  return true;
143  }
144  }
145 
146  return false;
147 }
148 
149 bool SIInsertSkips::skipIfDead(MachineInstr &MI, MachineBasicBlock &NextBB) {
150  MachineBasicBlock &MBB = *MI.getParent();
151  MachineFunction *MF = MBB.getParent();
152 
154  !shouldSkip(MBB, MBB.getParent()->back()))
155  return false;
156 
157  MachineBasicBlock *SkipBB = insertSkipBlock(MBB, MI.getIterator());
158 
159  const DebugLoc &DL = MI.getDebugLoc();
160 
161  // If the exec mask is non-zero, skip the next two instructions
162  BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
163  .addMBB(&NextBB);
164 
165  MachineBasicBlock::iterator Insert = SkipBB->begin();
166 
167  // Exec mask is zero: Export to NULL target...
168  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
169  .addImm(0x09) // V_008DFC_SQ_EXP_NULL
170  .addReg(AMDGPU::VGPR0, RegState::Undef)
171  .addReg(AMDGPU::VGPR0, RegState::Undef)
172  .addReg(AMDGPU::VGPR0, RegState::Undef)
173  .addReg(AMDGPU::VGPR0, RegState::Undef)
174  .addImm(1) // vm
175  .addImm(0) // compr
176  .addImm(0); // en
177 
178  // ... and terminate wavefront.
179  BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
180 
181  return true;
182 }
183 
184 void SIInsertSkips::kill(MachineInstr &MI) {
185  MachineBasicBlock &MBB = *MI.getParent();
186  DebugLoc DL = MI.getDebugLoc();
187 
188  switch (MI.getOpcode()) {
189  case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR: {
190  unsigned Opcode = 0;
191 
192  // The opcodes are inverted because the inline immediate has to be
193  // the first operand, e.g. from "x < imm" to "imm > x"
194  switch (MI.getOperand(2).getImm()) {
195  case ISD::SETOEQ:
196  case ISD::SETEQ:
197  Opcode = AMDGPU::V_CMPX_EQ_F32_e64;
198  break;
199  case ISD::SETOGT:
200  case ISD::SETGT:
201  Opcode = AMDGPU::V_CMPX_LT_F32_e64;
202  break;
203  case ISD::SETOGE:
204  case ISD::SETGE:
205  Opcode = AMDGPU::V_CMPX_LE_F32_e64;
206  break;
207  case ISD::SETOLT:
208  case ISD::SETLT:
209  Opcode = AMDGPU::V_CMPX_GT_F32_e64;
210  break;
211  case ISD::SETOLE:
212  case ISD::SETLE:
213  Opcode = AMDGPU::V_CMPX_GE_F32_e64;
214  break;
215  case ISD::SETONE:
216  case ISD::SETNE:
217  Opcode = AMDGPU::V_CMPX_LG_F32_e64;
218  break;
219  case ISD::SETO:
220  Opcode = AMDGPU::V_CMPX_O_F32_e64;
221  break;
222  case ISD::SETUO:
223  Opcode = AMDGPU::V_CMPX_U_F32_e64;
224  break;
225  case ISD::SETUEQ:
226  Opcode = AMDGPU::V_CMPX_NLG_F32_e64;
227  break;
228  case ISD::SETUGT:
229  Opcode = AMDGPU::V_CMPX_NGE_F32_e64;
230  break;
231  case ISD::SETUGE:
232  Opcode = AMDGPU::V_CMPX_NGT_F32_e64;
233  break;
234  case ISD::SETULT:
235  Opcode = AMDGPU::V_CMPX_NLE_F32_e64;
236  break;
237  case ISD::SETULE:
238  Opcode = AMDGPU::V_CMPX_NLT_F32_e64;
239  break;
240  case ISD::SETUNE:
241  Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;
242  break;
243  default:
244  llvm_unreachable("invalid ISD:SET cond code");
245  }
246 
247  assert(MI.getOperand(0).isReg());
248 
249  if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
250  MI.getOperand(0).getReg())) {
251  Opcode = AMDGPU::getVOPe32(Opcode);
252  BuildMI(MBB, &MI, DL, TII->get(Opcode))
253  .add(MI.getOperand(1))
254  .add(MI.getOperand(0));
255  } else {
256  BuildMI(MBB, &MI, DL, TII->get(Opcode))
257  .addReg(AMDGPU::VCC, RegState::Define)
258  .addImm(0) // src0 modifiers
259  .add(MI.getOperand(1))
260  .addImm(0) // src1 modifiers
261  .add(MI.getOperand(0))
262  .addImm(0); // omod
263  }
264  break;
265  }
266  case AMDGPU::SI_KILL_I1_TERMINATOR: {
267  const MachineOperand &Op = MI.getOperand(0);
268  int64_t KillVal = MI.getOperand(1).getImm();
269  assert(KillVal == 0 || KillVal == -1);
270 
271  // Kill all threads if Op0 is an immediate and equal to the Kill value.
272  if (Op.isImm()) {
273  int64_t Imm = Op.getImm();
274  assert(Imm == 0 || Imm == -1);
275 
276  if (Imm == KillVal)
277  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
278  .addImm(0);
279  break;
280  }
281 
282  unsigned Opcode = KillVal ? AMDGPU::S_ANDN2_B64 : AMDGPU::S_AND_B64;
283  BuildMI(MBB, &MI, DL, TII->get(Opcode), AMDGPU::EXEC)
284  .addReg(AMDGPU::EXEC)
285  .add(Op);
286  break;
287  }
288  default:
289  llvm_unreachable("invalid opcode, expected SI_KILL_*_TERMINATOR");
290  }
291 }
292 
293 MachineBasicBlock *SIInsertSkips::insertSkipBlock(
295  MachineFunction *MF = MBB.getParent();
296 
298  MachineFunction::iterator MBBI(MBB);
299  ++MBBI;
300 
301  MF->insert(MBBI, SkipBB);
302  MBB.addSuccessor(SkipBB);
303 
304  return SkipBB;
305 }
306 
307 // Returns true if a branch over the block was inserted.
308 bool SIInsertSkips::skipMaskBranch(MachineInstr &MI,
309  MachineBasicBlock &SrcMBB) {
310  MachineBasicBlock *DestBB = MI.getOperand(0).getMBB();
311 
312  if (!shouldSkip(**SrcMBB.succ_begin(), *DestBB))
313  return false;
314 
315  const DebugLoc &DL = MI.getDebugLoc();
316  MachineBasicBlock::iterator InsPt = std::next(MI.getIterator());
317 
318  BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
319  .addMBB(DestBB);
320 
321  return true;
322 }
323 
324 bool SIInsertSkips::optimizeVccBranch(MachineInstr &MI) const {
325  // Match:
326  // sreg = -1
327  // vcc = S_AND_B64 exec, sreg
328  // S_CBRANCH_VCC[N]Z
329  // =>
330  // S_CBRANCH_EXEC[N]Z
331  bool Changed = false;
332  MachineBasicBlock &MBB = *MI.getParent();
333  const unsigned CondReg = AMDGPU::VCC;
334  const unsigned ExecReg = AMDGPU::EXEC;
335  const unsigned And = AMDGPU::S_AND_B64;
336 
338  E = MBB.rend();
339  bool ReadsCond = false;
340  unsigned Threshold = 5;
341  for (++A ; A != E ; ++A) {
342  if (!--Threshold)
343  return false;
344  if (A->modifiesRegister(ExecReg, TRI))
345  return false;
346  if (A->modifiesRegister(CondReg, TRI)) {
347  if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And)
348  return false;
349  break;
350  }
351  ReadsCond |= A->readsRegister(CondReg, TRI);
352  }
353  if (A == E)
354  return false;
355 
356  MachineOperand &Op1 = A->getOperand(1);
357  MachineOperand &Op2 = A->getOperand(2);
358  if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
359  TII->commuteInstruction(*A);
360  Changed = true;
361  }
362  if (Op1.getReg() != ExecReg)
363  return Changed;
364  if (Op2.isImm() && Op2.getImm() != -1)
365  return Changed;
366 
367  unsigned SReg = AMDGPU::NoRegister;
368  if (Op2.isReg()) {
369  SReg = Op2.getReg();
370  auto M = std::next(A);
371  bool ReadsSreg = false;
372  for ( ; M != E ; ++M) {
373  if (M->definesRegister(SReg, TRI))
374  break;
375  if (M->modifiesRegister(SReg, TRI))
376  return Changed;
377  ReadsSreg |= M->readsRegister(SReg, TRI);
378  }
379  if (M == E ||
380  !M->isMoveImmediate() ||
381  !M->getOperand(1).isImm() ||
382  M->getOperand(1).getImm() != -1)
383  return Changed;
384  // First if sreg is only used in and instruction fold the immediate
385  // into that and.
386  if (!ReadsSreg && Op2.isKill()) {
387  A->getOperand(2).ChangeToImmediate(-1);
388  M->eraseFromParent();
389  }
390  }
391 
392  if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&
393  MI.killsRegister(CondReg, TRI))
394  A->eraseFromParent();
395 
396  bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
397  if (SReg == ExecReg) {
398  if (IsVCCZ) {
399  MI.eraseFromParent();
400  return true;
401  }
402  MI.setDesc(TII->get(AMDGPU::S_BRANCH));
403  } else {
404  MI.setDesc(TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ
405  : AMDGPU::S_CBRANCH_EXECNZ));
406  }
407 
408  MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
410 
411  return true;
412 }
413 
414 bool SIInsertSkips::runOnMachineFunction(MachineFunction &MF) {
415  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
416  TII = ST.getInstrInfo();
417  TRI = &TII->getRegisterInfo();
418  SkipThreshold = SkipThresholdFlag;
419 
420  bool HaveKill = false;
421  bool MadeChange = false;
422 
423  // Track depth of exec mask, divergent branches.
424  SmallVector<MachineBasicBlock *, 16> ExecBranchStack;
425 
427 
428  MachineBasicBlock *EmptyMBBAtEnd = nullptr;
429 
430  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
431  BI != BE; BI = NextBB) {
432  NextBB = std::next(BI);
433  MachineBasicBlock &MBB = *BI;
434  bool HaveSkipBlock = false;
435 
436  if (!ExecBranchStack.empty() && ExecBranchStack.back() == &MBB) {
437  // Reached convergence point for last divergent branch.
438  ExecBranchStack.pop_back();
439  }
440 
441  if (HaveKill && ExecBranchStack.empty()) {
442  HaveKill = false;
443 
444  // TODO: Insert skip if exec is 0?
445  }
446 
448  for (I = MBB.begin(); I != MBB.end(); I = Next) {
449  Next = std::next(I);
450 
451  MachineInstr &MI = *I;
452 
453  switch (MI.getOpcode()) {
454  case AMDGPU::SI_MASK_BRANCH:
455  ExecBranchStack.push_back(MI.getOperand(0).getMBB());
456  MadeChange |= skipMaskBranch(MI, MBB);
457  break;
458 
459  case AMDGPU::S_BRANCH:
460  // Optimize out branches to the next block.
461  // FIXME: Shouldn't this be handled by BranchFolding?
462  if (MBB.isLayoutSuccessor(MI.getOperand(0).getMBB())) {
463  MI.eraseFromParent();
464  } else if (HaveSkipBlock) {
465  // Remove the given unconditional branch when a skip block has been
466  // inserted after the current one and let skip the two instructions
467  // performing the kill if the exec mask is non-zero.
468  MI.eraseFromParent();
469  }
470  break;
471 
472  case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
473  case AMDGPU::SI_KILL_I1_TERMINATOR:
474  MadeChange = true;
475  kill(MI);
476 
477  if (ExecBranchStack.empty()) {
478  if (NextBB != BE && skipIfDead(MI, *NextBB)) {
479  HaveSkipBlock = true;
480  NextBB = std::next(BI);
481  BE = MF.end();
482  }
483  } else {
484  HaveKill = true;
485  }
486 
487  MI.eraseFromParent();
488  break;
489 
490  case AMDGPU::SI_RETURN_TO_EPILOG:
491  // FIXME: Should move somewhere else
493 
494  // Graphics shaders returning non-void shouldn't contain S_ENDPGM,
495  // because external bytecode will be appended at the end.
496  if (BI != --MF.end() || I != MBB.getFirstTerminator()) {
497  // SI_RETURN_TO_EPILOG is not the last instruction. Add an empty block at
498  // the end and jump there.
499  if (!EmptyMBBAtEnd) {
500  EmptyMBBAtEnd = MF.CreateMachineBasicBlock();
501  MF.insert(MF.end(), EmptyMBBAtEnd);
502  }
503 
504  MBB.addSuccessor(EmptyMBBAtEnd);
505  BuildMI(*BI, I, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
506  .addMBB(EmptyMBBAtEnd);
507  I->eraseFromParent();
508  }
509  break;
510 
511  case AMDGPU::S_CBRANCH_VCCZ:
512  case AMDGPU::S_CBRANCH_VCCNZ:
513  MadeChange |= optimizeVccBranch(MI);
514  break;
515 
516  default:
517  break;
518  }
519  }
520  }
521 
522  return MadeChange;
523 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
AMDGPU specific subclass of TargetSubtarget.
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
const SIInstrInfo * getInstrInfo() const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static const AMDGPUSubtarget & get(const MachineFunction &MF)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
#define DEBUG_TYPE
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
reverse_iterator rend()
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
char & SIInsertSkipsPassID
Represent the analysis usage information of a pass.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
self_iterator getIterator()
Definition: ilist_node.h:81
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:676
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
BlockVerifier::State From
LLVM_READONLY int getVOPe32(uint16_t Opcode)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
reverse_self_iterator getReverseIterator()
Definition: ilist_node.h:84
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineBasicBlock & back() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
static cl::opt< unsigned > SkipThresholdFlag("amdgpu-skip-threshold", cl::desc("Number of instructions before jumping over divergent control flow"), cl::init(12), cl::Hidden)
static INITIALIZE_PASS(SIInsertSkips, DEBUG_TYPE, "SI insert s_cbranch_execz instructions", false, false) char &llvm bool opcodeEmitsNoInsts(unsigned Opc)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
const SIRegisterInfo * getRegisterInfo() const override