LLVM  8.0.0svn
SIMCCodeEmitter.cpp
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1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPU.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCFixup.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/Casting.h"
35 #include <cassert>
36 #include <cstdint>
37 #include <cstdlib>
38 
39 using namespace llvm;
40 
41 namespace {
42 
43 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
44  const MCRegisterInfo &MRI;
45 
46  /// Encode an fp or int literal
47  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
48  const MCSubtargetInfo &STI) const;
49 
50 public:
51  SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
52  MCContext &ctx)
53  : AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
54  SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
55  SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
56 
57  /// Encode the instruction and write it to the OS.
58  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
60  const MCSubtargetInfo &STI) const override;
61 
62  /// \returns the encoding for an MCOperand.
63  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
65  const MCSubtargetInfo &STI) const override;
66 
67  /// Use a fixup to encode the simm16 field for SOPP branch
68  /// instructions.
69  unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
71  const MCSubtargetInfo &STI) const override;
72 
73  unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const override;
76 
77  unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
79  const MCSubtargetInfo &STI) const override;
80 };
81 
82 } // end anonymous namespace
83 
85  const MCRegisterInfo &MRI,
86  MCContext &Ctx) {
87  return new SIMCCodeEmitter(MCII, MRI, Ctx);
88 }
89 
90 // Returns the encoding value to use if the given integer is an integer inline
91 // immediate value, or 0 if it is not.
92 template <typename IntTy>
93 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
94  if (Imm >= 0 && Imm <= 64)
95  return 128 + Imm;
96 
97  if (Imm >= -16 && Imm <= -1)
98  return 192 + std::abs(Imm);
99 
100  return 0;
101 }
102 
103 static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
104  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
105  if (IntImm != 0)
106  return IntImm;
107 
108  if (Val == 0x3800) // 0.5
109  return 240;
110 
111  if (Val == 0xB800) // -0.5
112  return 241;
113 
114  if (Val == 0x3C00) // 1.0
115  return 242;
116 
117  if (Val == 0xBC00) // -1.0
118  return 243;
119 
120  if (Val == 0x4000) // 2.0
121  return 244;
122 
123  if (Val == 0xC000) // -2.0
124  return 245;
125 
126  if (Val == 0x4400) // 4.0
127  return 246;
128 
129  if (Val == 0xC400) // -4.0
130  return 247;
131 
132  if (Val == 0x3118 && // 1.0 / (2.0 * pi)
133  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
134  return 248;
135 
136  return 255;
137 }
138 
140  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
141  if (IntImm != 0)
142  return IntImm;
143 
144  if (Val == FloatToBits(0.5f))
145  return 240;
146 
147  if (Val == FloatToBits(-0.5f))
148  return 241;
149 
150  if (Val == FloatToBits(1.0f))
151  return 242;
152 
153  if (Val == FloatToBits(-1.0f))
154  return 243;
155 
156  if (Val == FloatToBits(2.0f))
157  return 244;
158 
159  if (Val == FloatToBits(-2.0f))
160  return 245;
161 
162  if (Val == FloatToBits(4.0f))
163  return 246;
164 
165  if (Val == FloatToBits(-4.0f))
166  return 247;
167 
168  if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
169  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
170  return 248;
171 
172  return 255;
173 }
174 
175 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
176  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
177  if (IntImm != 0)
178  return IntImm;
179 
180  if (Val == DoubleToBits(0.5))
181  return 240;
182 
183  if (Val == DoubleToBits(-0.5))
184  return 241;
185 
186  if (Val == DoubleToBits(1.0))
187  return 242;
188 
189  if (Val == DoubleToBits(-1.0))
190  return 243;
191 
192  if (Val == DoubleToBits(2.0))
193  return 244;
194 
195  if (Val == DoubleToBits(-2.0))
196  return 245;
197 
198  if (Val == DoubleToBits(4.0))
199  return 246;
200 
201  if (Val == DoubleToBits(-4.0))
202  return 247;
203 
204  if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
205  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
206  return 248;
207 
208  return 255;
209 }
210 
211 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
212  const MCOperandInfo &OpInfo,
213  const MCSubtargetInfo &STI) const {
214  int64_t Imm;
215  if (MO.isExpr()) {
216  const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
217  if (!C)
218  return 255;
219 
220  Imm = C->getValue();
221  } else {
222 
223  assert(!MO.isFPImm());
224 
225  if (!MO.isImm())
226  return ~0;
227 
228  Imm = MO.getImm();
229  }
230 
231  switch (OpInfo.OperandType) {
236  return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
237 
242  return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
243 
248  // FIXME Is this correct? What do inline immediates do on SI for f16 src
249  // which does not have f16 support?
250  return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
251 
254  uint16_t Lo16 = static_cast<uint16_t>(Imm);
255  uint32_t Encoding = getLit16Encoding(Lo16, STI);
256  return Encoding;
257  }
258  default:
259  llvm_unreachable("invalid operand size");
260  }
261 }
262 
263 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
265  const MCSubtargetInfo &STI) const {
266  verifyInstructionPredicates(MI,
267  computeAvailableFeatures(STI.getFeatureBits()));
268 
269  uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
270  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
271  unsigned bytes = Desc.getSize();
272 
273  for (unsigned i = 0; i < bytes; i++) {
274  OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
275  }
276 
277  if (bytes > 4)
278  return;
279 
280  // Check for additional literals in SRC0/1/2 (Op 1/2/3)
281  for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
282 
283  // Check if this operand should be encoded as [SV]Src
284  if (!AMDGPU::isSISrcOperand(Desc, i))
285  continue;
286 
287  // Is this operand a literal immediate?
288  const MCOperand &Op = MI.getOperand(i);
289  if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
290  continue;
291 
292  // Yes! Encode it
293  int64_t Imm = 0;
294 
295  if (Op.isImm())
296  Imm = Op.getImm();
297  else if (Op.isExpr()) {
298  if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
299  Imm = C->getValue();
300 
301  } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
302  llvm_unreachable("Must be immediate or expr");
303 
304  for (unsigned j = 0; j < 4; j++) {
305  OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
306  }
307 
308  // Only one literal value allowed
309  break;
310  }
311 }
312 
313 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
314  SmallVectorImpl<MCFixup> &Fixups,
315  const MCSubtargetInfo &STI) const {
316  const MCOperand &MO = MI.getOperand(OpNo);
317 
318  if (MO.isExpr()) {
319  const MCExpr *Expr = MO.getExpr();
321  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
322  return 0;
323  }
324 
325  return getMachineOpValue(MI, MO, Fixups, STI);
326 }
327 
328 unsigned
329 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
330  SmallVectorImpl<MCFixup> &Fixups,
331  const MCSubtargetInfo &STI) const {
332  using namespace AMDGPU::SDWA;
333 
334  uint64_t RegEnc = 0;
335 
336  const MCOperand &MO = MI.getOperand(OpNo);
337 
338  if (MO.isReg()) {
339  unsigned Reg = MO.getReg();
340  RegEnc |= MRI.getEncodingValue(Reg);
344  }
345  return RegEnc;
346  } else {
347  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
348  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
349  if (Enc != ~0U && Enc != 255) {
350  return Enc | SDWA9EncValues::SRC_SGPR_MASK;
351  }
352  }
353 
354  llvm_unreachable("Unsupported operand kind");
355  return 0;
356 }
357 
358 unsigned
359 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
360  SmallVectorImpl<MCFixup> &Fixups,
361  const MCSubtargetInfo &STI) const {
362  using namespace AMDGPU::SDWA;
363 
364  uint64_t RegEnc = 0;
365 
366  const MCOperand &MO = MI.getOperand(OpNo);
367 
368  unsigned Reg = MO.getReg();
369  if (Reg != AMDGPU::VCC) {
370  RegEnc |= MRI.getEncodingValue(Reg);
373  }
374  return RegEnc;
375 }
376 
377 static bool needsPCRel(const MCExpr *Expr) {
378  switch (Expr->getKind()) {
379  case MCExpr::SymbolRef:
380  return true;
381  case MCExpr::Binary: {
382  auto *BE = cast<MCBinaryExpr>(Expr);
383  if (BE->getOpcode() == MCBinaryExpr::Sub)
384  return false;
385  return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
386  }
387  case MCExpr::Unary:
388  return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
389  case MCExpr::Target:
390  case MCExpr::Constant:
391  return false;
392  }
393  llvm_unreachable("invalid kind");
394 }
395 
396 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
397  const MCOperand &MO,
398  SmallVectorImpl<MCFixup> &Fixups,
399  const MCSubtargetInfo &STI) const {
400  if (MO.isReg())
401  return MRI.getEncodingValue(MO.getReg());
402 
403  if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
404  // FIXME: If this is expression is PCRel or not should not depend on what
405  // the expression looks like. Given that this is just a general expression,
406  // it should probably be FK_Data_4 and whatever is producing
407  //
408  // s_add_u32 s2, s2, (extern_const_addrspace+16
409  //
410  // And expecting a PCRel should instead produce
411  //
412  // .Ltmp1:
413  // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
415  if (needsPCRel(MO.getExpr()))
416  Kind = FK_PCRel_4;
417  else
418  Kind = FK_Data_4;
419  Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc()));
420  }
421 
422  // Figure out the operand number, needed for isSrcOperand check
423  unsigned OpNo = 0;
424  for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
425  if (&MO == &MI.getOperand(OpNo))
426  break;
427  }
428 
429  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
430  if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
431  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
432  if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
433  return Enc;
434 
435  } else if (MO.isImm())
436  return MO.getImm();
437 
438  llvm_unreachable("Encoding of this operand type is not supported yet.");
439  return 0;
440 }
441 
442 #define ENABLE_INSTR_PREDICATE_VERIFIER
443 #include "AMDGPUGenMCCodeEmitter.inc"
uint64_t CallInst * C
bool isImm() const
Definition: MCInst.h:59
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
bool isReg() const
Definition: MCInst.h:58
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:63
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:79
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI)
const MCExpr * getExpr() const
Definition: MCInst.h:96
Unary expressions.
Definition: MCExpr.h:42
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:601
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:76
unsigned const MachineRegisterInfo * MRI
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI)
bool isFPImm() const
Definition: MCInst.h:60
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
static uint32_t getIntInlineImmEncoding(IntTy Imm)
static bool needsPCRel(const MCExpr *Expr)
bool isExpr() const
Definition: MCInst.h:61
unsigned getNumOperands() const
Definition: MCInst.h:184
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Operands with register or inline constant.
Definition: SIDefines.h:124
raw_ostream & write(unsigned char C)
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI)
A four-byte pc relative fixup.
Definition: MCFixup.h:30
ExprKind getKind() const
Definition: MCExpr.h:73
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:591
SMLoc getLoc() const
Definition: MCInst.h:180
Provides AMDGPU specific target descriptions.
16-bit PC relative fixup for SOPP branch instructions.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1213
Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
References to labels and assigned expressions.
Definition: MCExpr.h:41
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Operands with register or 32-bit immediate.
Definition: SIDefines.h:116
const unsigned Kind
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Constant expressions.
Definition: MCExpr.h:40
Binary expressions.
Definition: MCExpr.h:39
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
Subtraction.
Definition: MCExpr.h:441
IRTranslator LLVM IR MI
Target specific expression.
Definition: MCExpr.h:43
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
unsigned getOpcode() const
Definition: MCInst.h:174
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:581