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SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIRegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
17 
18 #include "AMDGPURegisterInfo.h"
20 #include "SIDefines.h"
22 
23 namespace llvm {
24 
25 class LiveIntervals;
26 class MachineRegisterInfo;
27 class SISubtarget;
28 class SIMachineFunctionInfo;
29 
30 class SIRegisterInfo final : public AMDGPURegisterInfo {
31 private:
32  unsigned SGPRSetID;
33  unsigned VGPRSetID;
34  BitVector SGPRPressureSets;
35  BitVector VGPRPressureSets;
36  bool SpillSGPRToVGPR;
37  bool SpillSGPRToSMEM;
38 
39  void classifyPressureSet(unsigned PSetID, unsigned Reg,
40  BitVector &PressureSets) const;
41 public:
43 
44  bool spillSGPRToVGPR() const {
45  return SpillSGPRToVGPR;
46  }
47 
48  bool spillSGPRToSMEM() const {
49  return SpillSGPRToSMEM;
50  }
51 
52  /// Return the end register initially reserved for the scratch buffer in case
53  /// spilling is needed.
54  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
55 
56  /// Return the end register initially reserved for the scratch wave offset in
57  /// case spilling is needed.
59  const MachineFunction &MF) const;
60 
61  unsigned reservedStackPtrOffsetReg(const MachineFunction &MF) const;
62 
63  BitVector getReservedRegs(const MachineFunction &MF) const override;
64 
65  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
66  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
68  CallingConv::ID) const override;
69 
70  // Stack access is very expensive. CSRs are also the high registers, and we
71  // want to minimize the number of used registers.
72  unsigned getCSRFirstUseCost() const override {
73  return 100;
74  }
75 
76  unsigned getFrameRegister(const MachineFunction &MF) const override;
77 
78  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
79 
80  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
82  const MachineFunction &MF) const override;
83  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
84  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
85 
86  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
87 
88  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
89  int Idx) const override;
90 
91  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
92 
94  unsigned BaseReg, int FrameIdx,
95  int64_t Offset) const override;
96 
97  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
98  int64_t Offset) const override;
99 
100  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
101  int64_t Offset) const override;
102 
104  const MachineFunction &MF, unsigned Kind = 0) const override;
105 
106  /// If \p OnlyToVGPR is true, this will only succeed if this
108  int FI, RegScavenger *RS,
109  bool OnlyToVGPR = false) const;
110 
112  int FI, RegScavenger *RS,
113  bool OnlyToVGPR = false) const;
114 
116  unsigned FIOperandNum,
117  RegScavenger *RS) const override;
118 
120  int FI, RegScavenger *RS) const;
121 
122  StringRef getRegAsmName(unsigned Reg) const override;
123 
124  unsigned getHWRegIndex(unsigned Reg) const {
125  return getEncodingValue(Reg) & 0xff;
126  }
127 
128  /// \brief Return the 'base' register class for this register.
129  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
130  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
131 
132  /// \returns true if this class contains only SGPR registers
133  bool isSGPRClass(const TargetRegisterClass *RC) const {
134  return !hasVGPRs(RC);
135  }
136 
137  /// \returns true if this class ID contains only SGPR registers
138  bool isSGPRClassID(unsigned RCID) const {
139  return isSGPRClass(getRegClass(RCID));
140  }
141 
142  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
143  const TargetRegisterClass *RC;
145  RC = MRI.getRegClass(Reg);
146  else
147  RC = getPhysRegClass(Reg);
148  return isSGPRClass(RC);
149  }
150 
151  /// \returns true if this class contains VGPR registers.
152  bool hasVGPRs(const TargetRegisterClass *RC) const;
153 
154  /// \returns A VGPR reg class with the same width as \p SRC
156  const TargetRegisterClass *SRC) const;
157 
158  /// \returns A SGPR reg class with the same width as \p SRC
160  const TargetRegisterClass *VRC) const;
161 
162  /// \returns The register class that is used for a sub-register of \p RC for
163  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
164  /// be returned.
166  unsigned SubIdx) const;
167 
168  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
169  unsigned DefSubReg,
170  const TargetRegisterClass *SrcRC,
171  unsigned SrcSubReg) const override;
172 
173  /// \returns True if operands defined with this operand type can accept
174  /// a literal constant (i.e. any 32-bit immediate).
175  bool opCanUseLiteralConstant(unsigned OpType) const {
176  // TODO: 64-bit operands have extending behavior from 32-bit literal.
177  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
179  }
180 
181  /// \returns True if operands defined with this operand type can accept
182  /// an inline constant. i.e. An integer value in the range (-16, 64) or
183  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
184  bool opCanUseInlineConstant(unsigned OpType) const {
185  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
186  OpType <= AMDGPU::OPERAND_SRC_LAST;
187  }
188 
190  const TargetRegisterClass *RC,
191  const MachineFunction &MF) const;
192 
193  unsigned getSGPRPressureSet() const { return SGPRSetID; };
194  unsigned getVGPRPressureSet() const { return VGPRSetID; };
195 
197  unsigned Reg) const;
198  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
199 
200  bool isSGPRPressureSet(unsigned SetID) const {
201  return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
202  }
203  bool isVGPRPressureSet(unsigned SetID) const {
204  return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
205  }
206 
208  unsigned EltSize) const;
209 
210  bool shouldCoalesce(MachineInstr *MI,
211  const TargetRegisterClass *SrcRC,
212  unsigned SubReg,
213  const TargetRegisterClass *DstRC,
214  unsigned DstSubReg,
215  const TargetRegisterClass *NewRC,
216  LiveIntervals &LIS) const override;
217 
218  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
219  MachineFunction &MF) const override;
220 
221  unsigned getRegPressureSetLimit(const MachineFunction &MF,
222  unsigned Idx) const override;
223 
224  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
225 
226  unsigned getReturnAddressReg(const MachineFunction &MF) const {
227  // Not a callee saved register.
228  return AMDGPU::SGPR30_SGPR31;
229  }
230 
231 private:
232  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
233  unsigned LoadStoreOp,
234  int Index,
235  unsigned ValueReg,
236  bool ValueIsKill,
237  unsigned ScratchRsrcReg,
238  unsigned ScratchOffsetReg,
239  int64_t InstrOffset,
240  MachineMemOperand *MMO,
241  RegScavenger *RS) const;
242 };
243 
244 } // End namespace llvm
245 
246 #endif
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
SIRegisterInfo(const SISubtarget &ST)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isSGPRClassID(unsigned RCID) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
StringRef getRegAsmName(unsigned Reg) const override
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
unsigned getReturnAddressReg(const MachineFunction &MF) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool test(unsigned Idx) const
Definition: BitVector.h:502
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
A description of a memory reference used in the backend.
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
unsigned SubReg
bool opCanUseInlineConstant(unsigned OpType) const
Reg
All possible values of the reg field in the ModR/M byte.
static int getRegClass(RegisterKind Is, unsigned RegWidth)
bool opCanUseLiteralConstant(unsigned OpType) const
unsigned reservedStackPtrOffsetReg(const MachineFunction &MF) const
bool isSGPRClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool isSGPRPressureSet(unsigned SetID) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
unsigned getCSRFirstUseCost() const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const int * getRegUnitPressureSets(unsigned RegUnit) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned const MachineRegisterInfo * MRI
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasVGPRs(const TargetRegisterClass *RC) const
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
unsigned getSGPRPressureSet() const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
unsigned getVGPRPressureSet() const
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool spillSGPRToVGPR() const
bool spillSGPRToSMEM() const
const unsigned Kind
bool isVGPRPressureSet(unsigned SetID) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the &#39;base&#39; register class for this register.
unsigned getHWRegIndex(unsigned Reg) const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49