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SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #include "AMDGPURegisterInfo.h"
18 #include "SIDefines.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class LiveIntervals;
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
27 
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
29 private:
30  unsigned SGPRSetID;
31  unsigned VGPRSetID;
32  BitVector SGPRPressureSets;
33  BitVector VGPRPressureSets;
34  bool SpillSGPRToVGPR;
35  bool SpillSGPRToSMEM;
36 
37  void classifyPressureSet(unsigned PSetID, unsigned Reg,
38  BitVector &PressureSets) const;
39 public:
41 
42  bool spillSGPRToVGPR() const {
43  return SpillSGPRToVGPR;
44  }
45 
46  bool spillSGPRToSMEM() const {
47  return SpillSGPRToSMEM;
48  }
49 
50  /// Return the end register initially reserved for the scratch buffer in case
51  /// spilling is needed.
52  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
53 
54  /// Return the end register initially reserved for the scratch wave offset in
55  /// case spilling is needed.
57  const MachineFunction &MF) const;
58 
59  BitVector getReservedRegs(const MachineFunction &MF) const override;
60 
61  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
62  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
64  CallingConv::ID) const override;
65 
66  // Stack access is very expensive. CSRs are also the high registers, and we
67  // want to minimize the number of used registers.
68  unsigned getCSRFirstUseCost() const override {
69  return 100;
70  }
71 
72  unsigned getFrameRegister(const MachineFunction &MF) const override;
73 
74  bool canRealignStack(const MachineFunction &MF) const override;
75  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
76 
77  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
79  const MachineFunction &MF) const override;
80  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
81  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
82 
83  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
84 
85  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
86  int Idx) const override;
87 
88  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
89 
91  unsigned BaseReg, int FrameIdx,
92  int64_t Offset) const override;
93 
94  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
95  int64_t Offset) const override;
96 
97  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
98  int64_t Offset) const override;
99 
101  const MachineFunction &MF, unsigned Kind = 0) const override;
102 
103  /// If \p OnlyToVGPR is true, this will only succeed if this
105  int FI, RegScavenger *RS,
106  bool OnlyToVGPR = false) const;
107 
109  int FI, RegScavenger *RS,
110  bool OnlyToVGPR = false) const;
111 
113  unsigned FIOperandNum,
114  RegScavenger *RS) const override;
115 
117  int FI, RegScavenger *RS) const;
118 
119  StringRef getRegAsmName(unsigned Reg) const override;
120 
121  unsigned getHWRegIndex(unsigned Reg) const {
122  return getEncodingValue(Reg) & 0xff;
123  }
124 
125  /// Return the 'base' register class for this register.
126  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
127  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
128 
129  /// \returns true if this class contains only SGPR registers
130  bool isSGPRClass(const TargetRegisterClass *RC) const {
131  return !hasVGPRs(RC);
132  }
133 
134  /// \returns true if this class ID contains only SGPR registers
135  bool isSGPRClassID(unsigned RCID) const {
136  return isSGPRClass(getRegClass(RCID));
137  }
138 
139  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
140  const TargetRegisterClass *RC;
142  RC = MRI.getRegClass(Reg);
143  else
144  RC = getPhysRegClass(Reg);
145  return isSGPRClass(RC);
146  }
147 
148  /// \returns true if this class contains VGPR registers.
149  bool hasVGPRs(const TargetRegisterClass *RC) const;
150 
151  /// \returns A VGPR reg class with the same width as \p SRC
153  const TargetRegisterClass *SRC) const;
154 
155  /// \returns A SGPR reg class with the same width as \p SRC
157  const TargetRegisterClass *VRC) const;
158 
159  /// \returns The register class that is used for a sub-register of \p RC for
160  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
161  /// be returned.
163  unsigned SubIdx) const;
164 
165  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
166  unsigned DefSubReg,
167  const TargetRegisterClass *SrcRC,
168  unsigned SrcSubReg) const override;
169 
170  /// \returns True if operands defined with this operand type can accept
171  /// a literal constant (i.e. any 32-bit immediate).
172  bool opCanUseLiteralConstant(unsigned OpType) const {
173  // TODO: 64-bit operands have extending behavior from 32-bit literal.
174  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
176  }
177 
178  /// \returns True if operands defined with this operand type can accept
179  /// an inline constant. i.e. An integer value in the range (-16, 64) or
180  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
181  bool opCanUseInlineConstant(unsigned OpType) const {
182  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
183  OpType <= AMDGPU::OPERAND_SRC_LAST;
184  }
185 
187  const TargetRegisterClass *RC,
188  const MachineFunction &MF) const;
189 
190  unsigned getSGPRPressureSet() const { return SGPRSetID; };
191  unsigned getVGPRPressureSet() const { return VGPRSetID; };
192 
194  unsigned Reg) const;
195  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
196 
197  virtual bool
198  isDivergentRegClass(const TargetRegisterClass *RC) const override {
199  return !isSGPRClass(RC);
200  }
201 
202  bool isSGPRPressureSet(unsigned SetID) const {
203  return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
204  }
205  bool isVGPRPressureSet(unsigned SetID) const {
206  return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
207  }
208 
210  unsigned EltSize) const;
211 
212  bool shouldCoalesce(MachineInstr *MI,
213  const TargetRegisterClass *SrcRC,
214  unsigned SubReg,
215  const TargetRegisterClass *DstRC,
216  unsigned DstSubReg,
217  const TargetRegisterClass *NewRC,
218  LiveIntervals &LIS) const override;
219 
220  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
221  MachineFunction &MF) const override;
222 
223  unsigned getRegPressureSetLimit(const MachineFunction &MF,
224  unsigned Idx) const override;
225 
226  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
227 
228  unsigned getReturnAddressReg(const MachineFunction &MF) const;
229 
230  const TargetRegisterClass *
232  const MachineRegisterInfo &MRI) const override;
233 
234  // Find reaching register definition
235  MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
236  MachineInstr &Use,
237  MachineRegisterInfo &MRI,
238  LiveIntervals *LIS) const;
239 
240 private:
241  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
242  unsigned LoadStoreOp,
243  int Index,
244  unsigned ValueReg,
245  bool ValueIsKill,
246  unsigned ScratchRsrcReg,
247  unsigned ScratchOffsetReg,
248  int64_t InstrOffset,
249  MachineMemOperand *MMO,
250  RegScavenger *RS) const;
251 };
252 
253 } // End namespace llvm
254 
255 #endif
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isSGPRClassID(unsigned RCID) const
SIRegisterInfo(const GCNSubtarget &ST)
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
StringRef getRegAsmName(unsigned Reg) const override
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool canRealignStack(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
A description of a memory reference used in the backend.
MachineInstr * findReachingDef(unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
unsigned SubReg
bool opCanUseInlineConstant(unsigned OpType) const
static int getRegClass(RegisterKind Is, unsigned RegWidth)
bool opCanUseLiteralConstant(unsigned OpType) const
bool isSGPRClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool isSGPRPressureSet(unsigned SetID) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
unsigned getCSRFirstUseCost() const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const int * getRegUnitPressureSets(unsigned RegUnit) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const override
unsigned const MachineRegisterInfo * MRI
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
unsigned getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasVGPRs(const TargetRegisterClass *RC) const
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
unsigned getSGPRPressureSet() const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
unsigned getVGPRPressureSet() const
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool spillSGPRToVGPR() const
bool spillSGPRToSMEM() const
bool isVGPRPressureSet(unsigned SetID) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the &#39;base&#39; register class for this register.
unsigned getHWRegIndex(unsigned Reg) const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48