LLVM  6.0.0svn
Macros | Functions | Variables
ScheduleDAGFast.cpp File Reference
#include "InstrEmitter.h"
#include "ScheduleDAGSDNodes.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
Include dependency graph for ScheduleDAGFast.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "pre-RA-sched"
 

Functions

 STATISTIC (NumUnfolds, "Number of nodes unfolded")
 
 STATISTIC (NumDups, "Number of duplicated nodes")
 
 STATISTIC (NumPRCopies, "Number of physical copies")
 
static MVT getPhysicalRegisterVT (SDNode *N, unsigned Reg, const TargetInstrInfo *TII)
 getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node. More...
 
static bool CheckForLiveRegDef (SUnit *SU, unsigned Reg, std::vector< SUnit *> &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs, const TargetRegisterInfo *TRI)
 CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers. More...
 
static SDNodefindGluedUser (SDNode *N)
 findGluedUser - Find the representative use of a glue value by walking the use chain. More...
 

Variables

static RegisterScheduler fastDAGScheduler ("fast", "Fast suboptimal list scheduling", createFastDAGScheduler)
 
static RegisterScheduler linearizeDAGScheduler ("linearize", "Linearize DAG, no scheduling", createDAGLinearizer)
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "pre-RA-sched"

Definition at line 30 of file ScheduleDAGFast.cpp.

Function Documentation

◆ CheckForLiveRegDef()

static bool CheckForLiveRegDef ( SUnit SU,
unsigned  Reg,
std::vector< SUnit *> &  LiveRegDefs,
SmallSet< unsigned, 4 > &  RegAdded,
SmallVectorImpl< unsigned > &  LRegs,
const TargetRegisterInfo TRI 
)
static

CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers.

Definition at line 447 of file ScheduleDAGFast.cpp.

References llvm::SDep::Artificial, assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::clear(), llvm::SmallVectorImpl< T >::clear(), llvm::dbgs(), DEBUG, llvm::SDNode::dump(), llvm::SmallVectorBase::empty(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::ISD::EntryToken, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::SmallVectorTemplateCommon< T >::front(), llvm::SDNode::getGluedNode(), llvm::MCInstrDesc::getImplicitDefs(), llvm::SDValue::getNode(), llvm::SUnit::getNode(), llvm::SDNode::getNodeId(), llvm::InlineAsm::getNumOperandRegisters(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getPhysicalRegisterVT(), llvm::SDep::getReg(), getReg(), llvm::SDep::getSUnit(), llvm::SDValue::getValueType(), llvm::MVT::Glue, llvm::MCInstrDesc::ImplicitDefs, llvm::ISD::INLINEASM, llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::SDep::isAssignedRegDep(), llvm::zlib::isAvailable(), llvm::SUnit::isAvailable, llvm::InlineAsm::isClobberKind(), llvm::SDNode::isMachineOpcode(), llvm::SUnit::isPending, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::InlineAsm::isRegDefEarlyClobberKind(), llvm::InlineAsm::isRegDefKind(), llvm::MCRegAliasIterator::isValid(), llvm_unreachable, N, llvm::SUnit::NodeNum, llvm::InlineAsm::Op_FirstOperand, llvm::SUnit::Preds, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::report_fatal_error(), llvm::reverse(), llvm::SDNode::setNodeId(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::SUnit::Succs, and TII.

◆ findGluedUser()

static SDNode* findGluedUser ( SDNode N)
static

◆ getPhysicalRegisterVT()

static MVT getPhysicalRegisterVT ( SDNode N,
unsigned  Reg,
const TargetInstrInfo TII 
)
static

getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node.

FIXME: Move to SelectionDAG?

Definition at line 426 of file ScheduleDAGFast.cpp.

References assert(), llvm::ISD::CopyFromReg, llvm::MCInstrInfo::get(), llvm::MCInstrDesc::getImplicitDefs(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getOpcode(), llvm::SDNode::getSimpleValueType(), and llvm::MCInstrDesc::ImplicitDefs.

Referenced by CheckForLiveRegDef().

◆ STATISTIC() [1/3]

STATISTIC ( NumUnfolds  ,
"Number of nodes unfolded"   
)

◆ STATISTIC() [2/3]

STATISTIC ( NumDups  ,
"Number of duplicated nodes  
)

◆ STATISTIC() [3/3]

STATISTIC ( NumPRCopies  ,
"Number of physical copies  
)

Variable Documentation

◆ fastDAGScheduler

RegisterScheduler fastDAGScheduler("fast", "Fast suboptimal list scheduling", createFastDAGScheduler)
static

◆ linearizeDAGScheduler

RegisterScheduler linearizeDAGScheduler("linearize", "Linearize DAG, no scheduling", createDAGLinearizer)
static