37 #define DEBUG_TYPE "pre-RA-sched" 39 STATISTIC(NumNoops ,
"Number of noops inserted");
40 STATISTIC(NumStalls,
"Number of pipeline stalls");
61 std::vector<SUnit*> PendingQueue;
77 ~ScheduleDAGVLIW()
override {
79 delete AvailableQueue;
82 void Schedule()
override;
86 void releaseSuccessors(
SUnit *SU);
87 void scheduleNodeTopDown(
SUnit *SU,
unsigned CurCycle);
88 void listScheduleTopDown();
93 void ScheduleDAGVLIW::Schedule() {
95 <<
" '" << BB->getName() <<
"' **********\n");
102 listScheduleTopDown();
113 void ScheduleDAGVLIW::releaseSucc(
SUnit *SU,
const SDep &
D) {
118 dbgs() <<
"*** Scheduling failed! ***\n";
120 dbgs() <<
" has been released too many times!\n";
124 assert(!D.
isWeak() &&
"unexpected artificial DAG edge");
133 PendingQueue.push_back(SuccSU);
137 void ScheduleDAGVLIW::releaseSuccessors(
SUnit *SU) {
141 assert(!
I->isAssignedRegDep() &&
142 "The list-td scheduler doesn't yet support physreg dependencies!");
151 void ScheduleDAGVLIW::scheduleNodeTopDown(
SUnit *SU,
unsigned CurCycle) {
156 assert(CurCycle >= SU->
getDepth() &&
"Node scheduled above its depth!");
159 releaseSuccessors(SU);
166 void ScheduleDAGVLIW::listScheduleTopDown() {
167 unsigned CurCycle = 0;
170 releaseSuccessors(&EntrySU);
173 for (
unsigned i = 0,
e = SUnits.size(); i !=
e; ++i) {
175 if (SUnits[i].Preds.empty()) {
176 AvailableQueue->
push(&SUnits[i]);
177 SUnits[i].isAvailable =
true;
183 std::vector<SUnit*> NotReady;
185 while (!AvailableQueue->
empty() || !PendingQueue.empty()) {
188 for (
unsigned i = 0,
e = PendingQueue.size(); i !=
e; ++i) {
189 if (PendingQueue[i]->
getDepth() == CurCycle) {
190 AvailableQueue->
push(PendingQueue[i]);
191 PendingQueue[i]->isAvailable =
true;
192 PendingQueue[i] = PendingQueue.back();
193 PendingQueue.pop_back();
197 assert(PendingQueue[i]->
getDepth() > CurCycle &&
"Negative latency?");
203 if (AvailableQueue->
empty()) {
210 SUnit *FoundSUnit =
nullptr;
212 bool HasNoopHazards =
false;
213 while (!AvailableQueue->
empty()) {
214 SUnit *CurSUnit = AvailableQueue->
pop();
219 FoundSUnit = CurSUnit;
226 NotReady.push_back(CurSUnit);
230 if (!NotReady.empty()) {
237 scheduleNodeTopDown(FoundSUnit, CurCycle);
244 }
else if (!HasNoopHazards) {
264 VerifyScheduledSequence(
false);
virtual void initNodes(std::vector< SUnit > &SUnits)=0
This class represents lattice values for constants.
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
virtual void push(SUnit *U)=0
STATISTIC(NumFunctions, "Total number of functions")
SmallVectorImpl< SDep >::iterator succ_iterator
virtual void AdvanceCycle()
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
bool isScheduled
True once scheduled.
This interface is used to plug different priorities computation algorithms into the list scheduler...
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
virtual void releaseState()=0
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void push_all(const std::vector< SUnit *> &Nodes)
unsigned NumPredsLeft
of preds not scheduled.
virtual const TargetInstrInfo * getInstrInfo() const
void setDepthToAtLeast(unsigned NewDepth)
If NewDepth is greater than this node's depth value, sets it to be the new depth value.
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned short Latency
Node latency.
virtual bool empty() const =0
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual void EmitNoop()
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
virtual void EmitInstruction(SUnit *)
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
static unsigned getDepth(const SmallVectorImpl< const MachineBasicBlock *> &Stack, const MachineBasicBlock *MBB)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
virtual void scheduledNode(SUnit *)
As each node is scheduled, this method is invoked.
TargetSubtargetInfo - Generic base class for all target subtargets.
static RegisterScheduler VLIWScheduler("vliw-td", "VLIW scheduler", createVLIWDAGScheduler)
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Sequence
A sequence of states that a pointer may go through in which an objc_retain and objc_release are actua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SmallVector< SDep, 4 > Succs
All sunit successors.
bool isWeak() const
Tests if this a weak dependence.
virtual HazardType getHazardType(SUnit *m, int Stalls=0)
getHazardType - Return the hazard type of emitting this node.
Scheduling unit. This is a node in the scheduling DAG.