LLVM  10.0.0svn
SchedulerRegistry.h
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1 //===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation for instruction scheduler function
10 // pass registry (RegisterScheduler).
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
15 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
16 
18 #include "llvm/Support/CodeGen.h"
19 
20 namespace llvm {
21 
22 //===----------------------------------------------------------------------===//
23 ///
24 /// RegisterScheduler class - Track the registration of instruction schedulers.
25 ///
26 //===----------------------------------------------------------------------===//
27 
28 class ScheduleDAGSDNodes;
29 class SelectionDAGISel;
30 
32  : public MachinePassRegistryNode<
33  ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level)> {
34 public:
37 
39 
40  RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
41  : MachinePassRegistryNode(N, D, C) {
42  Registry.Add(this);
43  }
44  ~RegisterScheduler() { Registry.Remove(this); }
45 
46 
47  // Accessors.
50  }
51 
53  return (RegisterScheduler *)Registry.getList();
54  }
55 
57  Registry.setListener(L);
58  }
59 };
60 
61 /// createBURRListDAGScheduler - This creates a bottom up register usage
62 /// reduction list scheduler.
64  CodeGenOpt::Level OptLevel);
65 
66 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
67 /// schedules nodes in source code order when possible.
69  CodeGenOpt::Level OptLevel);
70 
71 /// createHybridListDAGScheduler - This creates a bottom up register pressure
72 /// aware list scheduler that make use of latency information to avoid stalls
73 /// for long latency instructions in low register pressure mode. In high
74 /// register pressure mode it schedules to reduce register pressure.
77 
78 /// createILPListDAGScheduler - This creates a bottom up register pressure
79 /// aware list scheduler that tries to increase instruction level parallelism
80 /// in low register pressure mode. In high register pressure mode it schedules
81 /// to reduce register pressure.
84 
85 /// createFastDAGScheduler - This creates a "fast" scheduler.
86 ///
88  CodeGenOpt::Level OptLevel);
89 
90 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
91 /// DFA driven list scheduler with clustering heuristic to control
92 /// register pressure.
94  CodeGenOpt::Level OptLevel);
95 /// createDefaultScheduler - This creates an instruction scheduler appropriate
96 /// for the target.
98  CodeGenOpt::Level OptLevel);
99 
100 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
101 /// linearize the DAG using topological order.
103  CodeGenOpt::Level OptLevel);
104 
105 } // end namespace llvm
106 
107 #endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H
uint64_t CallInst * C
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void Remove(MachinePassRegistryNode< PassCtorTy > *Node)
Remove - Removes a function pass from the registration list.
RegisterScheduler * getNext() const
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
void setListener(MachinePassRegistryListener< PassCtorTy > *L)
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler...
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterScheduler class - Track the registration of instruction schedulers.
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target...
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
static RegisterScheduler * getList()
void Add(MachinePassRegistryNode< PassCtorTy > *Node)
Add - Adds a function pass to the registration list.
MachinePassRegistryNode< PassCtorTy > * getList()
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source c...
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
static void setListener(MachinePassRegistryListener< FunctionPassCtor > *L)
MachinePassRegistryNode * getNext() const
#define N
MachinePassRegistryNode - Machine pass node stored in registration list.
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.