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SelectionDAGBuilder.h
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1 //===- SelectionDAGBuilder.h - Selection-DAG building -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating from LLVM IR into SelectionDAG IR.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
14 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 
16 #include "StatepointLowering.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/CallSite.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/Instruction.h"
30 #include "llvm/IR/Statepoint.h"
32 #include "llvm/Support/CodeGen.h"
35 #include <algorithm>
36 #include <cassert>
37 #include <cstdint>
38 #include <utility>
39 #include <vector>
40 
41 namespace llvm {
42 
43 class AllocaInst;
44 class AtomicCmpXchgInst;
45 class AtomicRMWInst;
46 class BasicBlock;
47 class BranchInst;
48 class CallInst;
49 class CallBrInst;
50 class CatchPadInst;
51 class CatchReturnInst;
52 class CatchSwitchInst;
53 class CleanupPadInst;
54 class CleanupReturnInst;
55 class Constant;
56 class ConstantInt;
57 class ConstrainedFPIntrinsic;
58 class DbgValueInst;
59 class DataLayout;
60 class DIExpression;
61 class DILocalVariable;
62 class DILocation;
63 class FenceInst;
64 class FunctionLoweringInfo;
65 class GCFunctionInfo;
66 class GCRelocateInst;
67 class GCResultInst;
68 class IndirectBrInst;
69 class InvokeInst;
70 class LandingPadInst;
71 class LLVMContext;
72 class LoadInst;
73 class MachineBasicBlock;
74 class PHINode;
75 class ResumeInst;
76 class ReturnInst;
77 class SDDbgValue;
78 class StoreInst;
79 class SwitchInst;
80 class TargetLibraryInfo;
81 class TargetMachine;
82 class Type;
83 class VAArgInst;
84 class UnreachableInst;
85 class Use;
86 class User;
87 class Value;
88 
89 //===----------------------------------------------------------------------===//
90 /// SelectionDAGBuilder - This is the common target-independent lowering
91 /// implementation that is parameterized by a TargetLowering object.
92 ///
94  /// The current instruction being visited.
95  const Instruction *CurInst = nullptr;
96 
98 
99  /// Maps argument value for unused arguments. This is used
100  /// to preserve debug information for incoming arguments.
101  DenseMap<const Value*, SDValue> UnusedArgNodeMap;
102 
103  /// Helper type for DanglingDebugInfoMap.
104  class DanglingDebugInfo {
105  const DbgValueInst* DI = nullptr;
106  DebugLoc dl;
107  unsigned SDNodeOrder = 0;
108 
109  public:
110  DanglingDebugInfo() = default;
111  DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO)
112  : DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {}
113 
114  const DbgValueInst* getDI() { return DI; }
115  DebugLoc getdl() { return dl; }
116  unsigned getSDNodeOrder() { return SDNodeOrder; }
117  };
118 
119  /// Helper type for DanglingDebugInfoMap.
120  typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector;
121 
122  /// Keeps track of dbg_values for which we have not yet seen the referent.
123  /// We defer handling these until we do see it.
125 
126 public:
127  /// Loads are not emitted to the program immediately. We bunch them up and
128  /// then emit token factor nodes when possible. This allows us to get simple
129  /// disambiguation between loads without worrying about alias analysis.
131 
132  /// State used while lowering a statepoint sequence (gc_statepoint,
133  /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
135 
136 private:
137  /// CopyToReg nodes that copy values to virtual registers for export to other
138  /// blocks need to be emitted before any terminator instruction, but they have
139  /// no other ordering requirements. We bunch them up and the emit a single
140  /// tokenfactor for them just before terminator instructions.
141  SmallVector<SDValue, 8> PendingExports;
142 
143  /// A unique monotonically increasing number used to order the SDNodes we
144  /// create.
145  unsigned SDNodeOrder;
146 
147  enum CaseClusterKind {
148  /// A cluster of adjacent case labels with the same destination, or just one
149  /// case.
150  CC_Range,
151  /// A cluster of cases suitable for jump table lowering.
152  CC_JumpTable,
153  /// A cluster of cases suitable for bit test lowering.
154  CC_BitTests
155  };
156 
157  /// A cluster of case labels.
158  struct CaseCluster {
159  CaseClusterKind Kind;
160  const ConstantInt *Low, *High;
161  union {
162  MachineBasicBlock *MBB;
163  unsigned JTCasesIndex;
164  unsigned BTCasesIndex;
165  };
166  BranchProbability Prob;
167 
168  static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
170  CaseCluster C;
171  C.Kind = CC_Range;
172  C.Low = Low;
173  C.High = High;
174  C.MBB = MBB;
175  C.Prob = Prob;
176  return C;
177  }
178 
179  static CaseCluster jumpTable(const ConstantInt *Low,
180  const ConstantInt *High, unsigned JTCasesIndex,
181  BranchProbability Prob) {
182  CaseCluster C;
183  C.Kind = CC_JumpTable;
184  C.Low = Low;
185  C.High = High;
186  C.JTCasesIndex = JTCasesIndex;
187  C.Prob = Prob;
188  return C;
189  }
190 
191  static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
192  unsigned BTCasesIndex, BranchProbability Prob) {
193  CaseCluster C;
194  C.Kind = CC_BitTests;
195  C.Low = Low;
196  C.High = High;
197  C.BTCasesIndex = BTCasesIndex;
198  C.Prob = Prob;
199  return C;
200  }
201  };
202 
203  using CaseClusterVector = std::vector<CaseCluster>;
204  using CaseClusterIt = CaseClusterVector::iterator;
205 
206  struct CaseBits {
207  uint64_t Mask = 0;
208  MachineBasicBlock* BB = nullptr;
209  unsigned Bits = 0;
210  BranchProbability ExtraProb;
211 
212  CaseBits() = default;
213  CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
214  BranchProbability Prob):
215  Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) {}
216  };
217 
218  using CaseBitsVector = std::vector<CaseBits>;
219 
220  /// Sort Clusters and merge adjacent cases.
221  void sortAndRangeify(CaseClusterVector &Clusters);
222 
223  /// This structure is used to communicate between SelectionDAGBuilder and
224  /// SDISel for the code generation of additional basic blocks needed by
225  /// multi-case switch statements.
226  struct CaseBlock {
227  // The condition code to use for the case block's setcc node.
228  ISD::CondCode CC;
229 
230  // The LHS/MHS/RHS of the comparison to emit.
231  // Emit by default LHS op RHS. MHS is used for range comparisons:
232  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
233  const Value *CmpLHS, *CmpMHS, *CmpRHS;
234 
235  // The block to branch to if the setcc is true/false.
236  MachineBasicBlock *TrueBB, *FalseBB;
237 
238  // The block into which to emit the code for the setcc and branches.
239  MachineBasicBlock *ThisBB;
240 
241  /// The debug location of the instruction this CaseBlock was
242  /// produced from.
243  SDLoc DL;
244 
245  // Branch weights.
246  BranchProbability TrueProb, FalseProb;
247 
248  CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
249  const Value *cmpmiddle, MachineBasicBlock *truebb,
250  MachineBasicBlock *falsebb, MachineBasicBlock *me,
251  SDLoc dl,
254  : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
255  TrueBB(truebb), FalseBB(falsebb), ThisBB(me), DL(dl),
256  TrueProb(trueprob), FalseProb(falseprob) {}
257  };
258 
259  struct JumpTable {
260  /// The virtual register containing the index of the jump table entry
261  /// to jump to.
262  unsigned Reg;
263  /// The JumpTableIndex for this jump table in the function.
264  unsigned JTI;
265  /// The MBB into which to emit the code for the indirect jump.
266  MachineBasicBlock *MBB;
267  /// The MBB of the default bb, which is a successor of the range
268  /// check MBB. This is when updating PHI nodes in successors.
270 
271  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
272  MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
273  };
274  struct JumpTableHeader {
275  APInt First;
276  APInt Last;
277  const Value *SValue;
278  MachineBasicBlock *HeaderBB;
279  bool Emitted;
280 
281  JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
282  bool E = false)
283  : First(std::move(F)), Last(std::move(L)), SValue(SV), HeaderBB(H),
284  Emitted(E) {}
285  };
286  using JumpTableBlock = std::pair<JumpTableHeader, JumpTable>;
287 
288  struct BitTestCase {
289  uint64_t Mask;
290  MachineBasicBlock *ThisBB;
291  MachineBasicBlock *TargetBB;
292  BranchProbability ExtraProb;
293 
294  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
295  BranchProbability Prob):
296  Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) {}
297  };
298 
300 
301  struct BitTestBlock {
302  APInt First;
303  APInt Range;
304  const Value *SValue;
305  unsigned Reg;
306  MVT RegVT;
307  bool Emitted;
308  bool ContiguousRange;
309  MachineBasicBlock *Parent;
311  BitTestInfo Cases;
312  BranchProbability Prob;
313  BranchProbability DefaultProb;
314 
315  BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT,
316  bool E, bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
318  : First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
319  RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
320  Cases(std::move(C)), Prob(Pr) {}
321  };
322 
323  /// Return the range of value in [First..Last].
324  uint64_t getJumpTableRange(const CaseClusterVector &Clusters, unsigned First,
325  unsigned Last) const;
326 
327  /// Return the number of cases in [First..Last].
328  uint64_t getJumpTableNumCases(const SmallVectorImpl<unsigned> &TotalCases,
329  unsigned First, unsigned Last) const;
330 
331  /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
332  /// decides it's not a good idea.
333  bool buildJumpTable(const CaseClusterVector &Clusters, unsigned First,
334  unsigned Last, const SwitchInst *SI,
335  MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
336 
337  /// Find clusters of cases suitable for jump table lowering.
338  void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
339  MachineBasicBlock *DefaultMBB);
340 
341  /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
342  /// decides it's not a good idea.
343  bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
344  const SwitchInst *SI, CaseCluster &BTCluster);
345 
346  /// Find clusters of cases suitable for bit test lowering.
347  void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
348 
349  struct SwitchWorkListItem {
350  MachineBasicBlock *MBB;
351  CaseClusterIt FirstCluster;
352  CaseClusterIt LastCluster;
353  const ConstantInt *GE;
354  const ConstantInt *LT;
355  BranchProbability DefaultProb;
356  };
358 
359  /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
360  /// than each cluster in the range, its rank is 0.
361  static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
362  CaseClusterIt Last);
363 
364  /// Emit comparison and split W into two subtrees.
365  void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
366  Value *Cond, MachineBasicBlock *SwitchMBB);
367 
368  /// Lower W.
369  void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
370  MachineBasicBlock *SwitchMBB,
371  MachineBasicBlock *DefaultMBB);
372 
373  /// Peel the top probability case if it exceeds the threshold
374  MachineBasicBlock *peelDominantCaseCluster(const SwitchInst &SI,
375  CaseClusterVector &Clusters,
376  BranchProbability &PeeledCaseProb);
377 
378  /// A class which encapsulates all of the information needed to generate a
379  /// stack protector check and signals to isel via its state being initialized
380  /// that a stack protector needs to be generated.
381  ///
382  /// *NOTE* The following is a high level documentation of SelectionDAG Stack
383  /// Protector Generation. The reason that it is placed here is for a lack of
384  /// other good places to stick it.
385  ///
386  /// High Level Overview of SelectionDAG Stack Protector Generation:
387  ///
388  /// Previously, generation of stack protectors was done exclusively in the
389  /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
390  /// splitting basic blocks at the IR level to create the success/failure basic
391  /// blocks in the tail of the basic block in question. As a result of this,
392  /// calls that would have qualified for the sibling call optimization were no
393  /// longer eligible for optimization since said calls were no longer right in
394  /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
395  /// instruction).
396  ///
397  /// Then it was noticed that since the sibling call optimization causes the
398  /// callee to reuse the caller's stack, if we could delay the generation of
399  /// the stack protector check until later in CodeGen after the sibling call
400  /// decision was made, we get both the tail call optimization and the stack
401  /// protector check!
402  ///
403  /// A few goals in solving this problem were:
404  ///
405  /// 1. Preserve the architecture independence of stack protector generation.
406  ///
407  /// 2. Preserve the normal IR level stack protector check for platforms like
408  /// OpenBSD for which we support platform-specific stack protector
409  /// generation.
410  ///
411  /// The main problem that guided the present solution is that one can not
412  /// solve this problem in an architecture independent manner at the IR level
413  /// only. This is because:
414  ///
415  /// 1. The decision on whether or not to perform a sibling call on certain
416  /// platforms (for instance i386) requires lower level information
417  /// related to available registers that can not be known at the IR level.
418  ///
419  /// 2. Even if the previous point were not true, the decision on whether to
420  /// perform a tail call is done in LowerCallTo in SelectionDAG which
421  /// occurs after the Stack Protector Pass. As a result, one would need to
422  /// put the relevant callinst into the stack protector check success
423  /// basic block (where the return inst is placed) and then move it back
424  /// later at SelectionDAG/MI time before the stack protector check if the
425  /// tail call optimization failed. The MI level option was nixed
426  /// immediately since it would require platform-specific pattern
427  /// matching. The SelectionDAG level option was nixed because
428  /// SelectionDAG only processes one IR level basic block at a time
429  /// implying one could not create a DAG Combine to move the callinst.
430  ///
431  /// To get around this problem a few things were realized:
432  ///
433  /// 1. While one can not handle multiple IR level basic blocks at the
434  /// SelectionDAG Level, one can generate multiple machine basic blocks
435  /// for one IR level basic block. This is how we handle bit tests and
436  /// switches.
437  ///
438  /// 2. At the MI level, tail calls are represented via a special return
439  /// MIInst called "tcreturn". Thus if we know the basic block in which we
440  /// wish to insert the stack protector check, we get the correct behavior
441  /// by always inserting the stack protector check right before the return
442  /// statement. This is a "magical transformation" since no matter where
443  /// the stack protector check intrinsic is, we always insert the stack
444  /// protector check code at the end of the BB.
445  ///
446  /// Given the aforementioned constraints, the following solution was devised:
447  ///
448  /// 1. On platforms that do not support SelectionDAG stack protector check
449  /// generation, allow for the normal IR level stack protector check
450  /// generation to continue.
451  ///
452  /// 2. On platforms that do support SelectionDAG stack protector check
453  /// generation:
454  ///
455  /// a. Use the IR level stack protector pass to decide if a stack
456  /// protector is required/which BB we insert the stack protector check
457  /// in by reusing the logic already therein. If we wish to generate a
458  /// stack protector check in a basic block, we place a special IR
459  /// intrinsic called llvm.stackprotectorcheck right before the BB's
460  /// returninst or if there is a callinst that could potentially be
461  /// sibling call optimized, before the call inst.
462  ///
463  /// b. Then when a BB with said intrinsic is processed, we codegen the BB
464  /// normally via SelectBasicBlock. In said process, when we visit the
465  /// stack protector check, we do not actually emit anything into the
466  /// BB. Instead, we just initialize the stack protector descriptor
467  /// class (which involves stashing information/creating the success
468  /// mbbb and the failure mbb if we have not created one for this
469  /// function yet) and export the guard variable that we are going to
470  /// compare.
471  ///
472  /// c. After we finish selecting the basic block, in FinishBasicBlock if
473  /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
474  /// initialized, we produce the validation code with one of these
475  /// techniques:
476  /// 1) with a call to a guard check function
477  /// 2) with inlined instrumentation
478  ///
479  /// 1) We insert a call to the check function before the terminator.
480  ///
481  /// 2) We first find a splice point in the parent basic block
482  /// before the terminator and then splice the terminator of said basic
483  /// block into the success basic block. Then we code-gen a new tail for
484  /// the parent basic block consisting of the two loads, the comparison,
485  /// and finally two branches to the success/failure basic blocks. We
486  /// conclude by code-gening the failure basic block if we have not
487  /// code-gened it already (all stack protector checks we generate in
488  /// the same function, use the same failure basic block).
489  class StackProtectorDescriptor {
490  public:
491  StackProtectorDescriptor() = default;
492 
493  /// Returns true if all fields of the stack protector descriptor are
494  /// initialized implying that we should/are ready to emit a stack protector.
495  bool shouldEmitStackProtector() const {
496  return ParentMBB && SuccessMBB && FailureMBB;
497  }
498 
499  bool shouldEmitFunctionBasedCheckStackProtector() const {
500  return ParentMBB && !SuccessMBB && !FailureMBB;
501  }
502 
503  /// Initialize the stack protector descriptor structure for a new basic
504  /// block.
505  void initialize(const BasicBlock *BB, MachineBasicBlock *MBB,
506  bool FunctionBasedInstrumentation) {
507  // Make sure we are not initialized yet.
508  assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
509  "already initialized!");
510  ParentMBB = MBB;
511  if (!FunctionBasedInstrumentation) {
512  SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
513  FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
514  }
515  }
516 
517  /// Reset state that changes when we handle different basic blocks.
518  ///
519  /// This currently includes:
520  ///
521  /// 1. The specific basic block we are generating a
522  /// stack protector for (ParentMBB).
523  ///
524  /// 2. The successor machine basic block that will contain the tail of
525  /// parent mbb after we create the stack protector check (SuccessMBB). This
526  /// BB is visited only on stack protector check success.
527  void resetPerBBState() {
528  ParentMBB = nullptr;
529  SuccessMBB = nullptr;
530  }
531 
532  /// Reset state that only changes when we switch functions.
533  ///
534  /// This currently includes:
535  ///
536  /// 1. FailureMBB since we reuse the failure code path for all stack
537  /// protector checks created in an individual function.
538  ///
539  /// 2.The guard variable since the guard variable we are checking against is
540  /// always the same.
541  void resetPerFunctionState() {
542  FailureMBB = nullptr;
543  }
544 
545  MachineBasicBlock *getParentMBB() { return ParentMBB; }
546  MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
547  MachineBasicBlock *getFailureMBB() { return FailureMBB; }
548 
549  private:
550  /// The basic block for which we are generating the stack protector.
551  ///
552  /// As a result of stack protector generation, we will splice the
553  /// terminators of this basic block into the successor mbb SuccessMBB and
554  /// replace it with a compare/branch to the successor mbbs
555  /// SuccessMBB/FailureMBB depending on whether or not the stack protector
556  /// was violated.
557  MachineBasicBlock *ParentMBB = nullptr;
558 
559  /// A basic block visited on stack protector check success that contains the
560  /// terminators of ParentMBB.
561  MachineBasicBlock *SuccessMBB = nullptr;
562 
563  /// This basic block visited on stack protector check failure that will
564  /// contain a call to __stack_chk_fail().
565  MachineBasicBlock *FailureMBB = nullptr;
566 
567  /// Add a successor machine basic block to ParentMBB. If the successor mbb
568  /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
569  /// block will be created. Assign a large weight if IsLikely is true.
570  MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
571  MachineBasicBlock *ParentMBB,
572  bool IsLikely,
573  MachineBasicBlock *SuccMBB = nullptr);
574  };
575 
576 private:
577  const TargetMachine &TM;
578 
579 public:
580  /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
581  /// nodes without a corresponding SDNode.
582  static const unsigned LowestSDNodeOrder = 1;
583 
585  const DataLayout *DL = nullptr;
586  AliasAnalysis *AA = nullptr;
588 
589  /// Vector of CaseBlock structures used to communicate SwitchInst code
590  /// generation information.
591  std::vector<CaseBlock> SwitchCases;
592 
593  /// Vector of JumpTable structures used to communicate SwitchInst code
594  /// generation information.
595  std::vector<JumpTableBlock> JTCases;
596 
597  /// Vector of BitTestBlock structures used to communicate SwitchInst code
598  /// generation information.
599  std::vector<BitTestBlock> BitTestCases;
600 
601  /// A StackProtectorDescriptor structure used to communicate stack protector
602  /// information in between SelectBasicBlock and FinishBasicBlock.
603  StackProtectorDescriptor SPDescriptor;
604 
605  // Emit PHI-node-operand constants only once even if used by multiple
606  // PHI nodes.
608 
609  /// Information about the function as a whole.
611 
612  /// Garbage collection metadata for the function.
614 
615  /// Map a landing pad to the call site indexes.
617 
618  /// This is set to true if a call in the current block has been translated as
619  /// a tail call. In this case, no subsequent DAG nodes should be created.
620  bool HasTailCall = false;
621 
623 
626  : SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
627  FuncInfo(funcinfo) {}
628 
629  void init(GCFunctionInfo *gfi, AliasAnalysis *AA,
630  const TargetLibraryInfo *li);
631 
632  /// Clear out the current SelectionDAG and the associated state and prepare
633  /// this SelectionDAGBuilder object to be used for a new block. This doesn't
634  /// clear out information about additional blocks that are needed to complete
635  /// switch lowering or PHI node updating; that information is cleared out as
636  /// it is consumed.
637  void clear();
638 
639  /// Clear the dangling debug information map. This function is separated from
640  /// the clear so that debug information that is dangling in a basic block can
641  /// be properly resolved in a different basic block. This allows the
642  /// SelectionDAG to resolve dangling debug information attached to PHI nodes.
643  void clearDanglingDebugInfo();
644 
645  /// Return the current virtual root of the Selection DAG, flushing any
646  /// PendingLoad items. This must be done before emitting a store or any other
647  /// node that may need to be ordered after any prior load instructions.
648  SDValue getRoot();
649 
650  /// Similar to getRoot, but instead of flushing all the PendingLoad items,
651  /// flush all the PendingExports items. It is necessary to do this before
652  /// emitting a terminator instruction.
654 
655  SDLoc getCurSDLoc() const {
656  return SDLoc(CurInst, SDNodeOrder);
657  }
658 
660  return CurInst ? CurInst->getDebugLoc() : DebugLoc();
661  }
662 
663  void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
664 
665  void visit(const Instruction &I);
666 
667  void visit(unsigned Opcode, const User &I);
668 
669  /// If there was virtual register allocated for the value V emit CopyFromReg
670  /// of the specified type Ty. Return empty SDValue() otherwise.
671  SDValue getCopyFromRegs(const Value *V, Type *Ty);
672 
673  /// If we have dangling debug info that describes \p Variable, or an
674  /// overlapping part of variable considering the \p Expr, then this method
675  /// will drop that debug info as it isn't valid any longer.
676  void dropDanglingDebugInfo(const DILocalVariable *Variable,
677  const DIExpression *Expr);
678 
679  /// If we saw an earlier dbg_value referring to V, generate the debug data
680  /// structures now that we've seen its definition.
681  void resolveDanglingDebugInfo(const Value *V, SDValue Val);
682 
683  /// For the given dangling debuginfo record, perform last-ditch efforts to
684  /// resolve the debuginfo to something that is represented in this DAG. If
685  /// this cannot be done, produce an Undef debug value record.
686  void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI);
687 
688  /// For a given Value, attempt to create and record a SDDbgValue in the
689  /// SelectionDAG.
690  bool handleDebugValue(const Value *V, DILocalVariable *Var,
691  DIExpression *Expr, DebugLoc CurDL,
692  DebugLoc InstDL, unsigned Order);
693 
694  /// Evict any dangling debug information, attempting to salvage it first.
695  void resolveOrClearDbgInfo();
696 
697  SDValue getValue(const Value *V);
698  bool findValue(const Value *V) const;
699 
700  /// Return the SDNode for the specified IR value if it exists.
702  if (NodeMap.find(V) == NodeMap.end())
703  return nullptr;
704  return NodeMap[V].getNode();
705  }
706 
708  SDValue getValueImpl(const Value *V);
709 
710  void setValue(const Value *V, SDValue NewN) {
711  SDValue &N = NodeMap[V];
712  assert(!N.getNode() && "Already set a value for this node!");
713  N = NewN;
714  }
715 
716  void setUnusedArgValue(const Value *V, SDValue NewN) {
717  SDValue &N = UnusedArgNodeMap[V];
718  assert(!N.getNode() && "Already set a value for this node!");
719  N = NewN;
720  }
721 
722  void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
724  MachineBasicBlock *SwitchBB,
726  BranchProbability FProb, bool InvertCond);
728  MachineBasicBlock *FBB,
729  MachineBasicBlock *CurBB,
730  MachineBasicBlock *SwitchBB,
732  bool InvertCond);
733  bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
734  bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
735  void CopyToExportRegsIfNeeded(const Value *V);
736  void ExportFromCurrentBlock(const Value *V);
737  void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
738  const BasicBlock *EHPadBB = nullptr);
739 
740  // Lower range metadata from 0 to N to assert zext to an integer of nearest
741  // floor power of two.
743  SDValue Op);
744 
746  const CallBase *Call, unsigned ArgIdx,
747  unsigned NumArgs, SDValue Callee,
748  Type *ReturnTy, bool IsPatchPoint);
749 
750  std::pair<SDValue, SDValue>
752  const BasicBlock *EHPadBB = nullptr);
753 
754  /// When an MBB was split during scheduling, update the
755  /// references that need to refer to the last resulting block.
757 
758  /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes
759  /// of lowering into a STATEPOINT node.
761  /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set
762  /// of gc pointers this STATEPOINT has to relocate.
765 
766  /// The set of gc.relocate calls associated with this gc.statepoint.
768 
769  /// The full list of gc arguments to the gc.statepoint being lowered.
771 
772  /// The gc.statepoint instruction.
773  const Instruction *StatepointInstr = nullptr;
774 
775  /// The list of gc transition arguments present in the gc.statepoint being
776  /// lowered.
778 
779  /// The ID that the resulting STATEPOINT instruction has to report.
780  unsigned ID = -1;
781 
782  /// Information regarding the underlying call instruction.
784 
785  /// The deoptimization state associated with this gc.statepoint call, if
786  /// any.
788 
789  /// Flags associated with the meta arguments being lowered.
790  uint64_t StatepointFlags = -1;
791 
792  /// The number of patchable bytes the call needs to get lowered into.
793  unsigned NumPatchBytes = -1;
794 
795  /// The exception handling unwind destination, in case this represents an
796  /// invoke of gc.statepoint.
797  const BasicBlock *EHPadBB = nullptr;
798 
799  explicit StatepointLoweringInfo(SelectionDAG &DAG) : CLI(DAG) {}
800  };
801 
802  /// Lower \p SLI into a STATEPOINT instruction.
804 
805  // This function is responsible for the whole statepoint lowering process.
806  // It uniformly handles invoke and call statepoints.
808  const BasicBlock *EHPadBB = nullptr);
809 
810  void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee,
811  const BasicBlock *EHPadBB);
812 
813  void LowerDeoptimizeCall(const CallInst *CI);
815 
816  void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee,
817  const BasicBlock *EHPadBB,
818  bool VarArgDisallowed,
819  bool ForceVoidReturnTy);
820 
821  /// Returns the type of FrameIndex and TargetFrameIndex nodes.
824  }
825 
826 private:
827  // Terminator instructions.
828  void visitRet(const ReturnInst &I);
829  void visitBr(const BranchInst &I);
830  void visitSwitch(const SwitchInst &I);
831  void visitIndirectBr(const IndirectBrInst &I);
832  void visitUnreachable(const UnreachableInst &I);
833  void visitCleanupRet(const CleanupReturnInst &I);
834  void visitCatchSwitch(const CatchSwitchInst &I);
835  void visitCatchRet(const CatchReturnInst &I);
836  void visitCatchPad(const CatchPadInst &I);
837  void visitCleanupPad(const CleanupPadInst &CPI);
838 
839  BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
840  const MachineBasicBlock *Dst) const;
841  void addSuccessorWithProb(
844 
845 public:
846  void visitSwitchCase(CaseBlock &CB,
847  MachineBasicBlock *SwitchBB);
848  void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
849  MachineBasicBlock *ParentBB);
850  void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
851  void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
852  void visitBitTestCase(BitTestBlock &BB,
853  MachineBasicBlock* NextMBB,
854  BranchProbability BranchProbToNext,
855  unsigned Reg,
856  BitTestCase &B,
857  MachineBasicBlock *SwitchBB);
858  void visitJumpTable(JumpTable &JT);
859  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
860  MachineBasicBlock *SwitchBB);
861 
862 private:
863  // These all get lowered before this pass.
864  void visitInvoke(const InvokeInst &I);
865  void visitCallBr(const CallBrInst &I);
866  void visitResume(const ResumeInst &I);
867 
868  void visitUnary(const User &I, unsigned Opcode);
869  void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
870 
871  void visitBinary(const User &I, unsigned Opcode);
872  void visitShift(const User &I, unsigned Opcode);
873  void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
874  void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
875  void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
876  void visitFSub(const User &I);
877  void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
878  void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
879  void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
880  void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
881  void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
882  void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
883  void visitSDiv(const User &I);
884  void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
885  void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
886  void visitOr (const User &I) { visitBinary(I, ISD::OR); }
887  void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
888  void visitShl (const User &I) { visitShift(I, ISD::SHL); }
889  void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
890  void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
891  void visitICmp(const User &I);
892  void visitFCmp(const User &I);
893  // Visit the conversion instructions
894  void visitTrunc(const User &I);
895  void visitZExt(const User &I);
896  void visitSExt(const User &I);
897  void visitFPTrunc(const User &I);
898  void visitFPExt(const User &I);
899  void visitFPToUI(const User &I);
900  void visitFPToSI(const User &I);
901  void visitUIToFP(const User &I);
902  void visitSIToFP(const User &I);
903  void visitPtrToInt(const User &I);
904  void visitIntToPtr(const User &I);
905  void visitBitCast(const User &I);
906  void visitAddrSpaceCast(const User &I);
907 
908  void visitExtractElement(const User &I);
909  void visitInsertElement(const User &I);
910  void visitShuffleVector(const User &I);
911 
912  void visitExtractValue(const User &I);
913  void visitInsertValue(const User &I);
914  void visitLandingPad(const LandingPadInst &LP);
915 
916  void visitGetElementPtr(const User &I);
917  void visitSelect(const User &I);
918 
919  void visitAlloca(const AllocaInst &I);
920  void visitLoad(const LoadInst &I);
921  void visitStore(const StoreInst &I);
922  void visitMaskedLoad(const CallInst &I, bool IsExpanding = false);
923  void visitMaskedStore(const CallInst &I, bool IsCompressing = false);
924  void visitMaskedGather(const CallInst &I);
925  void visitMaskedScatter(const CallInst &I);
926  void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
927  void visitAtomicRMW(const AtomicRMWInst &I);
928  void visitFence(const FenceInst &I);
929  void visitPHI(const PHINode &I);
930  void visitCall(const CallInst &I);
931  bool visitMemCmpCall(const CallInst &I);
932  bool visitMemPCpyCall(const CallInst &I);
933  bool visitMemChrCall(const CallInst &I);
934  bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
935  bool visitStrCmpCall(const CallInst &I);
936  bool visitStrLenCall(const CallInst &I);
937  bool visitStrNLenCall(const CallInst &I);
938  bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
939  bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
940  void visitAtomicLoad(const LoadInst &I);
941  void visitAtomicStore(const StoreInst &I);
942  void visitLoadFromSwiftError(const LoadInst &I);
943  void visitStoreToSwiftError(const StoreInst &I);
944 
945  void visitInlineAsm(ImmutableCallSite CS);
946  const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
947  void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
948  void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI);
949 
950  void visitVAStart(const CallInst &I);
951  void visitVAArg(const VAArgInst &I);
952  void visitVAEnd(const CallInst &I);
953  void visitVACopy(const CallInst &I);
954  void visitStackmap(const CallInst &I);
955  void visitPatchpoint(ImmutableCallSite CS,
956  const BasicBlock *EHPadBB = nullptr);
957 
958  // These two are implemented in StatepointLowering.cpp
959  void visitGCRelocate(const GCRelocateInst &Relocate);
960  void visitGCResult(const GCResultInst &I);
961 
962  void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
963 
964  void visitUserOp1(const Instruction &I) {
965  llvm_unreachable("UserOp1 should not exist at instruction selection time!");
966  }
967  void visitUserOp2(const Instruction &I) {
968  llvm_unreachable("UserOp2 should not exist at instruction selection time!");
969  }
970 
971  void processIntegerCallValue(const Instruction &I,
972  SDValue Value, bool IsSigned);
973 
974  void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
975 
976  void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
977 
978  /// If V is an function argument then create corresponding DBG_VALUE machine
979  /// instruction for it now. At the end of instruction selection, they will be
980  /// inserted to the entry BB.
981  bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
982  DIExpression *Expr, DILocation *DL,
983  bool IsDbgDeclare, const SDValue &N);
984 
985  /// Return the next block after MBB, or nullptr if there is none.
986  MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
987 
988  /// Update the DAG and DAG builder with the relevant information after
989  /// a new root node has been created which could be a tail call.
990  void updateDAGForMaybeTailCall(SDValue MaybeTC);
991 
992  /// Return the appropriate SDDbgValue based on N.
993  SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable,
994  DIExpression *Expr, const DebugLoc &dl,
995  unsigned DbgSDNodeOrder);
996 };
997 
998 /// This struct represents the registers (physical or virtual)
999 /// that a particular set of values is assigned, and the type information about
1000 /// the value. The most common situation is to represent one value at a time,
1001 /// but struct or array values are handled element-wise as multiple values. The
1002 /// splitting of aggregates is performed recursively, so that we never have
1003 /// aggregate-typed registers. The values at this point do not necessarily have
1004 /// legal types, so each value may require one or more registers of some legal
1005 /// type.
1006 ///
1008  /// The value types of the values, which may not be legal, and
1009  /// may need be promoted or synthesized from one or more registers.
1011 
1012  /// The value types of the registers. This is the same size as ValueVTs and it
1013  /// records, for each value, what the type of the assigned register or
1014  /// registers are. (Individual values are never synthesized from more than one
1015  /// type of register.)
1016  ///
1017  /// With virtual registers, the contents of RegVTs is redundant with TLI's
1018  /// getRegisterType member function, however when with physical registers
1019  /// it is necessary to have a separate record of the types.
1021 
1022  /// This list holds the registers assigned to the values.
1023  /// Each legal or promoted value requires one register, and each
1024  /// expanded value requires multiple registers.
1026 
1027  /// This list holds the number of registers for each value.
1029 
1030  /// Records if this value needs to be treated in an ABI dependant manner,
1031  /// different to normal type legalization.
1033 
1034  RegsForValue() = default;
1035  RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt, EVT valuevt,
1038  const DataLayout &DL, unsigned Reg, Type *Ty,
1040 
1041  bool isABIMangled() const {
1042  return CallConv.hasValue();
1043  }
1044 
1045  /// Add the specified values to this one.
1046  void append(const RegsForValue &RHS) {
1047  ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
1048  RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
1049  Regs.append(RHS.Regs.begin(), RHS.Regs.end());
1050  RegCount.push_back(RHS.Regs.size());
1051  }
1052 
1053  /// Emit a series of CopyFromReg nodes that copies from this value and returns
1054  /// the result as a ValueVTs value. This uses Chain/Flag as the input and
1055  /// updates them for the output Chain/Flag. If the Flag pointer is NULL, no
1056  /// flag is used.
1058  const SDLoc &dl, SDValue &Chain, SDValue *Flag,
1059  const Value *V = nullptr) const;
1060 
1061  /// Emit a series of CopyToReg nodes that copies the specified value into the
1062  /// registers specified by this object. This uses Chain/Flag as the input and
1063  /// updates them for the output Chain/Flag. If the Flag pointer is nullptr, no
1064  /// flag is used. If V is not nullptr, then it is used in printing better
1065  /// diagnostic messages on error.
1066  void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl,
1067  SDValue &Chain, SDValue *Flag, const Value *V = nullptr,
1068  ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
1069 
1070  /// Add this value to the specified inlineasm node operand list. This adds the
1071  /// code marker, matching input operand index (if applicable), and includes
1072  /// the number of values added into it.
1073  void AddInlineAsmOperands(unsigned Code, bool HasMatching,
1074  unsigned MatchingIdx, const SDLoc &dl,
1075  SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
1076 
1077  /// Check if the total RegCount is greater than one.
1078  bool occupiesMultipleRegs() const {
1079  return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
1080  }
1081 
1082  /// Return a list of registers and their sizes.
1083  SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
1084 };
1085 
1086 } // end namespace llvm
1087 
1088 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
uint64_t CallInst * C
Return a value (possibly void), from a function.
std::vector< BitTestBlock > BitTestCases
Vector of BitTestBlock structures used to communicate SwitchInst code generation information.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
Represents calls to the gc.result intrinsic.
Definition: Statepoint.h:396
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn&#39;t known to be exported from the current basic block...
const TargetLibraryInfo * LibInfo
StatepointFlags
The statepoint intrinsic accepts a set of flags as its third argument.
Definition: Statepoint.h:40
Various leaf nodes.
Definition: ISDOpcodes.h:59
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
Map a landing pad to the call site indexes.
void LowerDeoptimizeCall(const CallInst *CI)
An instruction for ordering other memory operations.
Definition: Instructions.h:454
TargetLowering::CallLoweringInfo CLI
Information regarding the underlying call instruction.
void CopyValueToVirtualRegister(const Value *V, unsigned Reg)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
SmallVector< const GCRelocateInst *, 16 > GCRelocates
The set of gc.relocate calls associated with this gc.statepoint.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
A specialization of it&#39;s base class for read only access to a gc.statepoint.
Definition: Statepoint.h:295
void push_back(const T &Elt)
Definition: SmallVector.h:211
void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB)
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, CodeGenOpt::Level ol)
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
void setValue(const Value *V, SDValue NewN)
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
Optional< CallingConv::ID > CallConv
Records if this value needs to be treated in an ABI dependant manner, different to normal type legali...
SDNode * getNodeForIRValue(const Value *V)
Return the SDNode for the specified IR value if it exists.
demanded bits
A debug info location.
Definition: DebugLoc.h:33
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1014
F(f)
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
SDNode * getNode() const
get the SDNode which holds the desired result
This is the common base class for constrained floating point intrinsics.
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
uint64_t High
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
Return the current virtual root of the Selection DAG, flushing any PendingLoad items.
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:409
void resolveOrClearDbgInfo()
Evict any dangling debug information, attempting to salvage it first.
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
ArrayRef< const Use > GCTransitionArgs
The list of gc transition arguments present in the gc.statepoint being lowered.
SmallVector< EVT, 4 > ValueVTs
The value types of the values, which may not be legal, and may need be promoted or synthesized from o...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI)
Lower SLI into a STATEPOINT instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don&#39;t look in FuncInfo.ValueMap for a virtual register.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool ShouldEmitAsBranches(const std::vector< CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
void init(GCFunctionInfo *gfi, AliasAnalysis *AA, const TargetLibraryInfo *li)
bool findValue(const Value *V) const
Debug location.
void append(const RegsForValue &RHS)
Add the specified values to this one.
void salvageUnresolvedDbgValue(DanglingDebugInfo &DDI)
For the given dangling debuginfo record, perform last-ditch efforts to resolve the debuginfo to somet...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
bool handleDebugValue(const Value *V, DILocalVariable *Var, DIExpression *Expr, DebugLoc CurDL, DebugLoc InstDL, unsigned Order)
For a given Value, attempt to create and record a SDDbgValue in the SelectionDAG. ...
#define P(N)
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
The landingpad instruction holds all of the information necessary to generate correct exception handl...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
bool HasTailCall
This is set to true if a call in the current block has been translated as a tail call.
ArrayRef< const Use > DeoptState
The deoptimization state associated with this gc.statepoint call, if any.
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
Conditional or Unconditional Branch instruction.
This function has undefined behavior.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Resume the propagation of an exception.
Indirect Branch Instruction.
#define H(x, y, z)
Definition: MD5.cpp:57
void LowerCallSiteWithDeoptBundleImpl(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB, bool VarArgDisallowed, bool ForceVoidReturnTy)
void dropDanglingDebugInfo(const DILocalVariable *Variable, const DIExpression *Expr)
If we have dangling debug info that describes Variable, or an overlapping part of variable considerin...
This class tracks both per-statepoint and per-selectiondag information.
Extended Value Type.
Definition: ValueTypes.h:33
This class represents the va_arg llvm instruction, which returns an argument of the specified type gi...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CallBr instruction, tracking function calls that may not return control but instead transfer it to a ...
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it, emit nodes to copy the value into the virtual registers.
static BranchProbability getUnknown()
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:403
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
SmallVector< unsigned, 4 > RegCount
This list holds the number of registers for each value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This struct represents the registers (physical or virtual) that a particular set of values is assigne...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
Provides information about what library functions are available for the current target.
void clear()
Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuilder obje...
void visit(const Instruction &I)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Represents one node in the SelectionDAG.
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
When an MBB was split during scheduling, update the references that need to refer to the last resulti...
DWARF expression.
GCFunctionInfo * GFI
Garbage collection metadata for the function.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringRef > StandardNames)
Initialize the set of available library functions based on the specified target triple.
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
std::vector< JumpTableBlock > JTCases
Vector of JumpTable structures used to communicate SwitchInst code generation information.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:386
could "use" a pointer
SmallVector< SDValue, 8 > PendingLoads
Loads are not emitted to the program immediately.
bool hasValue() const
Definition: Optional.h:259
void LowerStatepoint(ImmutableStatepoint ISP, const BasicBlock *EHPadBB=nullptr)
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:324
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
This represents the llvm.dbg.value instruction.
Establish a view to a call site for examination.
Definition: CallSite.h:892
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
SmallVector< const Value *, 16 > Bases
Bases[i] is the base pointer for Ptrs[i].
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
SDValue getCopyFromRegs(const Value *V, Type *Ty)
If there was virtual register allocated for the value V emit CopyFromReg of the specified type Ty...
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, const BasicBlock *EHPadBB=nullptr)
const unsigned Kind
Multiway switch.
FunctionLoweringInfo & FuncInfo
Information about the function as a whole.
SmallVector< MVT, 4 > RegVTs
The value types of the registers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void setUnusedArgValue(const Value *V, SDValue NewN)
Represents calls to the gc.relocate intrinsic.
Definition: Statepoint.h:363
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
ArrayRef< const Use > GCArgs
The full list of gc arguments to the gc.statepoint being lowered.
MVT getFrameIndexTy()
Returns the type of FrameIndex and TargetFrameIndex nodes.
Invoke instruction.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
std::vector< CaseBlock > SwitchCases
Vector of CaseBlock structures used to communicate SwitchInst code generation information.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
SDValue getControlRoot()
Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports i...
Garbage collection metadata for a single function.
Definition: GCMetadata.h:77
void clearDanglingDebugInfo()
Clear the dangling debug information map.
DenseMap< const Constant *, unsigned > ConstantsOut
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
Holds the information from a dbg_value node through SDISel.
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:585
SmallVector< unsigned, 4 > Regs
This list holds the registers assigned to the values.
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
If we saw an earlier dbg_value referring to V, generate the debug data structures now that we&#39;ve seen...
Describes a gc.statepoint or a gc.statepoint like thing for the purposes of lowering into a STATEPOIN...
This file describes how to lower LLVM code to machine code.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
bool occupiesMultipleRegs() const
Check if the total RegCount is greater than one.