LLVM  8.0.0svn
SelectionDAGDumper.cpp
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1 //===- SelectionDAGDumper.cpp - Implement SelectionDAG::dump() ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the SelectionDAG::dump method and friends.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/None.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/StringExtras.h"
30 #include "llvm/Config/llvm-config.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DebugLoc.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
38 #include "llvm/IR/Value.h"
39 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Printable.h"
49 #include "SDNodeDbgValue.h"
50 #include <cstdint>
51 #include <iterator>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool>
56 VerboseDAGDumping("dag-dump-verbose", cl::Hidden,
57  cl::desc("Display more information when dumping selection "
58  "DAG nodes."));
59 
60 std::string SDNode::getOperationName(const SelectionDAG *G) const {
61  switch (getOpcode()) {
62  default:
64  return "<<Unknown DAG Node>>";
65  if (isMachineOpcode()) {
66  if (G)
67  if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
68  if (getMachineOpcode() < TII->getNumOpcodes())
69  return TII->getName(getMachineOpcode());
70  return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
71  }
72  if (G) {
73  const TargetLowering &TLI = G->getTargetLoweringInfo();
74  const char *Name = TLI.getTargetNodeName(getOpcode());
75  if (Name) return Name;
76  return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
77  }
78  return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
79 
80 #ifndef NDEBUG
81  case ISD::DELETED_NODE: return "<<Deleted Node!>>";
82 #endif
83  case ISD::PREFETCH: return "Prefetch";
84  case ISD::ATOMIC_FENCE: return "AtomicFence";
85  case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
86  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
87  case ISD::ATOMIC_SWAP: return "AtomicSwap";
88  case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
89  case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
90  case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
91  case ISD::ATOMIC_LOAD_CLR: return "AtomicLoadClr";
92  case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
93  case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
94  case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
95  case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
96  case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
97  case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
98  case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
99  case ISD::ATOMIC_LOAD: return "AtomicLoad";
100  case ISD::ATOMIC_STORE: return "AtomicStore";
101  case ISD::PCMARKER: return "PCMarker";
102  case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
103  case ISD::SRCVALUE: return "SrcValue";
104  case ISD::MDNODE_SDNODE: return "MDNode";
105  case ISD::EntryToken: return "EntryToken";
106  case ISD::TokenFactor: return "TokenFactor";
107  case ISD::AssertSext: return "AssertSext";
108  case ISD::AssertZext: return "AssertZext";
109 
110  case ISD::BasicBlock: return "BasicBlock";
111  case ISD::VALUETYPE: return "ValueType";
112  case ISD::Register: return "Register";
113  case ISD::RegisterMask: return "RegisterMask";
114  case ISD::Constant:
115  if (cast<ConstantSDNode>(this)->isOpaque())
116  return "OpaqueConstant";
117  return "Constant";
118  case ISD::ConstantFP: return "ConstantFP";
119  case ISD::GlobalAddress: return "GlobalAddress";
120  case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
121  case ISD::FrameIndex: return "FrameIndex";
122  case ISD::JumpTable: return "JumpTable";
123  case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
124  case ISD::RETURNADDR: return "RETURNADDR";
125  case ISD::ADDROFRETURNADDR: return "ADDROFRETURNADDR";
126  case ISD::FRAMEADDR: return "FRAMEADDR";
127  case ISD::SPONENTRY: return "SPONENTRY";
128  case ISD::LOCAL_RECOVER: return "LOCAL_RECOVER";
129  case ISD::READ_REGISTER: return "READ_REGISTER";
130  case ISD::WRITE_REGISTER: return "WRITE_REGISTER";
131  case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
132  case ISD::EH_DWARF_CFA: return "EH_DWARF_CFA";
133  case ISD::EH_RETURN: return "EH_RETURN";
134  case ISD::EH_SJLJ_SETJMP: return "EH_SJLJ_SETJMP";
135  case ISD::EH_SJLJ_LONGJMP: return "EH_SJLJ_LONGJMP";
136  case ISD::EH_SJLJ_SETUP_DISPATCH: return "EH_SJLJ_SETUP_DISPATCH";
137  case ISD::ConstantPool: return "ConstantPool";
138  case ISD::TargetIndex: return "TargetIndex";
139  case ISD::ExternalSymbol: return "ExternalSymbol";
140  case ISD::BlockAddress: return "BlockAddress";
142  case ISD::INTRINSIC_VOID:
143  case ISD::INTRINSIC_W_CHAIN: {
144  unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
145  unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
146  if (IID < Intrinsic::num_intrinsics)
147  return Intrinsic::getName((Intrinsic::ID)IID, None);
148  else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
149  return TII->getName(IID);
150  llvm_unreachable("Invalid intrinsic ID");
151  }
152 
153  case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
154  case ISD::TargetConstant:
155  if (cast<ConstantSDNode>(this)->isOpaque())
156  return "OpaqueTargetConstant";
157  return "TargetConstant";
158  case ISD::TargetConstantFP: return "TargetConstantFP";
159  case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
160  case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
161  case ISD::TargetFrameIndex: return "TargetFrameIndex";
162  case ISD::TargetJumpTable: return "TargetJumpTable";
163  case ISD::TargetConstantPool: return "TargetConstantPool";
164  case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
165  case ISD::MCSymbol: return "MCSymbol";
166  case ISD::TargetBlockAddress: return "TargetBlockAddress";
167 
168  case ISD::CopyToReg: return "CopyToReg";
169  case ISD::CopyFromReg: return "CopyFromReg";
170  case ISD::UNDEF: return "undef";
171  case ISD::MERGE_VALUES: return "merge_values";
172  case ISD::INLINEASM: return "inlineasm";
173  case ISD::EH_LABEL: return "eh_label";
174  case ISD::HANDLENODE: return "handlenode";
175 
176  // Unary operators
177  case ISD::FABS: return "fabs";
178  case ISD::FMINNUM: return "fminnum";
179  case ISD::STRICT_FMINNUM: return "strict_fminnum";
180  case ISD::FMAXNUM: return "fmaxnum";
181  case ISD::STRICT_FMAXNUM: return "strict_fmaxnum";
182  case ISD::FMINNUM_IEEE: return "fminnum_ieee";
183  case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
184  case ISD::FMINIMUM: return "fminimum";
185  case ISD::FMAXIMUM: return "fmaximum";
186  case ISD::FNEG: return "fneg";
187  case ISD::FSQRT: return "fsqrt";
188  case ISD::STRICT_FSQRT: return "strict_fsqrt";
189  case ISD::FCBRT: return "fcbrt";
190  case ISD::FSIN: return "fsin";
191  case ISD::STRICT_FSIN: return "strict_fsin";
192  case ISD::FCOS: return "fcos";
193  case ISD::STRICT_FCOS: return "strict_fcos";
194  case ISD::FSINCOS: return "fsincos";
195  case ISD::FTRUNC: return "ftrunc";
196  case ISD::STRICT_FTRUNC: return "strict_ftrunc";
197  case ISD::FFLOOR: return "ffloor";
198  case ISD::STRICT_FFLOOR: return "strict_ffloor";
199  case ISD::FCEIL: return "fceil";
200  case ISD::STRICT_FCEIL: return "strict_fceil";
201  case ISD::FRINT: return "frint";
202  case ISD::STRICT_FRINT: return "strict_frint";
203  case ISD::FNEARBYINT: return "fnearbyint";
204  case ISD::STRICT_FNEARBYINT: return "strict_fnearbyint";
205  case ISD::FROUND: return "fround";
206  case ISD::STRICT_FROUND: return "strict_fround";
207  case ISD::FEXP: return "fexp";
208  case ISD::STRICT_FEXP: return "strict_fexp";
209  case ISD::FEXP2: return "fexp2";
210  case ISD::STRICT_FEXP2: return "strict_fexp2";
211  case ISD::FLOG: return "flog";
212  case ISD::STRICT_FLOG: return "strict_flog";
213  case ISD::FLOG2: return "flog2";
214  case ISD::STRICT_FLOG2: return "strict_flog2";
215  case ISD::FLOG10: return "flog10";
216  case ISD::STRICT_FLOG10: return "strict_flog10";
217 
218  // Binary operators
219  case ISD::ADD: return "add";
220  case ISD::SUB: return "sub";
221  case ISD::MUL: return "mul";
222  case ISD::MULHU: return "mulhu";
223  case ISD::MULHS: return "mulhs";
224  case ISD::SDIV: return "sdiv";
225  case ISD::UDIV: return "udiv";
226  case ISD::SREM: return "srem";
227  case ISD::UREM: return "urem";
228  case ISD::SMUL_LOHI: return "smul_lohi";
229  case ISD::UMUL_LOHI: return "umul_lohi";
230  case ISD::SDIVREM: return "sdivrem";
231  case ISD::UDIVREM: return "udivrem";
232  case ISD::AND: return "and";
233  case ISD::OR: return "or";
234  case ISD::XOR: return "xor";
235  case ISD::SHL: return "shl";
236  case ISD::SRA: return "sra";
237  case ISD::SRL: return "srl";
238  case ISD::ROTL: return "rotl";
239  case ISD::ROTR: return "rotr";
240  case ISD::FSHL: return "fshl";
241  case ISD::FSHR: return "fshr";
242  case ISD::FADD: return "fadd";
243  case ISD::STRICT_FADD: return "strict_fadd";
244  case ISD::FSUB: return "fsub";
245  case ISD::STRICT_FSUB: return "strict_fsub";
246  case ISD::FMUL: return "fmul";
247  case ISD::STRICT_FMUL: return "strict_fmul";
248  case ISD::FDIV: return "fdiv";
249  case ISD::STRICT_FDIV: return "strict_fdiv";
250  case ISD::FMA: return "fma";
251  case ISD::STRICT_FMA: return "strict_fma";
252  case ISD::FMAD: return "fmad";
253  case ISD::FREM: return "frem";
254  case ISD::STRICT_FREM: return "strict_frem";
255  case ISD::FCOPYSIGN: return "fcopysign";
256  case ISD::FGETSIGN: return "fgetsign";
257  case ISD::FCANONICALIZE: return "fcanonicalize";
258  case ISD::FPOW: return "fpow";
259  case ISD::STRICT_FPOW: return "strict_fpow";
260  case ISD::SMIN: return "smin";
261  case ISD::SMAX: return "smax";
262  case ISD::UMIN: return "umin";
263  case ISD::UMAX: return "umax";
264 
265  case ISD::FPOWI: return "fpowi";
266  case ISD::STRICT_FPOWI: return "strict_fpowi";
267  case ISD::SETCC: return "setcc";
268  case ISD::SETCCCARRY: return "setcccarry";
269  case ISD::SELECT: return "select";
270  case ISD::VSELECT: return "vselect";
271  case ISD::SELECT_CC: return "select_cc";
272  case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
273  case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
274  case ISD::CONCAT_VECTORS: return "concat_vectors";
275  case ISD::INSERT_SUBVECTOR: return "insert_subvector";
276  case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
277  case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
278  case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
279  case ISD::CARRY_FALSE: return "carry_false";
280  case ISD::ADDC: return "addc";
281  case ISD::ADDE: return "adde";
282  case ISD::ADDCARRY: return "addcarry";
283  case ISD::SADDO: return "saddo";
284  case ISD::UADDO: return "uaddo";
285  case ISD::SSUBO: return "ssubo";
286  case ISD::USUBO: return "usubo";
287  case ISD::SMULO: return "smulo";
288  case ISD::UMULO: return "umulo";
289  case ISD::SUBC: return "subc";
290  case ISD::SUBE: return "sube";
291  case ISD::SUBCARRY: return "subcarry";
292  case ISD::SHL_PARTS: return "shl_parts";
293  case ISD::SRA_PARTS: return "sra_parts";
294  case ISD::SRL_PARTS: return "srl_parts";
295 
296  case ISD::SADDSAT: return "saddsat";
297  case ISD::UADDSAT: return "uaddsat";
298  case ISD::SSUBSAT: return "ssubsat";
299  case ISD::USUBSAT: return "usubsat";
300 
301  // Conversion operators.
302  case ISD::SIGN_EXTEND: return "sign_extend";
303  case ISD::ZERO_EXTEND: return "zero_extend";
304  case ISD::ANY_EXTEND: return "any_extend";
305  case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
306  case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
307  case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
308  case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
309  case ISD::TRUNCATE: return "truncate";
310  case ISD::FP_ROUND: return "fp_round";
311  case ISD::FLT_ROUNDS_: return "flt_rounds";
312  case ISD::FP_ROUND_INREG: return "fp_round_inreg";
313  case ISD::FP_EXTEND: return "fp_extend";
314 
315  case ISD::SINT_TO_FP: return "sint_to_fp";
316  case ISD::UINT_TO_FP: return "uint_to_fp";
317  case ISD::FP_TO_SINT: return "fp_to_sint";
318  case ISD::FP_TO_UINT: return "fp_to_uint";
319  case ISD::BITCAST: return "bitcast";
320  case ISD::ADDRSPACECAST: return "addrspacecast";
321  case ISD::FP16_TO_FP: return "fp16_to_fp";
322  case ISD::FP_TO_FP16: return "fp_to_fp16";
323 
324  // Control flow instructions
325  case ISD::BR: return "br";
326  case ISD::BRIND: return "brind";
327  case ISD::BR_JT: return "br_jt";
328  case ISD::BRCOND: return "brcond";
329  case ISD::BR_CC: return "br_cc";
330  case ISD::CALLSEQ_START: return "callseq_start";
331  case ISD::CALLSEQ_END: return "callseq_end";
332 
333  // EH instructions
334  case ISD::CATCHRET: return "catchret";
335  case ISD::CLEANUPRET: return "cleanupret";
336 
337  // Other operators
338  case ISD::LOAD: return "load";
339  case ISD::STORE: return "store";
340  case ISD::MLOAD: return "masked_load";
341  case ISD::MSTORE: return "masked_store";
342  case ISD::MGATHER: return "masked_gather";
343  case ISD::MSCATTER: return "masked_scatter";
344  case ISD::VAARG: return "vaarg";
345  case ISD::VACOPY: return "vacopy";
346  case ISD::VAEND: return "vaend";
347  case ISD::VASTART: return "vastart";
348  case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
349  case ISD::EXTRACT_ELEMENT: return "extract_element";
350  case ISD::BUILD_PAIR: return "build_pair";
351  case ISD::STACKSAVE: return "stacksave";
352  case ISD::STACKRESTORE: return "stackrestore";
353  case ISD::TRAP: return "trap";
354  case ISD::DEBUGTRAP: return "debugtrap";
355  case ISD::LIFETIME_START: return "lifetime.start";
356  case ISD::LIFETIME_END: return "lifetime.end";
357  case ISD::GC_TRANSITION_START: return "gc_transition.start";
358  case ISD::GC_TRANSITION_END: return "gc_transition.end";
359  case ISD::GET_DYNAMIC_AREA_OFFSET: return "get.dynamic.area.offset";
360 
361  // Bit manipulation
362  case ISD::ABS: return "abs";
363  case ISD::BITREVERSE: return "bitreverse";
364  case ISD::BSWAP: return "bswap";
365  case ISD::CTPOP: return "ctpop";
366  case ISD::CTTZ: return "cttz";
367  case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef";
368  case ISD::CTLZ: return "ctlz";
369  case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef";
370 
371  // Trampolines
372  case ISD::INIT_TRAMPOLINE: return "init_trampoline";
373  case ISD::ADJUST_TRAMPOLINE: return "adjust_trampoline";
374 
375  case ISD::CONDCODE:
376  switch (cast<CondCodeSDNode>(this)->get()) {
377  default: llvm_unreachable("Unknown setcc condition!");
378  case ISD::SETOEQ: return "setoeq";
379  case ISD::SETOGT: return "setogt";
380  case ISD::SETOGE: return "setoge";
381  case ISD::SETOLT: return "setolt";
382  case ISD::SETOLE: return "setole";
383  case ISD::SETONE: return "setone";
384 
385  case ISD::SETO: return "seto";
386  case ISD::SETUO: return "setuo";
387  case ISD::SETUEQ: return "setueq";
388  case ISD::SETUGT: return "setugt";
389  case ISD::SETUGE: return "setuge";
390  case ISD::SETULT: return "setult";
391  case ISD::SETULE: return "setule";
392  case ISD::SETUNE: return "setune";
393 
394  case ISD::SETEQ: return "seteq";
395  case ISD::SETGT: return "setgt";
396  case ISD::SETGE: return "setge";
397  case ISD::SETLT: return "setlt";
398  case ISD::SETLE: return "setle";
399  case ISD::SETNE: return "setne";
400 
401  case ISD::SETTRUE: return "settrue";
402  case ISD::SETTRUE2: return "settrue2";
403  case ISD::SETFALSE: return "setfalse";
404  case ISD::SETFALSE2: return "setfalse2";
405  }
406  case ISD::VECREDUCE_FADD: return "vecreduce_fadd";
407  case ISD::VECREDUCE_STRICT_FADD: return "vecreduce_strict_fadd";
408  case ISD::VECREDUCE_FMUL: return "vecreduce_fmul";
409  case ISD::VECREDUCE_STRICT_FMUL: return "vecreduce_strict_fmul";
410  case ISD::VECREDUCE_ADD: return "vecreduce_add";
411  case ISD::VECREDUCE_MUL: return "vecreduce_mul";
412  case ISD::VECREDUCE_AND: return "vecreduce_and";
413  case ISD::VECREDUCE_OR: return "vecreduce_or";
414  case ISD::VECREDUCE_XOR: return "vecreduce_xor";
415  case ISD::VECREDUCE_SMAX: return "vecreduce_smax";
416  case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
417  case ISD::VECREDUCE_UMAX: return "vecreduce_umax";
418  case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
419  case ISD::VECREDUCE_FMAX: return "vecreduce_fmax";
420  case ISD::VECREDUCE_FMIN: return "vecreduce_fmin";
421  }
422 }
423 
425  switch (AM) {
426  default: return "";
427  case ISD::PRE_INC: return "<pre-inc>";
428  case ISD::PRE_DEC: return "<pre-dec>";
429  case ISD::POST_INC: return "<post-inc>";
430  case ISD::POST_DEC: return "<post-dec>";
431  }
432 }
433 
435  return Printable([&Node](raw_ostream &OS) {
436 #ifndef NDEBUG
437  OS << 't' << Node.PersistentId;
438 #else
439  OS << (const void*)&Node;
440 #endif
441  });
442 }
443 
444 // Print the MMO with more information from the SelectionDAG.
445 static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
446  const MachineFunction *MF, const Module *M,
447  const MachineFrameInfo *MFI,
448  const TargetInstrInfo *TII, LLVMContext &Ctx) {
449  ModuleSlotTracker MST(M);
450  if (MF)
451  MST.incorporateFunction(MF->getFunction());
453  MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
454 }
455 
456 static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
457  const SelectionDAG *G) {
458  if (G) {
459  const MachineFunction *MF = &G->getMachineFunction();
460  return printMemOperand(OS, MMO, MF, MF->getFunction().getParent(),
461  &MF->getFrameInfo(), G->getSubtarget().getInstrInfo(),
462  *G->getContext());
463  } else {
464  LLVMContext Ctx;
465  return printMemOperand(OS, MMO, /*MF=*/nullptr, /*M=*/nullptr,
466  /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
467  }
468 }
469 
470 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
471 LLVM_DUMP_METHOD void SDNode::dump() const { dump(nullptr); }
472 
474  print(dbgs(), G);
475  dbgs() << '\n';
476 }
477 #endif
478 
480  for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
481  if (i) OS << ",";
482  if (getValueType(i) == MVT::Other)
483  OS << "ch";
484  else
485  OS << getValueType(i).getEVTString();
486  }
487 }
488 
490  if (getFlags().hasNoUnsignedWrap())
491  OS << " nuw";
492 
493  if (getFlags().hasNoSignedWrap())
494  OS << " nsw";
495 
496  if (getFlags().hasExact())
497  OS << " exact";
498 
499  if (getFlags().hasNoNaNs())
500  OS << " nnan";
501 
502  if (getFlags().hasNoInfs())
503  OS << " ninf";
504 
505  if (getFlags().hasNoSignedZeros())
506  OS << " nsz";
507 
508  if (getFlags().hasAllowReciprocal())
509  OS << " arcp";
510 
511  if (getFlags().hasAllowContract())
512  OS << " contract";
513 
514  if (getFlags().hasApproximateFuncs())
515  OS << " afn";
516 
517  if (getFlags().hasAllowReassociation())
518  OS << " reassoc";
519 
520  if (getFlags().hasVectorReduction())
521  OS << " vector-reduction";
522 
523  if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) {
524  if (!MN->memoperands_empty()) {
525  OS << "<";
526  OS << "Mem:";
527  for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
528  e = MN->memoperands_end(); i != e; ++i) {
529  printMemOperand(OS, **i, G);
530  if (std::next(i) != e)
531  OS << " ";
532  }
533  OS << ">";
534  }
535  } else if (const ShuffleVectorSDNode *SVN =
536  dyn_cast<ShuffleVectorSDNode>(this)) {
537  OS << "<";
538  for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
539  int Idx = SVN->getMaskElt(i);
540  if (i) OS << ",";
541  if (Idx < 0)
542  OS << "u";
543  else
544  OS << Idx;
545  }
546  OS << ">";
547  } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
548  OS << '<' << CSDN->getAPIntValue() << '>';
549  } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
550  if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEsingle())
551  OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
552  else if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEdouble())
553  OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
554  else {
555  OS << "<APFloat(";
556  CSDN->getValueAPF().bitcastToAPInt().print(OS, false);
557  OS << ")>";
558  }
559  } else if (const GlobalAddressSDNode *GADN =
560  dyn_cast<GlobalAddressSDNode>(this)) {
561  int64_t offset = GADN->getOffset();
562  OS << '<';
563  GADN->getGlobal()->printAsOperand(OS);
564  OS << '>';
565  if (offset > 0)
566  OS << " + " << offset;
567  else
568  OS << " " << offset;
569  if (unsigned int TF = GADN->getTargetFlags())
570  OS << " [TF=" << TF << ']';
571  } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
572  OS << "<" << FIDN->getIndex() << ">";
573  } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
574  OS << "<" << JTDN->getIndex() << ">";
575  if (unsigned int TF = JTDN->getTargetFlags())
576  OS << " [TF=" << TF << ']';
577  } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
578  int offset = CP->getOffset();
579  if (CP->isMachineConstantPoolEntry())
580  OS << "<" << *CP->getMachineCPVal() << ">";
581  else
582  OS << "<" << *CP->getConstVal() << ">";
583  if (offset > 0)
584  OS << " + " << offset;
585  else
586  OS << " " << offset;
587  if (unsigned int TF = CP->getTargetFlags())
588  OS << " [TF=" << TF << ']';
589  } else if (const TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(this)) {
590  OS << "<" << TI->getIndex() << '+' << TI->getOffset() << ">";
591  if (unsigned TF = TI->getTargetFlags())
592  OS << " [TF=" << TF << ']';
593  } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
594  OS << "<";
595  const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
596  if (LBB)
597  OS << LBB->getName() << " ";
598  OS << (const void*)BBDN->getBasicBlock() << ">";
599  } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
600  OS << ' ' << printReg(R->getReg(),
601  G ? G->getSubtarget().getRegisterInfo() : nullptr);
602  } else if (const ExternalSymbolSDNode *ES =
603  dyn_cast<ExternalSymbolSDNode>(this)) {
604  OS << "'" << ES->getSymbol() << "'";
605  if (unsigned int TF = ES->getTargetFlags())
606  OS << " [TF=" << TF << ']';
607  } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
608  if (M->getValue())
609  OS << "<" << M->getValue() << ">";
610  else
611  OS << "<null>";
612  } else if (const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(this)) {
613  if (MD->getMD())
614  OS << "<" << MD->getMD() << ">";
615  else
616  OS << "<null>";
617  } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
618  OS << ":" << N->getVT().getEVTString();
619  }
620  else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
621  OS << "<";
622 
623  printMemOperand(OS, *LD->getMemOperand(), G);
624 
625  bool doExt = true;
626  switch (LD->getExtensionType()) {
627  default: doExt = false; break;
628  case ISD::EXTLOAD: OS << ", anyext"; break;
629  case ISD::SEXTLOAD: OS << ", sext"; break;
630  case ISD::ZEXTLOAD: OS << ", zext"; break;
631  }
632  if (doExt)
633  OS << " from " << LD->getMemoryVT().getEVTString();
634 
635  const char *AM = getIndexedModeName(LD->getAddressingMode());
636  if (*AM)
637  OS << ", " << AM;
638 
639  OS << ">";
640  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
641  OS << "<";
642  printMemOperand(OS, *ST->getMemOperand(), G);
643 
644  if (ST->isTruncatingStore())
645  OS << ", trunc to " << ST->getMemoryVT().getEVTString();
646 
647  const char *AM = getIndexedModeName(ST->getAddressingMode());
648  if (*AM)
649  OS << ", " << AM;
650 
651  OS << ">";
652  } else if (const MemSDNode* M = dyn_cast<MemSDNode>(this)) {
653  OS << "<";
654  printMemOperand(OS, *M->getMemOperand(), G);
655  OS << ">";
656  } else if (const BlockAddressSDNode *BA =
657  dyn_cast<BlockAddressSDNode>(this)) {
658  int64_t offset = BA->getOffset();
659  OS << "<";
660  BA->getBlockAddress()->getFunction()->printAsOperand(OS, false);
661  OS << ", ";
662  BA->getBlockAddress()->getBasicBlock()->printAsOperand(OS, false);
663  OS << ">";
664  if (offset > 0)
665  OS << " + " << offset;
666  else
667  OS << " " << offset;
668  if (unsigned int TF = BA->getTargetFlags())
669  OS << " [TF=" << TF << ']';
670  } else if (const AddrSpaceCastSDNode *ASC =
671  dyn_cast<AddrSpaceCastSDNode>(this)) {
672  OS << '['
673  << ASC->getSrcAddressSpace()
674  << " -> "
675  << ASC->getDestAddressSpace()
676  << ']';
677  }
678 
679  if (VerboseDAGDumping) {
680  if (unsigned Order = getIROrder())
681  OS << " [ORD=" << Order << ']';
682 
683  if (getNodeId() != -1)
684  OS << " [ID=" << getNodeId() << ']';
685  if (!(isa<ConstantSDNode>(this) || (isa<ConstantFPSDNode>(this))))
686  OS << "# D:" << isDivergent();
687 
688  if (!G)
689  return;
690 
691  DILocation *L = getDebugLoc();
692  if (!L)
693  return;
694 
695  if (auto *Scope = L->getScope())
696  OS << Scope->getFilename();
697  else
698  OS << "<unknown>";
699  OS << ':' << L->getLine();
700  if (unsigned C = L->getColumn())
701  OS << ':' << C;
702 
703  for (SDDbgValue *Dbg : G->GetDbgValues(this)) {
704  if (Dbg->getKind() != SDDbgValue::SDNODE || Dbg->isInvalidated())
705  continue;
706  Dbg->dump(OS);
707  }
708  }
709 }
710 
711 LLVM_DUMP_METHOD void SDDbgValue::dump(raw_ostream &OS) const {
712  OS << " DbgVal";
713  if (kind==SDNODE)
714  OS << '(' << u.s.ResNo << ')';
715  OS << ":\"" << Var->getName() << '"';
716 #ifndef NDEBUG
717  if (Expr->getNumElements())
718  Expr->dump();
719 #endif
720 }
721 
722 /// Return true if this node is so simple that we should just print it inline
723 /// if it appears as an operand.
724 static bool shouldPrintInline(const SDNode &Node) {
725  if (Node.getOpcode() == ISD::EntryToken)
726  return false;
727  return Node.getNumOperands() == 0;
728 }
729 
730 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
731 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
732  for (const SDValue &Op : N->op_values()) {
733  if (shouldPrintInline(*Op.getNode()))
734  continue;
735  if (Op.getNode()->hasOneUse())
736  DumpNodes(Op.getNode(), indent+2, G);
737  }
738 
739  dbgs().indent(indent);
740  N->dump(G);
741 }
742 
743 LLVM_DUMP_METHOD void SelectionDAG::dump() const {
744  dbgs() << "SelectionDAG has " << AllNodes.size() << " nodes:\n";
745 
746  for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end();
747  I != E; ++I) {
748  const SDNode *N = &*I;
749  if (!N->hasOneUse() && N != getRoot().getNode() &&
750  (!shouldPrintInline(*N) || N->use_empty()))
751  DumpNodes(N, 2, this);
752  }
753 
754  if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
755  dbgs() << "\n\n";
756 }
757 #endif
758 
759 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
760  OS << PrintNodeId(*this) << ": ";
761  print_types(OS, G);
762  OS << " = " << getOperationName(G);
763  print_details(OS, G);
764 }
765 
766 static bool printOperand(raw_ostream &OS, const SelectionDAG *G,
767  const SDValue Value) {
768  if (!Value.getNode()) {
769  OS << "<null>";
770  return false;
771  } else if (shouldPrintInline(*Value.getNode())) {
772  OS << Value->getOperationName(G) << ':';
773  Value->print_types(OS, G);
774  Value->print_details(OS, G);
775  return true;
776  } else {
777  OS << PrintNodeId(*Value.getNode());
778  if (unsigned RN = Value.getResNo())
779  OS << ':' << RN;
780  return false;
781  }
782 }
783 
784 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
785 using VisitedSDNodeSet = SmallPtrSet<const SDNode *, 32>;
786 
787 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
788  const SelectionDAG *G, VisitedSDNodeSet &once) {
789  if (!once.insert(N).second) // If we've been here before, return now.
790  return;
791 
792  // Dump the current SDNode, but don't end the line yet.
793  OS.indent(indent);
794  N->printr(OS, G);
795 
796  // Having printed this SDNode, walk the children:
797  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
798  if (i) OS << ",";
799  OS << " ";
800 
801  const SDValue Op = N->getOperand(i);
802  bool printedInline = printOperand(OS, G, Op);
803  if (printedInline)
804  once.insert(Op.getNode());
805  }
806 
807  OS << "\n";
808 
809  // Dump children that have grandchildren on their own line(s).
810  for (const SDValue &Op : N->op_values())
811  DumpNodesr(OS, Op.getNode(), indent+2, G, once);
812 }
813 
814 LLVM_DUMP_METHOD void SDNode::dumpr() const {
815  VisitedSDNodeSet once;
816  DumpNodesr(dbgs(), this, 0, nullptr, once);
817 }
818 
819 LLVM_DUMP_METHOD void SDNode::dumpr(const SelectionDAG *G) const {
820  VisitedSDNodeSet once;
821  DumpNodesr(dbgs(), this, 0, G, once);
822 }
823 #endif
824 
825 static void printrWithDepthHelper(raw_ostream &OS, const SDNode *N,
826  const SelectionDAG *G, unsigned depth,
827  unsigned indent) {
828  if (depth == 0)
829  return;
830 
831  OS.indent(indent);
832 
833  N->print(OS, G);
834 
835  if (depth < 1)
836  return;
837 
838  for (const SDValue &Op : N->op_values()) {
839  // Don't follow chain operands.
840  if (Op.getValueType() == MVT::Other)
841  continue;
842  OS << '\n';
843  printrWithDepthHelper(OS, Op.getNode(), G, depth-1, indent+2);
844  }
845 }
846 
847 void SDNode::printrWithDepth(raw_ostream &OS, const SelectionDAG *G,
848  unsigned depth) const {
849  printrWithDepthHelper(OS, this, G, depth, 0);
850 }
851 
852 void SDNode::printrFull(raw_ostream &OS, const SelectionDAG *G) const {
853  // Don't print impossibly deep things.
854  printrWithDepth(OS, G, 10);
855 }
856 
857 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
858 LLVM_DUMP_METHOD
859 void SDNode::dumprWithDepth(const SelectionDAG *G, unsigned depth) const {
860  printrWithDepth(dbgs(), G, depth);
861 }
862 
863 LLVM_DUMP_METHOD void SDNode::dumprFull(const SelectionDAG *G) const {
864  // Don't print impossibly deep things.
865  dumprWithDepth(G, 10);
866 }
867 #endif
868 
869 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
870  printr(OS, G);
871  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
872  if (i) OS << ", "; else OS << " ";
873  printOperand(OS, G, getOperand(i));
874  }
875  if (DebugLoc DL = getDebugLoc()) {
876  OS << ", ";
877  DL.print(OS);
878  }
879 }
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:757
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:564
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:531
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:870
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:587
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:289
std::string getOperationName(const SelectionDAG *G=nullptr) const
Return the opcode of this operation for printing.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:42
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR...
Definition: ISDOpcodes.h:729
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:351
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:643
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Various leaf nodes.
Definition: ISDOpcodes.h:60
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:598
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:360
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:512
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:692
void print_details(raw_ostream &OS, const SelectionDAG *G) const
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:131
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:795
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:282
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:501
Manage lifetime of a slot tracker for printing IR.
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:377
const SDNodeFlags getFlags() const
Same for subtraction.
Definition: ISDOpcodes.h:254
void print(raw_ostream &OS) const
Support for operator<<.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:346
uint16_t PersistentId
Unique and persistent id per SDNode in the DAG.
The address of the GOT.
Definition: ISDOpcodes.h:66
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:45
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:774
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:428
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:309
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:114
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:449
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:683
static Printable PrintNodeId(const SDNode &Node)
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
PCMARKER - This corresponds to the pcmarker intrinsic.
Definition: ISDOpcodes.h:732
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:627
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:403
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:386
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:191
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:170
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:539
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:706
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:96
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:803
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:660
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:688
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:91
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:471
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:118
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:399
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:422
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
virtual const TargetInstrInfo * getInstrInfo() const
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:123
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:125
static const char * getIndexedModeName(ISD::MemIndexedMode AM)
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:740
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:490
Generic reduction nodes.
Definition: ISDOpcodes.h:859
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
UNDEF - An undefined node.
Definition: ISDOpcodes.h:178
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:517
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:320
TargetInstrInfo - Interface to description of machine instruction set.
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:837
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:861
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:622
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:85
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
Definition: ISDOpcodes.h:845
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition: ISDOpcodes.h:81
static cl::opt< bool > VerboseDAGDumping("dag-dump-verbose", cl::Hidden, cl::desc("Display more information when dumping selection " "DAG nodes."))
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Simple binary floating point operators.
Definition: ISDOpcodes.h:276
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:721
const SDValue & getOperand(unsigned Num) const
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:325
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
This file declares a class to represent arbitrary precision floating point values and provide a varie...
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:751
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:760
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition: ISDOpcodes.h:144
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:763
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:712
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:409
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:789
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:549
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:842
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
HANDLENODE node - Used as a handle for various purposes.
Definition: ISDOpcodes.h:743
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:665
TargetIntrinsicInfo - Interface to description of machine instruction set.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:265
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
void dump() const
Dump this node, for debugging.
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:120
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:401
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:312
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:332
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:444
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:546
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:568
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:637
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:593
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
An SDNode that represents everything that will be needed to construct a MachineInstr.
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:406
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:574
Represents one node in the SelectionDAG.
std::string utostr(uint64_t X, bool isNeg=false)
Definition: StringExtras.h:224
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:413
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:461
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:464
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:305
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:679
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:852
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:631
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:717
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:380
iterator_range< typename GraphTraits< GraphType >::nodes_iterator > nodes(const GraphType &G)
Definition: GraphTraits.h:109
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:479
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:607
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:400
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:273
Same for multiplication.
Definition: ISDOpcodes.h:257
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:601
void print_types(raw_ostream &OS, const SelectionDAG *G) const
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.setjmp intrinsic.
Definition: ISDOpcodes.h:108
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:102
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:338
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:295
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:866
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:769
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:299
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:436
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:198
Conversion operators.
Definition: ISDOpcodes.h:458
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:782
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:467
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:577
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:778
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:368
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:242
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition: ISDOpcodes.h:214
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:907
BRIND - Indirect branch.
Definition: ISDOpcodes.h:627
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:373
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
Definition: ISDOpcodes.h:725
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:616