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SparcISelLowering.h
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
17 
18 #include "Sparc.h"
20 
21 namespace llvm {
22  class SparcSubtarget;
23 
24  namespace SPISD {
25  enum NodeType : unsigned {
27  CMPICC, // Compare two GPR operands, set icc+xcc.
28  CMPFCC, // Compare two FP operands, set fcc.
29  BRICC, // Branch to dest on icc condition
30  BRXCC, // Branch to dest on xcc condition (64-bit only).
31  BRFCC, // Branch to dest on fcc condition
32  SELECT_ICC, // Select between two values using the current ICC flags.
33  SELECT_XCC, // Select between two values using the current XCC flags.
34  SELECT_FCC, // Select between two values using the current FCC flags.
35 
36  Hi, Lo, // Hi/Lo operations, typically on a global address.
37 
38  FTOI, // FP to Int within a FP register.
39  ITOF, // Int to FP within a FP register.
40  FTOX, // FP to Int64 within a FP register.
41  XTOF, // Int64 to FP within a FP register.
42 
43  CALL, // A call instruction.
44  RET_FLAG, // Return with a flag operand.
45  GLOBAL_BASE_REG, // Global base reg for PIC.
46  FLUSHW, // FLUSH register windows to stack.
47 
48  TLS_ADD, // For Thread Local Storage (TLS).
51  };
52  }
53 
55  const SparcSubtarget *Subtarget;
56  public:
58  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
59 
60  bool useSoftFloat() const override;
61 
62  /// computeKnownBitsForTargetNode - Determine which of the bits specified
63  /// in Mask are known to be either zero or one and return them in the
64  /// KnownZero/KnownOne bitsets.
65  void computeKnownBitsForTargetNode(const SDValue Op,
66  KnownBits &Known,
67  const APInt &DemandedElts,
68  const SelectionDAG &DAG,
69  unsigned Depth = 0) const override;
70 
72  EmitInstrWithCustomInserter(MachineInstr &MI,
73  MachineBasicBlock *MBB) const override;
74 
75  const char *getTargetNodeName(unsigned Opcode) const override;
76 
77  ConstraintType getConstraintType(StringRef Constraint) const override;
79  getSingleConstraintMatchWeight(AsmOperandInfo &info,
80  const char *constraint) const override;
81  void LowerAsmOperandForConstraint(SDValue Op,
82  std::string &Constraint,
83  std::vector<SDValue> &Ops,
84  SelectionDAG &DAG) const override;
85 
86  unsigned
87  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
88  if (ConstraintCode == "o")
90  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
91  }
92 
93  std::pair<unsigned, const TargetRegisterClass *>
94  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
95  StringRef Constraint, MVT VT) const override;
96 
97  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
98  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
99  return MVT::i32;
100  }
101 
102  unsigned getRegisterByName(const char* RegName, EVT VT,
103  SelectionDAG &DAG) const override;
104 
105  /// If a physical register, this returns the register that receives the
106  /// exception address on entry to an EH pad.
107  unsigned
108  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
109  return SP::I0;
110  }
111 
112  /// If a physical register, this returns the register that receives the
113  /// exception typeid on entry to a landing pad.
114  unsigned
115  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
116  return SP::I1;
117  }
118 
119  /// Override to support customized stack guard loading.
120  bool useLoadStackGuardNode() const override;
121  void insertSSPDeclarations(Module &M) const override;
122 
123  /// getSetCCResultType - Return the ISD::SETCC ValueType
124  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
125  EVT VT) const override;
126 
127  SDValue
128  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
130  const SDLoc &dl, SelectionDAG &DAG,
131  SmallVectorImpl<SDValue> &InVals) const override;
132  SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
133  bool isVarArg,
135  const SDLoc &dl, SelectionDAG &DAG,
136  SmallVectorImpl<SDValue> &InVals) const;
137  SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
138  bool isVarArg,
140  const SDLoc &dl, SelectionDAG &DAG,
141  SmallVectorImpl<SDValue> &InVals) const;
142 
143  SDValue
144  LowerCall(TargetLowering::CallLoweringInfo &CLI,
145  SmallVectorImpl<SDValue> &InVals) const override;
146  SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
147  SmallVectorImpl<SDValue> &InVals) const;
148  SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
149  SmallVectorImpl<SDValue> &InVals) const;
150 
151  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
153  const SmallVectorImpl<SDValue> &OutVals,
154  const SDLoc &dl, SelectionDAG &DAG) const override;
155  SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
156  bool IsVarArg,
158  const SmallVectorImpl<SDValue> &OutVals,
159  const SDLoc &DL, SelectionDAG &DAG) const;
160  SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
161  bool IsVarArg,
163  const SmallVectorImpl<SDValue> &OutVals,
164  const SDLoc &DL, SelectionDAG &DAG) const;
165 
166  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
167  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
168  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
169  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
170 
171  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
172  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
173  SelectionDAG &DAG) const;
174  SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
175 
176  SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
177  const SDLoc &DL, SelectionDAG &DAG) const;
178  SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
179  const char *LibFuncName,
180  unsigned numArgs) const;
181  SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
182  const SDLoc &DL, SelectionDAG &DAG) const;
183 
184  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
185 
186  SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187 
188  SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL,
189  SelectionDAG &DAG) const;
190 
191  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
192 
193  bool ShouldShrinkFPConstant(EVT VT) const override {
194  // Do not shrink FP constpool if VT == MVT::f128.
195  // (ldd, call _Q_fdtoq) is more expensive than two ldds.
196  return VT != MVT::f128;
197  }
198 
199  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
200  // FIXME: We insert fences for each atomics and generate
201  // sub-optimal code for PSO/TSO. (Approximately nobody uses any
202  // mode but TSO, which makes this even more silly)
203  return true;
204  }
205 
206  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
207 
208  void ReplaceNodeResults(SDNode *N,
210  SelectionDAG &DAG) const override;
211 
212  MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
213  unsigned BROpcode) const;
214  };
215 } // end namespace llvm
216 
217 #endif // SPARC_ISELLOWERING_H
uint64_t CallInst * C
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:877
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This contains information for each constraint that we are lowering.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Machine Value Type.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
lazy value info
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:70
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This file describes how to lower LLVM code to machine code.