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SparcISelLowering.h
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
17 
18 #include "Sparc.h"
20 
21 namespace llvm {
22  class SparcSubtarget;
23 
24  namespace SPISD {
25  enum NodeType : unsigned {
27  CMPICC, // Compare two GPR operands, set icc+xcc.
28  CMPFCC, // Compare two FP operands, set fcc.
29  BRICC, // Branch to dest on icc condition
30  BRXCC, // Branch to dest on xcc condition (64-bit only).
31  BRFCC, // Branch to dest on fcc condition
32  SELECT_ICC, // Select between two values using the current ICC flags.
33  SELECT_XCC, // Select between two values using the current XCC flags.
34  SELECT_FCC, // Select between two values using the current FCC flags.
35 
36  EH_SJLJ_SETJMP, // builtin setjmp operation
37  EH_SJLJ_LONGJMP, // builtin longjmp operation
38 
39  Hi, Lo, // Hi/Lo operations, typically on a global address.
40 
41  FTOI, // FP to Int within a FP register.
42  ITOF, // Int to FP within a FP register.
43  FTOX, // FP to Int64 within a FP register.
44  XTOF, // Int64 to FP within a FP register.
45 
46  CALL, // A call instruction.
47  RET_FLAG, // Return with a flag operand.
48  GLOBAL_BASE_REG, // Global base reg for PIC.
49  FLUSHW, // FLUSH register windows to stack.
50 
51  TLS_ADD, // For Thread Local Storage (TLS).
54  };
55  }
56 
58  const SparcSubtarget *Subtarget;
59  public:
61  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
62 
63  bool useSoftFloat() const override;
64 
65  /// computeKnownBitsForTargetNode - Determine which of the bits specified
66  /// in Mask are known to be either zero or one and return them in the
67  /// KnownZero/KnownOne bitsets.
68  void computeKnownBitsForTargetNode(const SDValue Op,
69  KnownBits &Known,
70  const APInt &DemandedElts,
71  const SelectionDAG &DAG,
72  unsigned Depth = 0) const override;
73 
75  EmitInstrWithCustomInserter(MachineInstr &MI,
76  MachineBasicBlock *MBB) const override;
77 
78  const char *getTargetNodeName(unsigned Opcode) const override;
79 
80  ConstraintType getConstraintType(StringRef Constraint) const override;
82  getSingleConstraintMatchWeight(AsmOperandInfo &info,
83  const char *constraint) const override;
84  void LowerAsmOperandForConstraint(SDValue Op,
85  std::string &Constraint,
86  std::vector<SDValue> &Ops,
87  SelectionDAG &DAG) const override;
88 
89  unsigned
90  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
91  if (ConstraintCode == "o")
93  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
94  }
95 
96  std::pair<unsigned, const TargetRegisterClass *>
97  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
98  StringRef Constraint, MVT VT) const override;
99 
100  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
101  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
102  return MVT::i32;
103  }
104 
105  unsigned getRegisterByName(const char* RegName, EVT VT,
106  SelectionDAG &DAG) const override;
107 
108  /// If a physical register, this returns the register that receives the
109  /// exception address on entry to an EH pad.
110  unsigned
111  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
112  return SP::I0;
113  }
114 
115  /// If a physical register, this returns the register that receives the
116  /// exception typeid on entry to a landing pad.
117  unsigned
118  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
119  return SP::I1;
120  }
121 
122  /// Override to support customized stack guard loading.
123  bool useLoadStackGuardNode() const override;
124  void insertSSPDeclarations(Module &M) const override;
125 
126  /// getSetCCResultType - Return the ISD::SETCC ValueType
127  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
128  EVT VT) const override;
129 
130  SDValue
131  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
133  const SDLoc &dl, SelectionDAG &DAG,
134  SmallVectorImpl<SDValue> &InVals) const override;
135  SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv,
136  bool isVarArg,
138  const SDLoc &dl, SelectionDAG &DAG,
139  SmallVectorImpl<SDValue> &InVals) const;
140  SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv,
141  bool isVarArg,
143  const SDLoc &dl, SelectionDAG &DAG,
144  SmallVectorImpl<SDValue> &InVals) const;
145 
146  SDValue
147  LowerCall(TargetLowering::CallLoweringInfo &CLI,
148  SmallVectorImpl<SDValue> &InVals) const override;
149  SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
150  SmallVectorImpl<SDValue> &InVals) const;
151  SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
152  SmallVectorImpl<SDValue> &InVals) const;
153 
154  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
156  const SmallVectorImpl<SDValue> &OutVals,
157  const SDLoc &dl, SelectionDAG &DAG) const override;
158  SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
159  bool IsVarArg,
161  const SmallVectorImpl<SDValue> &OutVals,
162  const SDLoc &DL, SelectionDAG &DAG) const;
163  SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
164  bool IsVarArg,
166  const SmallVectorImpl<SDValue> &OutVals,
167  const SDLoc &DL, SelectionDAG &DAG) const;
168 
169  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
170  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
172  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
173 
174  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
175  const SparcTargetLowering &TLI) const ;
176  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
177  const SparcTargetLowering &TLI) const ;
178 
179  unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
180  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
181  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
182  SelectionDAG &DAG) const;
183  SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
184 
185  SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg,
186  const SDLoc &DL, SelectionDAG &DAG) const;
187  SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
188  const char *LibFuncName,
189  unsigned numArgs) const;
190  SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
191  const SDLoc &DL, SelectionDAG &DAG) const;
192 
193  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
194 
195  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
196 
197  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
198 
199  bool ShouldShrinkFPConstant(EVT VT) const override {
200  // Do not shrink FP constpool if VT == MVT::f128.
201  // (ldd, call _Q_fdtoq) is more expensive than two ldds.
202  return VT != MVT::f128;
203  }
204 
205  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
206  // FIXME: We insert fences for each atomics and generate
207  // sub-optimal code for PSO/TSO. (Approximately nobody uses any
208  // mode but TSO, which makes this even more silly)
209  return true;
210  }
211 
212  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
213 
214  void ReplaceNodeResults(SDNode *N,
216  SelectionDAG &DAG) const override;
217 
218  MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
219  unsigned BROpcode) const;
220  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
221  MachineBasicBlock *MBB) const;
222  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
223  MachineBasicBlock *MBB) const;
224  };
225 } // end namespace llvm
226 
227 #endif // SPARC_ISELLOWERING_H
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
Function Alias Analysis Results
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This contains information for each constraint that we are lowering.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
Machine Value Type.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
lazy value info
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false Value Value * Arg
Representation of each machine instruction.
Definition: MachineInstr.h:59
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This file describes how to lower LLVM code to machine code.