LLVM  6.0.0svn
SparcMCCodeEmitter.cpp
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1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SparcMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "SparcMCExpr.h"
16 #include "SparcMCTargetDesc.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Endian.h"
35 #include <cassert>
36 #include <cstdint>
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mccodeemitter"
41 
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43 
44 namespace {
45 
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47  const MCInstrInfo &MCII;
48  MCContext &Ctx;
49 
50 public:
51  SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
52  : MCII(mcii), Ctx(ctx) {}
53  SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
54  SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
55  ~SparcMCCodeEmitter() override = default;
56 
57  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
59  const MCSubtargetInfo &STI) const override;
60 
61  // getBinaryCodeForInstr - TableGen'erated function for getting the
62  // binary encoding for an instruction.
63  uint64_t getBinaryCodeForInstr(const MCInst &MI,
65  const MCSubtargetInfo &STI) const;
66 
67  /// getMachineOpValue - Return binary encoding of operand. If the machine
68  /// operand requires relocation, record the relocation and return zero.
69  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
71  const MCSubtargetInfo &STI) const;
72 
73  unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const;
76  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
78  const MCSubtargetInfo &STI) const;
79  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
81  const MCSubtargetInfo &STI) const;
82  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
84  const MCSubtargetInfo &STI) const;
85 
86 private:
87  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
88  void verifyInstructionPredicates(const MCInst &MI,
89  uint64_t AvailableFeatures) const;
90 };
91 
92 } // end anonymous namespace
93 
94 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
96  const MCSubtargetInfo &STI) const {
97  verifyInstructionPredicates(MI,
98  computeAvailableFeatures(STI.getFeatureBits()));
99 
100  unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
101 
102  if (Ctx.getAsmInfo()->isLittleEndian()) {
103  // Output the bits in little-endian byte order.
104  support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
105  } else {
106  // Output the bits in big-endian byte order.
107  support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
108  }
109  unsigned tlsOpNo = 0;
110  switch (MI.getOpcode()) {
111  default: break;
112  case SP::TLS_CALL: tlsOpNo = 1; break;
113  case SP::TLS_ADDrr:
114  case SP::TLS_ADDXrr:
115  case SP::TLS_LDrr:
116  case SP::TLS_LDXrr: tlsOpNo = 3; break;
117  }
118  if (tlsOpNo != 0) {
119  const MCOperand &MO = MI.getOperand(tlsOpNo);
120  uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
121  assert(op == 0 && "Unexpected operand value!");
122  (void)op; // suppress warning.
123  }
124 
125  ++MCNumEmitted; // Keep track of the # of mi's emitted.
126 }
127 
128 unsigned SparcMCCodeEmitter::
129 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
130  SmallVectorImpl<MCFixup> &Fixups,
131  const MCSubtargetInfo &STI) const {
132  if (MO.isReg())
133  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
134 
135  if (MO.isImm())
136  return MO.getImm();
137 
138  assert(MO.isExpr());
139  const MCExpr *Expr = MO.getExpr();
140  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
141  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
142  Fixups.push_back(MCFixup::create(0, Expr, Kind));
143  return 0;
144  }
145 
146  int64_t Res;
147  if (Expr->evaluateAsAbsolute(Res))
148  return Res;
149 
150  llvm_unreachable("Unhandled expression!");
151  return 0;
152 }
153 
154 unsigned SparcMCCodeEmitter::
155 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
156  SmallVectorImpl<MCFixup> &Fixups,
157  const MCSubtargetInfo &STI) const {
158  const MCOperand &MO = MI.getOperand(OpNo);
159  if (MO.isReg() || MO.isImm())
160  return getMachineOpValue(MI, MO, Fixups, STI);
161 
162  if (MI.getOpcode() == SP::TLS_CALL) {
163  // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
164  // encodeInstruction.
165 #ifndef NDEBUG
166  // Verify that the callee is actually __tls_get_addr.
167  const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
168  assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
169  "Unexpected expression in TLS_CALL");
170  const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
171  assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
172  "Unexpected function for TLS_CALL");
173 #endif
174  return 0;
175  }
176 
178 
179  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
180  if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
182  }
183 
184  Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
185 
186  return 0;
187 }
188 
189 unsigned SparcMCCodeEmitter::
190 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
191  SmallVectorImpl<MCFixup> &Fixups,
192  const MCSubtargetInfo &STI) const {
193  const MCOperand &MO = MI.getOperand(OpNo);
194  if (MO.isReg() || MO.isImm())
195  return getMachineOpValue(MI, MO, Fixups, STI);
196 
197  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
199  return 0;
200 }
201 
202 unsigned SparcMCCodeEmitter::
203 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
204  SmallVectorImpl<MCFixup> &Fixups,
205  const MCSubtargetInfo &STI) const {
206  const MCOperand &MO = MI.getOperand(OpNo);
207  if (MO.isReg() || MO.isImm())
208  return getMachineOpValue(MI, MO, Fixups, STI);
209 
210  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
212  return 0;
213 }
214 
215 unsigned SparcMCCodeEmitter::
216 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
217  SmallVectorImpl<MCFixup> &Fixups,
218  const MCSubtargetInfo &STI) const {
219  const MCOperand &MO = MI.getOperand(OpNo);
220  if (MO.isReg() || MO.isImm())
221  return getMachineOpValue(MI, MO, Fixups, STI);
222 
223  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
225  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
227 
228  return 0;
229 }
230 
231 #define ENABLE_INSTR_PREDICATE_VERIFIER
232 #include "SparcGenMCCodeEmitter.inc"
233 
235  const MCRegisterInfo &MRI,
236  MCContext &Ctx) {
237  return new SparcMCCodeEmitter(MCII, Ctx);
238 }
bool isImm() const
Definition: MCInst.h:59
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isReg() const
Definition: MCInst.h:58
STATISTIC(NumFunctions, "Total number of functions")
#define op(i)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:59
const MCExpr * getExpr() const
Definition: MCInst.h:96
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:76
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:61
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:82
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:82
fixup_sparc_bpr - 16-bit fixup for bpr
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ExprKind getKind() const
Definition: MCExpr.h:73
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:41
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
fixup_sparc_br22 - 22-bit PC relative relocation for branches
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: SparcMCExpr.h:79
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
unsigned getOpcode() const
Definition: MCInst.h:172
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35