LLVM  6.0.0svn
SystemZAsmParser.cpp
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1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
23 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/SMLoc.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42  int64_t Value = CE->getValue();
43  return Value >= MinValue && Value <= MaxValue;
44  }
45  return false;
46 }
47 
48 namespace {
49 
51  GR32Reg,
52  GRH32Reg,
53  GR64Reg,
54  GR128Reg,
55  ADDR32Reg,
56  ADDR64Reg,
57  FP32Reg,
58  FP64Reg,
59  FP128Reg,
60  VR32Reg,
61  VR64Reg,
62  VR128Reg,
63  AR32Reg,
64  CR64Reg,
65 };
66 
67 enum MemoryKind {
68  BDMem,
69  BDXMem,
70  BDLMem,
71  BDRMem,
72  BDVMem
73 };
74 
75 class SystemZOperand : public MCParsedAsmOperand {
76 private:
77  enum OperandKind {
78  KindInvalid,
79  KindToken,
80  KindReg,
81  KindImm,
82  KindImmTLS,
83  KindMem
84  };
85 
86  OperandKind Kind;
87  SMLoc StartLoc, EndLoc;
88 
89  // A string of length Length, starting at Data.
90  struct TokenOp {
91  const char *Data;
92  unsigned Length;
93  };
94 
95  // LLVM register Num, which has kind Kind. In some ways it might be
96  // easier for this class to have a register bank (general, floating-point
97  // or access) and a raw register number (0-15). This would postpone the
98  // interpretation of the operand to the add*() methods and avoid the need
99  // for context-dependent parsing. However, we do things the current way
100  // because of the virtual getReg() method, which needs to distinguish
101  // between (say) %r0 used as a single register and %r0 used as a pair.
102  // Context-dependent parsing can also give us slightly better error
103  // messages when invalid pairs like %r1 are used.
104  struct RegOp {
106  unsigned Num;
107  };
108 
109  // Base + Disp + Index, where Base and Index are LLVM registers or 0.
110  // MemKind says what type of memory this is and RegKind says what type
111  // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
112  // length for D(L,B)-style operands, otherwise it is null.
113  struct MemOp {
114  unsigned Base : 12;
115  unsigned Index : 12;
116  unsigned MemKind : 4;
117  unsigned RegKind : 4;
118  const MCExpr *Disp;
119  union {
120  const MCExpr *Imm;
121  unsigned Reg;
122  } Length;
123  };
124 
125  // Imm is an immediate operand, and Sym is an optional TLS symbol
126  // for use with a __tls_get_offset marker relocation.
127  struct ImmTLSOp {
128  const MCExpr *Imm;
129  const MCExpr *Sym;
130  };
131 
132  union {
133  TokenOp Token;
134  RegOp Reg;
135  const MCExpr *Imm;
136  ImmTLSOp ImmTLS;
137  MemOp Mem;
138  };
139 
140  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
141  // Add as immediates when possible. Null MCExpr = 0.
142  if (!Expr)
144  else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
145  Inst.addOperand(MCOperand::createImm(CE->getValue()));
146  else
147  Inst.addOperand(MCOperand::createExpr(Expr));
148  }
149 
150 public:
151  SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
152  : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
153 
154  // Create particular kinds of operand.
155  static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
156  SMLoc EndLoc) {
157  return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
158  }
159 
160  static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
161  auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
162  Op->Token.Data = Str.data();
163  Op->Token.Length = Str.size();
164  return Op;
165  }
166 
167  static std::unique_ptr<SystemZOperand>
168  createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
169  auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
170  Op->Reg.Kind = Kind;
171  Op->Reg.Num = Num;
172  return Op;
173  }
174 
175  static std::unique_ptr<SystemZOperand>
176  createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
177  auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
178  Op->Imm = Expr;
179  return Op;
180  }
181 
182  static std::unique_ptr<SystemZOperand>
183  createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
184  const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
185  unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
186  auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
187  Op->Mem.MemKind = MemKind;
188  Op->Mem.RegKind = RegKind;
189  Op->Mem.Base = Base;
190  Op->Mem.Index = Index;
191  Op->Mem.Disp = Disp;
192  if (MemKind == BDLMem)
193  Op->Mem.Length.Imm = LengthImm;
194  if (MemKind == BDRMem)
195  Op->Mem.Length.Reg = LengthReg;
196  return Op;
197  }
198 
199  static std::unique_ptr<SystemZOperand>
200  createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
201  SMLoc StartLoc, SMLoc EndLoc) {
202  auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
203  Op->ImmTLS.Imm = Imm;
204  Op->ImmTLS.Sym = Sym;
205  return Op;
206  }
207 
208  // Token operands
209  bool isToken() const override {
210  return Kind == KindToken;
211  }
212  StringRef getToken() const {
213  assert(Kind == KindToken && "Not a token");
214  return StringRef(Token.Data, Token.Length);
215  }
216 
217  // Register operands.
218  bool isReg() const override {
219  return Kind == KindReg;
220  }
221  bool isReg(RegisterKind RegKind) const {
222  return Kind == KindReg && Reg.Kind == RegKind;
223  }
224  unsigned getReg() const override {
225  assert(Kind == KindReg && "Not a register");
226  return Reg.Num;
227  }
228 
229  // Immediate operands.
230  bool isImm() const override {
231  return Kind == KindImm;
232  }
233  bool isImm(int64_t MinValue, int64_t MaxValue) const {
234  return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
235  }
236  const MCExpr *getImm() const {
237  assert(Kind == KindImm && "Not an immediate");
238  return Imm;
239  }
240 
241  // Immediate operands with optional TLS symbol.
242  bool isImmTLS() const {
243  return Kind == KindImmTLS;
244  }
245 
246  // Memory operands.
247  bool isMem() const override {
248  return Kind == KindMem;
249  }
250  bool isMem(MemoryKind MemKind) const {
251  return (Kind == KindMem &&
252  (Mem.MemKind == MemKind ||
253  // A BDMem can be treated as a BDXMem in which the index
254  // register field is 0.
255  (Mem.MemKind == BDMem && MemKind == BDXMem)));
256  }
257  bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
258  return isMem(MemKind) && Mem.RegKind == RegKind;
259  }
260  bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
261  return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
262  }
263  bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
264  return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
265  }
266  bool isMemDisp12Len4(RegisterKind RegKind) const {
267  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
268  }
269  bool isMemDisp12Len8(RegisterKind RegKind) const {
270  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
271  }
272 
273  // Override MCParsedAsmOperand.
274  SMLoc getStartLoc() const override { return StartLoc; }
275  SMLoc getEndLoc() const override { return EndLoc; }
276  void print(raw_ostream &OS) const override;
277 
278  /// getLocRange - Get the range between the first and last token of this
279  /// operand.
280  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
281 
282  // Used by the TableGen code to add particular types of operand
283  // to an instruction.
284  void addRegOperands(MCInst &Inst, unsigned N) const {
285  assert(N == 1 && "Invalid number of operands");
287  }
288  void addImmOperands(MCInst &Inst, unsigned N) const {
289  assert(N == 1 && "Invalid number of operands");
290  addExpr(Inst, getImm());
291  }
292  void addBDAddrOperands(MCInst &Inst, unsigned N) const {
293  assert(N == 2 && "Invalid number of operands");
294  assert(isMem(BDMem) && "Invalid operand type");
295  Inst.addOperand(MCOperand::createReg(Mem.Base));
296  addExpr(Inst, Mem.Disp);
297  }
298  void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
299  assert(N == 3 && "Invalid number of operands");
300  assert(isMem(BDXMem) && "Invalid operand type");
301  Inst.addOperand(MCOperand::createReg(Mem.Base));
302  addExpr(Inst, Mem.Disp);
303  Inst.addOperand(MCOperand::createReg(Mem.Index));
304  }
305  void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
306  assert(N == 3 && "Invalid number of operands");
307  assert(isMem(BDLMem) && "Invalid operand type");
308  Inst.addOperand(MCOperand::createReg(Mem.Base));
309  addExpr(Inst, Mem.Disp);
310  addExpr(Inst, Mem.Length.Imm);
311  }
312  void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
313  assert(N == 3 && "Invalid number of operands");
314  assert(isMem(BDRMem) && "Invalid operand type");
315  Inst.addOperand(MCOperand::createReg(Mem.Base));
316  addExpr(Inst, Mem.Disp);
317  Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
318  }
319  void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
320  assert(N == 3 && "Invalid number of operands");
321  assert(isMem(BDVMem) && "Invalid operand type");
322  Inst.addOperand(MCOperand::createReg(Mem.Base));
323  addExpr(Inst, Mem.Disp);
324  Inst.addOperand(MCOperand::createReg(Mem.Index));
325  }
326  void addImmTLSOperands(MCInst &Inst, unsigned N) const {
327  assert(N == 2 && "Invalid number of operands");
328  assert(Kind == KindImmTLS && "Invalid operand type");
329  addExpr(Inst, ImmTLS.Imm);
330  if (ImmTLS.Sym)
331  addExpr(Inst, ImmTLS.Sym);
332  }
333 
334  // Used by the TableGen code to check for particular operand types.
335  bool isGR32() const { return isReg(GR32Reg); }
336  bool isGRH32() const { return isReg(GRH32Reg); }
337  bool isGRX32() const { return false; }
338  bool isGR64() const { return isReg(GR64Reg); }
339  bool isGR128() const { return isReg(GR128Reg); }
340  bool isADDR32() const { return isReg(ADDR32Reg); }
341  bool isADDR64() const { return isReg(ADDR64Reg); }
342  bool isADDR128() const { return false; }
343  bool isFP32() const { return isReg(FP32Reg); }
344  bool isFP64() const { return isReg(FP64Reg); }
345  bool isFP128() const { return isReg(FP128Reg); }
346  bool isVR32() const { return isReg(VR32Reg); }
347  bool isVR64() const { return isReg(VR64Reg); }
348  bool isVF128() const { return false; }
349  bool isVR128() const { return isReg(VR128Reg); }
350  bool isAR32() const { return isReg(AR32Reg); }
351  bool isCR64() const { return isReg(CR64Reg); }
352  bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
353  bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
354  bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
355  bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
356  bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
357  bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
358  bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
359  bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
360  bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
361  bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
362  bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
363  bool isU1Imm() const { return isImm(0, 1); }
364  bool isU2Imm() const { return isImm(0, 3); }
365  bool isU3Imm() const { return isImm(0, 7); }
366  bool isU4Imm() const { return isImm(0, 15); }
367  bool isU6Imm() const { return isImm(0, 63); }
368  bool isU8Imm() const { return isImm(0, 255); }
369  bool isS8Imm() const { return isImm(-128, 127); }
370  bool isU12Imm() const { return isImm(0, 4095); }
371  bool isU16Imm() const { return isImm(0, 65535); }
372  bool isS16Imm() const { return isImm(-32768, 32767); }
373  bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
374  bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
375  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
376 };
377 
378 class SystemZAsmParser : public MCTargetAsmParser {
379 #define GET_ASSEMBLER_HEADER
380 #include "SystemZGenAsmMatcher.inc"
381 
382 private:
383  MCAsmParser &Parser;
384  enum RegisterGroup {
385  RegGR,
386  RegFP,
387  RegV,
388  RegAR,
389  RegCR
390  };
391  struct Register {
392  RegisterGroup Group;
393  unsigned Num;
394  SMLoc StartLoc, EndLoc;
395  };
396 
397  bool parseRegister(Register &Reg);
398 
399  bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
400  bool IsAddress = false);
401 
402  OperandMatchResultTy parseRegister(OperandVector &Operands,
403  RegisterGroup Group, const unsigned *Regs,
405 
406  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
407 
408  bool parseAddress(bool &HaveReg1, Register &Reg1,
409  bool &HaveReg2, Register &Reg2,
410  const MCExpr *&Disp, const MCExpr *&Length);
411  bool parseAddressRegister(Register &Reg);
412 
413  bool ParseDirectiveInsn(SMLoc L);
414 
415  OperandMatchResultTy parseAddress(OperandVector &Operands,
416  MemoryKind MemKind, const unsigned *Regs,
418 
419  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
420  int64_t MaxVal, bool AllowTLS);
421 
422  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
423 
424 public:
425  SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
426  const MCInstrInfo &MII,
427  const MCTargetOptions &Options)
428  : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
430 
431  // Alias the .word directive to .short.
432  parser.addAliasForDirective(".word", ".short");
433 
434  // Initialize the set of available features.
435  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
436  }
437 
438  // Override MCTargetAsmParser.
439  bool ParseDirective(AsmToken DirectiveID) override;
440  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
441  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
442  SMLoc NameLoc, OperandVector &Operands) override;
443  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
444  OperandVector &Operands, MCStreamer &Out,
445  uint64_t &ErrorInfo,
446  bool MatchingInlineAsm) override;
447 
448  // Used by the TableGen code to parse particular operand types.
449  OperandMatchResultTy parseGR32(OperandVector &Operands) {
450  return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
451  }
452  OperandMatchResultTy parseGRH32(OperandVector &Operands) {
453  return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
454  }
455  OperandMatchResultTy parseGRX32(OperandVector &Operands) {
456  llvm_unreachable("GRX32 should only be used for pseudo instructions");
457  }
458  OperandMatchResultTy parseGR64(OperandVector &Operands) {
459  return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
460  }
461  OperandMatchResultTy parseGR128(OperandVector &Operands) {
462  return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
463  }
464  OperandMatchResultTy parseADDR32(OperandVector &Operands) {
465  return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
466  }
467  OperandMatchResultTy parseADDR64(OperandVector &Operands) {
468  return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
469  }
470  OperandMatchResultTy parseADDR128(OperandVector &Operands) {
471  llvm_unreachable("Shouldn't be used as an operand");
472  }
473  OperandMatchResultTy parseFP32(OperandVector &Operands) {
474  return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
475  }
476  OperandMatchResultTy parseFP64(OperandVector &Operands) {
477  return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
478  }
479  OperandMatchResultTy parseFP128(OperandVector &Operands) {
480  return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
481  }
482  OperandMatchResultTy parseVR32(OperandVector &Operands) {
483  return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
484  }
485  OperandMatchResultTy parseVR64(OperandVector &Operands) {
486  return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
487  }
488  OperandMatchResultTy parseVF128(OperandVector &Operands) {
489  llvm_unreachable("Shouldn't be used as an operand");
490  }
491  OperandMatchResultTy parseVR128(OperandVector &Operands) {
492  return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
493  }
494  OperandMatchResultTy parseAR32(OperandVector &Operands) {
495  return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
496  }
497  OperandMatchResultTy parseCR64(OperandVector &Operands) {
498  return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
499  }
500  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
501  return parseAnyRegister(Operands);
502  }
503  OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
504  return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
505  }
506  OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
507  return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
508  }
509  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
510  return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
511  }
512  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
513  return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
514  }
515  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
516  return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
517  }
518  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
519  return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
520  }
521  OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
522  return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
523  }
524  OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
525  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
526  }
527  OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
528  return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
529  }
530  OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
531  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
532  }
533  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
534  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
535  }
536  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
537  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
538  }
539 };
540 
541 } // end anonymous namespace
542 
543 #define GET_REGISTER_MATCHER
544 #define GET_SUBTARGET_FEATURE_NAME
545 #define GET_MATCHER_IMPLEMENTATION
546 #define GET_MNEMONIC_SPELL_CHECKER
547 #include "SystemZGenAsmMatcher.inc"
548 
549 // Used for the .insn directives; contains information needed to parse the
550 // operands in the directive.
553  uint64_t Opcode;
554  int32_t NumOperands;
555  MatchClassKind OperandKinds[5];
556 };
557 
558 // For equal_range comparison.
559 struct CompareInsn {
560  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
561  return LHS.Format < RHS;
562  }
563  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
564  return LHS < RHS.Format;
565  }
566  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
567  return LHS.Format < RHS.Format;
568  }
569 };
570 
571 // Table initializing information for parsing the .insn directive.
572 static struct InsnMatchEntry InsnMatchTable[] = {
573  /* Format, Opcode, NumOperands, OperandKinds */
574  { "e", SystemZ::InsnE, 1,
575  { MCK_U16Imm } },
576  { "ri", SystemZ::InsnRI, 3,
577  { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
578  { "rie", SystemZ::InsnRIE, 4,
579  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
580  { "ril", SystemZ::InsnRIL, 3,
581  { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
582  { "rilu", SystemZ::InsnRILU, 3,
583  { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
584  { "ris", SystemZ::InsnRIS, 5,
585  { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
586  { "rr", SystemZ::InsnRR, 3,
587  { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
588  { "rre", SystemZ::InsnRRE, 3,
589  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
590  { "rrf", SystemZ::InsnRRF, 5,
591  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
592  { "rrs", SystemZ::InsnRRS, 5,
593  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
594  { "rs", SystemZ::InsnRS, 4,
595  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
596  { "rse", SystemZ::InsnRSE, 4,
597  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
598  { "rsi", SystemZ::InsnRSI, 4,
599  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
600  { "rsy", SystemZ::InsnRSY, 4,
601  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
602  { "rx", SystemZ::InsnRX, 3,
603  { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
604  { "rxe", SystemZ::InsnRXE, 3,
605  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
606  { "rxf", SystemZ::InsnRXF, 4,
607  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
608  { "rxy", SystemZ::InsnRXY, 3,
609  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
610  { "s", SystemZ::InsnS, 2,
611  { MCK_U32Imm, MCK_BDAddr64Disp12 } },
612  { "si", SystemZ::InsnSI, 3,
613  { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
614  { "sil", SystemZ::InsnSIL, 3,
615  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
616  { "siy", SystemZ::InsnSIY, 3,
617  { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
618  { "ss", SystemZ::InsnSS, 4,
619  { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
620  { "sse", SystemZ::InsnSSE, 3,
621  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
622  { "ssf", SystemZ::InsnSSF, 4,
623  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
624 };
625 
626 void SystemZOperand::print(raw_ostream &OS) const {
627  llvm_unreachable("Not implemented");
628 }
629 
630 // Parse one register of the form %<prefix><number>.
631 bool SystemZAsmParser::parseRegister(Register &Reg) {
632  Reg.StartLoc = Parser.getTok().getLoc();
633 
634  // Eat the % prefix.
635  if (Parser.getTok().isNot(AsmToken::Percent))
636  return Error(Parser.getTok().getLoc(), "register expected");
637  Parser.Lex();
638 
639  // Expect a register name.
640  if (Parser.getTok().isNot(AsmToken::Identifier))
641  return Error(Reg.StartLoc, "invalid register");
642 
643  // Check that there's a prefix.
644  StringRef Name = Parser.getTok().getString();
645  if (Name.size() < 2)
646  return Error(Reg.StartLoc, "invalid register");
647  char Prefix = Name[0];
648 
649  // Treat the rest of the register name as a register number.
650  if (Name.substr(1).getAsInteger(10, Reg.Num))
651  return Error(Reg.StartLoc, "invalid register");
652 
653  // Look for valid combinations of prefix and number.
654  if (Prefix == 'r' && Reg.Num < 16)
655  Reg.Group = RegGR;
656  else if (Prefix == 'f' && Reg.Num < 16)
657  Reg.Group = RegFP;
658  else if (Prefix == 'v' && Reg.Num < 32)
659  Reg.Group = RegV;
660  else if (Prefix == 'a' && Reg.Num < 16)
661  Reg.Group = RegAR;
662  else if (Prefix == 'c' && Reg.Num < 16)
663  Reg.Group = RegCR;
664  else
665  return Error(Reg.StartLoc, "invalid register");
666 
667  Reg.EndLoc = Parser.getTok().getLoc();
668  Parser.Lex();
669  return false;
670 }
671 
672 // Parse a register of group Group. If Regs is nonnull, use it to map
673 // the raw register number to LLVM numbering, with zero entries
674 // indicating an invalid register. IsAddress says whether the
675 // register appears in an address context. Allow FP Group if expecting
676 // RegV Group, since the f-prefix yields the FP group even while used
677 // with vector instructions.
678 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
679  const unsigned *Regs, bool IsAddress) {
680  if (parseRegister(Reg))
681  return true;
682  if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
683  return Error(Reg.StartLoc, "invalid operand for instruction");
684  if (Regs && Regs[Reg.Num] == 0)
685  return Error(Reg.StartLoc, "invalid register pair");
686  if (Reg.Num == 0 && IsAddress)
687  return Error(Reg.StartLoc, "%r0 used in an address");
688  if (Regs)
689  Reg.Num = Regs[Reg.Num];
690  return false;
691 }
692 
693 // Parse a register and add it to Operands. The other arguments are as above.
695 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
696  const unsigned *Regs, RegisterKind Kind) {
697  if (Parser.getTok().isNot(AsmToken::Percent))
698  return MatchOperand_NoMatch;
699 
700  Register Reg;
701  bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
702  if (parseRegister(Reg, Group, Regs, IsAddress))
703  return MatchOperand_ParseFail;
704 
705  Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
706  Reg.StartLoc, Reg.EndLoc));
707  return MatchOperand_Success;
708 }
709 
710 // Parse any type of register (including integers) and add it to Operands.
712 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
713  // Handle integer values.
714  if (Parser.getTok().is(AsmToken::Integer)) {
715  const MCExpr *Register;
716  SMLoc StartLoc = Parser.getTok().getLoc();
717  if (Parser.parseExpression(Register))
718  return MatchOperand_ParseFail;
719 
720  if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
721  int64_t Value = CE->getValue();
722  if (Value < 0 || Value > 15) {
723  Error(StartLoc, "invalid register");
724  return MatchOperand_ParseFail;
725  }
726  }
727 
728  SMLoc EndLoc =
729  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
730 
731  Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
732  }
733  else {
734  Register Reg;
735  if (parseRegister(Reg))
736  return MatchOperand_ParseFail;
737 
738  // Map to the correct register kind.
740  unsigned RegNo;
741  if (Reg.Group == RegGR) {
742  Kind = GR64Reg;
743  RegNo = SystemZMC::GR64Regs[Reg.Num];
744  }
745  else if (Reg.Group == RegFP) {
746  Kind = FP64Reg;
747  RegNo = SystemZMC::FP64Regs[Reg.Num];
748  }
749  else if (Reg.Group == RegV) {
750  Kind = VR128Reg;
751  RegNo = SystemZMC::VR128Regs[Reg.Num];
752  }
753  else if (Reg.Group == RegAR) {
754  Kind = AR32Reg;
755  RegNo = SystemZMC::AR32Regs[Reg.Num];
756  }
757  else if (Reg.Group == RegCR) {
758  Kind = CR64Reg;
759  RegNo = SystemZMC::CR64Regs[Reg.Num];
760  }
761  else {
762  return MatchOperand_ParseFail;
763  }
764 
765  Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
766  Reg.StartLoc, Reg.EndLoc));
767  }
768  return MatchOperand_Success;
769 }
770 
771 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
772 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
773  bool &HaveReg2, Register &Reg2,
774  const MCExpr *&Disp,
775  const MCExpr *&Length) {
776  // Parse the displacement, which must always be present.
777  if (getParser().parseExpression(Disp))
778  return true;
779 
780  // Parse the optional base and index.
781  HaveReg1 = false;
782  HaveReg2 = false;
783  Length = nullptr;
784  if (getLexer().is(AsmToken::LParen)) {
785  Parser.Lex();
786 
787  if (getLexer().is(AsmToken::Percent)) {
788  // Parse the first register.
789  HaveReg1 = true;
790  if (parseRegister(Reg1))
791  return true;
792  } else {
793  // Parse the length.
794  if (getParser().parseExpression(Length))
795  return true;
796  }
797 
798  // Check whether there's a second register.
799  if (getLexer().is(AsmToken::Comma)) {
800  Parser.Lex();
801  HaveReg2 = true;
802  if (parseRegister(Reg2))
803  return true;
804  }
805 
806  // Consume the closing bracket.
807  if (getLexer().isNot(AsmToken::RParen))
808  return Error(Parser.getTok().getLoc(), "unexpected token in address");
809  Parser.Lex();
810  }
811  return false;
812 }
813 
814 // Verify that Reg is a valid address register (base or index).
815 bool
816 SystemZAsmParser::parseAddressRegister(Register &Reg) {
817  if (Reg.Group == RegV) {
818  Error(Reg.StartLoc, "invalid use of vector addressing");
819  return true;
820  } else if (Reg.Group != RegGR) {
821  Error(Reg.StartLoc, "invalid address register");
822  return true;
823  } else if (Reg.Num == 0) {
824  Error(Reg.StartLoc, "%r0 used in an address");
825  return true;
826  }
827  return false;
828 }
829 
830 // Parse a memory operand and add it to Operands. The other arguments
831 // are as above.
833 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
834  const unsigned *Regs, RegisterKind RegKind) {
835  SMLoc StartLoc = Parser.getTok().getLoc();
836  unsigned Base = 0, Index = 0, LengthReg = 0;
837  Register Reg1, Reg2;
838  bool HaveReg1, HaveReg2;
839  const MCExpr *Disp;
840  const MCExpr *Length;
841  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
842  return MatchOperand_ParseFail;
843 
844  switch (MemKind) {
845  case BDMem:
846  // If we have Reg1, it must be an address register.
847  if (HaveReg1) {
848  if (parseAddressRegister(Reg1))
849  return MatchOperand_ParseFail;
850  Base = Regs[Reg1.Num];
851  }
852  // There must be no Reg2 or length.
853  if (Length) {
854  Error(StartLoc, "invalid use of length addressing");
855  return MatchOperand_ParseFail;
856  }
857  if (HaveReg2) {
858  Error(StartLoc, "invalid use of indexed addressing");
859  return MatchOperand_ParseFail;
860  }
861  break;
862  case BDXMem:
863  // If we have Reg1, it must be an address register.
864  if (HaveReg1) {
865  if (parseAddressRegister(Reg1))
866  return MatchOperand_ParseFail;
867  // If the are two registers, the first one is the index and the
868  // second is the base.
869  if (HaveReg2)
870  Index = Regs[Reg1.Num];
871  else
872  Base = Regs[Reg1.Num];
873  }
874  // If we have Reg2, it must be an address register.
875  if (HaveReg2) {
876  if (parseAddressRegister(Reg2))
877  return MatchOperand_ParseFail;
878  Base = Regs[Reg2.Num];
879  }
880  // There must be no length.
881  if (Length) {
882  Error(StartLoc, "invalid use of length addressing");
883  return MatchOperand_ParseFail;
884  }
885  break;
886  case BDLMem:
887  // If we have Reg2, it must be an address register.
888  if (HaveReg2) {
889  if (parseAddressRegister(Reg2))
890  return MatchOperand_ParseFail;
891  Base = Regs[Reg2.Num];
892  }
893  // We cannot support base+index addressing.
894  if (HaveReg1 && HaveReg2) {
895  Error(StartLoc, "invalid use of indexed addressing");
896  return MatchOperand_ParseFail;
897  }
898  // We must have a length.
899  if (!Length) {
900  Error(StartLoc, "missing length in address");
901  return MatchOperand_ParseFail;
902  }
903  break;
904  case BDRMem:
905  // We must have Reg1, and it must be a GPR.
906  if (!HaveReg1 || Reg1.Group != RegGR) {
907  Error(StartLoc, "invalid operand for instruction");
908  return MatchOperand_ParseFail;
909  }
910  LengthReg = SystemZMC::GR64Regs[Reg1.Num];
911  // If we have Reg2, it must be an address register.
912  if (HaveReg2) {
913  if (parseAddressRegister(Reg2))
914  return MatchOperand_ParseFail;
915  Base = Regs[Reg2.Num];
916  }
917  // There must be no length.
918  if (Length) {
919  Error(StartLoc, "invalid use of length addressing");
920  return MatchOperand_ParseFail;
921  }
922  break;
923  case BDVMem:
924  // We must have Reg1, and it must be a vector register.
925  if (!HaveReg1 || Reg1.Group != RegV) {
926  Error(StartLoc, "vector index required in address");
927  return MatchOperand_ParseFail;
928  }
929  Index = SystemZMC::VR128Regs[Reg1.Num];
930  // If we have Reg2, it must be an address register.
931  if (HaveReg2) {
932  if (parseAddressRegister(Reg2))
933  return MatchOperand_ParseFail;
934  Base = Regs[Reg2.Num];
935  }
936  // There must be no length.
937  if (Length) {
938  Error(StartLoc, "invalid use of length addressing");
939  return MatchOperand_ParseFail;
940  }
941  break;
942  }
943 
944  SMLoc EndLoc =
945  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
946  Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
947  Index, Length, LengthReg,
948  StartLoc, EndLoc));
949  return MatchOperand_Success;
950 }
951 
952 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
953  StringRef IDVal = DirectiveID.getIdentifier();
954 
955  if (IDVal == ".insn")
956  return ParseDirectiveInsn(DirectiveID.getLoc());
957 
958  return true;
959 }
960 
961 /// ParseDirectiveInsn
962 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
963 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
964  MCAsmParser &Parser = getParser();
965 
966  // Expect instruction format as identifier.
968  SMLoc ErrorLoc = Parser.getTok().getLoc();
969  if (Parser.parseIdentifier(Format))
970  return Error(ErrorLoc, "expected instruction format");
971 
973 
974  // Find entry for this format in InsnMatchTable.
975  auto EntryRange =
976  std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
977  Format, CompareInsn());
978 
979  // If first == second, couldn't find a match in the table.
980  if (EntryRange.first == EntryRange.second)
981  return Error(ErrorLoc, "unrecognized format");
982 
983  struct InsnMatchEntry *Entry = EntryRange.first;
984 
985  // Format should match from equal_range.
986  assert(Entry->Format == Format);
987 
988  // Parse the following operands using the table's information.
989  for (int i = 0; i < Entry->NumOperands; i++) {
990  MatchClassKind Kind = Entry->OperandKinds[i];
991 
992  SMLoc StartLoc = Parser.getTok().getLoc();
993 
994  // Always expect commas as separators for operands.
995  if (getLexer().isNot(AsmToken::Comma))
996  return Error(StartLoc, "unexpected token in directive");
997  Lex();
998 
999  // Parse operands.
1000  OperandMatchResultTy ResTy;
1001  if (Kind == MCK_AnyReg)
1002  ResTy = parseAnyReg(Operands);
1003  else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1004  ResTy = parseBDXAddr64(Operands);
1005  else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1006  ResTy = parseBDAddr64(Operands);
1007  else if (Kind == MCK_PCRel32)
1008  ResTy = parsePCRel32(Operands);
1009  else if (Kind == MCK_PCRel16)
1010  ResTy = parsePCRel16(Operands);
1011  else {
1012  // Only remaining operand kind is an immediate.
1013  const MCExpr *Expr;
1014  SMLoc StartLoc = Parser.getTok().getLoc();
1015 
1016  // Expect immediate expression.
1017  if (Parser.parseExpression(Expr))
1018  return Error(StartLoc, "unexpected token in directive");
1019 
1020  SMLoc EndLoc =
1021  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1022 
1023  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1024  ResTy = MatchOperand_Success;
1025  }
1026 
1027  if (ResTy != MatchOperand_Success)
1028  return true;
1029  }
1030 
1031  // Build the instruction with the parsed operands.
1032  MCInst Inst = MCInstBuilder(Entry->Opcode);
1033 
1034  for (size_t i = 0; i < Operands.size(); i++) {
1035  MCParsedAsmOperand &Operand = *Operands[i];
1036  MatchClassKind Kind = Entry->OperandKinds[i];
1037 
1038  // Verify operand.
1039  unsigned Res = validateOperandClass(Operand, Kind);
1040  if (Res != Match_Success)
1041  return Error(Operand.getStartLoc(), "unexpected operand type");
1042 
1043  // Add operands to instruction.
1044  SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1045  if (ZOperand.isReg())
1046  ZOperand.addRegOperands(Inst, 1);
1047  else if (ZOperand.isMem(BDMem))
1048  ZOperand.addBDAddrOperands(Inst, 2);
1049  else if (ZOperand.isMem(BDXMem))
1050  ZOperand.addBDXAddrOperands(Inst, 3);
1051  else if (ZOperand.isImm())
1052  ZOperand.addImmOperands(Inst, 1);
1053  else
1054  llvm_unreachable("unexpected operand type");
1055  }
1056 
1057  // Emit as a regular instruction.
1058  Parser.getStreamer().EmitInstruction(Inst, getSTI());
1059 
1060  return false;
1061 }
1062 
1063 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1064  SMLoc &EndLoc) {
1065  Register Reg;
1066  if (parseRegister(Reg))
1067  return true;
1068  if (Reg.Group == RegGR)
1069  RegNo = SystemZMC::GR64Regs[Reg.Num];
1070  else if (Reg.Group == RegFP)
1071  RegNo = SystemZMC::FP64Regs[Reg.Num];
1072  else if (Reg.Group == RegV)
1073  RegNo = SystemZMC::VR128Regs[Reg.Num];
1074  else if (Reg.Group == RegAR)
1075  RegNo = SystemZMC::AR32Regs[Reg.Num];
1076  else if (Reg.Group == RegCR)
1077  RegNo = SystemZMC::CR64Regs[Reg.Num];
1078  StartLoc = Reg.StartLoc;
1079  EndLoc = Reg.EndLoc;
1080  return false;
1081 }
1082 
1083 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1084  StringRef Name, SMLoc NameLoc,
1085  OperandVector &Operands) {
1086  Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1087 
1088  // Read the remaining operands.
1089  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1090  // Read the first operand.
1091  if (parseOperand(Operands, Name)) {
1092  return true;
1093  }
1094 
1095  // Read any subsequent operands.
1096  while (getLexer().is(AsmToken::Comma)) {
1097  Parser.Lex();
1098  if (parseOperand(Operands, Name)) {
1099  return true;
1100  }
1101  }
1102  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1103  SMLoc Loc = getLexer().getLoc();
1104  return Error(Loc, "unexpected token in argument list");
1105  }
1106  }
1107 
1108  // Consume the EndOfStatement.
1109  Parser.Lex();
1110  return false;
1111 }
1112 
1113 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1114  StringRef Mnemonic) {
1115  // Check if the current operand has a custom associated parser, if so, try to
1116  // custom parse the operand, or fallback to the general approach. Force all
1117  // features to be available during the operand check, or else we will fail to
1118  // find the custom parser, and then we will later get an InvalidOperand error
1119  // instead of a MissingFeature errror.
1120  uint64_t AvailableFeatures = getAvailableFeatures();
1121  setAvailableFeatures(~(uint64_t)0);
1122  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1123  setAvailableFeatures(AvailableFeatures);
1124  if (ResTy == MatchOperand_Success)
1125  return false;
1126 
1127  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1128  // there was a match, but an error occurred, in which case, just return that
1129  // the operand parsing failed.
1130  if (ResTy == MatchOperand_ParseFail)
1131  return true;
1132 
1133  // Check for a register. All real register operands should have used
1134  // a context-dependent parse routine, which gives the required register
1135  // class. The code is here to mop up other cases, like those where
1136  // the instruction isn't recognized.
1137  if (Parser.getTok().is(AsmToken::Percent)) {
1138  Register Reg;
1139  if (parseRegister(Reg))
1140  return true;
1141  Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1142  return false;
1143  }
1144 
1145  // The only other type of operand is an immediate or address. As above,
1146  // real address operands should have used a context-dependent parse routine,
1147  // so we treat any plain expression as an immediate.
1148  SMLoc StartLoc = Parser.getTok().getLoc();
1149  Register Reg1, Reg2;
1150  bool HaveReg1, HaveReg2;
1151  const MCExpr *Expr;
1152  const MCExpr *Length;
1153  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1154  return true;
1155  // If the register combination is not valid for any instruction, reject it.
1156  // Otherwise, fall back to reporting an unrecognized instruction.
1157  if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1158  && parseAddressRegister(Reg1))
1159  return true;
1160  if (HaveReg2 && parseAddressRegister(Reg2))
1161  return true;
1162 
1163  SMLoc EndLoc =
1164  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1165  if (HaveReg1 || HaveReg2 || Length)
1166  Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1167  else
1168  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1169  return false;
1170 }
1171 
1172 static std::string SystemZMnemonicSpellCheck(StringRef S, uint64_t FBS,
1173  unsigned VariantID = 0);
1174 
1175 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1176  OperandVector &Operands,
1177  MCStreamer &Out,
1178  uint64_t &ErrorInfo,
1179  bool MatchingInlineAsm) {
1180  MCInst Inst;
1181  unsigned MatchResult;
1182 
1183  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1184  MatchingInlineAsm);
1185  switch (MatchResult) {
1186  case Match_Success:
1187  Inst.setLoc(IDLoc);
1188  Out.EmitInstruction(Inst, getSTI());
1189  return false;
1190 
1191  case Match_MissingFeature: {
1192  assert(ErrorInfo && "Unknown missing feature!");
1193  // Special case the error message for the very common case where only
1194  // a single subtarget feature is missing
1195  std::string Msg = "instruction requires:";
1196  uint64_t Mask = 1;
1197  for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1198  if (ErrorInfo & Mask) {
1199  Msg += " ";
1200  Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1201  }
1202  Mask <<= 1;
1203  }
1204  return Error(IDLoc, Msg);
1205  }
1206 
1207  case Match_InvalidOperand: {
1208  SMLoc ErrorLoc = IDLoc;
1209  if (ErrorInfo != ~0ULL) {
1210  if (ErrorInfo >= Operands.size())
1211  return Error(IDLoc, "too few operands for instruction");
1212 
1213  ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1214  if (ErrorLoc == SMLoc())
1215  ErrorLoc = IDLoc;
1216  }
1217  return Error(ErrorLoc, "invalid operand for instruction");
1218  }
1219 
1220  case Match_MnemonicFail: {
1221  uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1222  std::string Suggestion = SystemZMnemonicSpellCheck(
1223  ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1224  return Error(IDLoc, "invalid instruction" + Suggestion,
1225  ((SystemZOperand &)*Operands[0]).getLocRange());
1226  }
1227  }
1228 
1229  llvm_unreachable("Unexpected match type");
1230 }
1231 
1233 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1234  int64_t MaxVal, bool AllowTLS) {
1235  MCContext &Ctx = getContext();
1236  MCStreamer &Out = getStreamer();
1237  const MCExpr *Expr;
1238  SMLoc StartLoc = Parser.getTok().getLoc();
1239  if (getParser().parseExpression(Expr))
1240  return MatchOperand_NoMatch;
1241 
1242  // For consistency with the GNU assembler, treat immediates as offsets
1243  // from ".".
1244  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1245  int64_t Value = CE->getValue();
1246  if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1247  Error(StartLoc, "offset out of range");
1248  return MatchOperand_ParseFail;
1249  }
1250  MCSymbol *Sym = Ctx.createTempSymbol();
1251  Out.EmitLabel(Sym);
1253  Ctx);
1254  Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1255  }
1256 
1257  // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1258  const MCExpr *Sym = nullptr;
1259  if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1260  Parser.Lex();
1261 
1262  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1263  Error(Parser.getTok().getLoc(), "unexpected token");
1264  return MatchOperand_ParseFail;
1265  }
1266 
1268  StringRef Name = Parser.getTok().getString();
1269  if (Name == "tls_gdcall")
1271  else if (Name == "tls_ldcall")
1273  else {
1274  Error(Parser.getTok().getLoc(), "unknown TLS tag");
1275  return MatchOperand_ParseFail;
1276  }
1277  Parser.Lex();
1278 
1279  if (Parser.getTok().isNot(AsmToken::Colon)) {
1280  Error(Parser.getTok().getLoc(), "unexpected token");
1281  return MatchOperand_ParseFail;
1282  }
1283  Parser.Lex();
1284 
1285  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1286  Error(Parser.getTok().getLoc(), "unexpected token");
1287  return MatchOperand_ParseFail;
1288  }
1289 
1290  StringRef Identifier = Parser.getTok().getString();
1291  Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1292  Kind, Ctx);
1293  Parser.Lex();
1294  }
1295 
1296  SMLoc EndLoc =
1297  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1298 
1299  if (AllowTLS)
1300  Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1301  StartLoc, EndLoc));
1302  else
1303  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1304 
1305  return MatchOperand_Success;
1306 }
1307 
1308 // Force static initialization.
1311 }
static bool isReg(const MCInst &MI, unsigned OpNo)
Represents a range in source code.
Definition: SMLoc.h:49
void push_back(const T &Elt)
Definition: SmallVector.h:212
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const unsigned GR32Regs[16]
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:235
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const unsigned FP128Regs[16]
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:110
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
MatchClassKind OperandKinds[5]
const unsigned FP32Regs[16]
static struct InsnMatchEntry InsnMatchTable[]
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
MemoryKind
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:863
const unsigned VR64Regs[32]
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmLexer.h:105
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
RegisterKind
const unsigned AR32Regs[16]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:27
const unsigned GRH32Regs[16]
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:137
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
Context object for machine code objects.
Definition: MCContext.h:59
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
const RegList & Regs
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:443
const unsigned CR64Regs[16]
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
static std::string SystemZMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID=0)
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
const char * getPointer() const
Definition: SMLoc.h:35
Streaming machine code generation interface.
Definition: MCStreamer.h:169
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:215
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
void setLoc(SMLoc loc)
Definition: MCInst.h:177
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
void LLVMInitializeSystemZAsmParser()
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
const unsigned FP64Regs[16]
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
Promote Memory to Register
Definition: Mem2Reg.cpp:110
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:331
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
Target & getTheSystemZTarget()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:121
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
MCSubtargetInfo - Generic base class for all target subtargets.
const unsigned VR32Regs[32]
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:300
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:24
static const char * getSubtargetFeatureName(uint64_t Val)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
const unsigned VR128Regs[32]