LLVM  10.0.0svn
SystemZISelLowering.h
Go to the documentation of this file.
1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer absolute.
55 
56  // Integer comparisons. There are three operands: the two values
57  // to compare, and an integer of type SystemZICMP.
59 
60  // Floating-point comparisons. The two operands are the values to compare.
62 
63  // Test under mask. The first operand is ANDed with the second operand
64  // and the condition codes are set on the result. The third operand is
65  // a boolean that is true if the condition codes need to distinguish
66  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67  // register forms do but the memory forms don't).
68  TM,
69 
70  // Branches if a condition is true. Operand 0 is the chain operand;
71  // operand 1 is the 4-bit condition-code mask, with bit N in
72  // big-endian order meaning "branch if CC=N"; operand 2 is the
73  // target block and operand 3 is the flag operand.
75 
76  // Selects between operand 0 and operand 1. Operand 2 is the
77  // mask of condition-code values for which operand 0 should be
78  // chosen over operand 1; it has the same form as BR_CCMASK.
79  // Operand 3 is the flag operand.
81 
82  // Evaluates to the gap between the stack pointer and the
83  // base of the dynamically-allocatable area.
85 
86  // Count number of bits set in operand 0 per byte.
88 
89  // Wrappers around the ISD opcodes of the same name. The output is GR128.
90  // Input operands may be GR64 or GR32, depending on the instruction.
95 
96  // Add/subtract with overflow/carry. These have the same operands as
97  // the corresponding standard operations, except with the carry flag
98  // replaced by a condition code value.
100 
101  // Set the condition code from a boolean value in operand 0.
102  // Operand 1 is a mask of all condition-code values that may result of this
103  // operation, operand 2 is a mask of condition-code values that may result
104  // if the boolean is true.
105  // Note that this operation is always optimized away, we will never
106  // generate any code for it.
108 
109  // Use a series of MVCs to copy bytes from one memory location to another.
110  // The operands are:
111  // - the target address
112  // - the source address
113  // - the constant length
114  //
115  // This isn't a memory opcode because we'd need to attach two
116  // MachineMemOperands rather than one.
118 
119  // Like MVC, but implemented as a loop that handles X*256 bytes
120  // followed by straight-line code to handle the rest (if any).
121  // The value of X is passed as an additional operand.
123 
124  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
125  NC,
127  OC,
129  XC,
131 
132  // Use CLC to compare two blocks of memory, with the same comments
133  // as for MVC and MVC_LOOP.
136 
137  // Use an MVST-based sequence to implement stpcpy().
139 
140  // Use a CLST-based sequence to implement strcmp(). The two input operands
141  // are the addresses of the strings to compare.
143 
144  // Use an SRST-based sequence to search a block of memory. The first
145  // operand is the end address, the second is the start, and the third
146  // is the character to search for. CC is set to 1 on success and 2
147  // on failure.
149 
150  // Store the CC value in bits 29 and 28 of an integer.
152 
153  // Compiler barrier only; generate a no-op.
155 
156  // Transaction begin. The first operand is the chain, the second
157  // the TDB pointer, and the third the immediate control field.
158  // Returns CC value and chain.
161 
162  // Transaction end. Just the chain operand. Returns CC value and chain.
164 
165  // Create a vector constant by filling byte N of the result with bit
166  // 15-N of the single operand.
168 
169  // Create a vector constant by replicating an element-sized RISBG-style mask.
170  // The first operand specifies the starting set bit and the second operand
171  // specifies the ending set bit. Both operands count from the MSB of the
172  // element.
174 
175  // Replicate a GPR scalar value into all elements of a vector.
177 
178  // Create a vector from two i64 GPRs.
180 
181  // Replicate one element of a vector into all elements. The first operand
182  // is the vector and the second is the index of the element to replicate.
184 
185  // Interleave elements from the high half of operand 0 and the high half
186  // of operand 1.
188 
189  // Likewise for the low halves.
191 
192  // Concatenate the vectors in the first two operands, shift them left
193  // by the third operand, and take the first half of the result.
195 
196  // Take one element of the first v2i64 operand and the one element of
197  // the second v2i64 operand and concatenate them to form a v2i64 result.
198  // The third operand is a 4-bit value of the form 0A0B, where A and B
199  // are the element selectors for the first operand and second operands
200  // respectively.
202 
203  // Perform a general vector permute on vector operands 0 and 1.
204  // Each byte of operand 2 controls the corresponding byte of the result,
205  // in the same way as a byte-level VECTOR_SHUFFLE mask.
207 
208  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
210 
211  // Likewise, but saturate the result and set CC. PACKS_CC does signed
212  // saturation and PACKLS_CC does unsigned saturation.
215 
216  // Unpack the first half of vector operand 0 into double-sized elements.
217  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
220 
221  // Likewise for the second half.
224 
225  // Shift each element of vector operand 0 by the number of bits specified
226  // by scalar operand 1.
230 
231  // For each element of the output type, sum across all sub-elements of
232  // operand 0 belonging to the corresponding element, and add in the
233  // rightmost sub-element of the corresponding element of operand 1.
235 
236  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
237  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
238  // and VICMPHL for "unsigned greater than".
242 
243  // Likewise, but also set the condition codes on the result.
247 
248  // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
249  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
250  // greater than" and VFCMPHE for "ordered and greater than or equal to".
254 
255  // Likewise, but also set the condition codes on the result.
259 
260  // Test floating-point data class for vectors.
262 
263  // Extend the even f32 elements of vector operand 0 to produce a vector
264  // of f64 elements.
266 
267  // Round the f64 elements of vector operand 0 to f32s and store them in the
268  // even elements of the result.
270 
271  // AND the two vector operands together and set CC based on the result.
273 
274  // String operations that set CC as a side-effect.
286 
287  // Test Data Class.
288  //
289  // Operand 0: the value to test
290  // Operand 1: the bit mask
292 
293  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
294  // ATOMIC_LOAD_<op>.
295  //
296  // Operand 0: the address of the containing 32-bit-aligned field
297  // Operand 1: the second operand of <op>, in the high bits of an i32
298  // for everything except ATOMIC_SWAPW
299  // Operand 2: how many bits to rotate the i32 left to bring the first
300  // operand into the high bits
301  // Operand 3: the negative of operand 2, for rotating the other way
302  // Operand 4: the width of the field in bits (8 or 16)
314 
315  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
316  //
317  // Operand 0: the address of the containing 32-bit-aligned field
318  // Operand 1: the compare value, in the low bits of an i32
319  // Operand 2: the swap value, in the low bits of an i32
320  // Operand 3: how many bits to rotate the i32 left to bring the first
321  // operand into the high bits
322  // Operand 4: the negative of operand 2, for rotating the other way
323  // Operand 5: the width of the field in bits (8 or 16)
325 
326  // Atomic compare-and-swap returning CC value.
327  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
329 
330  // 128-bit atomic load.
331  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
333 
334  // 128-bit atomic store.
335  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
337 
338  // 128-bit atomic compare-and-swap.
339  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
341 
342  // Byte swapping load/store. Same operands as regular load/store.
344 
345  // Element swapping load/store. Same operands as regular load/store.
347 
348  // Prefetch from the second operand using the 4-bit control code in
349  // the first operand. The code is 1 for a load prefetch and 2 for
350  // a store prefetch.
352 };
353 
354 // Return true if OPCODE is some kind of PC-relative address.
355 inline bool isPCREL(unsigned Opcode) {
356  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
357 }
358 } // end namespace SystemZISD
359 
360 namespace SystemZICMP {
361 // Describes whether an integer comparison needs to be signed or unsigned,
362 // or whether either type is OK.
363 enum {
367 };
368 } // end namespace SystemZICMP
369 
370 class SystemZSubtarget;
372 
374 public:
375  explicit SystemZTargetLowering(const TargetMachine &TM,
376  const SystemZSubtarget &STI);
377 
378  // Override TargetLowering.
379  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
380  return MVT::i32;
381  }
382  MVT getVectorIdxTy(const DataLayout &DL) const override {
383  // Only the lower 12 bits of an element index are used, so we don't
384  // want to clobber the upper 32 bits of a GPR unnecessarily.
385  return MVT::i32;
386  }
388  const override {
389  // Widen subvectors to the full width rather than promoting integer
390  // elements. This is better because:
391  //
392  // (a) it means that we can handle the ABI for passing and returning
393  // sub-128 vectors without having to handle them as legal types.
394  //
395  // (b) we don't have instructions to extend on load and truncate on store,
396  // so promoting the integers is less efficient.
397  //
398  // (c) there are no multiplication instructions for the widest integer
399  // type (v2i64).
400  if (VT.getScalarSizeInBits() % 8 == 0)
401  return TypeWidenVector;
403  }
404  bool isCheapToSpeculateCtlz() const override { return true; }
405  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
406  EVT) const override;
407  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
408  bool isFPImmLegal(const APFloat &Imm, EVT VT,
409  bool ForCodeSize) const override;
410  bool isLegalICmpImmediate(int64_t Imm) const override;
411  bool isLegalAddImmediate(int64_t Imm) const override;
412  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
413  unsigned AS,
414  Instruction *I = nullptr) const override;
415  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
416  unsigned Align,
418  bool *Fast) const override;
419  bool isTruncateFree(Type *, Type *) const override;
420  bool isTruncateFree(EVT, EVT) const override;
421  const char *getTargetNodeName(unsigned Opcode) const override;
422  std::pair<unsigned, const TargetRegisterClass *>
423  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
424  StringRef Constraint, MVT VT) const override;
426  getConstraintType(StringRef Constraint) const override;
428  getSingleConstraintMatchWeight(AsmOperandInfo &info,
429  const char *constraint) const override;
430  void LowerAsmOperandForConstraint(SDValue Op,
431  std::string &Constraint,
432  std::vector<SDValue> &Ops,
433  SelectionDAG &DAG) const override;
434 
435  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
436  if (ConstraintCode.size() == 1) {
437  switch(ConstraintCode[0]) {
438  default:
439  break;
440  case 'o':
442  case 'Q':
444  case 'R':
446  case 'S':
448  case 'T':
450  }
451  }
452  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
453  }
454 
455  /// If a physical register, this returns the register that receives the
456  /// exception address on entry to an EH pad.
457  unsigned
458  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
459  return SystemZ::R6D;
460  }
461 
462  /// If a physical register, this returns the register that receives the
463  /// exception typeid on entry to a landing pad.
464  unsigned
465  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
466  return SystemZ::R7D;
467  }
468 
469  /// Override to support customized stack guard loading.
470  bool useLoadStackGuardNode() const override {
471  return true;
472  }
473  void insertSSPDeclarations(Module &M) const override {
474  }
475 
477  EmitInstrWithCustomInserter(MachineInstr &MI,
478  MachineBasicBlock *BB) const override;
479  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
480  void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
481  SelectionDAG &DAG) const override;
482  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
483  SelectionDAG &DAG) const override;
484  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
485  bool allowTruncateForTailCall(Type *, Type *) const override;
486  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
487  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
488  bool isVarArg,
490  const SDLoc &DL, SelectionDAG &DAG,
491  SmallVectorImpl<SDValue> &InVals) const override;
492  SDValue LowerCall(CallLoweringInfo &CLI,
493  SmallVectorImpl<SDValue> &InVals) const override;
494 
495  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
496  bool isVarArg,
498  LLVMContext &Context) const override;
499  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
501  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
502  SelectionDAG &DAG) const override;
503  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
504 
505  /// Determine which of the bits specified in Mask are known to be either
506  /// zero or one and return them in the KnownZero/KnownOne bitsets.
507  void computeKnownBitsForTargetNode(const SDValue Op,
508  KnownBits &Known,
509  const APInt &DemandedElts,
510  const SelectionDAG &DAG,
511  unsigned Depth = 0) const override;
512 
513  /// Determine the number of bits in the operation that are sign bits.
514  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
515  const APInt &DemandedElts,
516  const SelectionDAG &DAG,
517  unsigned Depth) const override;
518 
520  return ISD::ANY_EXTEND;
521  }
522 
523  bool supportSwiftError() const override {
524  return true;
525  }
526 
527 private:
528  const SystemZSubtarget &Subtarget;
529 
530  // Implement LowerOperation for individual opcodes.
531  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
532  const SDLoc &DL, EVT VT,
533  SDValue CmpOp0, SDValue CmpOp1) const;
534  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
535  EVT VT, ISD::CondCode CC,
536  SDValue CmpOp0, SDValue CmpOp1) const;
537  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
541  SelectionDAG &DAG) const;
542  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
543  SelectionDAG &DAG, unsigned Opcode,
544  SDValue GOTOffset) const;
545  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
546  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
547  SelectionDAG &DAG) const;
548  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
549  SelectionDAG &DAG) const;
550  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
551  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
552  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
555  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
556  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
557  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
558  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
559  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
560  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
561  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
562  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
563  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
564  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
565  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
566  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
567  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
568  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
569  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
570  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
571  unsigned Opcode) const;
572  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
573  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
574  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
575  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
576  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
577  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
578  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
579  bool isVectorElementLoad(SDValue Op) const;
580  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
581  SmallVectorImpl<SDValue> &Elems) const;
582  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
583  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
584  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
585  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
586  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
587  SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
588  unsigned UnpackHigh) const;
589  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
590 
591  bool canTreatAsByteVector(EVT VT) const;
592  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
593  unsigned Index, DAGCombinerInfo &DCI,
594  bool Force) const;
595  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
596  DAGCombinerInfo &DCI) const;
597  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
598  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
599  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
600  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
601  bool canLoadStoreByteSwapped(EVT VT) const;
602  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
603  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
604  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
605  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
606  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
607  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
608  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
609  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
610  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
611  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
612  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
613  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
614 
615  SDValue unwrapAddress(SDValue N) const override;
616 
617  // If the last instruction before MBBI in MBB was some form of COMPARE,
618  // try to replace it with a COMPARE AND BRANCH just before MBBI.
619  // CCMask and Target are the BRC-like operands for the branch.
620  // Return true if the change was made.
621  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
623  unsigned CCMask,
624  MachineBasicBlock *Target) const;
625 
626  // Implement EmitInstrWithCustomInserter for individual operation types.
627  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
628  MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
629  unsigned StoreOpcode, unsigned STOCOpcode,
630  bool Invert) const;
631  MachineBasicBlock *emitPair128(MachineInstr &MI,
632  MachineBasicBlock *MBB) const;
633  MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
634  bool ClearEven) const;
635  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
636  MachineBasicBlock *BB,
637  unsigned BinOpcode, unsigned BitSize,
638  bool Invert = false) const;
639  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
640  MachineBasicBlock *MBB,
641  unsigned CompareOpcode,
642  unsigned KeepOldMask,
643  unsigned BitSize) const;
644  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
645  MachineBasicBlock *BB) const;
646  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
647  unsigned Opcode) const;
648  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
649  unsigned Opcode) const;
650  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
651  MachineBasicBlock *MBB,
652  unsigned Opcode, bool NoFloat) const;
653  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
654  MachineBasicBlock *MBB,
655  unsigned Opcode) const;
656 
657  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
658  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
659 };
660 
662 private:
663  APInt IntBits; // The 128 bits as an integer.
664  APInt SplatBits; // Smallest splat value.
665  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
666  unsigned SplatBitSize = 0;
667  bool isFP128 = false;
668 
669 public:
670  unsigned Opcode = 0;
675  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
676 };
677 
678 } // end namespace llvm
679 
680 #endif
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
Definition: Any.h:26
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
This class represents a function call, abstracting a target machine&#39;s calling convention.
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This contains information for each constraint that we are lowering.
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
unsigned getScalarSizeInBits() const
This is an important base class in LLVM.
Definition: Constant.h:41
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool isPCREL(unsigned Opcode)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:920
Represents one node in the SelectionDAG.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
A "pseudo-class" with methods for operating on BUILD_VECTORs.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:502
Flags
Flags values. These may be or&#39;d together.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Representation of each machine instruction.
Definition: MachineInstr.h:64
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
SmallVector< unsigned, 2 > OpVals
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
This file describes how to lower LLVM code to machine code.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.