LLVM  6.0.0svn
SystemZISelLowering.h
Go to the documentation of this file.
1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 
18 #include "SystemZ.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer absolute.
55 
56  // Integer comparisons. There are three operands: the two values
57  // to compare, and an integer of type SystemZICMP.
59 
60  // Floating-point comparisons. The two operands are the values to compare.
62 
63  // Test under mask. The first operand is ANDed with the second operand
64  // and the condition codes are set on the result. The third operand is
65  // a boolean that is true if the condition codes need to distinguish
66  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67  // register forms do but the memory forms don't).
68  TM,
69 
70  // Branches if a condition is true. Operand 0 is the chain operand;
71  // operand 1 is the 4-bit condition-code mask, with bit N in
72  // big-endian order meaning "branch if CC=N"; operand 2 is the
73  // target block and operand 3 is the flag operand.
75 
76  // Selects between operand 0 and operand 1. Operand 2 is the
77  // mask of condition-code values for which operand 0 should be
78  // chosen over operand 1; it has the same form as BR_CCMASK.
79  // Operand 3 is the flag operand.
81 
82  // Evaluates to the gap between the stack pointer and the
83  // base of the dynamically-allocatable area.
85 
86  // Count number of bits set in operand 0 per byte.
88 
89  // Wrappers around the ISD opcodes of the same name. The output is GR128.
90  // Input operands may be GR64 or GR32, depending on the instruction.
95 
96  // Use a series of MVCs to copy bytes from one memory location to another.
97  // The operands are:
98  // - the target address
99  // - the source address
100  // - the constant length
101  //
102  // This isn't a memory opcode because we'd need to attach two
103  // MachineMemOperands rather than one.
105 
106  // Like MVC, but implemented as a loop that handles X*256 bytes
107  // followed by straight-line code to handle the rest (if any).
108  // The value of X is passed as an additional operand.
110 
111  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
112  NC,
114  OC,
116  XC,
118 
119  // Use CLC to compare two blocks of memory, with the same comments
120  // as for MVC and MVC_LOOP.
123 
124  // Use an MVST-based sequence to implement stpcpy().
126 
127  // Use a CLST-based sequence to implement strcmp(). The two input operands
128  // are the addresses of the strings to compare.
130 
131  // Use an SRST-based sequence to search a block of memory. The first
132  // operand is the end address, the second is the start, and the third
133  // is the character to search for. CC is set to 1 on success and 2
134  // on failure.
136 
137  // Store the CC value in bits 29 and 28 of an integer.
139 
140  // Compiler barrier only; generate a no-op.
142 
143  // Transaction begin. The first operand is the chain, the second
144  // the TDB pointer, and the third the immediate control field.
145  // Returns chain and glue.
148 
149  // Transaction end. Just the chain operand. Returns chain and glue.
151 
152  // Create a vector constant by filling byte N of the result with bit
153  // 15-N of the single operand.
155 
156  // Create a vector constant by replicating an element-sized RISBG-style mask.
157  // The first operand specifies the starting set bit and the second operand
158  // specifies the ending set bit. Both operands count from the MSB of the
159  // element.
161 
162  // Replicate a GPR scalar value into all elements of a vector.
164 
165  // Create a vector from two i64 GPRs.
167 
168  // Replicate one element of a vector into all elements. The first operand
169  // is the vector and the second is the index of the element to replicate.
171 
172  // Interleave elements from the high half of operand 0 and the high half
173  // of operand 1.
175 
176  // Likewise for the low halves.
178 
179  // Concatenate the vectors in the first two operands, shift them left
180  // by the third operand, and take the first half of the result.
182 
183  // Take one element of the first v2i64 operand and the one element of
184  // the second v2i64 operand and concatenate them to form a v2i64 result.
185  // The third operand is a 4-bit value of the form 0A0B, where A and B
186  // are the element selectors for the first operand and second operands
187  // respectively.
189 
190  // Perform a general vector permute on vector operands 0 and 1.
191  // Each byte of operand 2 controls the corresponding byte of the result,
192  // in the same way as a byte-level VECTOR_SHUFFLE mask.
194 
195  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
197 
198  // Likewise, but saturate the result and set CC. PACKS_CC does signed
199  // saturation and PACKLS_CC does unsigned saturation.
202 
203  // Unpack the first half of vector operand 0 into double-sized elements.
204  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
207 
208  // Likewise for the second half.
211 
212  // Shift each element of vector operand 0 by the number of bits specified
213  // by scalar operand 1.
217 
218  // For each element of the output type, sum across all sub-elements of
219  // operand 0 belonging to the corresponding element, and add in the
220  // rightmost sub-element of the corresponding element of operand 1.
222 
223  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
224  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
225  // and VICMPHL for "unsigned greater than".
229 
230  // Likewise, but also set the condition codes on the result.
234 
235  // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
236  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
237  // greater than" and VFCMPHE for "ordered and greater than or equal to".
241 
242  // Likewise, but also set the condition codes on the result.
246 
247  // Test floating-point data class for vectors.
249 
250  // Extend the even f32 elements of vector operand 0 to produce a vector
251  // of f64 elements.
253 
254  // Round the f64 elements of vector operand 0 to f32s and store them in the
255  // even elements of the result.
257 
258  // AND the two vector operands together and set CC based on the result.
260 
261  // String operations that set CC as a side-effect.
271 
272  // Test Data Class.
273  //
274  // Operand 0: the value to test
275  // Operand 1: the bit mask
277 
278  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
279  // ATOMIC_LOAD_<op>.
280  //
281  // Operand 0: the address of the containing 32-bit-aligned field
282  // Operand 1: the second operand of <op>, in the high bits of an i32
283  // for everything except ATOMIC_SWAPW
284  // Operand 2: how many bits to rotate the i32 left to bring the first
285  // operand into the high bits
286  // Operand 3: the negative of operand 2, for rotating the other way
287  // Operand 4: the width of the field in bits (8 or 16)
299 
300  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
301  //
302  // Operand 0: the address of the containing 32-bit-aligned field
303  // Operand 1: the compare value, in the low bits of an i32
304  // Operand 2: the swap value, in the low bits of an i32
305  // Operand 3: how many bits to rotate the i32 left to bring the first
306  // operand into the high bits
307  // Operand 4: the negative of operand 2, for rotating the other way
308  // Operand 5: the width of the field in bits (8 or 16)
310 
311  // Atomic compare-and-swap returning glue (condition code).
312  // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
314 
315  // 128-bit atomic load.
316  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
318 
319  // 128-bit atomic store.
320  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
322 
323  // 128-bit atomic compare-and-swap.
324  // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
326 
327  // Byte swapping load.
328  //
329  // Operand 0: the address to load from
330  // Operand 1: the type of load (i16, i32, i64)
332 
333  // Byte swapping store.
334  //
335  // Operand 0: the value to store
336  // Operand 1: the address to store to
337  // Operand 2: the type of store (i16, i32, i64)
339 
340  // Prefetch from the second operand using the 4-bit control code in
341  // the first operand. The code is 1 for a load prefetch and 2 for
342  // a store prefetch.
344 };
345 
346 // Return true if OPCODE is some kind of PC-relative address.
347 inline bool isPCREL(unsigned Opcode) {
348  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
349 }
350 } // end namespace SystemZISD
351 
352 namespace SystemZICMP {
353 // Describes whether an integer comparison needs to be signed or unsigned,
354 // or whether either type is OK.
355 enum {
359 };
360 } // end namespace SystemZICMP
361 
362 class SystemZSubtarget;
364 
366 public:
367  explicit SystemZTargetLowering(const TargetMachine &TM,
368  const SystemZSubtarget &STI);
369 
370  // Override TargetLowering.
371  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
372  return MVT::i32;
373  }
374  MVT getVectorIdxTy(const DataLayout &DL) const override {
375  // Only the lower 12 bits of an element index are used, so we don't
376  // want to clobber the upper 32 bits of a GPR unnecessarily.
377  return MVT::i32;
378  }
380  const override {
381  // Widen subvectors to the full width rather than promoting integer
382  // elements. This is better because:
383  //
384  // (a) it means that we can handle the ABI for passing and returning
385  // sub-128 vectors without having to handle them as legal types.
386  //
387  // (b) we don't have instructions to extend on load and truncate on store,
388  // so promoting the integers is less efficient.
389  //
390  // (c) there are no multiplication instructions for the widest integer
391  // type (v2i64).
392  if (VT.getScalarSizeInBits() % 8 == 0)
393  return TypeWidenVector;
395  }
396  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
397  EVT) const override;
398  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
399  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
400  bool isLegalICmpImmediate(int64_t Imm) const override;
401  bool isLegalAddImmediate(int64_t Imm) const override;
402  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
403  unsigned AS,
404  Instruction *I = nullptr) const override;
405  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
406  unsigned Align,
407  bool *Fast) const override;
408  bool isTruncateFree(Type *, Type *) const override;
409  bool isTruncateFree(EVT, EVT) const override;
410  const char *getTargetNodeName(unsigned Opcode) const override;
411  std::pair<unsigned, const TargetRegisterClass *>
412  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
413  StringRef Constraint, MVT VT) const override;
415  getConstraintType(StringRef Constraint) const override;
417  getSingleConstraintMatchWeight(AsmOperandInfo &info,
418  const char *constraint) const override;
419  void LowerAsmOperandForConstraint(SDValue Op,
420  std::string &Constraint,
421  std::vector<SDValue> &Ops,
422  SelectionDAG &DAG) const override;
423 
424  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
425  if (ConstraintCode.size() == 1) {
426  switch(ConstraintCode[0]) {
427  default:
428  break;
429  case 'Q':
431  case 'R':
433  case 'S':
435  case 'T':
437  }
438  }
439  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
440  }
441 
442  /// If a physical register, this returns the register that receives the
443  /// exception address on entry to an EH pad.
444  unsigned
445  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
446  return SystemZ::R6D;
447  }
448 
449  /// If a physical register, this returns the register that receives the
450  /// exception typeid on entry to a landing pad.
451  unsigned
452  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
453  return SystemZ::R7D;
454  }
455 
456  /// Override to support customized stack guard loading.
457  bool useLoadStackGuardNode() const override {
458  return true;
459  }
460  void insertSSPDeclarations(Module &M) const override {
461  }
462 
464  EmitInstrWithCustomInserter(MachineInstr &MI,
465  MachineBasicBlock *BB) const override;
466  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
467  void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
468  SelectionDAG &DAG) const override;
469  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
470  SelectionDAG &DAG) const override;
471  bool allowTruncateForTailCall(Type *, Type *) const override;
472  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
473  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
474  bool isVarArg,
476  const SDLoc &DL, SelectionDAG &DAG,
477  SmallVectorImpl<SDValue> &InVals) const override;
478  SDValue LowerCall(CallLoweringInfo &CLI,
479  SmallVectorImpl<SDValue> &InVals) const override;
480 
481  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
482  bool isVarArg,
484  LLVMContext &Context) const override;
485  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
487  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
488  SelectionDAG &DAG) const override;
489  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
490 
492  return ISD::ANY_EXTEND;
493  }
494 
495  bool supportSwiftError() const override {
496  return true;
497  }
498 
499 private:
500  const SystemZSubtarget &Subtarget;
501 
502  // Implement LowerOperation for individual opcodes.
503  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
504  const SDLoc &DL, EVT VT,
505  SDValue CmpOp0, SDValue CmpOp1) const;
506  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
507  EVT VT, ISD::CondCode CC,
508  SDValue CmpOp0, SDValue CmpOp1) const;
509  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
510  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
511  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
512  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
513  SelectionDAG &DAG) const;
514  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
515  SelectionDAG &DAG, unsigned Opcode,
516  SDValue GOTOffset) const;
517  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
518  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
519  SelectionDAG &DAG) const;
520  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
521  SelectionDAG &DAG) const;
522  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
523  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
524  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
525  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
526  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
527  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
528  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
529  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
530  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
531  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
533  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
541  unsigned Opcode) const;
542  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
548  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
549  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
550  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
551  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
555  unsigned UnpackHigh) const;
556  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
557 
558  bool canTreatAsByteVector(EVT VT) const;
559  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
560  unsigned Index, DAGCombinerInfo &DCI,
561  bool Force) const;
562  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
563  DAGCombinerInfo &DCI) const;
564  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
565  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
566  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
567  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
568  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
569  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
570  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
571  SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
572 
573  // If the last instruction before MBBI in MBB was some form of COMPARE,
574  // try to replace it with a COMPARE AND BRANCH just before MBBI.
575  // CCMask and Target are the BRC-like operands for the branch.
576  // Return true if the change was made.
577  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
579  unsigned CCMask,
580  MachineBasicBlock *Target) const;
581 
582  // Implement EmitInstrWithCustomInserter for individual operation types.
583  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB,
584  unsigned LOCROpcode) const;
585  MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
586  unsigned StoreOpcode, unsigned STOCOpcode,
587  bool Invert) const;
588  MachineBasicBlock *emitPair128(MachineInstr &MI,
589  MachineBasicBlock *MBB) const;
590  MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
591  bool ClearEven) const;
592  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
593  MachineBasicBlock *BB,
594  unsigned BinOpcode, unsigned BitSize,
595  bool Invert = false) const;
596  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
597  MachineBasicBlock *MBB,
598  unsigned CompareOpcode,
599  unsigned KeepOldMask,
600  unsigned BitSize) const;
601  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
602  MachineBasicBlock *BB) const;
603  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
604  unsigned Opcode) const;
605  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
606  unsigned Opcode) const;
607  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
608  MachineBasicBlock *MBB,
609  unsigned Opcode, bool NoFloat) const;
610  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
611  MachineBasicBlock *MBB,
612  unsigned Opcode) const;
613 
614  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
615 };
616 } // end namespace llvm
617 
618 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
This class represents a function call, abstracting a target machine&#39;s calling convention.
Function Alias Analysis Results
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
This contains information for each constraint that we are lowering.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
bool isPCREL(unsigned Opcode)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
Target - Wrapper for Target specific information.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Representation of each machine instruction.
Definition: MachineInstr.h:59
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.