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SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35  // See comments in SystemZInstrFormats.td.
36  SimpleBDXLoad = (1 << 0),
37  SimpleBDXStore = (1 << 1),
38  Has20BitOffset = (1 << 2),
39  HasIndex = (1 << 3),
40  Is128Bit = (1 << 4),
41  AccessSizeMask = (31 << 5),
43  CCValuesMask = (15 << 10),
45  CompareZeroCCMaskMask = (15 << 14),
47  CCMaskFirst = (1 << 18),
48  CCMaskLast = (1 << 19),
49  IsLogical = (1 << 20)
50 };
51 
52 static inline unsigned getAccessSize(unsigned int Flags) {
53  return (Flags & AccessSizeMask) >> AccessSizeShift;
54 }
55 
56 static inline unsigned getCCValues(unsigned int Flags) {
57  return (Flags & CCValuesMask) >> CCValuesShift;
58 }
59 
60 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
62 }
63 
64 // SystemZ MachineOperand target flags.
65 enum {
66  // Masks out the bits for the access model.
67  MO_SYMBOL_MODIFIER = (3 << 0),
68 
69  // @GOT (aka @GOTENT)
70  MO_GOT = (1 << 0),
71 
72  // @INDNTPOFF
73  MO_INDNTPOFF = (2 << 0)
74 };
75 
76 // Classifies a branch.
77 enum BranchType {
78  // An instruction that branches on the current value of CC.
80 
81  // An instruction that peforms a 32-bit signed comparison and branches
82  // on the result.
84 
85  // An instruction that peforms a 32-bit unsigned comparison and branches
86  // on the result.
88 
89  // An instruction that peforms a 64-bit signed comparison and branches
90  // on the result.
92 
93  // An instruction that peforms a 64-bit unsigned comparison and branches
94  // on the result.
96 
97  // An instruction that decrements a 32-bit register and branches if
98  // the result is nonzero.
100 
101  // An instruction that decrements a 64-bit register and branches if
102  // the result is nonzero.
104 };
105 
106 // Information about a branch instruction.
107 struct Branch {
108  // The type of the branch.
110 
111  // CCMASK_<N> is set if CC might be equal to N.
112  unsigned CCValid;
113 
114  // CCMASK_<N> is set if the branch should be taken when CC == N.
115  unsigned CCMask;
116 
117  // The target of the branch.
119 
120  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
121  const MachineOperand *target)
122  : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
123 };
124 
125 // Kinds of fused compares in compare-and-* instructions. Together with type
126 // of the converted compare, this identifies the compare-and-*
127 // instruction.
129  // Relative branch - CRJ etc.
131 
132  // Indirect branch, used for return - CRBReturn etc.
134 
135  // Indirect branch, used for sibcall - CRBCall etc.
137 
138  // Trap
140 };
141 
142 } // end namespace SystemZII
143 
145  const SystemZRegisterInfo RI;
146  SystemZSubtarget &STI;
147 
148  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
149  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
150  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
151  bool ConvertHigh) const;
152  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
153  unsigned LowOpcodeK, unsigned HighOpcode) const;
154  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
155  unsigned HighOpcode) const;
156  void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
157  unsigned HighOpcode) const;
158  void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
159  unsigned HighOpcode) const;
160  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
161  unsigned Size) const;
162  void expandLoadStackGuard(MachineInstr *MI) const;
163 
165  emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
166  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
167  unsigned LowLowOpcode, unsigned Size, bool KillSrc,
168  bool UndefSrc) const;
169 
170  virtual void anchor();
171 
172 protected:
173  /// Commutes the operands in the given instruction by changing the operands
174  /// order and/or changing the instruction's opcode and/or the immediate value
175  /// operand.
176  ///
177  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
178  /// to be commuted.
179  ///
180  /// Do not call this method for a non-commutable instruction or
181  /// non-commutable operands.
182  /// Even though the instruction is commutable, the method may still
183  /// fail to commute the operands, null pointer is returned in such cases.
184  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
185  unsigned CommuteOpIdx1,
186  unsigned CommuteOpIdx2) const override;
187 
188 public:
189  explicit SystemZInstrInfo(SystemZSubtarget &STI);
190 
191  // Override TargetInstrInfo.
192  unsigned isLoadFromStackSlot(const MachineInstr &MI,
193  int &FrameIndex) const override;
194  unsigned isStoreToStackSlot(const MachineInstr &MI,
195  int &FrameIndex) const override;
196  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
197  int &SrcFrameIndex) const override;
198  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
199  MachineBasicBlock *&FBB,
201  bool AllowModify) const override;
202  unsigned removeBranch(MachineBasicBlock &MBB,
203  int *BytesRemoved = nullptr) const override;
204  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
206  const DebugLoc &DL,
207  int *BytesAdded = nullptr) const override;
208  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
209  unsigned &SrcReg2, int &Mask, int &Value) const override;
210  bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
211  unsigned, unsigned, int&, int&, int&) const override;
212  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
213  const DebugLoc &DL, unsigned DstReg,
214  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
215  unsigned FalseReg) const override;
216  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
217  MachineRegisterInfo *MRI) const override;
218  bool isPredicable(const MachineInstr &MI) const override;
219  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
220  unsigned ExtraPredCycles,
221  BranchProbability Probability) const override;
222  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
223  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
224  MachineBasicBlock &FMBB,
225  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
226  BranchProbability Probability) const override;
227  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
228  BranchProbability Probability) const override;
229  bool PredicateInstruction(MachineInstr &MI,
230  ArrayRef<MachineOperand> Pred) const override;
231  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
232  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
233  bool KillSrc) const override;
234  void storeRegToStackSlot(MachineBasicBlock &MBB,
236  unsigned SrcReg, bool isKill, int FrameIndex,
237  const TargetRegisterClass *RC,
238  const TargetRegisterInfo *TRI) const override;
239  void loadRegFromStackSlot(MachineBasicBlock &MBB,
241  unsigned DestReg, int FrameIdx,
242  const TargetRegisterClass *RC,
243  const TargetRegisterInfo *TRI) const override;
244  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
245  MachineInstr &MI,
246  LiveVariables *LV) const override;
247  MachineInstr *
248  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
249  ArrayRef<unsigned> Ops,
250  MachineBasicBlock::iterator InsertPt, int FrameIndex,
251  LiveIntervals *LIS = nullptr) const override;
252  MachineInstr *foldMemoryOperandImpl(
254  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
255  LiveIntervals *LIS = nullptr) const override;
256  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
257  bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
258  override;
259 
260  // Return the SystemZRegisterInfo, which this class owns.
261  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
262 
263  // Return the size in bytes of MI.
264  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
265 
266  // Return true if MI is a conditional or unconditional branch.
267  // When returning true, set Cond to the mask of condition-code
268  // values on which the instruction will branch, and set Target
269  // to the operand that contains the branch target. This target
270  // can be a register or a basic block.
271  SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
272 
273  // Get the load and store opcodes for a given register class.
274  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
275  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
276 
277  // Opcode is the opcode of an instruction that has an address operand,
278  // and the caller wants to perform that instruction's operation on an
279  // address that has displacement Offset. Return the opcode of a suitable
280  // instruction (which might be Opcode itself) or 0 if no such instruction
281  // exists.
282  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
283 
284  // If Opcode is a load instruction that has a LOAD AND TEST form,
285  // return the opcode for the testing form, otherwise return 0.
286  unsigned getLoadAndTest(unsigned Opcode) const;
287 
288  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
289  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
290  // significant. Set Start and End to the I3 and I4 operands if so.
291  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
292  unsigned &Start, unsigned &End) const;
293 
294  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
295  // operation exists, return the opcode for the latter, otherwise return 0.
296  // MI, if nonnull, is the compare instruction.
297  unsigned getFusedCompare(unsigned Opcode,
299  const MachineInstr *MI = nullptr) const;
300 
301  // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
302  // operation exists, returh the opcode for the latter, otherwise return 0.
303  unsigned getLoadAndTrap(unsigned Opcode) const;
304 
305  // Emit code before MBBI in MI to move immediate value Value into
306  // physical register Reg.
307  void loadImmediate(MachineBasicBlock &MBB,
309  unsigned Reg, uint64_t Value) const;
310 
311  // Sometimes, it is possible for the target to tell, even without
312  // aliasing information, that two MIs access different memory
313  // addresses. This function returns true if two MIs access different
314  // memory addresses and false otherwise.
315  bool
316  areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
317  AliasAnalysis *AA = nullptr) const override;
318 };
319 
320 } // end namespace llvm
321 
322 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
const SystemZRegisterInfo & getRegisterInfo() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
const MachineOperand * Target
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static unsigned getAccessSize(unsigned int Flags)
MachineInstrBuilder & UseMI
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getCompareZeroCCMask(unsigned int Flags)
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
static unsigned getCCValues(unsigned int Flags)
uint32_t Size
Definition: Profile.cpp:46
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI