LLVM  7.0.0svn
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZRegisterInfo.h"
11 #include "SystemZInstrInfo.h"
12 #include "SystemZSubtarget.h"
14 #include "llvm/ADT/SmallSet.h"
19 
20 using namespace llvm;
21 
22 #define GET_REGINFO_TARGET_DESC
23 #include "SystemZGenRegisterInfo.inc"
24 
26  : SystemZGenRegisterInfo(SystemZ::R14D) {}
27 
28 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
29 // somehow belongs in it. Otherwise, return GRX32.
31  const VirtRegMap *VRM,
32  const MachineRegisterInfo *MRI) {
33  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
34 
35  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
36  MO.getSubReg() == SystemZ::subreg_l32 ||
37  MO.getSubReg() == SystemZ::subreg_hl32)
38  return &SystemZ::GR32BitRegClass;
39  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
40  MO.getSubReg() == SystemZ::subreg_h32 ||
41  MO.getSubReg() == SystemZ::subreg_hh32)
42  return &SystemZ::GRH32BitRegClass;
43 
44  if (VRM && VRM->hasPhys(MO.getReg())) {
45  unsigned PhysReg = VRM->getPhys(MO.getReg());
46  if (SystemZ::GR32BitRegClass.contains(PhysReg))
47  return &SystemZ::GR32BitRegClass;
48  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
49  "Phys reg not in GR32 or GRH32?");
50  return &SystemZ::GRH32BitRegClass;
51  }
52 
53  assert (RC == &SystemZ::GRX32BitRegClass);
54  return RC;
55 }
56 
57 bool
59  ArrayRef<MCPhysReg> Order,
61  const MachineFunction &MF,
62  const VirtRegMap *VRM,
63  const LiveRegMatrix *Matrix) const {
64  const MachineRegisterInfo *MRI = &MF.getRegInfo();
66  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
67  SmallVector<unsigned, 8> Worklist;
68  SmallSet<unsigned, 4> DoneRegs;
69  Worklist.push_back(VirtReg);
70  while (Worklist.size()) {
71  unsigned Reg = Worklist.pop_back_val();
72  if (!DoneRegs.insert(Reg).second)
73  continue;
74 
75  for (auto &Use : MRI->use_instructions(Reg))
76  // For LOCRMux, see if the other operand is already a high or low
77  // register, and in that case give the correpsonding hints for
78  // VirtReg. LOCR instructions need both operands in either high or
79  // low parts.
80  if (Use.getOpcode() == SystemZ::LOCRMux) {
81  MachineOperand &TrueMO = Use.getOperand(1);
82  MachineOperand &FalseMO = Use.getOperand(2);
83  const TargetRegisterClass *RC =
84  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
85  getRC32(TrueMO, VRM, MRI));
86  if (RC && RC != &SystemZ::GRX32BitRegClass) {
87  for (MCPhysReg Reg : Order)
88  if (RC->contains(Reg) && !MRI->isReserved(Reg))
89  Hints.push_back(Reg);
90  // Return true to make these hints the only regs available to
91  // RA. This may mean extra spilling but since the alternative is
92  // a jump sequence expansion of the LOCRMux, it is preferred.
93  return true;
94  }
95 
96  // Add the other operand of the LOCRMux to the worklist.
97  unsigned OtherReg =
98  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
99  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
100  Worklist.push_back(OtherReg);
101  }
102  }
103  }
104 
105  return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
106  VRM, Matrix);
107 }
108 
109 const MCPhysReg *
111  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
113  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
114  : CSR_SystemZ_AllRegs_SaveList;
117  Attribute::SwiftError))
118  return CSR_SystemZ_SwiftError_SaveList;
119  return CSR_SystemZ_SaveList;
120 }
121 
122 const uint32_t *
124  CallingConv::ID CC) const {
125  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
126  if (CC == CallingConv::AnyReg)
127  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
128  : CSR_SystemZ_AllRegs_RegMask;
131  Attribute::SwiftError))
132  return CSR_SystemZ_SwiftError_RegMask;
133  return CSR_SystemZ_RegMask;
134 }
135 
136 BitVector
138  BitVector Reserved(getNumRegs());
139  const SystemZFrameLowering *TFI = getFrameLowering(MF);
140 
141  if (TFI->hasFP(MF)) {
142  // R11D is the frame pointer. Reserve all aliases.
143  Reserved.set(SystemZ::R11D);
144  Reserved.set(SystemZ::R11L);
145  Reserved.set(SystemZ::R11H);
146  Reserved.set(SystemZ::R10Q);
147  }
148 
149  // R15D is the stack pointer. Reserve all aliases.
150  Reserved.set(SystemZ::R15D);
151  Reserved.set(SystemZ::R15L);
152  Reserved.set(SystemZ::R15H);
153  Reserved.set(SystemZ::R14Q);
154 
155  // A0 and A1 hold the thread pointer.
156  Reserved.set(SystemZ::A0);
157  Reserved.set(SystemZ::A1);
158 
159  return Reserved;
160 }
161 
162 void
164  int SPAdj, unsigned FIOperandNum,
165  RegScavenger *RS) const {
166  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
167 
168  MachineBasicBlock &MBB = *MI->getParent();
169  MachineFunction &MF = *MBB.getParent();
170  auto *TII =
171  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
172  const SystemZFrameLowering *TFI = getFrameLowering(MF);
173  DebugLoc DL = MI->getDebugLoc();
174 
175  // Decompose the frame index into a base and offset.
176  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
177  unsigned BasePtr;
178  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
179  MI->getOperand(FIOperandNum + 1).getImm());
180 
181  // Special handling of dbg_value instructions.
182  if (MI->isDebugValue()) {
183  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
184  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
185  return;
186  }
187 
188  // See if the offset is in range, or if an equivalent instruction that
189  // accepts the offset exists.
190  unsigned Opcode = MI->getOpcode();
191  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
192  if (OpcodeForOffset) {
193  if (OpcodeForOffset == SystemZ::LE &&
195  // If LE is ok for offset, use LDE instead on z13.
196  OpcodeForOffset = SystemZ::LDE32;
197  }
198  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
199  }
200  else {
201  // Create an anchor point that is in range. Start at 0xffff so that
202  // can use LLILH to load the immediate.
203  int64_t OldOffset = Offset;
204  int64_t Mask = 0xffff;
205  do {
206  Offset = OldOffset & Mask;
207  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
208  Mask >>= 1;
209  assert(Mask && "One offset must be OK");
210  } while (!OpcodeForOffset);
211 
212  unsigned ScratchReg =
213  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
214  int64_t HighOffset = OldOffset - Offset;
215 
216  if (MI->getDesc().TSFlags & SystemZII::HasIndex
217  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
218  // Load the offset into the scratch register and use it as an index.
219  // The scratch register then dies here.
220  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
221  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
222  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
223  false, false, true);
224  } else {
225  // Load the anchor address into a scratch register.
226  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
227  if (LAOpcode)
228  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
229  .addReg(BasePtr).addImm(HighOffset).addReg(0);
230  else {
231  // Load the high offset into the scratch register and use it as
232  // an index.
233  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
234  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
235  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
236  }
237 
238  // Use the scratch register as the base. It then dies here.
239  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
240  false, false, true);
241  }
242  }
243  MI->setDesc(TII->get(OpcodeForOffset));
244  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
245 }
246 
248  const TargetRegisterClass *SrcRC,
249  unsigned SubReg,
250  const TargetRegisterClass *DstRC,
251  unsigned DstSubReg,
252  const TargetRegisterClass *NewRC,
253  LiveIntervals &LIS) const {
254  assert (MI->isCopy() && "Only expecting COPY instructions");
255 
256  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
257  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
258  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
259  return true;
260 
261  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
262  // and local to one MBB with not too much interferring registers. Otherwise
263  // regalloc may run out of registers.
264 
265  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
266  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
267  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
268  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
269  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
270 
271  // Check that the two virtual registers are local to MBB.
272  MachineBasicBlock *MBB = MI->getParent();
273  if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
274  LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
275  return false;
276 
277  // Find the first and last MIs of the registers.
278  MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
279  if (WideOpNo == 1) {
280  FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
281  LastMI = LIS.getInstructionFromIndex(IntGRNar.endIndex());
282  } else {
283  FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
284  LastMI = LIS.getInstructionFromIndex(IntGR128.endIndex());
285  }
286  assert (FirstMI && LastMI && "No instruction from index?");
287 
288  // Check if coalescing seems safe by finding the set of clobbered physreg
289  // pairs in the region.
290  BitVector PhysClobbered(getNumRegs());
291  MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
292  MEE++;
293  for (; MII != MEE; ++MII) {
294  for (const MachineOperand &MO : MII->operands())
295  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
296  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
297  SI.isValid(); ++SI)
298  if (NewRC->contains(*SI)) {
299  PhysClobbered.set(*SI);
300  break;
301  }
302  }
303  }
304 
305  // Demand an arbitrary margin of free regs.
306  unsigned const DemandedFreeGR128 = 3;
307  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
308  return false;
309 
310  return true;
311 }
312 
313 unsigned
315  const SystemZFrameLowering *TFI = getFrameLowering(MF);
316  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
317 }
318 
319 const TargetRegisterClass *
321  if (RC == &SystemZ::CCRRegClass)
322  return &SystemZ::GR32BitRegClass;
323  return RC;
324 }
325 
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:213
BitVector & set()
Definition: BitVector.h:398
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
unsigned SubReg
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:380
unsigned const MachineRegisterInfo * MRI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
bool isCopy() const
Definition: MachineInstr.h:892
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
MachineOperand class - Representation of each machine instruction operand.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:382
LiveInterval & getInterval(unsigned Reg)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:95
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:373
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.