LLVM  9.0.0svn
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
13 #include "llvm/ADT/SmallSet.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
23 
25  : SystemZGenRegisterInfo(SystemZ::R14D) {}
26 
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
30  const VirtRegMap *VRM,
31  const MachineRegisterInfo *MRI) {
32  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33 
34  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35  MO.getSubReg() == SystemZ::subreg_l32 ||
36  MO.getSubReg() == SystemZ::subreg_hl32)
37  return &SystemZ::GR32BitRegClass;
38  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39  MO.getSubReg() == SystemZ::subreg_h32 ||
40  MO.getSubReg() == SystemZ::subreg_hh32)
41  return &SystemZ::GRH32BitRegClass;
42 
43  if (VRM && VRM->hasPhys(MO.getReg())) {
44  unsigned PhysReg = VRM->getPhys(MO.getReg());
45  if (SystemZ::GR32BitRegClass.contains(PhysReg))
46  return &SystemZ::GR32BitRegClass;
47  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48  "Phys reg not in GR32 or GRH32?");
49  return &SystemZ::GRH32BitRegClass;
50  }
51 
52  assert (RC == &SystemZ::GRX32BitRegClass);
53  return RC;
54 }
55 
56 bool
58  ArrayRef<MCPhysReg> Order,
60  const MachineFunction &MF,
61  const VirtRegMap *VRM,
62  const LiveRegMatrix *Matrix) const {
63  const MachineRegisterInfo *MRI = &MF.getRegInfo();
65 
66  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
67  VirtReg, Order, Hints, MF, VRM, Matrix);
68 
69  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
70  SmallVector<unsigned, 8> Worklist;
71  SmallSet<unsigned, 4> DoneRegs;
72  Worklist.push_back(VirtReg);
73  while (Worklist.size()) {
74  unsigned Reg = Worklist.pop_back_val();
75  if (!DoneRegs.insert(Reg).second)
76  continue;
77 
78  for (auto &Use : MRI->use_instructions(Reg))
79  // For LOCRMux, see if the other operand is already a high or low
80  // register, and in that case give the correpsonding hints for
81  // VirtReg. LOCR instructions need both operands in either high or
82  // low parts.
83  if (Use.getOpcode() == SystemZ::LOCRMux) {
84  MachineOperand &TrueMO = Use.getOperand(1);
85  MachineOperand &FalseMO = Use.getOperand(2);
86  const TargetRegisterClass *RC =
87  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
88  getRC32(TrueMO, VRM, MRI));
89  if (RC && RC != &SystemZ::GRX32BitRegClass) {
90  // Pass the registers of RC as hints while making sure that if
91  // any of these registers are copy hints, hint them first.
92  SmallSet<unsigned, 4> CopyHints;
93  CopyHints.insert(Hints.begin(), Hints.end());
94  Hints.clear();
95  for (MCPhysReg Reg : Order)
96  if (CopyHints.count(Reg) &&
97  RC->contains(Reg) && !MRI->isReserved(Reg))
98  Hints.push_back(Reg);
99  for (MCPhysReg Reg : Order)
100  if (!CopyHints.count(Reg) &&
101  RC->contains(Reg) && !MRI->isReserved(Reg))
102  Hints.push_back(Reg);
103  // Return true to make these hints the only regs available to
104  // RA. This may mean extra spilling but since the alternative is
105  // a jump sequence expansion of the LOCRMux, it is preferred.
106  return true;
107  }
108 
109  // Add the other operand of the LOCRMux to the worklist.
110  unsigned OtherReg =
111  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
112  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
113  Worklist.push_back(OtherReg);
114  }
115  }
116  }
117 
118  return BaseImplRetVal;
119 }
120 
121 const MCPhysReg *
123  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
125  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
126  : CSR_SystemZ_AllRegs_SaveList;
129  Attribute::SwiftError))
130  return CSR_SystemZ_SwiftError_SaveList;
131  return CSR_SystemZ_SaveList;
132 }
133 
134 const uint32_t *
136  CallingConv::ID CC) const {
137  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
138  if (CC == CallingConv::AnyReg)
139  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
140  : CSR_SystemZ_AllRegs_RegMask;
143  Attribute::SwiftError))
144  return CSR_SystemZ_SwiftError_RegMask;
145  return CSR_SystemZ_RegMask;
146 }
147 
148 BitVector
150  BitVector Reserved(getNumRegs());
151  const SystemZFrameLowering *TFI = getFrameLowering(MF);
152 
153  if (TFI->hasFP(MF)) {
154  // R11D is the frame pointer. Reserve all aliases.
155  Reserved.set(SystemZ::R11D);
156  Reserved.set(SystemZ::R11L);
157  Reserved.set(SystemZ::R11H);
158  Reserved.set(SystemZ::R10Q);
159  }
160 
161  // R15D is the stack pointer. Reserve all aliases.
162  Reserved.set(SystemZ::R15D);
163  Reserved.set(SystemZ::R15L);
164  Reserved.set(SystemZ::R15H);
165  Reserved.set(SystemZ::R14Q);
166 
167  // A0 and A1 hold the thread pointer.
168  Reserved.set(SystemZ::A0);
169  Reserved.set(SystemZ::A1);
170 
171  return Reserved;
172 }
173 
174 void
176  int SPAdj, unsigned FIOperandNum,
177  RegScavenger *RS) const {
178  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
179 
180  MachineBasicBlock &MBB = *MI->getParent();
181  MachineFunction &MF = *MBB.getParent();
182  auto *TII =
183  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
184  const SystemZFrameLowering *TFI = getFrameLowering(MF);
185  DebugLoc DL = MI->getDebugLoc();
186 
187  // Decompose the frame index into a base and offset.
188  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
189  unsigned BasePtr;
190  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
191  MI->getOperand(FIOperandNum + 1).getImm());
192 
193  // Special handling of dbg_value instructions.
194  if (MI->isDebugValue()) {
195  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
196  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
197  return;
198  }
199 
200  // See if the offset is in range, or if an equivalent instruction that
201  // accepts the offset exists.
202  unsigned Opcode = MI->getOpcode();
203  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
204  if (OpcodeForOffset) {
205  if (OpcodeForOffset == SystemZ::LE &&
207  // If LE is ok for offset, use LDE instead on z13.
208  OpcodeForOffset = SystemZ::LDE32;
209  }
210  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
211  }
212  else {
213  // Create an anchor point that is in range. Start at 0xffff so that
214  // can use LLILH to load the immediate.
215  int64_t OldOffset = Offset;
216  int64_t Mask = 0xffff;
217  do {
218  Offset = OldOffset & Mask;
219  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
220  Mask >>= 1;
221  assert(Mask && "One offset must be OK");
222  } while (!OpcodeForOffset);
223 
224  unsigned ScratchReg =
225  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
226  int64_t HighOffset = OldOffset - Offset;
227 
228  if (MI->getDesc().TSFlags & SystemZII::HasIndex
229  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
230  // Load the offset into the scratch register and use it as an index.
231  // The scratch register then dies here.
232  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
233  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
234  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
235  false, false, true);
236  } else {
237  // Load the anchor address into a scratch register.
238  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
239  if (LAOpcode)
240  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
241  .addReg(BasePtr).addImm(HighOffset).addReg(0);
242  else {
243  // Load the high offset into the scratch register and use it as
244  // an index.
245  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
246  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
247  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
248  }
249 
250  // Use the scratch register as the base. It then dies here.
251  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
252  false, false, true);
253  }
254  }
255  MI->setDesc(TII->get(OpcodeForOffset));
256  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
257 }
258 
260  const TargetRegisterClass *SrcRC,
261  unsigned SubReg,
262  const TargetRegisterClass *DstRC,
263  unsigned DstSubReg,
264  const TargetRegisterClass *NewRC,
265  LiveIntervals &LIS) const {
266  assert (MI->isCopy() && "Only expecting COPY instructions");
267 
268  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
269  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
270  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
271  return true;
272 
273  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
274  // and local to one MBB with not too much interferring registers. Otherwise
275  // regalloc may run out of registers.
276 
277  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
278  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
279  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
280  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
281  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
282 
283  // Check that the two virtual registers are local to MBB.
284  MachineBasicBlock *MBB = MI->getParent();
285  MachineInstr *FirstMI_GR128 =
286  LIS.getInstructionFromIndex(IntGR128.beginIndex());
287  MachineInstr *FirstMI_GRNar =
288  LIS.getInstructionFromIndex(IntGRNar.beginIndex());
289  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
290  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
291  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
292  (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
293  (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
294  (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
295  return false;
296 
297  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
298  if (WideOpNo == 1) {
299  MII = FirstMI_GR128;
300  MEE = LastMI_GRNar;
301  } else {
302  MII = FirstMI_GRNar;
303  MEE = LastMI_GR128;
304  }
305 
306  // Check if coalescing seems safe by finding the set of clobbered physreg
307  // pairs in the region.
308  BitVector PhysClobbered(getNumRegs());
309  MEE++;
310  for (; MII != MEE; ++MII) {
311  for (const MachineOperand &MO : MII->operands())
312  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
313  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
314  SI.isValid(); ++SI)
315  if (NewRC->contains(*SI)) {
316  PhysClobbered.set(*SI);
317  break;
318  }
319  }
320  }
321 
322  // Demand an arbitrary margin of free regs.
323  unsigned const DemandedFreeGR128 = 3;
324  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
325  return false;
326 
327  return true;
328 }
329 
330 unsigned
332  const SystemZFrameLowering *TFI = getFrameLowering(MF);
333  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
334 }
335 
336 const TargetRegisterClass *
338  if (RC == &SystemZ::CCRRegClass)
339  return &SystemZ::GR32BitRegClass;
340  return RC;
341 }
342 
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
BitVector & set()
Definition: BitVector.h:397
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:211
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:637
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned SubReg
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:379
unsigned const MachineRegisterInfo * MRI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:373
LiveInterval & getInterval(unsigned Reg)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:94
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:100
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:372
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164