LLVM  9.0.0svn
SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
13 #include "llvm/ADT/SmallSet.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
23 
25  : SystemZGenRegisterInfo(SystemZ::R14D) {}
26 
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
30  const VirtRegMap *VRM,
31  const MachineRegisterInfo *MRI) {
32  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33 
34  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35  MO.getSubReg() == SystemZ::subreg_l32 ||
36  MO.getSubReg() == SystemZ::subreg_hl32)
37  return &SystemZ::GR32BitRegClass;
38  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39  MO.getSubReg() == SystemZ::subreg_h32 ||
40  MO.getSubReg() == SystemZ::subreg_hh32)
41  return &SystemZ::GRH32BitRegClass;
42 
43  if (VRM && VRM->hasPhys(MO.getReg())) {
44  unsigned PhysReg = VRM->getPhys(MO.getReg());
45  if (SystemZ::GR32BitRegClass.contains(PhysReg))
46  return &SystemZ::GR32BitRegClass;
47  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48  "Phys reg not in GR32 or GRH32?");
49  return &SystemZ::GRH32BitRegClass;
50  }
51 
52  assert (RC == &SystemZ::GRX32BitRegClass);
53  return RC;
54 }
55 
56 // Pass the registers of RC as hints while making sure that if any of these
57 // registers are copy hints (and therefore already in Hints), hint them
58 // first.
59 static void addHints(ArrayRef<MCPhysReg> Order,
61  const TargetRegisterClass *RC,
62  const MachineRegisterInfo *MRI) {
63  SmallSet<unsigned, 4> CopyHints;
64  CopyHints.insert(Hints.begin(), Hints.end());
65  Hints.clear();
66  for (MCPhysReg Reg : Order)
67  if (CopyHints.count(Reg) &&
68  RC->contains(Reg) && !MRI->isReserved(Reg))
69  Hints.push_back(Reg);
70  for (MCPhysReg Reg : Order)
71  if (!CopyHints.count(Reg) &&
72  RC->contains(Reg) && !MRI->isReserved(Reg))
73  Hints.push_back(Reg);
74 }
75 
76 bool
78  ArrayRef<MCPhysReg> Order,
80  const MachineFunction &MF,
81  const VirtRegMap *VRM,
82  const LiveRegMatrix *Matrix) const {
83  const MachineRegisterInfo *MRI = &MF.getRegInfo();
84  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
85  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
86 
87  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
88  VirtReg, Order, Hints, MF, VRM, Matrix);
89 
90  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
91  SmallVector<unsigned, 8> Worklist;
92  SmallSet<unsigned, 4> DoneRegs;
93  Worklist.push_back(VirtReg);
94  while (Worklist.size()) {
95  unsigned Reg = Worklist.pop_back_val();
96  if (!DoneRegs.insert(Reg).second)
97  continue;
98 
99  for (auto &Use : MRI->use_instructions(Reg)) {
100  // For LOCRMux, see if the other operand is already a high or low
101  // register, and in that case give the correpsonding hints for
102  // VirtReg. LOCR instructions need both operands in either high or
103  // low parts.
104  if (Use.getOpcode() == SystemZ::LOCRMux) {
105  MachineOperand &TrueMO = Use.getOperand(1);
106  MachineOperand &FalseMO = Use.getOperand(2);
107  const TargetRegisterClass *RC =
108  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
109  getRC32(TrueMO, VRM, MRI));
110  if (RC && RC != &SystemZ::GRX32BitRegClass) {
111  addHints(Order, Hints, RC, MRI);
112  // Return true to make these hints the only regs available to
113  // RA. This may mean extra spilling but since the alternative is
114  // a jump sequence expansion of the LOCRMux, it is preferred.
115  return true;
116  }
117 
118  // Add the other operand of the LOCRMux to the worklist.
119  unsigned OtherReg =
120  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
121  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
122  Worklist.push_back(OtherReg);
123  } // end LOCRMux
124  else if (Use.getOpcode() == SystemZ::CHIMux ||
125  Use.getOpcode() == SystemZ::CFIMux) {
126  if (Use.getOperand(1).getImm() == 0) {
127  bool OnlyLMuxes = true;
128  for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
129  if (DefMI.getOpcode() != SystemZ::LMux)
130  OnlyLMuxes = false;
131  if (OnlyLMuxes) {
132  addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
133  // Return false to make these hints preferred but not obligatory.
134  return false;
135  }
136  }
137  } // end CHIMux / CFIMux
138  }
139  }
140  }
141 
142  if (VRM == nullptr)
143  return BaseImplRetVal;
144 
145  // Add any two address hints after any copy hints.
146  SmallSet<unsigned, 4> TwoAddrHints;
147  for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
148  if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
149  const MachineOperand *VRRegMO = nullptr;
150  const MachineOperand *OtherMO = nullptr;
151  const MachineOperand *CommuMO = nullptr;
152  if (VirtReg == Use.getOperand(0).getReg()) {
153  VRRegMO = &Use.getOperand(0);
154  OtherMO = &Use.getOperand(1);
155  if (Use.isCommutable())
156  CommuMO = &Use.getOperand(2);
157  } else if (VirtReg == Use.getOperand(1).getReg()) {
158  VRRegMO = &Use.getOperand(1);
159  OtherMO = &Use.getOperand(0);
160  } else if (VirtReg == Use.getOperand(2).getReg() && Use.isCommutable()) {
161  VRRegMO = &Use.getOperand(2);
162  OtherMO = &Use.getOperand(0);
163  } else
164  continue;
165 
166  auto tryAddHint = [&](const MachineOperand *MO) -> void {
167  unsigned Reg = MO->getReg();
168  unsigned PhysReg = isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
169  if (PhysReg) {
170  if (MO->getSubReg())
171  PhysReg = getSubReg(PhysReg, MO->getSubReg());
172  if (VRRegMO->getSubReg())
173  PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
174  MRI->getRegClass(VirtReg));
175  if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
176  TwoAddrHints.insert(PhysReg);
177  }
178  };
179  tryAddHint(OtherMO);
180  if (CommuMO)
181  tryAddHint(CommuMO);
182  }
183  for (MCPhysReg OrderReg : Order)
184  if (TwoAddrHints.count(OrderReg))
185  Hints.push_back(OrderReg);
186 
187  return BaseImplRetVal;
188 }
189 
190 const MCPhysReg *
192  const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
194  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
195  : CSR_SystemZ_AllRegs_SaveList;
198  Attribute::SwiftError))
199  return CSR_SystemZ_SwiftError_SaveList;
200  return CSR_SystemZ_SaveList;
201 }
202 
203 const uint32_t *
205  CallingConv::ID CC) const {
206  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
207  if (CC == CallingConv::AnyReg)
208  return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
209  : CSR_SystemZ_AllRegs_RegMask;
212  Attribute::SwiftError))
213  return CSR_SystemZ_SwiftError_RegMask;
214  return CSR_SystemZ_RegMask;
215 }
216 
217 BitVector
219  BitVector Reserved(getNumRegs());
220  const SystemZFrameLowering *TFI = getFrameLowering(MF);
221 
222  if (TFI->hasFP(MF)) {
223  // R11D is the frame pointer. Reserve all aliases.
224  Reserved.set(SystemZ::R11D);
225  Reserved.set(SystemZ::R11L);
226  Reserved.set(SystemZ::R11H);
227  Reserved.set(SystemZ::R10Q);
228  }
229 
230  // R15D is the stack pointer. Reserve all aliases.
231  Reserved.set(SystemZ::R15D);
232  Reserved.set(SystemZ::R15L);
233  Reserved.set(SystemZ::R15H);
234  Reserved.set(SystemZ::R14Q);
235 
236  // A0 and A1 hold the thread pointer.
237  Reserved.set(SystemZ::A0);
238  Reserved.set(SystemZ::A1);
239 
240  // FPC is the floating-point control register.
241  Reserved.set(SystemZ::FPC);
242 
243  return Reserved;
244 }
245 
246 void
248  int SPAdj, unsigned FIOperandNum,
249  RegScavenger *RS) const {
250  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
251 
252  MachineBasicBlock &MBB = *MI->getParent();
253  MachineFunction &MF = *MBB.getParent();
254  auto *TII =
255  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
256  const SystemZFrameLowering *TFI = getFrameLowering(MF);
257  DebugLoc DL = MI->getDebugLoc();
258 
259  // Decompose the frame index into a base and offset.
260  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
261  unsigned BasePtr;
262  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
263  MI->getOperand(FIOperandNum + 1).getImm());
264 
265  // Special handling of dbg_value instructions.
266  if (MI->isDebugValue()) {
267  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
268  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
269  return;
270  }
271 
272  // See if the offset is in range, or if an equivalent instruction that
273  // accepts the offset exists.
274  unsigned Opcode = MI->getOpcode();
275  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
276  if (OpcodeForOffset) {
277  if (OpcodeForOffset == SystemZ::LE &&
279  // If LE is ok for offset, use LDE instead on z13.
280  OpcodeForOffset = SystemZ::LDE32;
281  }
282  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
283  }
284  else {
285  // Create an anchor point that is in range. Start at 0xffff so that
286  // can use LLILH to load the immediate.
287  int64_t OldOffset = Offset;
288  int64_t Mask = 0xffff;
289  do {
290  Offset = OldOffset & Mask;
291  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
292  Mask >>= 1;
293  assert(Mask && "One offset must be OK");
294  } while (!OpcodeForOffset);
295 
296  unsigned ScratchReg =
297  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
298  int64_t HighOffset = OldOffset - Offset;
299 
300  if (MI->getDesc().TSFlags & SystemZII::HasIndex
301  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
302  // Load the offset into the scratch register and use it as an index.
303  // The scratch register then dies here.
304  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
305  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
306  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
307  false, false, true);
308  } else {
309  // Load the anchor address into a scratch register.
310  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
311  if (LAOpcode)
312  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
313  .addReg(BasePtr).addImm(HighOffset).addReg(0);
314  else {
315  // Load the high offset into the scratch register and use it as
316  // an index.
317  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
318  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
319  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
320  }
321 
322  // Use the scratch register as the base. It then dies here.
323  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
324  false, false, true);
325  }
326  }
327  MI->setDesc(TII->get(OpcodeForOffset));
328  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
329 }
330 
332  const TargetRegisterClass *SrcRC,
333  unsigned SubReg,
334  const TargetRegisterClass *DstRC,
335  unsigned DstSubReg,
336  const TargetRegisterClass *NewRC,
337  LiveIntervals &LIS) const {
338  assert (MI->isCopy() && "Only expecting COPY instructions");
339 
340  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
341  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
342  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
343  return true;
344 
345  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
346  // and local to one MBB with not too much interferring registers. Otherwise
347  // regalloc may run out of registers.
348 
349  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
350  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
351  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
352  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
353  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
354 
355  // Check that the two virtual registers are local to MBB.
356  MachineBasicBlock *MBB = MI->getParent();
357  MachineInstr *FirstMI_GR128 =
358  LIS.getInstructionFromIndex(IntGR128.beginIndex());
359  MachineInstr *FirstMI_GRNar =
360  LIS.getInstructionFromIndex(IntGRNar.beginIndex());
361  MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
362  MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
363  if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
364  (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
365  (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
366  (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
367  return false;
368 
369  MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
370  if (WideOpNo == 1) {
371  MII = FirstMI_GR128;
372  MEE = LastMI_GRNar;
373  } else {
374  MII = FirstMI_GRNar;
375  MEE = LastMI_GR128;
376  }
377 
378  // Check if coalescing seems safe by finding the set of clobbered physreg
379  // pairs in the region.
380  BitVector PhysClobbered(getNumRegs());
381  MEE++;
382  for (; MII != MEE; ++MII) {
383  for (const MachineOperand &MO : MII->operands())
384  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
385  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
386  SI.isValid(); ++SI)
387  if (NewRC->contains(*SI)) {
388  PhysClobbered.set(*SI);
389  break;
390  }
391  }
392  }
393 
394  // Demand an arbitrary margin of free regs.
395  unsigned const DemandedFreeGR128 = 3;
396  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
397  return false;
398 
399  return true;
400 }
401 
402 unsigned
404  const SystemZFrameLowering *TFI = getFrameLowering(MF);
405  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
406 }
407 
408 const TargetRegisterClass *
410  if (RC == &SystemZ::CCRRegClass)
411  return &SystemZ::GR32BitRegClass;
412  return RC;
413 }
414 
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
BitVector & set()
Definition: BitVector.h:397
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
virtual int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void push_back(const T &Elt)
Definition: SmallVector.h:211
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:675
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
static void addHints(ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI)
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
unsigned SubReg
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
virtual const TargetInstrInfo * getInstrInfo() const
int getTwoOperandOpcode(uint16_t Opcode)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:379
unsigned const MachineRegisterInfo * MRI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
LiveInterval & getInterval(unsigned Reg)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:94
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:100
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:372
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
const SystemZRegisterInfo * getRegisterInfo() const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1251