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SystemZRegisterInfo.cpp
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1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZRegisterInfo.h"
11 #include "SystemZInstrInfo.h"
12 #include "SystemZSubtarget.h"
14 #include "llvm/ADT/SmallSet.h"
19 
20 using namespace llvm;
21 
22 #define GET_REGINFO_TARGET_DESC
23 #include "SystemZGenRegisterInfo.inc"
24 
26  : SystemZGenRegisterInfo(SystemZ::R14D) {}
27 
28 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
29 // somehow belongs in it. Otherwise, return GRX32.
31  const VirtRegMap *VRM,
32  const MachineRegisterInfo *MRI) {
33  const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
34 
35  if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
36  MO.getSubReg() == SystemZ::subreg_l32 ||
37  MO.getSubReg() == SystemZ::subreg_hl32)
38  return &SystemZ::GR32BitRegClass;
39  if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
40  MO.getSubReg() == SystemZ::subreg_h32 ||
41  MO.getSubReg() == SystemZ::subreg_hh32)
42  return &SystemZ::GRH32BitRegClass;
43 
44  if (VRM && VRM->hasPhys(MO.getReg())) {
45  unsigned PhysReg = VRM->getPhys(MO.getReg());
46  if (SystemZ::GR32BitRegClass.contains(PhysReg))
47  return &SystemZ::GR32BitRegClass;
48  assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
49  "Phys reg not in GR32 or GRH32?");
50  return &SystemZ::GRH32BitRegClass;
51  }
52 
53  assert (RC == &SystemZ::GRX32BitRegClass);
54  return RC;
55 }
56 
57 bool
59  ArrayRef<MCPhysReg> Order,
61  const MachineFunction &MF,
62  const VirtRegMap *VRM,
63  const LiveRegMatrix *Matrix) const {
64  const MachineRegisterInfo *MRI = &MF.getRegInfo();
66  if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
67  SmallVector<unsigned, 8> Worklist;
68  SmallSet<unsigned, 4> DoneRegs;
69  Worklist.push_back(VirtReg);
70  while (Worklist.size()) {
71  unsigned Reg = Worklist.pop_back_val();
72  if (!DoneRegs.insert(Reg).second)
73  continue;
74 
75  for (auto &Use : MRI->use_instructions(Reg))
76  // For LOCRMux, see if the other operand is already a high or low
77  // register, and in that case give the correpsonding hints for
78  // VirtReg. LOCR instructions need both operands in either high or
79  // low parts.
80  if (Use.getOpcode() == SystemZ::LOCRMux) {
81  MachineOperand &TrueMO = Use.getOperand(1);
82  MachineOperand &FalseMO = Use.getOperand(2);
83  const TargetRegisterClass *RC =
84  TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
85  getRC32(TrueMO, VRM, MRI));
86  if (RC && RC != &SystemZ::GRX32BitRegClass) {
87  for (MCPhysReg Reg : Order)
88  if (RC->contains(Reg) && !MRI->isReserved(Reg))
89  Hints.push_back(Reg);
90  // Return true to make these hints the only regs available to
91  // RA. This may mean extra spilling but since the alternative is
92  // a jump sequence expansion of the LOCRMux, it is preferred.
93  return true;
94  }
95 
96  // Add the other operand of the LOCRMux to the worklist.
97  unsigned OtherReg =
98  (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
99  if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
100  Worklist.push_back(OtherReg);
101  }
102  }
103  }
104 
105  return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
106  VRM, Matrix);
107 }
108 
109 const MCPhysReg *
113  Attribute::SwiftError))
114  return CSR_SystemZ_SwiftError_SaveList;
115  return CSR_SystemZ_SaveList;
116 }
117 
118 const uint32_t *
120  CallingConv::ID CC) const {
123  Attribute::SwiftError))
124  return CSR_SystemZ_SwiftError_RegMask;
125  return CSR_SystemZ_RegMask;
126 }
127 
128 BitVector
130  BitVector Reserved(getNumRegs());
131  const SystemZFrameLowering *TFI = getFrameLowering(MF);
132 
133  if (TFI->hasFP(MF)) {
134  // R11D is the frame pointer. Reserve all aliases.
135  Reserved.set(SystemZ::R11D);
136  Reserved.set(SystemZ::R11L);
137  Reserved.set(SystemZ::R11H);
138  Reserved.set(SystemZ::R10Q);
139  }
140 
141  // R15D is the stack pointer. Reserve all aliases.
142  Reserved.set(SystemZ::R15D);
143  Reserved.set(SystemZ::R15L);
144  Reserved.set(SystemZ::R15H);
145  Reserved.set(SystemZ::R14Q);
146 
147  // A0 and A1 hold the thread pointer.
148  Reserved.set(SystemZ::A0);
149  Reserved.set(SystemZ::A1);
150 
151  return Reserved;
152 }
153 
154 void
156  int SPAdj, unsigned FIOperandNum,
157  RegScavenger *RS) const {
158  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
159 
160  MachineBasicBlock &MBB = *MI->getParent();
161  MachineFunction &MF = *MBB.getParent();
162  auto *TII =
163  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
164  const SystemZFrameLowering *TFI = getFrameLowering(MF);
165  DebugLoc DL = MI->getDebugLoc();
166 
167  // Decompose the frame index into a base and offset.
168  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
169  unsigned BasePtr;
170  int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
171  MI->getOperand(FIOperandNum + 1).getImm());
172 
173  // Special handling of dbg_value instructions.
174  if (MI->isDebugValue()) {
175  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
176  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
177  return;
178  }
179 
180  // See if the offset is in range, or if an equivalent instruction that
181  // accepts the offset exists.
182  unsigned Opcode = MI->getOpcode();
183  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
184  if (OpcodeForOffset) {
185  if (OpcodeForOffset == SystemZ::LE &&
187  // If LE is ok for offset, use LDE instead on z13.
188  OpcodeForOffset = SystemZ::LDE32;
189  }
190  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
191  }
192  else {
193  // Create an anchor point that is in range. Start at 0xffff so that
194  // can use LLILH to load the immediate.
195  int64_t OldOffset = Offset;
196  int64_t Mask = 0xffff;
197  do {
198  Offset = OldOffset & Mask;
199  OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
200  Mask >>= 1;
201  assert(Mask && "One offset must be OK");
202  } while (!OpcodeForOffset);
203 
204  unsigned ScratchReg =
205  MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
206  int64_t HighOffset = OldOffset - Offset;
207 
208  if (MI->getDesc().TSFlags & SystemZII::HasIndex
209  && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
210  // Load the offset into the scratch register and use it as an index.
211  // The scratch register then dies here.
212  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
213  MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
214  MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
215  false, false, true);
216  } else {
217  // Load the anchor address into a scratch register.
218  unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
219  if (LAOpcode)
220  BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
221  .addReg(BasePtr).addImm(HighOffset).addReg(0);
222  else {
223  // Load the high offset into the scratch register and use it as
224  // an index.
225  TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
226  BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
227  .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
228  }
229 
230  // Use the scratch register as the base. It then dies here.
231  MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
232  false, false, true);
233  }
234  }
235  MI->setDesc(TII->get(OpcodeForOffset));
236  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
237 }
238 
240  const TargetRegisterClass *SrcRC,
241  unsigned SubReg,
242  const TargetRegisterClass *DstRC,
243  unsigned DstSubReg,
244  const TargetRegisterClass *NewRC,
245  LiveIntervals &LIS) const {
246  assert (MI->isCopy() && "Only expecting COPY instructions");
247 
248  // Coalesce anything which is not a COPY involving a subreg to/from GR128.
249  if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
250  (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
251  return true;
252 
253  // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
254  // and local to one MBB with not too much interferring registers. Otherwise
255  // regalloc may run out of registers.
256 
257  unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
258  unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
259  unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
260  LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
261  LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
262 
263  // Check that the two virtual registers are local to MBB.
264  MachineBasicBlock *MBB = MI->getParent();
265  if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
266  LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
267  return false;
268 
269  // Find the first and last MIs of the registers.
270  MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
271  if (WideOpNo == 1) {
272  FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
273  LastMI = LIS.getInstructionFromIndex(IntGRNar.endIndex());
274  } else {
275  FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
276  LastMI = LIS.getInstructionFromIndex(IntGR128.endIndex());
277  }
278  assert (FirstMI && LastMI && "No instruction from index?");
279 
280  // Check if coalescing seems safe by finding the set of clobbered physreg
281  // pairs in the region.
282  BitVector PhysClobbered(getNumRegs());
283  MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
284  MEE++;
285  for (; MII != MEE; ++MII) {
286  for (const MachineOperand &MO : MII->operands())
287  if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
288  for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
289  SI.isValid(); ++SI)
290  if (NewRC->contains(*SI)) {
291  PhysClobbered.set(*SI);
292  break;
293  }
294  }
295  }
296 
297  // Demand an arbitrary margin of free regs.
298  unsigned const DemandedFreeGR128 = 3;
299  if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
300  return false;
301 
302  return true;
303 }
304 
305 unsigned
307  const SystemZFrameLowering *TFI = getFrameLowering(MF);
308  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
309 }
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void push_back(const T &Elt)
Definition: SmallVector.h:212
BitVector & set()
Definition: BitVector.h:398
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getNumRegs() const
Return the number of registers in this class.
BitVector getReservedRegs(const MachineFunction &MF) const override
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
unsigned getReg() const
getReg - Returns the register number.
unsigned getSubReg() const
virtual const TargetLowering * getTargetLowering() const
A debug info location.
Definition: DebugLoc.h:34
return AArch64::GPR64RegClass contains(Reg)
Live Register Matrix
bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
MCSuperRegIterator enumerates all super-registers of Reg.
const HexagonInstrInfo * TII
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:380
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
bool isCopy() const
Definition: MachineInstr.h:857
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const TargetRegisterClass * getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI)
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
MachineOperand class - Representation of each machine instruction operand.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:385
LiveInterval & getInterval(unsigned Reg)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:95
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:101
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:373
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.