LLVM  8.0.0svn
SystemZRegisterInfo.h
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1 //===-- SystemZRegisterInfo.h - SystemZ register information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZREGISTERINFO_H
12 
13 #include "SystemZ.h"
15 
16 #define GET_REGINFO_HEADER
17 #include "SystemZGenRegisterInfo.inc"
18 
19 namespace llvm {
20 
21 class LiveIntervals;
22 
23 namespace SystemZ {
24 // Return the subreg to use for referring to the even and odd registers
25 // in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
26 inline unsigned even128(bool Is32bit) {
27  return Is32bit ? subreg_hl32 : subreg_h64;
28 }
29 inline unsigned odd128(bool Is32bit) {
30  return Is32bit ? subreg_l32 : subreg_l64;
31 }
32 } // end namespace SystemZ
33 
35 public:
37 
38  /// getPointerRegClass - Return the register class to use to hold pointers.
39  /// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
40  /// register, hence ADDR64.
41  const TargetRegisterClass *
43  unsigned Kind=0) const override {
44  return &SystemZ::ADDR64BitRegClass;
45  }
46 
47  /// getCrossCopyRegClass - Returns a legal register class to copy a register
48  /// in the specified class to or from. Returns NULL if it is possible to copy
49  /// between a two registers of the specified class.
50  const TargetRegisterClass *
51  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
52 
53  bool getRegAllocationHints(unsigned VirtReg,
54  ArrayRef<MCPhysReg> Order,
56  const MachineFunction &MF,
57  const VirtRegMap *VRM,
58  const LiveRegMatrix *Matrix) const override;
59 
60  // Override TargetRegisterInfo.h.
61  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
62  return true;
63  }
64  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
65  return true;
66  }
67  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
68  return true;
69  }
70  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
71  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
72  CallingConv::ID CC) const override;
73  BitVector getReservedRegs(const MachineFunction &MF) const override;
74  void eliminateFrameIndex(MachineBasicBlock::iterator MI,
75  int SPAdj, unsigned FIOperandNum,
76  RegScavenger *RS) const override;
77 
78  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
79  bool shouldCoalesce(MachineInstr *MI,
80  const TargetRegisterClass *SrcRC,
81  unsigned SubReg,
82  const TargetRegisterClass *DstRC,
83  unsigned DstSubReg,
84  const TargetRegisterClass *NewRC,
85  LiveIntervals &LIS) const override;
86 
87  unsigned getFrameRegister(const MachineFunction &MF) const override;
88 };
89 
90 } // end namespace llvm
91 
92 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned odd128(bool Is32bit)
Live Register Matrix
unsigned SubReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const unsigned Kind
unsigned even128(bool Is32bit)
IRTranslator LLVM IR MI