LLVM  8.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file describes how to lower LLVM code to machine code. This has two
12 /// main components:
13 ///
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
17 ///
18 /// In addition it has a few other components, like information about FP
19 /// immediates.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
25 
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/CallSite.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/IRBuilder.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h"
50 #include "llvm/IR/Type.h"
51 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class IntrinsicInst;
77 struct KnownBits;
78 class LLVMContext;
79 class MachineBasicBlock;
80 class MachineFunction;
81 class MachineInstr;
82 class MachineJumpTableInfo;
83 class MachineLoop;
84 class MachineRegisterInfo;
85 class MCContext;
86 class MCExpr;
87 class Module;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
91 class Value;
92 
93 namespace Sched {
94 
95  enum Preference {
96  None, // No preference
97  Source, // Follow source order.
98  RegPressure, // Scheduling for lowest register pressure.
99  Hybrid, // Scheduling for both latency and register pressure.
100  ILP, // Scheduling for ILP in low register pressure mode.
101  VLIW // Scheduling for VLIW targets.
102  };
103 
104 } // end namespace Sched
105 
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
109 public:
110  /// This enum indicates whether operations are valid for a target, and if not,
111  /// what action should be used to make them valid.
112  enum LegalizeAction : uint8_t {
113  Legal, // The target natively supports this operation.
114  Promote, // This operation should be executed in a larger type.
115  Expand, // Try to expand this to other ops, otherwise use a libcall.
116  LibCall, // Don't try to expand this to other ops, always use a libcall.
117  Custom // Use the LowerOperation hook to implement custom lowering.
118  };
119 
120  /// This enum indicates whether a types are legal for a target, and if not,
121  /// what action should be used to make them valid.
122  enum LegalizeTypeAction : uint8_t {
123  TypeLegal, // The target natively supports this type.
124  TypePromoteInteger, // Replace this integer with a larger one.
125  TypeExpandInteger, // Split this integer into two of half the size.
126  TypeSoftenFloat, // Convert this float to a same size integer type,
127  // if an operation is not supported in target HW.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167  };
168 
169  /// Enum that specifies when a multiplication should be expanded.
170  enum class MulExpansionKind {
171  Always, // Always expand the instruction.
172  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173  // or custom.
174  };
175 
176  class ArgListEntry {
177  public:
178  Value *Val = nullptr;
179  SDValue Node = SDValue();
180  Type *Ty = nullptr;
181  bool IsSExt : 1;
182  bool IsZExt : 1;
183  bool IsInReg : 1;
184  bool IsSRet : 1;
185  bool IsNest : 1;
186  bool IsByVal : 1;
187  bool IsInAlloca : 1;
188  bool IsReturned : 1;
189  bool IsSwiftSelf : 1;
190  bool IsSwiftError : 1;
191  uint16_t Alignment = 0;
192 
194  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196  IsSwiftSelf(false), IsSwiftError(false) {}
197 
198  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
199  };
200  using ArgListTy = std::vector<ArgListEntry>;
201 
202  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
203  ArgListTy &Args) const {};
204 
206  switch (Content) {
207  case UndefinedBooleanContent:
208  // Extend by adding rubbish bits.
209  return ISD::ANY_EXTEND;
210  case ZeroOrOneBooleanContent:
211  // Extend by adding zero bits.
212  return ISD::ZERO_EXTEND;
213  case ZeroOrNegativeOneBooleanContent:
214  // Extend by copying the sign bit.
215  return ISD::SIGN_EXTEND;
216  }
217  llvm_unreachable("Invalid content kind");
218  }
219 
220  /// NOTE: The TargetMachine owns TLOF.
221  explicit TargetLoweringBase(const TargetMachine &TM);
222  TargetLoweringBase(const TargetLoweringBase &) = delete;
223  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
224  virtual ~TargetLoweringBase() = default;
225 
226 protected:
227  /// Initialize all of the actions to default values.
228  void initActions();
229 
230 public:
231  const TargetMachine &getTargetMachine() const { return TM; }
232 
233  virtual bool useSoftFloat() const { return false; }
234 
235  /// Return the pointer type for the given address space, defaults to
236  /// the pointer type from the data layout.
237  /// FIXME: The default needs to be removed once all the code is updated.
238  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
240  }
241 
242  /// Return the type for frame index, which is determined by
243  /// the alloca address space specified through the data layout.
244  MVT getFrameIndexTy(const DataLayout &DL) const {
245  return getPointerTy(DL, DL.getAllocaAddrSpace());
246  }
247 
248  /// Return the type for operands of fence.
249  /// TODO: Let fence operands be of i32 type and remove this.
250  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
251  return getPointerTy(DL);
252  }
253 
254  /// EVT is not used in-tree, but is used by out-of-tree target.
255  /// A documentation for this function would be nice...
256  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
257 
258  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
259  bool LegalTypes = true) const;
260 
261  /// Returns the type to be used for the index operand of:
262  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
263  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
264  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
265  return getPointerTy(DL);
266  }
267 
268  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
269  return true;
270  }
271 
272  /// Return true if multiple condition registers are available.
274  return HasMultipleConditionRegisters;
275  }
276 
277  /// Return true if the target has BitExtract instructions.
278  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
279 
280  /// Return the preferred vector type legalization action.
283  // The default action for one element vectors is to scalarize
284  if (VT.getVectorNumElements() == 1)
285  return TypeScalarizeVector;
286  // The default action for other vectors is to promote
287  return TypePromoteInteger;
288  }
289 
290  // There are two general methods for expanding a BUILD_VECTOR node:
291  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
292  // them together.
293  // 2. Build the vector on the stack and then load it.
294  // If this function returns true, then method (1) will be used, subject to
295  // the constraint that all of the necessary shuffles are legal (as determined
296  // by isShuffleMaskLegal). If this function returns false, then method (2) is
297  // always used. The vector type, and the number of defined values, are
298  // provided.
299  virtual bool
301  unsigned DefinedValues) const {
302  return DefinedValues < 3;
303  }
304 
305  /// Return true if integer divide is usually cheaper than a sequence of
306  /// several shifts, adds, and multiplies for this target.
307  /// The definition of "cheaper" may depend on whether we're optimizing
308  /// for speed or for size.
309  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
310 
311  /// Return true if the target can handle a standalone remainder operation.
312  virtual bool hasStandaloneRem(EVT VT) const {
313  return true;
314  }
315 
316  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
317  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
318  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
319  return false;
320  }
321 
322  /// Reciprocal estimate status values used by the functions below.
323  enum ReciprocalEstimate : int {
324  Unspecified = -1,
325  Disabled = 0,
327  };
328 
329  /// Return a ReciprocalEstimate enum value for a square root of the given type
330  /// based on the function's attributes. If the operation is not overridden by
331  /// the function's attributes, "Unspecified" is returned and target defaults
332  /// are expected to be used for instruction selection.
333  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
334 
335  /// Return a ReciprocalEstimate enum value for a division of the given type
336  /// based on the function's attributes. If the operation is not overridden by
337  /// the function's attributes, "Unspecified" is returned and target defaults
338  /// are expected to be used for instruction selection.
339  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
340 
341  /// Return the refinement step count for a square root of the given type based
342  /// on the function's attributes. If the operation is not overridden by
343  /// the function's attributes, "Unspecified" is returned and target defaults
344  /// are expected to be used for instruction selection.
345  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
346 
347  /// Return the refinement step count for a division of the given type based
348  /// on the function's attributes. If the operation is not overridden by
349  /// the function's attributes, "Unspecified" is returned and target defaults
350  /// are expected to be used for instruction selection.
351  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
352 
353  /// Returns true if target has indicated at least one type should be bypassed.
354  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
355 
356  /// Returns map of slow types for division or remainder with corresponding
357  /// fast types
359  return BypassSlowDivWidths;
360  }
361 
362  /// Return true if Flow Control is an expensive operation that should be
363  /// avoided.
364  bool isJumpExpensive() const { return JumpIsExpensive; }
365 
366  /// Return true if selects are only cheaper than branches if the branch is
367  /// unlikely to be predicted right.
369  return PredictableSelectIsExpensive;
370  }
371 
372  /// If a branch or a select condition is skewed in one direction by more than
373  /// this factor, it is very likely to be predicted correctly.
374  virtual BranchProbability getPredictableBranchThreshold() const;
375 
376  /// Return true if the following transform is beneficial:
377  /// fold (conv (load x)) -> (load (conv*)x)
378  /// On architectures that don't natively support some vector loads
379  /// efficiently, casting the load to a smaller vector of larger types and
380  /// loading is more efficient, however, this can be undone by optimizations in
381  /// dag combiner.
382  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
383  EVT BitcastVT) const {
384  // Don't do if we could do an indexed load on the original type, but not on
385  // the new one.
386  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
387  return true;
388 
389  MVT LoadMVT = LoadVT.getSimpleVT();
390 
391  // Don't bother doing this if it's just going to be promoted again later, as
392  // doing so might interfere with other combines.
393  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
394  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
395  return false;
396 
397  return true;
398  }
399 
400  /// Return true if the following transform is beneficial:
401  /// (store (y (conv x)), y*)) -> (store x, (x*))
402  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
403  // Default to the same logic as loads.
404  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
405  }
406 
407  /// Return true if it is expected to be cheaper to do a store of a non-zero
408  /// vector constant with the given size and type for the address space than to
409  /// store the individual scalar element constants.
410  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
411  unsigned NumElem,
412  unsigned AddrSpace) const {
413  return false;
414  }
415 
416  /// Allow store merging after legalization in addition to before legalization.
417  /// This may catch stores that do not exist earlier (eg, stores created from
418  /// intrinsics).
419  virtual bool mergeStoresAfterLegalization() const { return true; }
420 
421  /// Returns if it's reasonable to merge stores to MemVT size.
422  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
423  const SelectionDAG &DAG) const {
424  return true;
425  }
426 
427  /// Return true if it is cheap to speculate a call to intrinsic cttz.
428  virtual bool isCheapToSpeculateCttz() const {
429  return false;
430  }
431 
432  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
433  virtual bool isCheapToSpeculateCtlz() const {
434  return false;
435  }
436 
437  /// Return true if ctlz instruction is fast.
438  virtual bool isCtlzFast() const {
439  return false;
440  }
441 
442  /// Return true if it is safe to transform an integer-domain bitwise operation
443  /// into the equivalent floating-point operation. This should be set to true
444  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
445  /// type.
446  virtual bool hasBitPreservingFPLogic(EVT VT) const {
447  return false;
448  }
449 
450  /// Return true if it is cheaper to split the store of a merged int val
451  /// from a pair of smaller values into multiple stores.
452  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
453  return false;
454  }
455 
456  /// Return if the target supports combining a
457  /// chain like:
458  /// \code
459  /// %andResult = and %val1, #mask
460  /// %icmpResult = icmp %andResult, 0
461  /// \endcode
462  /// into a single machine instruction of a form like:
463  /// \code
464  /// cc = test %register, #mask
465  /// \endcode
466  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
467  return false;
468  }
469 
470  /// Use bitwise logic to make pairs of compares more efficient. For example:
471  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
472  /// This should be true when it takes more than one instruction to lower
473  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
474  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
475  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
476  return false;
477  }
478 
479  /// Return the preferred operand type if the target has a quick way to compare
480  /// integer values of the given size. Assume that any legal integer type can
481  /// be compared efficiently. Targets may override this to allow illegal wide
482  /// types to return a vector type if there is support to compare that type.
483  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
484  MVT VT = MVT::getIntegerVT(NumBits);
485  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
486  }
487 
488  /// Return true if the target should transform:
489  /// (X & Y) == Y ---> (~X & Y) == 0
490  /// (X & Y) != Y ---> (~X & Y) != 0
491  ///
492  /// This may be profitable if the target has a bitwise and-not operation that
493  /// sets comparison flags. A target may want to limit the transformation based
494  /// on the type of Y or if Y is a constant.
495  ///
496  /// Note that the transform will not occur if Y is known to be a power-of-2
497  /// because a mask and compare of a single bit can be handled by inverting the
498  /// predicate, for example:
499  /// (X & 8) == 8 ---> (X & 8) != 0
500  virtual bool hasAndNotCompare(SDValue Y) const {
501  return false;
502  }
503 
504  /// Return true if the target has a bitwise and-not operation:
505  /// X = ~A & B
506  /// This can be used to simplify select or other instructions.
507  virtual bool hasAndNot(SDValue X) const {
508  // If the target has the more complex version of this operation, assume that
509  // it has this operation too.
510  return hasAndNotCompare(X);
511  }
512 
513  /// There are two ways to clear extreme bits (either low or high):
514  /// Mask: x & (-1 << y) (the instcombine canonical form)
515  /// Shifts: x >> y << y
516  /// Return true if the variant with 2 shifts is preferred.
517  /// Return false if there is no preference.
519  // By default, let's assume that no one prefers shifts.
520  return false;
521  }
522 
523  /// Should we tranform the IR-optimal check for whether given truncation
524  /// down into KeptBits would be truncating or not:
525  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
526  /// Into it's more traditional form:
527  /// ((%x << C) a>> C) dstcond %x
528  /// Return true if we should transform.
529  /// Return false if there is no preference.
531  unsigned KeptBits) const {
532  // By default, let's assume that no one prefers shifts.
533  return false;
534  }
535 
536  /// Return true if the target wants to use the optimization that
537  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
538  /// promotedInst1(...(promotedInstN(ext(load)))).
539  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
540 
541  /// Return true if the target can combine store(extractelement VectorTy,
542  /// Idx).
543  /// \p Cost[out] gives the cost of that transformation when this is true.
544  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
545  unsigned &Cost) const {
546  return false;
547  }
548 
549  /// Return true if inserting a scalar into a variable element of an undef
550  /// vector is more efficiently handled by splatting the scalar instead.
551  virtual bool shouldSplatInsEltVarIndex(EVT) const {
552  return false;
553  }
554 
555  /// Return true if target supports floating point exceptions.
557  return HasFloatingPointExceptions;
558  }
559 
560  /// Return true if target always beneficiates from combining into FMA for a
561  /// given value type. This must typically return false on targets where FMA
562  /// takes more cycles to execute than FADD.
563  virtual bool enableAggressiveFMAFusion(EVT VT) const {
564  return false;
565  }
566 
567  /// Return the ValueType of the result of SETCC operations.
568  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
569  EVT VT) const;
570 
571  /// Return the ValueType for comparison libcalls. Comparions libcalls include
572  /// floating point comparion calls, and Ordered/Unordered check calls on
573  /// floating point numbers.
574  virtual
575  MVT::SimpleValueType getCmpLibcallReturnType() const;
576 
577  /// For targets without i1 registers, this gives the nature of the high-bits
578  /// of boolean values held in types wider than i1.
579  ///
580  /// "Boolean values" are special true/false values produced by nodes like
581  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
582  /// Not to be confused with general values promoted from i1. Some cpus
583  /// distinguish between vectors of boolean and scalars; the isVec parameter
584  /// selects between the two kinds. For example on X86 a scalar boolean should
585  /// be zero extended from i1, while the elements of a vector of booleans
586  /// should be sign extended from i1.
587  ///
588  /// Some cpus also treat floating point types the same way as they treat
589  /// vectors instead of the way they treat scalars.
590  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
591  if (isVec)
592  return BooleanVectorContents;
593  return isFloat ? BooleanFloatContents : BooleanContents;
594  }
595 
597  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
598  }
599 
600  /// Return target scheduling preference.
602  return SchedPreferenceInfo;
603  }
604 
605  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
606  /// for different nodes. This function returns the preference (or none) for
607  /// the given node.
609  return Sched::None;
610  }
611 
612  /// Return the register class that should be used for the specified value
613  /// type.
614  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
615  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
616  assert(RC && "This value type is not natively supported!");
617  return RC;
618  }
619 
620  /// Return the 'representative' register class for the specified value
621  /// type.
622  ///
623  /// The 'representative' register class is the largest legal super-reg
624  /// register class for the register class of the value type. For example, on
625  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
626  /// register class is GR64 on x86_64.
627  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
628  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
629  return RC;
630  }
631 
632  /// Return the cost of the 'representative' register class for the specified
633  /// value type.
634  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
635  return RepRegClassCostForVT[VT.SimpleTy];
636  }
637 
638  /// Return true if the target has native support for the specified value type.
639  /// This means that it has a register that directly holds it without
640  /// promotions or expansions.
641  bool isTypeLegal(EVT VT) const {
642  assert(!VT.isSimple() ||
643  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
644  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
645  }
646 
648  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
649  /// that indicates how instruction selection should deal with the type.
650  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
651 
652  public:
654  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
655  TypeLegal);
656  }
657 
659  return ValueTypeActions[VT.SimpleTy];
660  }
661 
663  ValueTypeActions[VT.SimpleTy] = Action;
664  }
665  };
666 
668  return ValueTypeActions;
669  }
670 
671  /// Return how we should legalize values of this type, either it is already
672  /// legal (return 'Legal') or we need to promote it to a larger type (return
673  /// 'Promote'), or we need to expand it into multiple registers of smaller
674  /// integer type (return 'Expand'). 'Custom' is not an option.
676  return getTypeConversion(Context, VT).first;
677  }
679  return ValueTypeActions.getTypeAction(VT);
680  }
681 
682  /// For types supported by the target, this is an identity function. For
683  /// types that must be promoted to larger types, this returns the larger type
684  /// to promote to. For integer types that are larger than the largest integer
685  /// register, this contains one step in the expansion to get to the smaller
686  /// register. For illegal floating point types, this returns the integer type
687  /// to transform to.
688  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
689  return getTypeConversion(Context, VT).second;
690  }
691 
692  /// For types supported by the target, this is an identity function. For
693  /// types that must be expanded (i.e. integer types that are larger than the
694  /// largest integer register or illegal floating point types), this returns
695  /// the largest legal type it will be expanded to.
696  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
697  assert(!VT.isVector());
698  while (true) {
699  switch (getTypeAction(Context, VT)) {
700  case TypeLegal:
701  return VT;
702  case TypeExpandInteger:
703  VT = getTypeToTransformTo(Context, VT);
704  break;
705  default:
706  llvm_unreachable("Type is not legal nor is it to be expanded!");
707  }
708  }
709  }
710 
711  /// Vector types are broken down into some number of legal first class types.
712  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
713  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
714  /// turns into 4 EVT::i32 values with both PPC and X86.
715  ///
716  /// This method returns the number of registers needed, and the VT for each
717  /// register. It also returns the VT and quantity of the intermediate values
718  /// before they are promoted/expanded.
719  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
720  EVT &IntermediateVT,
721  unsigned &NumIntermediates,
722  MVT &RegisterVT) const;
723 
724  /// Certain targets such as MIPS require that some types such as vectors are
725  /// always broken down into scalars in some contexts. This occurs even if the
726  /// vector type is legal.
728  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
729  unsigned &NumIntermediates, MVT &RegisterVT) const {
730  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
731  RegisterVT);
732  }
733 
734  struct IntrinsicInfo {
735  unsigned opc = 0; // target opcode
736  EVT memVT; // memory VT
737 
738  // value representing memory location
740 
741  int offset = 0; // offset off of ptrVal
742  unsigned size = 0; // the size of the memory location
743  // (taken from memVT if zero)
744  unsigned align = 1; // alignment
745 
747  IntrinsicInfo() = default;
748  };
749 
750  /// Given an intrinsic, checks if on the target the intrinsic will need to map
751  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
752  /// true and store the intrinsic information into the IntrinsicInfo that was
753  /// passed to the function.
754  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
755  MachineFunction &,
756  unsigned /*Intrinsic*/) const {
757  return false;
758  }
759 
760  /// Returns true if the target can instruction select the specified FP
761  /// immediate natively. If false, the legalizer will materialize the FP
762  /// immediate as a load from a constant pool.
763  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
764  return false;
765  }
766 
767  /// Targets can use this to indicate that they only support *some*
768  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
769  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
770  /// legal.
771  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
772  return true;
773  }
774 
775  /// Returns true if the operation can trap for the value type.
776  ///
777  /// VT must be a legal type. By default, we optimistically assume most
778  /// operations don't trap except for integer divide and remainder.
779  virtual bool canOpTrap(unsigned Op, EVT VT) const;
780 
781  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
782  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
783  /// constant pool entry.
784  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
785  EVT /*VT*/) const {
786  return false;
787  }
788 
789  /// Return how this operation should be treated: either it is legal, needs to
790  /// be promoted to a larger size, needs to be expanded to some other code
791  /// sequence, or the target has a custom expander for it.
792  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
793  if (VT.isExtended()) return Expand;
794  // If a target-specific SDNode requires legalization, require the target
795  // to provide custom legalization for it.
796  if (Op >= array_lengthof(OpActions[0])) return Custom;
797  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
798  }
799 
801  unsigned EqOpc;
802  switch (Op) {
803  default: llvm_unreachable("Unexpected FP pseudo-opcode");
804  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
805  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
806  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
807  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
808  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
809  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
810  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
811  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
812  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
813  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
814  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
815  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
816  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
817  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
818  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
819  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
820  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
821  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
822  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
823  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
824  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
825  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
826  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
827  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
828  }
829 
830  auto Action = getOperationAction(EqOpc, VT);
831 
832  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
833  // For now, we just expand for those cases.
834  if (Action != Legal)
835  Action = Expand;
836 
837  return Action;
838  }
839 
840  /// Return true if the specified operation is legal on this target or can be
841  /// made legal with custom lowering. This is used to help guide high-level
842  /// lowering decisions.
843  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
844  return (VT == MVT::Other || isTypeLegal(VT)) &&
845  (getOperationAction(Op, VT) == Legal ||
846  getOperationAction(Op, VT) == Custom);
847  }
848 
849  /// Return true if the specified operation is legal on this target or can be
850  /// made legal using promotion. This is used to help guide high-level lowering
851  /// decisions.
852  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
853  return (VT == MVT::Other || isTypeLegal(VT)) &&
854  (getOperationAction(Op, VT) == Legal ||
855  getOperationAction(Op, VT) == Promote);
856  }
857 
858  /// Return true if the specified operation is legal on this target or can be
859  /// made legal with custom lowering or using promotion. This is used to help
860  /// guide high-level lowering decisions.
861  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
862  return (VT == MVT::Other || isTypeLegal(VT)) &&
863  (getOperationAction(Op, VT) == Legal ||
864  getOperationAction(Op, VT) == Custom ||
865  getOperationAction(Op, VT) == Promote);
866  }
867 
868  /// Return true if the operation uses custom lowering, regardless of whether
869  /// the type is legal or not.
870  bool isOperationCustom(unsigned Op, EVT VT) const {
871  return getOperationAction(Op, VT) == Custom;
872  }
873 
874  /// Return true if lowering to a jump table is allowed.
875  virtual bool areJTsAllowed(const Function *Fn) const {
876  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
877  return false;
878 
879  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
880  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
881  }
882 
883  /// Check whether the range [Low,High] fits in a machine word.
884  bool rangeFitsInWord(const APInt &Low, const APInt &High,
885  const DataLayout &DL) const {
886  // FIXME: Using the pointer type doesn't seem ideal.
887  uint64_t BW = DL.getIndexSizeInBits(0u);
888  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
889  return Range <= BW;
890  }
891 
892  /// Return true if lowering to a jump table is suitable for a set of case
893  /// clusters which may contain \p NumCases cases, \p Range range of values.
894  /// FIXME: This function check the maximum table size and density, but the
895  /// minimum size is not checked. It would be nice if the minimum size is
896  /// also combined within this function. Currently, the minimum size check is
897  /// performed in findJumpTable() in SelectionDAGBuiler and
898  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
899  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
900  uint64_t Range) const {
901  const bool OptForSize = SI->getParent()->getParent()->optForSize();
902  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
903  const unsigned MaxJumpTableSize =
904  OptForSize || getMaximumJumpTableSize() == 0
905  ? UINT_MAX
906  : getMaximumJumpTableSize();
907  // Check whether a range of clusters is dense enough for a jump table.
908  if (Range <= MaxJumpTableSize &&
909  (NumCases * 100 >= Range * MinDensity)) {
910  return true;
911  }
912  return false;
913  }
914 
915  /// Return true if lowering to a bit test is suitable for a set of case
916  /// clusters which contains \p NumDests unique destinations, \p Low and
917  /// \p High as its lowest and highest case values, and expects \p NumCmps
918  /// case value comparisons. Check if the number of destinations, comparison
919  /// metric, and range are all suitable.
920  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
921  const APInt &Low, const APInt &High,
922  const DataLayout &DL) const {
923  // FIXME: I don't think NumCmps is the correct metric: a single case and a
924  // range of cases both require only one branch to lower. Just looking at the
925  // number of clusters and destinations should be enough to decide whether to
926  // build bit tests.
927 
928  // To lower a range with bit tests, the range must fit the bitwidth of a
929  // machine word.
930  if (!rangeFitsInWord(Low, High, DL))
931  return false;
932 
933  // Decide whether it's profitable to lower this range with bit tests. Each
934  // destination requires a bit test and branch, and there is an overall range
935  // check branch. For a small number of clusters, separate comparisons might
936  // be cheaper, and for many destinations, splitting the range might be
937  // better.
938  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
939  (NumDests == 3 && NumCmps >= 6);
940  }
941 
942  /// Return true if the specified operation is illegal on this target or
943  /// unlikely to be made legal with custom lowering. This is used to help guide
944  /// high-level lowering decisions.
945  bool isOperationExpand(unsigned Op, EVT VT) const {
946  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
947  }
948 
949  /// Return true if the specified operation is legal on this target.
950  bool isOperationLegal(unsigned Op, EVT VT) const {
951  return (VT == MVT::Other || isTypeLegal(VT)) &&
952  getOperationAction(Op, VT) == Legal;
953  }
954 
955  /// Return how this load with extension should be treated: either it is legal,
956  /// needs to be promoted to a larger size, needs to be expanded to some other
957  /// code sequence, or the target has a custom expander for it.
959  EVT MemVT) const {
960  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
961  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
962  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
963  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
964  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
965  unsigned Shift = 4 * ExtType;
966  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
967  }
968 
969  /// Return true if the specified load with extension is legal on this target.
970  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
971  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
972  }
973 
974  /// Return true if the specified load with extension is legal or custom
975  /// on this target.
976  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
977  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
978  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
979  }
980 
981  /// Return how this store with truncation should be treated: either it is
982  /// legal, needs to be promoted to a larger size, needs to be expanded to some
983  /// other code sequence, or the target has a custom expander for it.
985  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
986  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
987  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
989  "Table isn't big enough!");
990  return TruncStoreActions[ValI][MemI];
991  }
992 
993  /// Return true if the specified store with truncation is legal on this
994  /// target.
995  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
996  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
997  }
998 
999  /// Return true if the specified store with truncation has solution on this
1000  /// target.
1001  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1002  return isTypeLegal(ValVT) &&
1003  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1004  getTruncStoreAction(ValVT, MemVT) == Custom);
1005  }
1006 
1007  /// Return how the indexed load should be treated: either it is legal, needs
1008  /// to be promoted to a larger size, needs to be expanded to some other code
1009  /// sequence, or the target has a custom expander for it.
1011  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1012  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1013  "Table isn't big enough!");
1014  unsigned Ty = (unsigned)VT.SimpleTy;
1015  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1016  }
1017 
1018  /// Return true if the specified indexed load is legal on this target.
1019  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1020  return VT.isSimple() &&
1021  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1022  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1023  }
1024 
1025  /// Return how the indexed store should be treated: either it is legal, needs
1026  /// to be promoted to a larger size, needs to be expanded to some other code
1027  /// sequence, or the target has a custom expander for it.
1029  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1030  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1031  "Table isn't big enough!");
1032  unsigned Ty = (unsigned)VT.SimpleTy;
1033  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1034  }
1035 
1036  /// Return true if the specified indexed load is legal on this target.
1037  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1038  return VT.isSimple() &&
1039  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1040  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1041  }
1042 
1043  /// Return how the condition code should be treated: either it is legal, needs
1044  /// to be expanded to some other code sequence, or the target has a custom
1045  /// expander for it.
1048  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1049  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1050  "Table isn't big enough!");
1051  // See setCondCodeAction for how this is encoded.
1052  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1053  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1054  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1055  assert(Action != Promote && "Can't promote condition code!");
1056  return Action;
1057  }
1058 
1059  /// Return true if the specified condition code is legal on this target.
1060  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1061  return getCondCodeAction(CC, VT) == Legal;
1062  }
1063 
1064  /// Return true if the specified condition code is legal or custom on this
1065  /// target.
1067  return getCondCodeAction(CC, VT) == Legal ||
1068  getCondCodeAction(CC, VT) == Custom;
1069  }
1070 
1071  /// If the action for this operation is to promote, this method returns the
1072  /// ValueType to promote to.
1073  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1074  assert(getOperationAction(Op, VT) == Promote &&
1075  "This operation isn't promoted!");
1076 
1077  // See if this has an explicit type specified.
1078  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1079  MVT::SimpleValueType>::const_iterator PTTI =
1080  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1081  if (PTTI != PromoteToType.end()) return PTTI->second;
1082 
1083  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1084  "Cannot autopromote this type, add it with AddPromotedToType.");
1085 
1086  MVT NVT = VT;
1087  do {
1088  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1089  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1090  "Didn't find type to promote to!");
1091  } while (!isTypeLegal(NVT) ||
1092  getOperationAction(Op, NVT) == Promote);
1093  return NVT;
1094  }
1095 
1096  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1097  /// operations except for the pointer size. If AllowUnknown is true, this
1098  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1099  /// otherwise it will assert.
1101  bool AllowUnknown = false) const {
1102  // Lower scalar pointers to native pointer types.
1103  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1104  return getPointerTy(DL, PTy->getAddressSpace());
1105 
1106  if (Ty->isVectorTy()) {
1107  VectorType *VTy = cast<VectorType>(Ty);
1108  Type *Elm = VTy->getElementType();
1109  // Lower vectors of pointers to native pointer types.
1110  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1111  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1112  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1113  }
1114 
1115  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1116  VTy->getNumElements());
1117  }
1118  return EVT::getEVT(Ty, AllowUnknown);
1119  }
1120 
1121  /// Return the MVT corresponding to this LLVM type. See getValueType.
1123  bool AllowUnknown = false) const {
1124  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1125  }
1126 
1127  /// Return the desired alignment for ByVal or InAlloca aggregate function
1128  /// arguments in the caller parameter area. This is the actual alignment, not
1129  /// its logarithm.
1130  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1131 
1132  /// Return the type of registers that this ValueType will eventually require.
1134  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1135  return RegisterTypeForVT[VT.SimpleTy];
1136  }
1137 
1138  /// Return the type of registers that this ValueType will eventually require.
1139  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1140  if (VT.isSimple()) {
1141  assert((unsigned)VT.getSimpleVT().SimpleTy <
1142  array_lengthof(RegisterTypeForVT));
1143  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1144  }
1145  if (VT.isVector()) {
1146  EVT VT1;
1147  MVT RegisterVT;
1148  unsigned NumIntermediates;
1149  (void)getVectorTypeBreakdown(Context, VT, VT1,
1150  NumIntermediates, RegisterVT);
1151  return RegisterVT;
1152  }
1153  if (VT.isInteger()) {
1154  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1155  }
1156  llvm_unreachable("Unsupported extended type!");
1157  }
1158 
1159  /// Return the number of registers that this ValueType will eventually
1160  /// require.
1161  ///
1162  /// This is one for any types promoted to live in larger registers, but may be
1163  /// more than one for types (like i64) that are split into pieces. For types
1164  /// like i140, which are first promoted then expanded, it is the number of
1165  /// registers needed to hold all the bits of the original type. For an i140
1166  /// on a 32 bit machine this means 5 registers.
1167  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1168  if (VT.isSimple()) {
1169  assert((unsigned)VT.getSimpleVT().SimpleTy <
1170  array_lengthof(NumRegistersForVT));
1171  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1172  }
1173  if (VT.isVector()) {
1174  EVT VT1;
1175  MVT VT2;
1176  unsigned NumIntermediates;
1177  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1178  }
1179  if (VT.isInteger()) {
1180  unsigned BitWidth = VT.getSizeInBits();
1181  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1182  return (BitWidth + RegWidth - 1) / RegWidth;
1183  }
1184  llvm_unreachable("Unsupported extended type!");
1185  }
1186 
1187  /// Certain combinations of ABIs, Targets and features require that types
1188  /// are legal for some operations and not for other operations.
1189  /// For MIPS all vector types must be passed through the integer register set.
1191  CallingConv::ID CC, EVT VT) const {
1192  return getRegisterType(Context, VT);
1193  }
1194 
1195  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1196  /// this occurs when a vector type is used, as vector are passed through the
1197  /// integer register set.
1198  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1199  CallingConv::ID CC,
1200  EVT VT) const {
1201  return getNumRegisters(Context, VT);
1202  }
1203 
1204  /// Certain targets have context senstive alignment requirements, where one
1205  /// type has the alignment requirement of another type.
1206  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1207  DataLayout DL) const {
1208  return DL.getABITypeAlignment(ArgTy);
1209  }
1210 
1211  /// If true, then instruction selection should seek to shrink the FP constant
1212  /// of the specified type to a smaller type in order to save space and / or
1213  /// reduce runtime.
1214  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1215 
1216  /// Return true if it is profitable to reduce a load to a smaller type.
1217  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1219  EVT NewVT) const {
1220  // By default, assume that it is cheaper to extract a subvector from a wide
1221  // vector load rather than creating multiple narrow vector loads.
1222  if (NewVT.isVector() && !Load->hasOneUse())
1223  return false;
1224 
1225  return true;
1226  }
1227 
1228  /// When splitting a value of the specified type into parts, does the Lo
1229  /// or Hi part come first? This usually follows the endianness, except
1230  /// for ppcf128, where the Hi part always comes first.
1231  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1232  return DL.isBigEndian() || VT == MVT::ppcf128;
1233  }
1234 
1235  /// If true, the target has custom DAG combine transformations that it can
1236  /// perform for the specified node.
1238  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1239  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1240  }
1241 
1242  unsigned getGatherAllAliasesMaxDepth() const {
1243  return GatherAllAliasesMaxDepth;
1244  }
1245 
1246  /// Returns the size of the platform's va_list object.
1247  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1248  return getPointerTy(DL).getSizeInBits();
1249  }
1250 
1251  /// Get maximum # of store operations permitted for llvm.memset
1252  ///
1253  /// This function returns the maximum number of store operations permitted
1254  /// to replace a call to llvm.memset. The value is set by the target at the
1255  /// performance threshold for such a replacement. If OptSize is true,
1256  /// return the limit for functions that have OptSize attribute.
1257  unsigned getMaxStoresPerMemset(bool OptSize) const {
1258  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1259  }
1260 
1261  /// Get maximum # of store operations permitted for llvm.memcpy
1262  ///
1263  /// This function returns the maximum number of store operations permitted
1264  /// to replace a call to llvm.memcpy. The value is set by the target at the
1265  /// performance threshold for such a replacement. If OptSize is true,
1266  /// return the limit for functions that have OptSize attribute.
1267  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1268  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1269  }
1270 
1271  /// \brief Get maximum # of store operations to be glued together
1272  ///
1273  /// This function returns the maximum number of store operations permitted
1274  /// to glue together during lowering of llvm.memcpy. The value is set by
1275  // the target at the performance threshold for such a replacement.
1276  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1277  return MaxGluedStoresPerMemcpy;
1278  }
1279 
1280  /// Get maximum # of load operations permitted for memcmp
1281  ///
1282  /// This function returns the maximum number of load operations permitted
1283  /// to replace a call to memcmp. The value is set by the target at the
1284  /// performance threshold for such a replacement. If OptSize is true,
1285  /// return the limit for functions that have OptSize attribute.
1286  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1287  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1288  }
1289 
1290  /// For memcmp expansion when the memcmp result is only compared equal or
1291  /// not-equal to 0, allow up to this number of load pairs per block. As an
1292  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1293  /// a0 = load2bytes &a[0]
1294  /// b0 = load2bytes &b[0]
1295  /// a2 = load1byte &a[2]
1296  /// b2 = load1byte &b[2]
1297  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1298  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1299  return 1;
1300  }
1301 
1302  /// Get maximum # of store operations permitted for llvm.memmove
1303  ///
1304  /// This function returns the maximum number of store operations permitted
1305  /// to replace a call to llvm.memmove. The value is set by the target at the
1306  /// performance threshold for such a replacement. If OptSize is true,
1307  /// return the limit for functions that have OptSize attribute.
1308  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1309  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1310  }
1311 
1312  /// Determine if the target supports unaligned memory accesses.
1313  ///
1314  /// This function returns true if the target allows unaligned memory accesses
1315  /// of the specified type in the given address space. If true, it also returns
1316  /// whether the unaligned memory access is "fast" in the last argument by
1317  /// reference. This is used, for example, in situations where an array
1318  /// copy/move/set is converted to a sequence of store operations. Its use
1319  /// helps to ensure that such replacements don't generate code that causes an
1320  /// alignment error (trap) on the target machine.
1322  unsigned AddrSpace = 0,
1323  unsigned Align = 1,
1324  bool * /*Fast*/ = nullptr) const {
1325  return false;
1326  }
1327 
1328  /// Return true if the target supports a memory access of this type for the
1329  /// given address space and alignment. If the access is allowed, the optional
1330  /// final parameter returns if the access is also fast (as defined by the
1331  /// target).
1332  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1333  unsigned AddrSpace = 0, unsigned Alignment = 1,
1334  bool *Fast = nullptr) const;
1335 
1336  /// Returns the target specific optimal type for load and store operations as
1337  /// a result of memset, memcpy, and memmove lowering.
1338  ///
1339  /// If DstAlign is zero that means it's safe to destination alignment can
1340  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1341  /// a need to check it against alignment requirement, probably because the
1342  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1343  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1344  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1345  /// does not need to be loaded. It returns EVT::Other if the type should be
1346  /// determined using generic target-independent logic.
1347  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1348  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1349  bool /*IsMemset*/,
1350  bool /*ZeroMemset*/,
1351  bool /*MemcpyStrSrc*/,
1352  MachineFunction &/*MF*/) const {
1353  return MVT::Other;
1354  }
1355 
1356  /// Returns true if it's safe to use load / store of the specified type to
1357  /// expand memcpy / memset inline.
1358  ///
1359  /// This is mostly true for all types except for some special cases. For
1360  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1361  /// fstpl which also does type conversion. Note the specified type doesn't
1362  /// have to be legal as the hook is used before type legalization.
1363  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1364 
1365  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1366  bool usesUnderscoreSetJmp() const {
1367  return UseUnderscoreSetJmp;
1368  }
1369 
1370  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1371  bool usesUnderscoreLongJmp() const {
1372  return UseUnderscoreLongJmp;
1373  }
1374 
1375  /// Return lower limit for number of blocks in a jump table.
1376  virtual unsigned getMinimumJumpTableEntries() const;
1377 
1378  /// Return lower limit of the density in a jump table.
1379  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1380 
1381  /// Return upper limit for number of entries in a jump table.
1382  /// Zero if no limit.
1383  unsigned getMaximumJumpTableSize() const;
1384 
1385  virtual bool isJumpTableRelative() const {
1386  return TM.isPositionIndependent();
1387  }
1388 
1389  /// If a physical register, this specifies the register that
1390  /// llvm.savestack/llvm.restorestack should save and restore.
1392  return StackPointerRegisterToSaveRestore;
1393  }
1394 
1395  /// If a physical register, this returns the register that receives the
1396  /// exception address on entry to an EH pad.
1397  virtual unsigned
1398  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1399  // 0 is guaranteed to be the NoRegister value on all targets
1400  return 0;
1401  }
1402 
1403  /// If a physical register, this returns the register that receives the
1404  /// exception typeid on entry to a landing pad.
1405  virtual unsigned
1406  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1407  // 0 is guaranteed to be the NoRegister value on all targets
1408  return 0;
1409  }
1410 
1411  virtual bool needsFixedCatchObjects() const {
1412  report_fatal_error("Funclet EH is not implemented for this target");
1413  }
1414 
1415  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1416  /// 200)
1417  unsigned getJumpBufSize() const {
1418  return JumpBufSize;
1419  }
1420 
1421  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1422  /// is 0)
1423  unsigned getJumpBufAlignment() const {
1424  return JumpBufAlignment;
1425  }
1426 
1427  /// Return the minimum stack alignment of an argument.
1428  unsigned getMinStackArgumentAlignment() const {
1429  return MinStackArgumentAlignment;
1430  }
1431 
1432  /// Return the minimum function alignment.
1433  unsigned getMinFunctionAlignment() const {
1434  return MinFunctionAlignment;
1435  }
1436 
1437  /// Return the preferred function alignment.
1438  unsigned getPrefFunctionAlignment() const {
1439  return PrefFunctionAlignment;
1440  }
1441 
1442  /// Return the preferred loop alignment.
1443  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1444  return PrefLoopAlignment;
1445  }
1446 
1447  /// Should loops be aligned even when the function is marked OptSize (but not
1448  /// MinSize).
1449  virtual bool alignLoopsWithOptSize() const {
1450  return false;
1451  }
1452 
1453  /// If the target has a standard location for the stack protector guard,
1454  /// returns the address of that location. Otherwise, returns nullptr.
1455  /// DEPRECATED: please override useLoadStackGuardNode and customize
1456  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1457  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1458 
1459  /// Inserts necessary declarations for SSP (stack protection) purpose.
1460  /// Should be used only when getIRStackGuard returns nullptr.
1461  virtual void insertSSPDeclarations(Module &M) const;
1462 
1463  /// Return the variable that's previously inserted by insertSSPDeclarations,
1464  /// if any, otherwise return nullptr. Should be used only when
1465  /// getIRStackGuard returns nullptr.
1466  virtual Value *getSDagStackGuard(const Module &M) const;
1467 
1468  /// If this function returns true, stack protection checks should XOR the
1469  /// frame pointer (or whichever pointer is used to address locals) into the
1470  /// stack guard value before checking it. getIRStackGuard must return nullptr
1471  /// if this returns true.
1472  virtual bool useStackGuardXorFP() const { return false; }
1473 
1474  /// If the target has a standard stack protection check function that
1475  /// performs validation and error handling, returns the function. Otherwise,
1476  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1477  /// Should be used only when getIRStackGuard returns nullptr.
1478  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1479 
1480 protected:
1481  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1482  bool UseTLS) const;
1483 
1484 public:
1485  /// Returns the target-specific address of the unsafe stack pointer.
1486  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1487 
1488  /// Returns the name of the symbol used to emit stack probes or the empty
1489  /// string if not applicable.
1491  return "";
1492  }
1493 
1494  /// Returns true if a cast between SrcAS and DestAS is a noop.
1495  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1496  return false;
1497  }
1498 
1499  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1500  /// are happy to sink it into basic blocks.
1501  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1502  return isNoopAddrSpaceCast(SrcAS, DestAS);
1503  }
1504 
1505  /// Return true if the pointer arguments to CI should be aligned by aligning
1506  /// the object whose address is being passed. If so then MinSize is set to the
1507  /// minimum size the object must be to be aligned and PrefAlign is set to the
1508  /// preferred alignment.
1509  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1510  unsigned & /*PrefAlign*/) const {
1511  return false;
1512  }
1513 
1514  //===--------------------------------------------------------------------===//
1515  /// \name Helpers for TargetTransformInfo implementations
1516  /// @{
1517 
1518  /// Get the ISD node that corresponds to the Instruction class opcode.
1519  int InstructionOpcodeToISD(unsigned Opcode) const;
1520 
1521  /// Estimate the cost of type-legalization and the legalized type.
1522  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1523  Type *Ty) const;
1524 
1525  /// @}
1526 
1527  //===--------------------------------------------------------------------===//
1528  /// \name Helpers for atomic expansion.
1529  /// @{
1530 
1531  /// Returns the maximum atomic operation size (in bits) supported by
1532  /// the backend. Atomic operations greater than this size (as well
1533  /// as ones that are not naturally aligned), will be expanded by
1534  /// AtomicExpandPass into an __atomic_* library call.
1536  return MaxAtomicSizeInBitsSupported;
1537  }
1538 
1539  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1540  /// the backend supports. Any smaller operations are widened in
1541  /// AtomicExpandPass.
1542  ///
1543  /// Note that *unlike* operations above the maximum size, atomic ops
1544  /// are still natively supported below the minimum; they just
1545  /// require a more complex expansion.
1546  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1547 
1548  /// Whether the target supports unaligned atomic operations.
1549  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1550 
1551  /// Whether AtomicExpandPass should automatically insert fences and reduce
1552  /// ordering for this atomic. This should be true for most architectures with
1553  /// weak memory ordering. Defaults to false.
1554  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1555  return false;
1556  }
1557 
1558  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1559  /// corresponding pointee type. This may entail some non-trivial operations to
1560  /// truncate or reconstruct types that will be illegal in the backend. See
1561  /// ARMISelLowering for an example implementation.
1562  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1563  AtomicOrdering Ord) const {
1564  llvm_unreachable("Load linked unimplemented on this target");
1565  }
1566 
1567  /// Perform a store-conditional operation to Addr. Return the status of the
1568  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1569  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1570  Value *Addr, AtomicOrdering Ord) const {
1571  llvm_unreachable("Store conditional unimplemented on this target");
1572  }
1573 
1574  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1575  /// represents the core LL/SC loop which will be lowered at a late stage by
1576  /// the backend.
1578  AtomicRMWInst *AI,
1579  Value *AlignedAddr, Value *Incr,
1580  Value *Mask, Value *ShiftAmt,
1581  AtomicOrdering Ord) const {
1582  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1583  }
1584 
1585  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1586  /// represents the core LL/SC loop which will be lowered at a late stage by
1587  /// the backend.
1589  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1590  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1591  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1592  }
1593 
1594  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1595  /// It is called by AtomicExpandPass before expanding an
1596  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1597  /// if shouldInsertFencesForAtomic returns true.
1598  ///
1599  /// Inst is the original atomic instruction, prior to other expansions that
1600  /// may be performed.
1601  ///
1602  /// This function should either return a nullptr, or a pointer to an IR-level
1603  /// Instruction*. Even complex fence sequences can be represented by a
1604  /// single Instruction* through an intrinsic to be lowered later.
1605  /// Backends should override this method to produce target-specific intrinsic
1606  /// for their fences.
1607  /// FIXME: Please note that the default implementation here in terms of
1608  /// IR-level fences exists for historical/compatibility reasons and is
1609  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1610  /// consistency. For example, consider the following example:
1611  /// atomic<int> x = y = 0;
1612  /// int r1, r2, r3, r4;
1613  /// Thread 0:
1614  /// x.store(1);
1615  /// Thread 1:
1616  /// y.store(1);
1617  /// Thread 2:
1618  /// r1 = x.load();
1619  /// r2 = y.load();
1620  /// Thread 3:
1621  /// r3 = y.load();
1622  /// r4 = x.load();
1623  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1624  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1625  /// IR-level fences can prevent it.
1626  /// @{
1628  AtomicOrdering Ord) const {
1629  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1630  return Builder.CreateFence(Ord);
1631  else
1632  return nullptr;
1633  }
1634 
1636  Instruction *Inst,
1637  AtomicOrdering Ord) const {
1638  if (isAcquireOrStronger(Ord))
1639  return Builder.CreateFence(Ord);
1640  else
1641  return nullptr;
1642  }
1643  /// @}
1644 
1645  // Emits code that executes when the comparison result in the ll/sc
1646  // expansion of a cmpxchg instruction is such that the store-conditional will
1647  // not execute. This makes it possible to balance out the load-linked with
1648  // a dedicated instruction, if desired.
1649  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1650  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1651  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1652 
1653  /// Returns true if the given (atomic) store should be expanded by the
1654  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1656  return false;
1657  }
1658 
1659  /// Returns true if arguments should be sign-extended in lib calls.
1660  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1661  return IsSigned;
1662  }
1663 
1664  /// Returns how the given (atomic) load should be expanded by the
1665  /// IR-level AtomicExpand pass.
1668  }
1669 
1670  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1671  /// AtomicExpand pass.
1672  virtual AtomicExpansionKind
1675  }
1676 
1677  /// Returns how the IR-level AtomicExpand pass should expand the given
1678  /// AtomicRMW, if at all. Default is to never expand.
1681  }
1682 
1683  /// On some platforms, an AtomicRMW that never actually modifies the value
1684  /// (such as fetch_add of 0) can be turned into a fence followed by an
1685  /// atomic load. This may sound useless, but it makes it possible for the
1686  /// processor to keep the cacheline shared, dramatically improving
1687  /// performance. And such idempotent RMWs are useful for implementing some
1688  /// kinds of locks, see for example (justification + benchmarks):
1689  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1690  /// This method tries doing that transformation, returning the atomic load if
1691  /// it succeeds, and nullptr otherwise.
1692  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1693  /// another round of expansion.
1694  virtual LoadInst *
1696  return nullptr;
1697  }
1698 
1699  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1700  /// SIGN_EXTEND, or ANY_EXTEND).
1702  return ISD::ZERO_EXTEND;
1703  }
1704 
1705  /// @}
1706 
1707  /// Returns true if we should normalize
1708  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1709  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1710  /// that it saves us from materializing N0 and N1 in an integer register.
1711  /// Targets that are able to perform and/or on flags should return false here.
1713  EVT VT) const {
1714  // If a target has multiple condition registers, then it likely has logical
1715  // operations on those registers.
1716  if (hasMultipleConditionRegisters())
1717  return false;
1718  // Only do the transform if the value won't be split into multiple
1719  // registers.
1720  LegalizeTypeAction Action = getTypeAction(Context, VT);
1721  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1722  Action != TypeSplitVector;
1723  }
1724 
1725  /// Return true if a select of constants (select Cond, C1, C2) should be
1726  /// transformed into simple math ops with the condition value. For example:
1727  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1728  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1729  return false;
1730  }
1731 
1732  /// Return true if it is profitable to transform an integer
1733  /// multiplication-by-constant into simpler operations like shifts and adds.
1734  /// This may be true if the target does not directly support the
1735  /// multiplication operation for the specified type or the sequence of simpler
1736  /// ops is faster than the multiply.
1737  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1738  return false;
1739  }
1740 
1741  //===--------------------------------------------------------------------===//
1742  // TargetLowering Configuration Methods - These methods should be invoked by
1743  // the derived class constructor to configure this object for the target.
1744  //
1745 protected:
1746  /// Specify how the target extends the result of integer and floating point
1747  /// boolean values from i1 to a wider type. See getBooleanContents.
1749  BooleanContents = Ty;
1750  BooleanFloatContents = Ty;
1751  }
1752 
1753  /// Specify how the target extends the result of integer and floating point
1754  /// boolean values from i1 to a wider type. See getBooleanContents.
1756  BooleanContents = IntTy;
1757  BooleanFloatContents = FloatTy;
1758  }
1759 
1760  /// Specify how the target extends the result of a vector boolean value from a
1761  /// vector of i1 to a wider type. See getBooleanContents.
1763  BooleanVectorContents = Ty;
1764  }
1765 
1766  /// Specify the target scheduling preference.
1768  SchedPreferenceInfo = Pref;
1769  }
1770 
1771  /// Indicate whether this target prefers to use _setjmp to implement
1772  /// llvm.setjmp or the version without _. Defaults to false.
1773  void setUseUnderscoreSetJmp(bool Val) {
1774  UseUnderscoreSetJmp = Val;
1775  }
1776 
1777  /// Indicate whether this target prefers to use _longjmp to implement
1778  /// llvm.longjmp or the version without _. Defaults to false.
1779  void setUseUnderscoreLongJmp(bool Val) {
1780  UseUnderscoreLongJmp = Val;
1781  }
1782 
1783  /// Indicate the minimum number of blocks to generate jump tables.
1784  void setMinimumJumpTableEntries(unsigned Val);
1785 
1786  /// Indicate the maximum number of entries in jump tables.
1787  /// Set to zero to generate unlimited jump tables.
1788  void setMaximumJumpTableSize(unsigned);
1789 
1790  /// If set to a physical register, this specifies the register that
1791  /// llvm.savestack/llvm.restorestack should save and restore.
1793  StackPointerRegisterToSaveRestore = R;
1794  }
1795 
1796  /// Tells the code generator that the target has multiple (allocatable)
1797  /// condition registers that can be used to store the results of comparisons
1798  /// for use by selects and conditional branches. With multiple condition
1799  /// registers, the code generator will not aggressively sink comparisons into
1800  /// the blocks of their users.
1801  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1802  HasMultipleConditionRegisters = hasManyRegs;
1803  }
1804 
1805  /// Tells the code generator that the target has BitExtract instructions.
1806  /// The code generator will aggressively sink "shift"s into the blocks of
1807  /// their users if the users will generate "and" instructions which can be
1808  /// combined with "shift" to BitExtract instructions.
1809  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1810  HasExtractBitsInsn = hasExtractInsn;
1811  }
1812 
1813  /// Tells the code generator not to expand logic operations on comparison
1814  /// predicates into separate sequences that increase the amount of flow
1815  /// control.
1816  void setJumpIsExpensive(bool isExpensive = true);
1817 
1818  /// Tells the code generator that this target supports floating point
1819  /// exceptions and cares about preserving floating point exception behavior.
1820  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1821  HasFloatingPointExceptions = FPExceptions;
1822  }
1823 
1824  /// Tells the code generator which bitwidths to bypass.
1825  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1826  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1827  }
1828 
1829  /// Add the specified register class as an available regclass for the
1830  /// specified value type. This indicates the selector can handle values of
1831  /// that class natively.
1833  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1834  RegClassForVT[VT.SimpleTy] = RC;
1835  }
1836 
1837  /// Return the largest legal super-reg register class of the register class
1838  /// for the specified type and its associated "cost".
1839  virtual std::pair<const TargetRegisterClass *, uint8_t>
1840  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1841 
1842  /// Once all of the register classes are added, this allows us to compute
1843  /// derived properties we expose.
1844  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1845 
1846  /// Indicate that the specified operation does not work with the specified
1847  /// type and indicate what to do about it. Note that VT may refer to either
1848  /// the type of a result or that of an operand of Op.
1849  void setOperationAction(unsigned Op, MVT VT,
1850  LegalizeAction Action) {
1851  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1852  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1853  }
1854 
1855  /// Indicate that the specified load with extension does not work with the
1856  /// specified type and indicate what to do about it.
1857  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1858  LegalizeAction Action) {
1859  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1860  MemVT.isValid() && "Table isn't big enough!");
1861  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1862  unsigned Shift = 4 * ExtType;
1863  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1864  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1865  }
1866 
1867  /// Indicate that the specified truncating store does not work with the
1868  /// specified type and indicate what to do about it.
1869  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1870  LegalizeAction Action) {
1871  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1872  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1873  }
1874 
1875  /// Indicate that the specified indexed load does or does not work with the
1876  /// specified type and indicate what to do abort it.
1877  ///
1878  /// NOTE: All indexed mode loads are initialized to Expand in
1879  /// TargetLowering.cpp
1880  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1881  LegalizeAction Action) {
1882  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1883  (unsigned)Action < 0xf && "Table isn't big enough!");
1884  // Load action are kept in the upper half.
1885  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1886  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1887  }
1888 
1889  /// Indicate that the specified indexed store does or does not work with the
1890  /// specified type and indicate what to do about it.
1891  ///
1892  /// NOTE: All indexed mode stores are initialized to Expand in
1893  /// TargetLowering.cpp
1894  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1895  LegalizeAction Action) {
1896  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1897  (unsigned)Action < 0xf && "Table isn't big enough!");
1898  // Store action are kept in the lower half.
1899  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1900  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1901  }
1902 
1903  /// Indicate that the specified condition code is or isn't supported on the
1904  /// target and indicate what to do about it.
1906  LegalizeAction Action) {
1907  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1908  "Table isn't big enough!");
1909  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1910  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1911  /// value and the upper 29 bits index into the second dimension of the array
1912  /// to select what 32-bit value to use.
1913  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1914  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1915  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1916  }
1917 
1918  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1919  /// to trying a larger integer/fp until it can find one that works. If that
1920  /// default is insufficient, this method can be used by the target to override
1921  /// the default.
1922  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1923  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1924  }
1925 
1926  /// Convenience method to set an operation to Promote and specify the type
1927  /// in a single call.
1928  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1929  setOperationAction(Opc, OrigVT, Promote);
1930  AddPromotedToType(Opc, OrigVT, DestVT);
1931  }
1932 
1933  /// Targets should invoke this method for each target independent node that
1934  /// they want to provide a custom DAG combiner for by implementing the
1935  /// PerformDAGCombine virtual method.
1937  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1938  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1939  }
1940 
1941  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1942  void setJumpBufSize(unsigned Size) {
1943  JumpBufSize = Size;
1944  }
1945 
1946  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1947  /// 0
1948  void setJumpBufAlignment(unsigned Align) {
1949  JumpBufAlignment = Align;
1950  }
1951 
1952  /// Set the target's minimum function alignment (in log2(bytes))
1954  MinFunctionAlignment = Align;
1955  }
1956 
1957  /// Set the target's preferred function alignment. This should be set if
1958  /// there is a performance benefit to higher-than-minimum alignment (in
1959  /// log2(bytes))
1961  PrefFunctionAlignment = Align;
1962  }
1963 
1964  /// Set the target's preferred loop alignment. Default alignment is zero, it
1965  /// means the target does not care about loop alignment. The alignment is
1966  /// specified in log2(bytes). The target may also override
1967  /// getPrefLoopAlignment to provide per-loop values.
1968  void setPrefLoopAlignment(unsigned Align) {
1969  PrefLoopAlignment = Align;
1970  }
1971 
1972  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1974  MinStackArgumentAlignment = Align;
1975  }
1976 
1977  /// Set the maximum atomic operation size supported by the
1978  /// backend. Atomic operations greater than this size (as well as
1979  /// ones that are not naturally aligned), will be expanded by
1980  /// AtomicExpandPass into an __atomic_* library call.
1981  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1982  MaxAtomicSizeInBitsSupported = SizeInBits;
1983  }
1984 
1985  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1986  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1987  MinCmpXchgSizeInBits = SizeInBits;
1988  }
1989 
1990  /// Sets whether unaligned atomic operations are supported.
1991  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1992  SupportsUnalignedAtomics = UnalignedSupported;
1993  }
1994 
1995 public:
1996  //===--------------------------------------------------------------------===//
1997  // Addressing mode description hooks (used by LSR etc).
1998  //
1999 
2000  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2001  /// instructions reading the address. This allows as much computation as
2002  /// possible to be done in the address mode for that operand. This hook lets
2003  /// targets also pass back when this should be done on intrinsics which
2004  /// load/store.
2005  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2006  SmallVectorImpl<Value*> &/*Ops*/,
2007  Type *&/*AccessTy*/) const {
2008  return false;
2009  }
2010 
2011  /// This represents an addressing mode of:
2012  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2013  /// If BaseGV is null, there is no BaseGV.
2014  /// If BaseOffs is zero, there is no base offset.
2015  /// If HasBaseReg is false, there is no base register.
2016  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2017  /// no scale.
2018  struct AddrMode {
2019  GlobalValue *BaseGV = nullptr;
2020  int64_t BaseOffs = 0;
2021  bool HasBaseReg = false;
2022  int64_t Scale = 0;
2023  AddrMode() = default;
2024  };
2025 
2026  /// Return true if the addressing mode represented by AM is legal for this
2027  /// target, for a load/store of the specified type.
2028  ///
2029  /// The type may be VoidTy, in which case only return true if the addressing
2030  /// mode is legal for a load/store of any legal type. TODO: Handle
2031  /// pre/postinc as well.
2032  ///
2033  /// If the address space cannot be determined, it will be -1.
2034  ///
2035  /// TODO: Remove default argument
2036  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2037  Type *Ty, unsigned AddrSpace,
2038  Instruction *I = nullptr) const;
2039 
2040  /// Return the cost of the scaling factor used in the addressing mode
2041  /// represented by AM for this target, for a load/store of the specified type.
2042  ///
2043  /// If the AM is supported, the return value must be >= 0.
2044  /// If the AM is not supported, it returns a negative value.
2045  /// TODO: Handle pre/postinc as well.
2046  /// TODO: Remove default argument
2047  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2048  Type *Ty, unsigned AS = 0) const {
2049  // Default: assume that any scaling factor used in a legal AM is free.
2050  if (isLegalAddressingMode(DL, AM, Ty, AS))
2051  return 0;
2052  return -1;
2053  }
2054 
2055  /// Return true if the specified immediate is legal icmp immediate, that is
2056  /// the target has icmp instructions which can compare a register against the
2057  /// immediate without having to materialize the immediate into a register.
2058  virtual bool isLegalICmpImmediate(int64_t) const {
2059  return true;
2060  }
2061 
2062  /// Return true if the specified immediate is legal add immediate, that is the
2063  /// target has add instructions which can add a register with the immediate
2064  /// without having to materialize the immediate into a register.
2065  virtual bool isLegalAddImmediate(int64_t) const {
2066  return true;
2067  }
2068 
2069  /// Return true if the specified immediate is legal for the value input of a
2070  /// store instruction.
2071  virtual bool isLegalStoreImmediate(int64_t Value) const {
2072  // Default implementation assumes that at least 0 works since it is likely
2073  // that a zero register exists or a zero immediate is allowed.
2074  return Value == 0;
2075  }
2076 
2077  /// Return true if it's significantly cheaper to shift a vector by a uniform
2078  /// scalar than by an amount which will vary across each lane. On x86, for
2079  /// example, there is a "psllw" instruction for the former case, but no simple
2080  /// instruction for a general "a << b" operation on vectors.
2081  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2082  return false;
2083  }
2084 
2085  /// Returns true if the opcode is a commutative binary operation.
2086  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2087  // FIXME: This should get its info from the td file.
2088  switch (Opcode) {
2089  case ISD::ADD:
2090  case ISD::SMIN:
2091  case ISD::SMAX:
2092  case ISD::UMIN:
2093  case ISD::UMAX:
2094  case ISD::MUL:
2095  case ISD::MULHU:
2096  case ISD::MULHS:
2097  case ISD::SMUL_LOHI:
2098  case ISD::UMUL_LOHI:
2099  case ISD::FADD:
2100  case ISD::FMUL:
2101  case ISD::AND:
2102  case ISD::OR:
2103  case ISD::XOR:
2104  case ISD::SADDO:
2105  case ISD::UADDO:
2106  case ISD::ADDC:
2107  case ISD::ADDE:
2108  case ISD::FMINNUM:
2109  case ISD::FMAXNUM:
2110  case ISD::FMINIMUM:
2111  case ISD::FMAXIMUM:
2112  return true;
2113  default: return false;
2114  }
2115  }
2116 
2117  /// Return true if it's free to truncate a value of type FromTy to type
2118  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2119  /// by referencing its sub-register AX.
2120  /// Targets must return false when FromTy <= ToTy.
2121  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2122  return false;
2123  }
2124 
2125  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2126  /// whether a call is in tail position. Typically this means that both results
2127  /// would be assigned to the same register or stack slot, but it could mean
2128  /// the target performs adequate checks of its own before proceeding with the
2129  /// tail call. Targets must return false when FromTy <= ToTy.
2130  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2131  return false;
2132  }
2133 
2134  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2135  return false;
2136  }
2137 
2138  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2139 
2140  /// Return true if the extension represented by \p I is free.
2141  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2142  /// this method can use the context provided by \p I to decide
2143  /// whether or not \p I is free.
2144  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2145  /// In other words, if is[Z|FP]Free returns true, then this method
2146  /// returns true as well. The converse is not true.
2147  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2148  /// \pre \p I must be a sign, zero, or fp extension.
2149  bool isExtFree(const Instruction *I) const {
2150  switch (I->getOpcode()) {
2151  case Instruction::FPExt:
2152  if (isFPExtFree(EVT::getEVT(I->getType()),
2153  EVT::getEVT(I->getOperand(0)->getType())))
2154  return true;
2155  break;
2156  case Instruction::ZExt:
2157  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2158  return true;
2159  break;
2160  case Instruction::SExt:
2161  break;
2162  default:
2163  llvm_unreachable("Instruction is not an extension");
2164  }
2165  return isExtFreeImpl(I);
2166  }
2167 
2168  /// Return true if \p Load and \p Ext can form an ExtLoad.
2169  /// For example, in AArch64
2170  /// %L = load i8, i8* %ptr
2171  /// %E = zext i8 %L to i32
2172  /// can be lowered into one load instruction
2173  /// ldrb w0, [x0]
2174  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2175  const DataLayout &DL) const {
2176  EVT VT = getValueType(DL, Ext->getType());
2177  EVT LoadVT = getValueType(DL, Load->getType());
2178 
2179  // If the load has other users and the truncate is not free, the ext
2180  // probably isn't free.
2181  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2182  !isTruncateFree(Ext->getType(), Load->getType()))
2183  return false;
2184 
2185  // Check whether the target supports casts folded into loads.
2186  unsigned LType;
2187  if (isa<ZExtInst>(Ext))
2188  LType = ISD::ZEXTLOAD;
2189  else {
2190  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2191  LType = ISD::SEXTLOAD;
2192  }
2193 
2194  return isLoadExtLegal(LType, VT, LoadVT);
2195  }
2196 
2197  /// Return true if any actual instruction that defines a value of type FromTy
2198  /// implicitly zero-extends the value to ToTy in the result register.
2199  ///
2200  /// The function should return true when it is likely that the truncate can
2201  /// be freely folded with an instruction defining a value of FromTy. If
2202  /// the defining instruction is unknown (because you're looking at a
2203  /// function argument, PHI, etc.) then the target may require an
2204  /// explicit truncate, which is not necessarily free, but this function
2205  /// does not deal with those cases.
2206  /// Targets must return false when FromTy >= ToTy.
2207  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2208  return false;
2209  }
2210 
2211  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2212  return false;
2213  }
2214 
2215  /// Return true if the target supplies and combines to a paired load
2216  /// two loaded values of type LoadedType next to each other in memory.
2217  /// RequiredAlignment gives the minimal alignment constraints that must be met
2218  /// to be able to select this paired load.
2219  ///
2220  /// This information is *not* used to generate actual paired loads, but it is
2221  /// used to generate a sequence of loads that is easier to combine into a
2222  /// paired load.
2223  /// For instance, something like this:
2224  /// a = load i64* addr
2225  /// b = trunc i64 a to i32
2226  /// c = lshr i64 a, 32
2227  /// d = trunc i64 c to i32
2228  /// will be optimized into:
2229  /// b = load i32* addr1
2230  /// d = load i32* addr2
2231  /// Where addr1 = addr2 +/- sizeof(i32).
2232  ///
2233  /// In other words, unless the target performs a post-isel load combining,
2234  /// this information should not be provided because it will generate more
2235  /// loads.
2236  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2237  unsigned & /*RequiredAlignment*/) const {
2238  return false;
2239  }
2240 
2241  /// Return true if the target has a vector blend instruction.
2242  virtual bool hasVectorBlend() const { return false; }
2243 
2244  /// Get the maximum supported factor for interleaved memory accesses.
2245  /// Default to be the minimum interleave factor: 2.
2246  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2247 
2248  /// Lower an interleaved load to target specific intrinsics. Return
2249  /// true on success.
2250  ///
2251  /// \p LI is the vector load instruction.
2252  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2253  /// \p Indices is the corresponding indices for each shufflevector.
2254  /// \p Factor is the interleave factor.
2255  virtual bool lowerInterleavedLoad(LoadInst *LI,
2257  ArrayRef<unsigned> Indices,
2258  unsigned Factor) const {
2259  return false;
2260  }
2261 
2262  /// Lower an interleaved store to target specific intrinsics. Return
2263  /// true on success.
2264  ///
2265  /// \p SI is the vector store instruction.
2266  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2267  /// \p Factor is the interleave factor.
2269  unsigned Factor) const {
2270  return false;
2271  }
2272 
2273  /// Return true if zero-extending the specific node Val to type VT2 is free
2274  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2275  /// because it's folded such as X86 zero-extending loads).
2276  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2277  return isZExtFree(Val.getValueType(), VT2);
2278  }
2279 
2280  /// Return true if an fpext operation is free (for instance, because
2281  /// single-precision floating-point numbers are implicitly extended to
2282  /// double-precision).
2283  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2284  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2285  "invalid fpext types");
2286  return false;
2287  }
2288 
2289  /// Return true if an fpext operation input to an \p Opcode operation is free
2290  /// (for instance, because half-precision floating-point numbers are
2291  /// implicitly extended to float-precision) for an FMA instruction.
2292  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2293  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2294  "invalid fpext types");
2295  return isFPExtFree(DestVT, SrcVT);
2296  }
2297 
2298  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2299  /// extend node) is profitable.
2300  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2301 
2302  /// Return true if an fneg operation is free to the point where it is never
2303  /// worthwhile to replace it with a bitwise operation.
2304  virtual bool isFNegFree(EVT VT) const {
2305  assert(VT.isFloatingPoint());
2306  return false;
2307  }
2308 
2309  /// Return true if an fabs operation is free to the point where it is never
2310  /// worthwhile to replace it with a bitwise operation.
2311  virtual bool isFAbsFree(EVT VT) const {
2312  assert(VT.isFloatingPoint());
2313  return false;
2314  }
2315 
2316  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2317  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2318  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2319  ///
2320  /// NOTE: This may be called before legalization on types for which FMAs are
2321  /// not legal, but should return true if those types will eventually legalize
2322  /// to types that support FMAs. After legalization, it will only be called on
2323  /// types that support FMAs (via Legal or Custom actions)
2324  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2325  return false;
2326  }
2327 
2328  /// Return true if it's profitable to narrow operations of type VT1 to
2329  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2330  /// i32 to i16.
2331  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2332  return false;
2333  }
2334 
2335  /// Return true if it is beneficial to convert a load of a constant to
2336  /// just the constant itself.
2337  /// On some targets it might be more efficient to use a combination of
2338  /// arithmetic instructions to materialize the constant instead of loading it
2339  /// from a constant pool.
2340  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2341  Type *Ty) const {
2342  return false;
2343  }
2344 
2345  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2346  /// from this source type with this index. This is needed because
2347  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2348  /// the first element, and only the target knows which lowering is cheap.
2349  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2350  unsigned Index) const {
2351  return false;
2352  }
2353 
2354  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2355  // even if the vector itself has multiple uses.
2356  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2357  return false;
2358  }
2359 
2360  // Return true if CodeGenPrepare should consider splitting large offset of a
2361  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2362  // same blocks of its users.
2363  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2364 
2365  //===--------------------------------------------------------------------===//
2366  // Runtime Library hooks
2367  //
2368 
2369  /// Rename the default libcall routine name for the specified libcall.
2370  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2371  LibcallRoutineNames[Call] = Name;
2372  }
2373 
2374  /// Get the libcall routine name for the specified libcall.
2375  const char *getLibcallName(RTLIB::Libcall Call) const {
2376  return LibcallRoutineNames[Call];
2377  }
2378 
2379  /// Override the default CondCode to be used to test the result of the
2380  /// comparison libcall against zero.
2382  CmpLibcallCCs[Call] = CC;
2383  }
2384 
2385  /// Get the CondCode that's to be used to test the result of the comparison
2386  /// libcall against zero.
2388  return CmpLibcallCCs[Call];
2389  }
2390 
2391  /// Set the CallingConv that should be used for the specified libcall.
2393  LibcallCallingConvs[Call] = CC;
2394  }
2395 
2396  /// Get the CallingConv that should be used for the specified libcall.
2398  return LibcallCallingConvs[Call];
2399  }
2400 
2401  /// Execute target specific actions to finalize target lowering.
2402  /// This is used to set extra flags in MachineFrameInformation and freezing
2403  /// the set of reserved registers.
2404  /// The default implementation just freezes the set of reserved registers.
2405  virtual void finalizeLowering(MachineFunction &MF) const;
2406 
2407 private:
2408  const TargetMachine &TM;
2409 
2410  /// Tells the code generator that the target has multiple (allocatable)
2411  /// condition registers that can be used to store the results of comparisons
2412  /// for use by selects and conditional branches. With multiple condition
2413  /// registers, the code generator will not aggressively sink comparisons into
2414  /// the blocks of their users.
2415  bool HasMultipleConditionRegisters;
2416 
2417  /// Tells the code generator that the target has BitExtract instructions.
2418  /// The code generator will aggressively sink "shift"s into the blocks of
2419  /// their users if the users will generate "and" instructions which can be
2420  /// combined with "shift" to BitExtract instructions.
2421  bool HasExtractBitsInsn;
2422 
2423  /// Tells the code generator to bypass slow divide or remainder
2424  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2425  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2426  /// div/rem when the operands are positive and less than 256.
2427  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2428 
2429  /// Tells the code generator that it shouldn't generate extra flow control
2430  /// instructions and should attempt to combine flow control instructions via
2431  /// predication.
2432  bool JumpIsExpensive;
2433 
2434  /// Whether the target supports or cares about preserving floating point
2435  /// exception behavior.
2436  bool HasFloatingPointExceptions;
2437 
2438  /// This target prefers to use _setjmp to implement llvm.setjmp.
2439  ///
2440  /// Defaults to false.
2441  bool UseUnderscoreSetJmp;
2442 
2443  /// This target prefers to use _longjmp to implement llvm.longjmp.
2444  ///
2445  /// Defaults to false.
2446  bool UseUnderscoreLongJmp;
2447 
2448  /// Information about the contents of the high-bits in boolean values held in
2449  /// a type wider than i1. See getBooleanContents.
2450  BooleanContent BooleanContents;
2451 
2452  /// Information about the contents of the high-bits in boolean values held in
2453  /// a type wider than i1. See getBooleanContents.
2454  BooleanContent BooleanFloatContents;
2455 
2456  /// Information about the contents of the high-bits in boolean vector values
2457  /// when the element type is wider than i1. See getBooleanContents.
2458  BooleanContent BooleanVectorContents;
2459 
2460  /// The target scheduling preference: shortest possible total cycles or lowest
2461  /// register usage.
2462  Sched::Preference SchedPreferenceInfo;
2463 
2464  /// The size, in bytes, of the target's jmp_buf buffers
2465  unsigned JumpBufSize;
2466 
2467  /// The alignment, in bytes, of the target's jmp_buf buffers
2468  unsigned JumpBufAlignment;
2469 
2470  /// The minimum alignment that any argument on the stack needs to have.
2471  unsigned MinStackArgumentAlignment;
2472 
2473  /// The minimum function alignment (used when optimizing for size, and to
2474  /// prevent explicitly provided alignment from leading to incorrect code).
2475  unsigned MinFunctionAlignment;
2476 
2477  /// The preferred function alignment (used when alignment unspecified and
2478  /// optimizing for speed).
2479  unsigned PrefFunctionAlignment;
2480 
2481  /// The preferred loop alignment.
2482  unsigned PrefLoopAlignment;
2483 
2484  /// Size in bits of the maximum atomics size the backend supports.
2485  /// Accesses larger than this will be expanded by AtomicExpandPass.
2486  unsigned MaxAtomicSizeInBitsSupported;
2487 
2488  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2489  /// backend supports.
2490  unsigned MinCmpXchgSizeInBits;
2491 
2492  /// This indicates if the target supports unaligned atomic operations.
2493  bool SupportsUnalignedAtomics;
2494 
2495  /// If set to a physical register, this specifies the register that
2496  /// llvm.savestack/llvm.restorestack should save and restore.
2497  unsigned StackPointerRegisterToSaveRestore;
2498 
2499  /// This indicates the default register class to use for each ValueType the
2500  /// target supports natively.
2501  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2502  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2503  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2504 
2505  /// This indicates the "representative" register class to use for each
2506  /// ValueType the target supports natively. This information is used by the
2507  /// scheduler to track register pressure. By default, the representative
2508  /// register class is the largest legal super-reg register class of the
2509  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2510  /// representative class would be GR32.
2511  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2512 
2513  /// This indicates the "cost" of the "representative" register class for each
2514  /// ValueType. The cost is used by the scheduler to approximate register
2515  /// pressure.
2516  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2517 
2518  /// For any value types we are promoting or expanding, this contains the value
2519  /// type that we are changing to. For Expanded types, this contains one step
2520  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2521  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2522  /// the same type (e.g. i32 -> i32).
2523  MVT TransformToType[MVT::LAST_VALUETYPE];
2524 
2525  /// For each operation and each value type, keep a LegalizeAction that
2526  /// indicates how instruction selection should deal with the operation. Most
2527  /// operations are Legal (aka, supported natively by the target), but
2528  /// operations that are not should be described. Note that operations on
2529  /// non-legal value types are not described here.
2531 
2532  /// For each load extension type and each value type, keep a LegalizeAction
2533  /// that indicates how instruction selection should deal with a load of a
2534  /// specific value type and extension type. Uses 4-bits to store the action
2535  /// for each of the 4 load ext types.
2536  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2537 
2538  /// For each value type pair keep a LegalizeAction that indicates whether a
2539  /// truncating store of a specific value type and truncating type is legal.
2541 
2542  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2543  /// that indicates how instruction selection should deal with the load /
2544  /// store.
2545  ///
2546  /// The first dimension is the value_type for the reference. The second
2547  /// dimension represents the various modes for load store.
2548  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2549 
2550  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2551  /// indicates how instruction selection should deal with the condition code.
2552  ///
2553  /// Because each CC action takes up 4 bits, we need to have the array size be
2554  /// large enough to fit all of the value types. This can be done by rounding
2555  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2556  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2557 
2558 protected:
2560 
2561 private:
2562  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2563 
2564  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2565  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2566  /// array.
2567  unsigned char
2568  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2569 
2570  /// For operations that must be promoted to a specific type, this holds the
2571  /// destination type. This map should be sparse, so don't hold it as an
2572  /// array.
2573  ///
2574  /// Targets add entries to this map with AddPromotedToType(..), clients access
2575  /// this with getTypeToPromoteTo(..).
2576  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2577  PromoteToType;
2578 
2579  /// Stores the name each libcall.
2580  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2581 
2582  /// The ISD::CondCode that should be used to test the result of each of the
2583  /// comparison libcall against zero.
2584  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2585 
2586  /// Stores the CallingConv that should be used for each libcall.
2587  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2588 
2589  /// Set default libcall names and calling conventions.
2590  void InitLibcalls(const Triple &TT);
2591 
2592 protected:
2593  /// Return true if the extension represented by \p I is free.
2594  /// \pre \p I is a sign, zero, or fp extension and
2595  /// is[Z|FP]ExtFree of the related types is not true.
2596  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2597 
2598  /// Depth that GatherAllAliases should should continue looking for chain
2599  /// dependencies when trying to find a more preferable chain. As an
2600  /// approximation, this should be more than the number of consecutive stores
2601  /// expected to be merged.
2603 
2604  /// Specify maximum number of store instructions per memset call.
2605  ///
2606  /// When lowering \@llvm.memset this field specifies the maximum number of
2607  /// store operations that may be substituted for the call to memset. Targets
2608  /// must set this value based on the cost threshold for that target. Targets
2609  /// should assume that the memset will be done using as many of the largest
2610  /// store operations first, followed by smaller ones, if necessary, per
2611  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2612  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2613  /// store. This only applies to setting a constant array of a constant size.
2615 
2616  /// Maximum number of stores operations that may be substituted for the call
2617  /// to memset, used for functions with OptSize attribute.
2619 
2620  /// Specify maximum bytes of store instructions per memcpy call.
2621  ///
2622  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2623  /// store operations that may be substituted for a call to memcpy. Targets
2624  /// must set this value based on the cost threshold for that target. Targets
2625  /// should assume that the memcpy will be done using as many of the largest
2626  /// store operations first, followed by smaller ones, if necessary, per
2627  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2628  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2629  /// and one 1-byte store. This only applies to copying a constant array of
2630  /// constant size.
2632 
2633 
2634  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2635  ///
2636  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2637  /// of store instructions to keep together. This helps in pairing and
2638  // vectorization later on.
2639  unsigned MaxGluedStoresPerMemcpy = 0;
2640 
2641  /// Maximum number of store operations that may be substituted for a call to
2642  /// memcpy, used for functions with OptSize attribute.
2646 
2647  /// Specify maximum bytes of store instructions per memmove call.
2648  ///
2649  /// When lowering \@llvm.memmove this field specifies the maximum number of
2650  /// store instructions that may be substituted for a call to memmove. Targets
2651  /// must set this value based on the cost threshold for that target. Targets
2652  /// should assume that the memmove will be done using as many of the largest
2653  /// store operations first, followed by smaller ones, if necessary, per
2654  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2655  /// with 8-bit alignment would result in nine 1-byte stores. This only
2656  /// applies to copying a constant array of constant size.
2658 
2659  /// Maximum number of store instructions that may be substituted for a call to
2660  /// memmove, used for functions with OptSize attribute.
2662 
2663  /// Tells the code generator that select is more expensive than a branch if
2664  /// the branch is usually predicted right.
2666 
2667  /// \see enableExtLdPromotion.
2669 
2670  /// Return true if the value types that can be represented by the specified
2671  /// register class are all legal.
2672  bool isLegalRC(const TargetRegisterInfo &TRI,
2673  const TargetRegisterClass &RC) const;
2674 
2675  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2676  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2677  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2678  MachineBasicBlock *MBB) const;
2679 
2680  /// Replace/modify the XRay custom event operands with target-dependent
2681  /// details.
2682  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2683  MachineBasicBlock *MBB) const;
2684 
2685  /// Replace/modify the XRay typed event operands with target-dependent
2686  /// details.
2687  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2688  MachineBasicBlock *MBB) const;
2689 };
2690 
2691 /// This class defines information used to lower LLVM code to legal SelectionDAG
2692 /// operators that the target instruction selector can accept natively.
2693 ///
2694 /// This class also defines callbacks that targets must implement to lower
2695 /// target-specific constructs to SelectionDAG operators.
2697 public:
2698  struct DAGCombinerInfo;
2699 
2700  TargetLowering(const TargetLowering &) = delete;
2701  TargetLowering &operator=(const TargetLowering &) = delete;
2702 
2703  /// NOTE: The TargetMachine owns TLOF.
2704  explicit TargetLowering(const TargetMachine &TM);
2705 
2706  bool isPositionIndependent() const;
2707 
2708  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2709  FunctionLoweringInfo *FLI,
2710  LegacyDivergenceAnalysis *DA) const {
2711  return false;
2712  }
2713 
2714  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2715  return false;
2716  }
2717 
2718  /// Returns true by value, base pointer and offset pointer and addressing mode
2719  /// by reference if the node's address can be legally represented as
2720  /// pre-indexed load / store address.
2721  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2722  SDValue &/*Offset*/,
2723  ISD::MemIndexedMode &/*AM*/,
2724  SelectionDAG &/*DAG*/) const {
2725  return false;
2726  }
2727 
2728  /// Returns true by value, base pointer and offset pointer and addressing mode
2729  /// by reference if this node can be combined with a load / store to form a
2730  /// post-indexed load / store.
2731  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2732  SDValue &/*Base*/,
2733  SDValue &/*Offset*/,
2734  ISD::MemIndexedMode &/*AM*/,
2735  SelectionDAG &/*DAG*/) const {
2736  return false;
2737  }
2738 
2739  /// Return the entry encoding for a jump table in the current function. The
2740  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2741  virtual unsigned getJumpTableEncoding() const;
2742 
2743  virtual const MCExpr *
2745  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2746  MCContext &/*Ctx*/) const {
2747  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2748  }
2749 
2750  /// Returns relocation base for the given PIC jumptable.
2751  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2752  SelectionDAG &DAG) const;
2753 
2754  /// This returns the relocation base for the given PIC jumptable, the same as
2755  /// getPICJumpTableRelocBase, but as an MCExpr.
2756  virtual const MCExpr *
2757  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2758  unsigned JTI, MCContext &Ctx) const;
2759 
2760  /// Return true if folding a constant offset with the given GlobalAddress is
2761  /// legal. It is frequently not legal in PIC relocation models.
2762  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2763 
2764  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2765  SDValue &Chain) const;
2766 
2767  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2768  SDValue &NewRHS, ISD::CondCode &CCCode,
2769  const SDLoc &DL) const;
2770 
2771  /// Returns a pair of (return value, chain).
2772  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2773  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2774  EVT RetVT, ArrayRef<SDValue> Ops,
2775  bool isSigned, const SDLoc &dl,
2776  bool doesNotReturn = false,
2777  bool isReturnValueUsed = true) const;
2778 
2779  /// Check whether parameters to a call that are passed in callee saved
2780  /// registers are the same as from the calling function. This needs to be
2781  /// checked for tail call eligibility.
2782  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2783  const uint32_t *CallerPreservedMask,
2784  const SmallVectorImpl<CCValAssign> &ArgLocs,
2785  const SmallVectorImpl<SDValue> &OutVals) const;
2786 
2787  //===--------------------------------------------------------------------===//
2788  // TargetLowering Optimization Methods
2789  //
2790 
2791  /// A convenience struct that encapsulates a DAG, and two SDValues for
2792  /// returning information from TargetLowering to its clients that want to
2793  /// combine.
2796  bool LegalTys;
2797  bool LegalOps;
2800 
2802  bool LT, bool LO) :
2803  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2804 
2805  bool LegalTypes() const { return LegalTys; }
2806  bool LegalOperations() const { return LegalOps; }
2807 
2809  Old = O;
2810  New = N;
2811  return true;
2812  }
2813  };
2814 
2815  /// Check to see if the specified operand of the specified instruction is a
2816  /// constant integer. If so, check to see if there are any bits set in the
2817  /// constant that are not demanded. If so, shrink the constant and return
2818  /// true.
2819  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2820  TargetLoweringOpt &TLO) const;
2821 
2822  // Target hook to do target-specific const optimization, which is called by
2823  // ShrinkDemandedConstant. This function should return true if the target
2824  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2825  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2826  TargetLoweringOpt &TLO) const {
2827  return false;
2828  }
2829 
2830  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2831  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2832  /// generalized for targets with other types of implicit widening casts.
2833  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2834  TargetLoweringOpt &TLO) const;
2835 
2836  /// Helper for SimplifyDemandedBits that can simplify an operation with
2837  /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2838  /// then updates \p User with the simplified version. No other uses of
2839  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2840  /// function behaves exactly like function SimplifyDemandedBits declared
2841  /// below except that it also updates the DAG by calling
2842  /// DCI.CommitTargetLoweringOpt.
2843  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2844  DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2845 
2846  /// Look at Op. At this point, we know that only the DemandedMask bits of the
2847  /// result of Op are ever used downstream. If we can use this information to
2848  /// simplify Op, create a new simplified DAG node and return true, returning
2849  /// the original and new nodes in Old and New. Otherwise, analyze the
2850  /// expression and return a mask of KnownOne and KnownZero bits for the
2851  /// expression (used to simplify the caller). The KnownZero/One bits may only
2852  /// be accurate for those bits in the DemandedMask.
2853  /// \p AssumeSingleUse When this parameter is true, this function will
2854  /// attempt to simplify \p Op even if there are multiple uses.
2855  /// Callers are responsible for correctly updating the DAG based on the
2856  /// results of this function, because simply replacing replacing TLO.Old
2857  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2858  /// has multiple uses.
2859  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2860  KnownBits &Known,
2861  TargetLoweringOpt &TLO,
2862  unsigned Depth = 0,
2863  bool AssumeSingleUse = false) const;
2864 
2865  /// Helper wrapper around SimplifyDemandedBits.
2866  /// Adds Op back to the worklist upon success.
2867  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2868  DAGCombinerInfo &DCI) const;
2869 
2870  /// Look at Vector Op. At this point, we know that only the DemandedElts
2871  /// elements of the result of Op are ever used downstream. If we can use
2872  /// this information to simplify Op, create a new simplified DAG node and
2873  /// return true, storing the original and new nodes in TLO.
2874  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2875  /// KnownZero elements for the expression (used to simplify the caller).
2876  /// The KnownUndef/Zero elements may only be accurate for those bits
2877  /// in the DemandedMask.
2878  /// \p AssumeSingleUse When this parameter is true, this function will
2879  /// attempt to simplify \p Op even if there are multiple uses.
2880  /// Callers are responsible for correctly updating the DAG based on the
2881  /// results of this function, because simply replacing replacing TLO.Old
2882  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2883  /// has multiple uses.
2884  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2885  APInt &KnownUndef, APInt &KnownZero,
2886  TargetLoweringOpt &TLO, unsigned Depth = 0,
2887  bool AssumeSingleUse = false) const;
2888 
2889  /// Helper wrapper around SimplifyDemandedVectorElts.
2890  /// Adds Op back to the worklist upon success.
2891  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2892  APInt &KnownUndef, APInt &KnownZero,
2893  DAGCombinerInfo &DCI) const;
2894 
2895  /// Determine which of the bits specified in Mask are known to be either zero
2896  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2897  /// argument allows us to only collect the known bits that are shared by the
2898  /// requested vector elements.
2899  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2900  KnownBits &Known,
2901  const APInt &DemandedElts,
2902  const SelectionDAG &DAG,
2903  unsigned Depth = 0) const;
2904 
2905  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2906  /// Default implementation computes low bits based on alignment
2907  /// information. This should preserve known bits passed into it.
2908  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2909  KnownBits &Known,
2910  const APInt &DemandedElts,
2911  const SelectionDAG &DAG,
2912  unsigned Depth = 0) const;
2913 
2914  /// This method can be implemented by targets that want to expose additional
2915  /// information about sign bits to the DAG Combiner. The DemandedElts
2916  /// argument allows us to only collect the minimum sign bits that are shared
2917  /// by the requested vector elements.
2918  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2919  const APInt &DemandedElts,
2920  const SelectionDAG &DAG,
2921  unsigned Depth = 0) const;
2922 
2923  /// Attempt to simplify any target nodes based on the demanded vector
2924  /// elements, returning true on success. Otherwise, analyze the expression and
2925  /// return a mask of KnownUndef and KnownZero elements for the expression
2926  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2927  /// accurate for those bits in the DemandedMask.
2928  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2929  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2930  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2931 
2932  /// Attempt to simplify any target nodes based on the demanded bits,
2933  /// returning true on success. Otherwise, analyze the
2934  /// expression and return a mask of KnownOne and KnownZero bits for the
2935  /// expression (used to simplify the caller). The KnownZero/One bits may only
2936  /// be accurate for those bits in the DemandedMask.
2937  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
2938  const APInt &DemandedBits,
2939  KnownBits &Known,
2940  TargetLoweringOpt &TLO,
2941  unsigned Depth = 0) const;
2942 
2943  /// If \p SNaN is false, \returns true if \p Op is known to never be any
2944  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
2945  /// NaN.
2946  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
2947  const SelectionDAG &DAG,
2948  bool SNaN = false,
2949  unsigned Depth = 0) const;
2951  void *DC; // The DAG Combiner object.
2954 
2955  public:
2957 
2958  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2959  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2960 
2961  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2962  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2963  bool isAfterLegalizeDAG() const {
2964  return Level == AfterLegalizeDAG;
2965  }
2967  bool isCalledByLegalizer() const { return CalledByLegalizer; }
2968 
2969  void AddToWorklist(SDNode *N);
2970  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2971  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2972  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2973 
2974  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2975  };
2976 
2977  /// Return if the N is a constant or constant vector equal to the true value
2978  /// from getBooleanContents().
2979  bool isConstTrueVal(const SDNode *N) const;
2980 
2981  /// Return if the N is a constant or constant vector equal to the false value
2982  /// from getBooleanContents().
2983  bool isConstFalseVal(const SDNode *N) const;
2984 
2985  /// Return if \p N is a True value when extended to \p VT.
2986  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
2987 
2988  /// Try to simplify a setcc built with the specified operands and cc. If it is
2989  /// unable to simplify it, return a null SDValue.
2990  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2991  bool foldBooleans, DAGCombinerInfo &DCI,
2992  const SDLoc &dl) const;
2993 
2994  // For targets which wrap address, unwrap for analysis.
2995  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2996 
2997  /// Returns true (and the GlobalValue and the offset) if the node is a
2998  /// GlobalAddress + offset.
2999  virtual bool
3000  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3001 
3002  /// This method will be invoked for all target nodes and for any
3003  /// target-independent nodes that the target has registered with invoke it
3004  /// for.
3005  ///
3006  /// The semantics are as follows:
3007  /// Return Value:
3008  /// SDValue.Val == 0 - No change was made
3009  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3010  /// otherwise - N should be replaced by the returned Operand.
3011  ///
3012  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3013  /// more complex transformations.
3014  ///
3015  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3016 
3017  /// Return true if it is profitable to move this shift by a constant amount
3018  /// though its operand, adjusting any immediate operands as necessary to
3019  /// preserve semantics. This transformation may not be desirable if it
3020  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3021  /// extraction in AArch64). By default, it returns true.
3022  ///
3023  /// @param N the shift node
3024  /// @param Level the current DAGCombine legalization level.
3025  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3026  CombineLevel Level) const {
3027  return true;
3028  }
3029 
3030  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3031  // to a shuffle and a truncate.
3032  // Example of such a combine:
3033  // v4i32 build_vector((extract_elt V, 1),
3034  // (extract_elt V, 3),
3035  // (extract_elt V, 5),
3036  // (extract_elt V, 7))
3037  // -->
3038  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3040  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3041  return false;
3042  }
3043 
3044  /// Return true if the target has native support for the specified value type
3045  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3046  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3047  /// and some i16 instructions are slow.
3048  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3049  // By default, assume all legal types are desirable.
3050  return isTypeLegal(VT);
3051  }
3052 
3053  /// Return true if it is profitable for dag combiner to transform a floating
3054  /// point op of specified opcode to a equivalent op of an integer
3055  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3056  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3057  EVT /*VT*/) const {
3058  return false;
3059  }
3060 
3061  /// This method query the target whether it is beneficial for dag combiner to
3062  /// promote the specified node. If true, it should return the desired
3063  /// promotion type by reference.
3064  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3065  return false;
3066  }
3067 
3068  /// Return true if the target supports swifterror attribute. It optimizes
3069  /// loads and stores to reading and writing a specific register.
3070  virtual bool supportSwiftError() const {
3071  return false;
3072  }
3073 
3074  /// Return true if the target supports that a subset of CSRs for the given
3075  /// machine function is handled explicitly via copies.
3076  virtual bool supportSplitCSR(MachineFunction *MF) const {
3077  return false;
3078  }
3079 
3080  /// Perform necessary initialization to handle a subset of CSRs explicitly
3081  /// via copies. This function is called at the beginning of instruction
3082  /// selection.
3083  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3084  llvm_unreachable("Not Implemented");
3085  }
3086 
3087  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3088  /// CSRs to virtual registers in the entry block, and copy them back to
3089  /// physical registers in the exit blocks. This function is called at the end
3090  /// of instruction selection.
3091  virtual void insertCopiesSplitCSR(
3092  MachineBasicBlock *Entry,
3093  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3094  llvm_unreachable("Not Implemented");
3095  }
3096 
3097  //===--------------------------------------------------------------------===//
3098  // Lowering methods - These methods must be implemented by targets so that
3099  // the SelectionDAGBuilder code knows how to lower these.
3100  //
3101 
3102  /// This hook must be implemented to lower the incoming (formal) arguments,
3103  /// described by the Ins array, into the specified DAG. The implementation
3104  /// should fill in the InVals array with legal-type argument values, and
3105  /// return the resulting token chain value.
3107  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3108  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3109  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3110  llvm_unreachable("Not Implemented");
3111  }
3112 
3113  /// This structure contains all information that is necessary for lowering
3114  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3115  /// needs to lower a call, and targets will see this struct in their LowerCall
3116  /// implementation.
3119  Type *RetTy = nullptr;
3120  bool RetSExt : 1;
3121  bool RetZExt : 1;
3122  bool IsVarArg : 1;
3123  bool IsInReg : 1;
3124  bool DoesNotReturn : 1;
3126  bool IsConvergent : 1;
3127  bool IsPatchPoint : 1;
3128 
3129  // IsTailCall should be modified by implementations of
3130  // TargetLowering::LowerCall that perform tail call conversions.
3131  bool IsTailCall = false;
3132 
3133  // Is Call lowering done post SelectionDAG type legalization.
3134  bool IsPostTypeLegalization = false;
3135 
3136  unsigned NumFixedArgs = -1;
3139  ArgListTy Args;
3147 
3149  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3150  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3151  IsPatchPoint(false), DAG(DAG) {}
3152 
3154  DL = dl;
3155  return *this;
3156  }
3157 
3159  Chain = InChain;
3160  return *this;
3161  }
3162 
3163  // setCallee with target/module-specific attributes
3165  SDValue Target, ArgListTy &&ArgsList) {
3166  RetTy = ResultType;
3167  Callee = Target;
3168  CallConv = CC;
3169  NumFixedArgs = ArgsList.size();
3170  Args = std::move(ArgsList);
3171 
3173  &(DAG.getMachineFunction()), CC, Args);
3174  return *this;
3175  }
3176 
3178  SDValue Target, ArgListTy &&ArgsList) {
3179  RetTy = ResultType;
3180  Callee = Target;
3181  CallConv = CC;
3182  NumFixedArgs = ArgsList.size();
3183  Args = std::move(ArgsList);
3184  return *this;
3185  }
3186 
3188  SDValue Target, ArgListTy &&ArgsList,
3189  ImmutableCallSite Call) {
3190  RetTy = ResultType;
3191 
3192  IsInReg = Call.hasRetAttr(Attribute::InReg);
3193  DoesNotReturn =
3194  Call.doesNotReturn() ||
3195  (!Call.isInvoke() &&
3196  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3197  IsVarArg = FTy->isVarArg();
3198  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3199  RetSExt = Call.hasRetAttr(Attribute::SExt);
3200  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3201 
3202  Callee = Target;
3203 
3204  CallConv = Call.getCallingConv();
3205  NumFixedArgs = FTy->getNumParams();
3206  Args = std::move(ArgsList);
3207 
3208  CS = Call;
3209 
3210  return *this;
3211  }
3212 
3214  IsInReg = Value;
3215  return *this;
3216  }
3217 
3219  DoesNotReturn = Value;
3220  return *this;
3221  }
3222 
3224  IsVarArg = Value;
3225  return *this;
3226  }
3227 
3229  IsTailCall = Value;
3230  return *this;
3231  }
3232 
3234  IsReturnValueUsed = !Value;
3235  return *this;
3236  }
3237 
3239  IsConvergent = Value;
3240  return *this;
3241  }
3242 
3244  RetSExt = Value;
3245  return *this;
3246  }
3247 
3249  RetZExt = Value;
3250  return *this;
3251  }
3252 
3254  IsPatchPoint = Value;
3255  return *this;
3256  }
3257 
3259  IsPostTypeLegalization = Value;
3260  return *this;
3261  }
3262 
3263  ArgListTy &getArgs() {
3264  return Args;
3265  }
3266  };
3267 
3268  /// This function lowers an abstract call to a function into an actual call.
3269  /// This returns a pair of operands. The first element is the return value
3270  /// for the function (if RetTy is not VoidTy). The second element is the
3271  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3272  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3273 
3274  /// This hook must be implemented to lower calls into the specified
3275  /// DAG. The outgoing arguments to the call are described by the Outs array,
3276  /// and the values to be returned by the call are described by the Ins
3277  /// array. The implementation should fill in the InVals array with legal-type
3278  /// return values from the call, and return the resulting token chain value.
3279  virtual SDValue
3281  SmallVectorImpl<SDValue> &/*InVals*/) const {
3282  llvm_unreachable("Not Implemented");
3283  }
3284 
3285  /// Target-specific cleanup for formal ByVal parameters.
3286  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3287 
3288  /// This hook should be implemented to check whether the return values
3289  /// described by the Outs array can fit into the return registers. If false
3290  /// is returned, an sret-demotion is performed.
3291  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3292  MachineFunction &/*MF*/, bool /*isVarArg*/,
3293  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3294  LLVMContext &/*Context*/) const
3295  {
3296  // Return true by default to get preexisting behavior.
3297  return true;
3298  }
3299 
3300  /// This hook must be implemented to lower outgoing return values, described
3301  /// by the Outs array, into the specified DAG. The implementation should
3302  /// return the resulting token chain value.
3303  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3304  bool /*isVarArg*/,
3305  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3306  const SmallVectorImpl<SDValue> & /*OutVals*/,
3307  const SDLoc & /*dl*/,
3308  SelectionDAG & /*DAG*/) const {
3309  llvm_unreachable("Not Implemented");
3310  }
3311 
3312  /// Return true if result of the specified node is used by a return node
3313  /// only. It also compute and return the input chain for the tail call.
3314  ///
3315  /// This is used to determine whether it is possible to codegen a libcall as
3316  /// tail call at legalization time.
3317  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3318  return false;
3319  }
3320 
3321  /// Return true if the target may be able emit the call instruction as a tail
3322  /// call. This is used by optimization passes to determine if it's profitable
3323  /// to duplicate return instructions to enable tailcall optimization.
3324  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3325  return false;
3326  }
3327 
3328  /// Return the builtin name for the __builtin___clear_cache intrinsic
3329  /// Default is to invoke the clear cache library call
3330  virtual const char * getClearCacheBuiltinName() const {
3331  return "__clear_cache";
3332  }
3333 
3334  /// Return the register ID of the name passed in. Used by named register
3335  /// global variables extension. There is no target-independent behaviour
3336  /// so the default action is to bail.
3337  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3338  SelectionDAG &DAG) const {
3339  report_fatal_error("Named registers not implemented for this target");
3340  }
3341 
3342  /// Return the type that should be used to zero or sign extend a
3343  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3344  /// require the return type to be promoted, but this is not true all the time,
3345  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3346  /// conventions. The frontend should handle this and include all of the
3347  /// necessary information.
3349  ISD::NodeType /*ExtendKind*/) const {
3350  EVT MinVT = getRegisterType(Context, MVT::i32);
3351  return VT.bitsLT(MinVT) ? MinVT : VT;
3352  }
3353 
3354  /// For some targets, an LLVM struct type must be broken down into multiple
3355  /// simple types, but the calling convention specifies that the entire struct
3356  /// must be passed in a block of consecutive registers.
3357  virtual bool
3359  bool isVarArg) const {
3360  return false;
3361  }
3362 
3363  /// Returns a 0 terminated array of registers that can be safely used as
3364  /// scratch registers.
3365  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3366  return nullptr;
3367  }
3368 
3369  /// This callback is used to prepare for a volatile or atomic load.
3370  /// It takes a chain node as input and returns the chain for the load itself.
3371  ///
3372  /// Having a callback like this is necessary for targets like SystemZ,
3373  /// which allows a CPU to reuse the result of a previous load indefinitely,
3374  /// even if a cache-coherent store is performed by another CPU. The default
3375  /// implementation does nothing.
3377  SelectionDAG &DAG) const {
3378  return Chain;
3379  }
3380 
3381  /// This callback is used to inspect load/store instructions and add
3382  /// target-specific MachineMemOperand flags to them. The default
3383  /// implementation does nothing.
3386  }
3387 
3388  /// This callback is invoked by the type legalizer to legalize nodes with an
3389  /// illegal operand type but legal result types. It replaces the
3390  /// LowerOperation callback in the type Legalizer. The reason we can not do
3391  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3392  /// use this callback.
3393  ///
3394  /// TODO: Consider merging with ReplaceNodeResults.
3395  ///
3396  /// The target places new result values for the node in Results (their number
3397  /// and types must exactly match those of the original return values of
3398  /// the node), or leaves Results empty, which indicates that the node is not
3399  /// to be custom lowered after all.
3400  /// The default implementation calls LowerOperation.
3401  virtual void LowerOperationWrapper(SDNode *N,
3403  SelectionDAG &DAG) const;
3404 
3405  /// This callback is invoked for operations that are unsupported by the
3406  /// target, which are registered to use 'custom' lowering, and whose defined
3407  /// values are all legal. If the target has no operations that require custom
3408  /// lowering, it need not implement this. The default implementation of this
3409  /// aborts.
3410  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3411 
3412  /// This callback is invoked when a node result type is illegal for the
3413  /// target, and the operation was registered to use 'custom' lowering for that
3414  /// result type. The target places new result values for the node in Results
3415  /// (their number and types must exactly match those of the original return
3416  /// values of the node), or leaves Results empty, which indicates that the
3417  /// node is not to be custom lowered after all.
3418  ///
3419  /// If the target has no operations that require custom lowering, it need not
3420  /// implement this. The default implementation aborts.
3421  virtual void ReplaceNodeResults(SDNode * /*N*/,
3422  SmallVectorImpl<SDValue> &/*Results*/,
3423  SelectionDAG &/*DAG*/) const {
3424  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3425  }
3426 
3427  /// This method returns the name of a target specific DAG node.
3428  virtual const char *getTargetNodeName(unsigned Opcode) const;
3429 
3430  /// This method returns a target specific FastISel object, or null if the
3431  /// target does not support "fast" ISel.
3433  const TargetLibraryInfo *) const {
3434  return nullptr;
3435  }
3436 
3437  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3438  SelectionDAG &DAG) const;
3439 
3440  //===--------------------------------------------------------------------===//
3441  // Inline Asm Support hooks
3442  //
3443 
3444  /// This hook allows the target to expand an inline asm call to be explicit
3445  /// llvm code if it wants to. This is useful for turning simple inline asms
3446  /// into LLVM intrinsics, which gives the compiler more information about the
3447  /// behavior of the code.
3448  virtual bool ExpandInlineAsm(CallInst *) const {
3449  return false;
3450  }
3451 
3453  C_Register, // Constraint represents specific register(s).
3454  C_RegisterClass, // Constraint represents any of register(s) in class.
3455  C_Memory, // Memory constraint.
3456  C_Other, // Something else.
3457  C_Unknown // Unsupported constraint.
3458  };
3459 
3461  // Generic weights.
3462  CW_Invalid = -1, // No match.
3463  CW_Okay = 0, // Acceptable.
3464  CW_Good = 1, // Good weight.
3465  CW_Better = 2, // Better weight.
3466  CW_Best = 3, // Best weight.
3467 
3468  // Well-known weights.
3469  CW_SpecificReg = CW_Okay, // Specific register operands.
3470  CW_Register = CW_Good, // Register operands.
3471  CW_Memory = CW_Better, // Memory operands.
3472  CW_Constant = CW_Best, // Constant operand.
3473  CW_Default = CW_Okay // Default or don't know type.
3474  };
3475 
3476  /// This contains information for each constraint that we are lowering.
3478  /// This contains the actual string for the code, like "m". TargetLowering
3479  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3480  /// matches the operand.
3481  std::string ConstraintCode;
3482 
3483  /// Information about the constraint code, e.g. Register, RegisterClass,
3484  /// Memory, Other, Unknown.
3486 
3487  /// If this is the result output operand or a clobber, this is null,
3488  /// otherwise it is the incoming operand to the CallInst. This gets
3489  /// modified as the asm is processed.
3490  Value *CallOperandVal = nullptr;
3491 
3492  /// The ValueType for the operand value.
3493  MVT ConstraintVT = MVT::Other;
3494 
3495  /// Copy constructor for copying from a ConstraintInfo.
3497  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3498 
3499  /// Return true of this is an input operand that is a matching constraint
3500  /// like "4".
3501  bool isMatchingInputConstraint() const;
3502 
3503  /// If this is an input matching constraint, this method returns the output
3504  /// operand it matches.
3505  unsigned getMatchedOperand() const;
3506  };
3507 
3508  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3509 
3510  /// Split up the constraint string from the inline assembly value into the
3511  /// specific constraints and their prefixes, and also tie in the associated
3512  /// operand values. If this returns an empty vector, and if the constraint
3513  /// string itself isn't empty, there was an error parsing.
3514  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3515  const TargetRegisterInfo *TRI,
3516  ImmutableCallSite CS) const;
3517 
3518  /// Examine constraint type and operand type and determine a weight value.
3519  /// The operand object must already have been set up with the operand type.
3520  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3521  AsmOperandInfo &info, int maIndex) const;
3522 
3523  /// Examine constraint string and operand type and determine a weight value.
3524  /// The operand object must already have been set up with the operand type.
3525  virtual ConstraintWeight getSingleConstraintMatchWeight(
3526  AsmOperandInfo &info, const char *constraint) const;
3527 
3528  /// Determines the constraint code and constraint type to use for the specific
3529  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3530  /// If the actual operand being passed in is available, it can be passed in as
3531  /// Op, otherwise an empty SDValue can be passed.
3532  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3533  SDValue Op,
3534  SelectionDAG *DAG = nullptr) const;
3535 
3536  /// Given a constraint, return the type of constraint it is for this target.
3537  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3538 
3539  /// Given a physical register constraint (e.g. {edx}), return the register
3540  /// number and the register class for the register.
3541  ///
3542  /// Given a register class constraint, like 'r', if this corresponds directly
3543  /// to an LLVM register class, return a register of 0 and the register class
3544  /// pointer.
3545  ///
3546  /// This should only be used for C_Register constraints. On error, this
3547  /// returns a register number of 0 and a null register class pointer.
3548  virtual std::pair<unsigned, const TargetRegisterClass *>
3549  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3550  StringRef Constraint, MVT VT) const;
3551 
3552  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3553  if (ConstraintCode == "i")
3554  return InlineAsm::Constraint_i;
3555  else if (ConstraintCode == "m")
3556  return InlineAsm::Constraint_m;
3558  }
3559 
3560  /// Try to replace an X constraint, which matches anything, with another that
3561  /// has more specific requirements based on the type of the corresponding
3562  /// operand. This returns null if there is no replacement to make.
3563  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3564 
3565  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3566  /// add anything to Ops.
3567  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3568  std::vector<SDValue> &Ops,
3569  SelectionDAG &DAG) const;
3570 
3571  //===--------------------------------------------------------------------===//
3572  // Div utility functions
3573  //
3574  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3575  SmallVectorImpl<SDNode *> &Created) const;
3576  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3577  SmallVectorImpl<SDNode *> &Created) const;
3578 
3579  /// Targets may override this function to provide custom SDIV lowering for
3580  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3581  /// assumes SDIV is expensive and replaces it with a series of other integer
3582  /// operations.
3583  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3584  SelectionDAG &DAG,
3585  SmallVectorImpl<SDNode *> &Created) const;
3586 
3587  /// Indicate whether this target prefers to combine FDIVs with the same
3588  /// divisor. If the transform should never be done, return zero. If the
3589  /// transform should be done, return the minimum number of divisor uses
3590  /// that must exist.
3591  virtual unsigned combineRepeatedFPDivisors() const {
3592  return 0;
3593  }
3594 
3595  /// Hooks for building estimates in place of slower divisions and square
3596  /// roots.
3597 
3598  /// Return either a square root or its reciprocal estimate value for the input
3599  /// operand.
3600  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3601  /// 'Enabled' as set by a potential default override attribute.
3602  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3603  /// refinement iterations required to generate a sufficient (though not
3604  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3605  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3606  /// algorithm implementation that uses either one or two constants.
3607  /// The boolean Reciprocal is used to select whether the estimate is for the
3608  /// square root of the input operand or the reciprocal of its square root.
3609  /// A target may choose to implement its own refinement within this function.
3610  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3611  /// any further refinement of the estimate.
3612  /// An empty SDValue return means no estimate sequence can be created.
3614  int Enabled, int &RefinementSteps,
3615  bool &UseOneConstNR, bool Reciprocal) const {
3616  return SDValue();
3617  }
3618 
3619  /// Return a reciprocal estimate value for the input operand.
3620  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3621  /// 'Enabled' as set by a potential default override attribute.
3622  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3623  /// refinement iterations required to generate a sufficient (though not
3624  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3625  /// A target may choose to implement its own refinement within this function.
3626  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3627  /// any further refinement of the estimate.
3628  /// An empty SDValue return means no estimate sequence can be created.
3630  int Enabled, int &RefinementSteps) const {
3631  return SDValue();
3632  }
3633 
3634  //===--------------------------------------------------------------------===//
3635  // Legalization utility functions
3636  //
3637 
3638  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3639  /// respectively, each computing an n/2-bit part of the result.
3640  /// \param Result A vector that will be filled with the parts of the result
3641  /// in little-endian order.
3642  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3643  /// if you want to control how low bits are extracted from the LHS.
3644  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3645  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3646  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3647  /// \returns true if the node has been expanded, false if it has not
3648  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3649  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3651  SDValue LL = SDValue(), SDValue LH = SDValue(),
3652  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3653 
3654  /// Expand a MUL into two nodes. One that computes the high bits of
3655  /// the result and one that computes the low bits.
3656  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3657  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3658  /// if you want to control how low bits are extracted from the LHS.
3659  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3660  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3661  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3662  /// \returns true if the node has been expanded. false if it has not
3663  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3664  SelectionDAG &DAG, MulExpansionKind Kind,
3665  SDValue LL = SDValue(), SDValue LH = SDValue(),
3666  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3667 
3668  /// Expand float(f32) to SINT(i64) conversion
3669  /// \param N Node to expand
3670  /// \param Result output after conversion
3671  /// \returns True, if the expansion was successful, false otherwise
3672  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3673 
3674  /// Expand float to UINT conversion
3675  /// \param N Node to expand
3676  /// \param Result output after conversion
3677  /// \returns True, if the expansion was successful, false otherwise
3678  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3679 
3680  /// Expand UINT(i64) to double(f64) conversion
3681  /// \param N Node to expand
3682  /// \param Result output after conversion
3683  /// \returns True, if the expansion was successful, false otherwise
3684  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3685 
3686  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3687  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3688 
3689  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3690  /// vector nodes can only succeed if all operations are legal/custom.
3691  /// \param N Node to expand
3692  /// \param Result output after conversion
3693  /// \returns True, if the expansion was successful, false otherwise
3694  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3695 
3696  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3697  /// vector nodes can only succeed if all operations are legal/custom.
3698  /// \param N Node to expand
3699  /// \param Result output after conversion
3700  /// \returns True, if the expansion was successful, false otherwise
3701  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3702 
3703  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3704  /// vector nodes can only succeed if all operations are legal/custom.
3705  /// \param N Node to expand
3706  /// \param Result output after conversion
3707  /// \returns True, if the expansion was successful, false otherwise
3708  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3709 
3710  /// Turn load of vector type into a load of the individual elements.
3711  /// \param LD load to expand
3712  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3713  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3714 
3715  // Turn a store of a vector type into stores of the individual elements.
3716  /// \param ST Store with a vector value type
3717  /// \returns MERGE_VALUs of the individual store chains.
3718  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3719 
3720  /// Expands an unaligned load to 2 half-size loads for an integer, and
3721  /// possibly more for vectors.
3722  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3723  SelectionDAG &DAG) const;
3724 
3725  /// Expands an unaligned store to 2 half-size stores for integer values, and
3726  /// possibly more for vectors.
3727  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3728 
3729  /// Increments memory address \p Addr according to the type of the value
3730  /// \p DataVT that should be stored. If the data is stored in compressed
3731  /// form, the memory address should be incremented according to the number of
3732  /// the stored elements. This number is equal to the number of '1's bits
3733  /// in the \p Mask.
3734  /// \p DataVT is a vector type. \p Mask is a vector value.
3735  /// \p DataVT and \p Mask have the same number of vector elements.
3736  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3737  EVT DataVT, SelectionDAG &DAG,
3738  bool IsCompressedMemory) const;
3739 
3740  /// Get a pointer to vector element \p Idx located in memory for a vector of
3741  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3742  /// bounds the returned pointer is unspecified, but will be within the vector
3743  /// bounds.
3744  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3745  SDValue Index) const;
3746 
3747  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3748  /// method accepts integers or vectors of integers as its arguments.
3749  SDValue getExpandedSaturationAdditionSubtraction(SDNode *Node,
3750  SelectionDAG &DAG) const;
3751 
3752  //===--------------------------------------------------------------------===//
3753  // Instruction Emitting Hooks
3754  //
3755 
3756  /// This method should be implemented by targets that mark instructions with
3757  /// the 'usesCustomInserter' flag. These instructions are special in various
3758  /// ways, which require special support to insert. The specified MachineInstr
3759  /// is created but not inserted into any basic blocks, and this method is
3760  /// called to expand it into a sequence of instructions, potentially also
3761  /// creating new basic blocks and control flow.
3762  /// As long as the returned basic block is different (i.e., we created a new
3763  /// one), the custom inserter is free to modify the rest of \p MBB.
3764  virtual MachineBasicBlock *
3765  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3766 
3767  /// This method should be implemented by targets that mark instructions with
3768  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3769  /// instruction selection by target hooks. e.g. To fill in optional defs for
3770  /// ARM 's' setting instructions.
3771  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3772  SDNode *Node) const;
3773 
3774  /// If this function returns true, SelectionDAGBuilder emits a
3775  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3776  virtual bool useLoadStackGuardNode() const {
3777  return false;
3778  }
3779 
3781  const SDLoc &DL) const {
3782  llvm_unreachable("not implemented for this target");
3783  }
3784 
3785  /// Lower TLS global address SDNode for target independent emulated TLS model.
3786  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3787  SelectionDAG &DAG) const;
3788 
3789  /// Expands target specific indirect branch for the case of JumpTable
3790  /// expanasion.
3792  SelectionDAG &DAG) const {
3793  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3794  }
3795 
3796  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3797  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3798  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3799  // combiner can fold the new nodes.
3800  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3801 
3802 private:
3803  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3804  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3805  const SDLoc &DL) const;
3806 
3807  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3808  SDValue N1, ISD::CondCode Cond,
3809  DAGCombinerInfo &DCI,
3810  const SDLoc &DL) const;
3811 };
3812 
3813 /// Given an LLVM IR type and return type attributes, compute the return value
3814 /// EVTs and flags, and optionally also the offsets, if the return value is
3815 /// being lowered to memory.
3818  const TargetLowering &TLI, const DataLayout &DL);
3819 
3820 } // end namespace llvm
3821 
3822 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:866
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:583
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:365
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:289
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:312
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:594
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:282
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:168
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:377
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
void * PointerTy
Definition: GenericValue.h:22
bool hasOneUse() const
Return true if there is exactly one use of this node.
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:497
amdgpu Simplify well known AMD library false Value Value const Twine & Name
Definition: BitVector.h:938
virtual bool decomposeMulByConstant(EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:743
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:63
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:310
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:948
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:170
Class to represent pointers.
Definition: DerivedTypes.h:467
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:276
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:42
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:923
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:16
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:598
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:471
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:90
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:401
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:930
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1029
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
virtual bool shouldConsiderGEPOffsetSplit() const
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:906
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
static bool Enabled
Definition: Statistic.cpp:51
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Class to represent vector types.
Definition: DerivedTypes.h:393
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:70
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform&#39;s va_list object.
virtual bool preferShiftsToClearExtremeBits(SDValue X) const
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
LegalizeTypeAction getTypeAction(MVT VT) const
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:457
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:186
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:460
ValueTypeActionImpl ValueTypeActions
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
virtual bool needsFixedCatchObjects() const
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Flags
Flags values. These may be or&#39;d together.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool useSoftFloat() const
CallLoweringInfo & setTailCall(bool Value=true)
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:627
Representation of each machine instruction.
Definition: MachineInstr.h:64
virtual bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const
Return true if it is profitable to move this shift by a constant amount though its operand...
CallLoweringInfo & setConvergent(bool Value=true)
SmallVector< SDValue, 32 > OutVals
Defi