LLVM  7.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file describes how to lower LLVM code to machine code. This has two
12 /// main components:
13 ///
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
17 ///
18 /// In addition it has a few other components, like information about FP
19 /// immediates.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
25 
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/CallSite.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/IRBuilder.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h"
50 #include "llvm/IR/Type.h"
51 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/Casting.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <climits>
59 #include <cstdint>
60 #include <iterator>
61 #include <map>
62 #include <string>
63 #include <utility>
64 #include <vector>
65 
66 namespace llvm {
67 
68 class BranchProbability;
69 class CCState;
70 class CCValAssign;
71 class Constant;
72 class FastISel;
73 class FunctionLoweringInfo;
74 class GlobalValue;
75 class IntrinsicInst;
76 struct KnownBits;
77 class LLVMContext;
78 class MachineBasicBlock;
79 class MachineFunction;
80 class MachineInstr;
81 class MachineJumpTableInfo;
82 class MachineLoop;
83 class MachineRegisterInfo;
84 class MCContext;
85 class MCExpr;
86 class Module;
87 class TargetRegisterClass;
88 class TargetLibraryInfo;
89 class TargetRegisterInfo;
90 class Value;
91 
92 namespace Sched {
93 
94  enum Preference {
95  None, // No preference
96  Source, // Follow source order.
97  RegPressure, // Scheduling for lowest register pressure.
98  Hybrid, // Scheduling for both latency and register pressure.
99  ILP, // Scheduling for ILP in low register pressure mode.
100  VLIW // Scheduling for VLIW targets.
101  };
102 
103 } // end namespace Sched
104 
105 /// This base class for TargetLowering contains the SelectionDAG-independent
106 /// parts that can be used from the rest of CodeGen.
108 public:
109  /// This enum indicates whether operations are valid for a target, and if not,
110  /// what action should be used to make them valid.
111  enum LegalizeAction : uint8_t {
112  Legal, // The target natively supports this operation.
113  Promote, // This operation should be executed in a larger type.
114  Expand, // Try to expand this to other ops, otherwise use a libcall.
115  LibCall, // Don't try to expand this to other ops, always use a libcall.
116  Custom // Use the LowerOperation hook to implement custom lowering.
117  };
118 
119  /// This enum indicates whether a types are legal for a target, and if not,
120  /// what action should be used to make them valid.
121  enum LegalizeTypeAction : uint8_t {
122  TypeLegal, // The target natively supports this type.
123  TypePromoteInteger, // Replace this integer with a larger one.
124  TypeExpandInteger, // Split this integer into two of half the size.
125  TypeSoftenFloat, // Convert this float to a same size integer type,
126  // if an operation is not supported in target HW.
127  TypeExpandFloat, // Split this float into two of half the size.
128  TypeScalarizeVector, // Replace this one-element vector with its element.
129  TypeSplitVector, // Split this vector into two of half the size.
130  TypeWidenVector, // This vector should be widened into a larger vector.
131  TypePromoteFloat // Replace this float with a larger one.
132  };
133 
134  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135  /// in order to type-legalize it.
136  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 
138  /// Enum that describes how the target represents true/false values.
140  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143  };
144 
145  /// Enum that describes what type of support for selects the target has.
147  ScalarValSelect, // The target supports scalar selects (ex: cmov).
148  ScalarCondVectorVal, // The target supports selects with a scalar condition
149  // and vector values (ex: cmov).
150  VectorMaskSelect // The target supports vector selects with a vector
151  // mask (ex: x86 blends).
152  };
153 
154  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155  /// to, if at all. Exists because different targets have different levels of
156  /// support for these atomic instructions, and also have different options
157  /// w.r.t. what they should expand to.
158  enum class AtomicExpansionKind {
159  None, // Don't expand the instruction.
160  LLSC, // Expand the instruction into loadlinked/storeconditional; used
161  // by ARM/AArch64.
162  LLOnly, // Expand the (load) instruction into just a load-linked, which has
163  // greater atomic guarantees than a normal load.
164  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165  };
166 
167  /// Enum that specifies when a multiplication should be expanded.
168  enum class MulExpansionKind {
169  Always, // Always expand the instruction.
170  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
171  // or custom.
172  };
173 
174  class ArgListEntry {
175  public:
176  Value *Val = nullptr;
177  SDValue Node = SDValue();
178  Type *Ty = nullptr;
179  bool IsSExt : 1;
180  bool IsZExt : 1;
181  bool IsInReg : 1;
182  bool IsSRet : 1;
183  bool IsNest : 1;
184  bool IsByVal : 1;
185  bool IsInAlloca : 1;
186  bool IsReturned : 1;
187  bool IsSwiftSelf : 1;
188  bool IsSwiftError : 1;
189  uint16_t Alignment = 0;
190 
192  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
193  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
194  IsSwiftSelf(false), IsSwiftError(false) {}
195 
196  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
197  };
198  using ArgListTy = std::vector<ArgListEntry>;
199 
200  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
201  ArgListTy &Args) const {};
202 
204  switch (Content) {
205  case UndefinedBooleanContent:
206  // Extend by adding rubbish bits.
207  return ISD::ANY_EXTEND;
208  case ZeroOrOneBooleanContent:
209  // Extend by adding zero bits.
210  return ISD::ZERO_EXTEND;
211  case ZeroOrNegativeOneBooleanContent:
212  // Extend by copying the sign bit.
213  return ISD::SIGN_EXTEND;
214  }
215  llvm_unreachable("Invalid content kind");
216  }
217 
218  /// NOTE: The TargetMachine owns TLOF.
219  explicit TargetLoweringBase(const TargetMachine &TM);
220  TargetLoweringBase(const TargetLoweringBase &) = delete;
221  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
222  virtual ~TargetLoweringBase() = default;
223 
224 protected:
225  /// \brief Initialize all of the actions to default values.
226  void initActions();
227 
228 public:
229  const TargetMachine &getTargetMachine() const { return TM; }
230 
231  virtual bool useSoftFloat() const { return false; }
232 
233  /// Return the pointer type for the given address space, defaults to
234  /// the pointer type from the data layout.
235  /// FIXME: The default needs to be removed once all the code is updated.
236  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
238  }
239 
240  /// Return the type for frame index, which is determined by
241  /// the alloca address space specified through the data layout.
242  MVT getFrameIndexTy(const DataLayout &DL) const {
243  return getPointerTy(DL, DL.getAllocaAddrSpace());
244  }
245 
246  /// Return the type for operands of fence.
247  /// TODO: Let fence operands be of i32 type and remove this.
248  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
249  return getPointerTy(DL);
250  }
251 
252  /// EVT is not used in-tree, but is used by out-of-tree target.
253  /// A documentation for this function would be nice...
254  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
255 
256  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
257 
258  /// Returns the type to be used for the index operand of:
259  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
260  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
261  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
262  return getPointerTy(DL);
263  }
264 
265  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
266  return true;
267  }
268 
269  /// Return true if multiple condition registers are available.
271  return HasMultipleConditionRegisters;
272  }
273 
274  /// Return true if the target has BitExtract instructions.
275  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
276 
277  /// Return the preferred vector type legalization action.
280  // The default action for one element vectors is to scalarize
281  if (VT.getVectorNumElements() == 1)
282  return TypeScalarizeVector;
283  // The default action for other vectors is to promote
284  return TypePromoteInteger;
285  }
286 
287  // There are two general methods for expanding a BUILD_VECTOR node:
288  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
289  // them together.
290  // 2. Build the vector on the stack and then load it.
291  // If this function returns true, then method (1) will be used, subject to
292  // the constraint that all of the necessary shuffles are legal (as determined
293  // by isShuffleMaskLegal). If this function returns false, then method (2) is
294  // always used. The vector type, and the number of defined values, are
295  // provided.
296  virtual bool
298  unsigned DefinedValues) const {
299  return DefinedValues < 3;
300  }
301 
302  /// Return true if integer divide is usually cheaper than a sequence of
303  /// several shifts, adds, and multiplies for this target.
304  /// The definition of "cheaper" may depend on whether we're optimizing
305  /// for speed or for size.
306  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
307 
308  /// Return true if the target can handle a standalone remainder operation.
309  virtual bool hasStandaloneRem(EVT VT) const {
310  return true;
311  }
312 
313  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
314  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
315  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
316  return false;
317  }
318 
319  /// Reciprocal estimate status values used by the functions below.
320  enum ReciprocalEstimate : int {
321  Unspecified = -1,
322  Disabled = 0,
324  };
325 
326  /// Return a ReciprocalEstimate enum value for a square root of the given type
327  /// based on the function's attributes. If the operation is not overridden by
328  /// the function's attributes, "Unspecified" is returned and target defaults
329  /// are expected to be used for instruction selection.
330  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
331 
332  /// Return a ReciprocalEstimate enum value for a division of the given type
333  /// based on the function's attributes. If the operation is not overridden by
334  /// the function's attributes, "Unspecified" is returned and target defaults
335  /// are expected to be used for instruction selection.
336  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
337 
338  /// Return the refinement step count for a square root of the given type based
339  /// on the function's attributes. If the operation is not overridden by
340  /// the function's attributes, "Unspecified" is returned and target defaults
341  /// are expected to be used for instruction selection.
342  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
343 
344  /// Return the refinement step count for a division of the given type based
345  /// on the function's attributes. If the operation is not overridden by
346  /// the function's attributes, "Unspecified" is returned and target defaults
347  /// are expected to be used for instruction selection.
348  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
349 
350  /// Returns true if target has indicated at least one type should be bypassed.
351  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
352 
353  /// Returns map of slow types for division or remainder with corresponding
354  /// fast types
356  return BypassSlowDivWidths;
357  }
358 
359  /// Return true if Flow Control is an expensive operation that should be
360  /// avoided.
361  bool isJumpExpensive() const { return JumpIsExpensive; }
362 
363  /// Return true if selects are only cheaper than branches if the branch is
364  /// unlikely to be predicted right.
366  return PredictableSelectIsExpensive;
367  }
368 
369  /// If a branch or a select condition is skewed in one direction by more than
370  /// this factor, it is very likely to be predicted correctly.
371  virtual BranchProbability getPredictableBranchThreshold() const;
372 
373  /// Return true if the following transform is beneficial:
374  /// fold (conv (load x)) -> (load (conv*)x)
375  /// On architectures that don't natively support some vector loads
376  /// efficiently, casting the load to a smaller vector of larger types and
377  /// loading is more efficient, however, this can be undone by optimizations in
378  /// dag combiner.
379  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
380  EVT BitcastVT) const {
381  // Don't do if we could do an indexed load on the original type, but not on
382  // the new one.
383  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
384  return true;
385 
386  MVT LoadMVT = LoadVT.getSimpleVT();
387 
388  // Don't bother doing this if it's just going to be promoted again later, as
389  // doing so might interfere with other combines.
390  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
391  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
392  return false;
393 
394  return true;
395  }
396 
397  /// Return true if the following transform is beneficial:
398  /// (store (y (conv x)), y*)) -> (store x, (x*))
399  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
400  // Default to the same logic as loads.
401  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
402  }
403 
404  /// Return true if it is expected to be cheaper to do a store of a non-zero
405  /// vector constant with the given size and type for the address space than to
406  /// store the individual scalar element constants.
407  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
408  unsigned NumElem,
409  unsigned AddrSpace) const {
410  return false;
411  }
412 
413  /// Allow store merging after legalization in addition to before legalization.
414  /// This may catch stores that do not exist earlier (eg, stores created from
415  /// intrinsics).
416  virtual bool mergeStoresAfterLegalization() const { return true; }
417 
418  /// Returns if it's reasonable to merge stores to MemVT size.
419  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
420  const SelectionDAG &DAG) const {
421  return true;
422  }
423 
424  /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
425  virtual bool isCheapToSpeculateCttz() const {
426  return false;
427  }
428 
429  /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
430  virtual bool isCheapToSpeculateCtlz() const {
431  return false;
432  }
433 
434  /// \brief Return true if ctlz instruction is fast.
435  virtual bool isCtlzFast() const {
436  return false;
437  }
438 
439  /// Return true if it is safe to transform an integer-domain bitwise operation
440  /// into the equivalent floating-point operation. This should be set to true
441  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
442  /// type.
443  virtual bool hasBitPreservingFPLogic(EVT VT) const {
444  return false;
445  }
446 
447  /// \brief Return true if it is cheaper to split the store of a merged int val
448  /// from a pair of smaller values into multiple stores.
449  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
450  return false;
451  }
452 
453  /// \brief Return if the target supports combining a
454  /// chain like:
455  /// \code
456  /// %andResult = and %val1, #mask
457  /// %icmpResult = icmp %andResult, 0
458  /// \endcode
459  /// into a single machine instruction of a form like:
460  /// \code
461  /// cc = test %register, #mask
462  /// \endcode
463  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
464  return false;
465  }
466 
467  /// Use bitwise logic to make pairs of compares more efficient. For example:
468  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
469  /// This should be true when it takes more than one instruction to lower
470  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
471  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
472  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
473  return false;
474  }
475 
476  /// Return the preferred operand type if the target has a quick way to compare
477  /// integer values of the given size. Assume that any legal integer type can
478  /// be compared efficiently. Targets may override this to allow illegal wide
479  /// types to return a vector type if there is support to compare that type.
480  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
481  MVT VT = MVT::getIntegerVT(NumBits);
482  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
483  }
484 
485  /// Return true if the target should transform:
486  /// (X & Y) == Y ---> (~X & Y) == 0
487  /// (X & Y) != Y ---> (~X & Y) != 0
488  ///
489  /// This may be profitable if the target has a bitwise and-not operation that
490  /// sets comparison flags. A target may want to limit the transformation based
491  /// on the type of Y or if Y is a constant.
492  ///
493  /// Note that the transform will not occur if Y is known to be a power-of-2
494  /// because a mask and compare of a single bit can be handled by inverting the
495  /// predicate, for example:
496  /// (X & 8) == 8 ---> (X & 8) != 0
497  virtual bool hasAndNotCompare(SDValue Y) const {
498  return false;
499  }
500 
501  /// Return true if the target has a bitwise and-not operation:
502  /// X = ~A & B
503  /// This can be used to simplify select or other instructions.
504  virtual bool hasAndNot(SDValue X) const {
505  // If the target has the more complex version of this operation, assume that
506  // it has this operation too.
507  return hasAndNotCompare(X);
508  }
509 
510  /// \brief Return true if the target wants to use the optimization that
511  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
512  /// promotedInst1(...(promotedInstN(ext(load)))).
513  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
514 
515  /// Return true if the target can combine store(extractelement VectorTy,
516  /// Idx).
517  /// \p Cost[out] gives the cost of that transformation when this is true.
518  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
519  unsigned &Cost) const {
520  return false;
521  }
522 
523  /// Return true if target supports floating point exceptions.
525  return HasFloatingPointExceptions;
526  }
527 
528  /// Return true if target always beneficiates from combining into FMA for a
529  /// given value type. This must typically return false on targets where FMA
530  /// takes more cycles to execute than FADD.
531  virtual bool enableAggressiveFMAFusion(EVT VT) const {
532  return false;
533  }
534 
535  /// Return the ValueType of the result of SETCC operations.
536  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
537  EVT VT) const;
538 
539  /// Return the ValueType for comparison libcalls. Comparions libcalls include
540  /// floating point comparion calls, and Ordered/Unordered check calls on
541  /// floating point numbers.
542  virtual
543  MVT::SimpleValueType getCmpLibcallReturnType() const;
544 
545  /// For targets without i1 registers, this gives the nature of the high-bits
546  /// of boolean values held in types wider than i1.
547  ///
548  /// "Boolean values" are special true/false values produced by nodes like
549  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
550  /// Not to be confused with general values promoted from i1. Some cpus
551  /// distinguish between vectors of boolean and scalars; the isVec parameter
552  /// selects between the two kinds. For example on X86 a scalar boolean should
553  /// be zero extended from i1, while the elements of a vector of booleans
554  /// should be sign extended from i1.
555  ///
556  /// Some cpus also treat floating point types the same way as they treat
557  /// vectors instead of the way they treat scalars.
558  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
559  if (isVec)
560  return BooleanVectorContents;
561  return isFloat ? BooleanFloatContents : BooleanContents;
562  }
563 
565  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
566  }
567 
568  /// Return target scheduling preference.
570  return SchedPreferenceInfo;
571  }
572 
573  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
574  /// for different nodes. This function returns the preference (or none) for
575  /// the given node.
577  return Sched::None;
578  }
579 
580  /// Return the register class that should be used for the specified value
581  /// type.
582  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
583  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
584  assert(RC && "This value type is not natively supported!");
585  return RC;
586  }
587 
588  /// Return the 'representative' register class for the specified value
589  /// type.
590  ///
591  /// The 'representative' register class is the largest legal super-reg
592  /// register class for the register class of the value type. For example, on
593  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
594  /// register class is GR64 on x86_64.
595  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
596  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
597  return RC;
598  }
599 
600  /// Return the cost of the 'representative' register class for the specified
601  /// value type.
602  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
603  return RepRegClassCostForVT[VT.SimpleTy];
604  }
605 
606  /// Return true if the target has native support for the specified value type.
607  /// This means that it has a register that directly holds it without
608  /// promotions or expansions.
609  bool isTypeLegal(EVT VT) const {
610  assert(!VT.isSimple() ||
611  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
612  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
613  }
614 
616  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
617  /// that indicates how instruction selection should deal with the type.
618  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
619 
620  public:
622  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
623  TypeLegal);
624  }
625 
627  return ValueTypeActions[VT.SimpleTy];
628  }
629 
631  ValueTypeActions[VT.SimpleTy] = Action;
632  }
633  };
634 
636  return ValueTypeActions;
637  }
638 
639  /// Return how we should legalize values of this type, either it is already
640  /// legal (return 'Legal') or we need to promote it to a larger type (return
641  /// 'Promote'), or we need to expand it into multiple registers of smaller
642  /// integer type (return 'Expand'). 'Custom' is not an option.
644  return getTypeConversion(Context, VT).first;
645  }
647  return ValueTypeActions.getTypeAction(VT);
648  }
649 
650  /// For types supported by the target, this is an identity function. For
651  /// types that must be promoted to larger types, this returns the larger type
652  /// to promote to. For integer types that are larger than the largest integer
653  /// register, this contains one step in the expansion to get to the smaller
654  /// register. For illegal floating point types, this returns the integer type
655  /// to transform to.
656  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
657  return getTypeConversion(Context, VT).second;
658  }
659 
660  /// For types supported by the target, this is an identity function. For
661  /// types that must be expanded (i.e. integer types that are larger than the
662  /// largest integer register or illegal floating point types), this returns
663  /// the largest legal type it will be expanded to.
664  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
665  assert(!VT.isVector());
666  while (true) {
667  switch (getTypeAction(Context, VT)) {
668  case TypeLegal:
669  return VT;
670  case TypeExpandInteger:
671  VT = getTypeToTransformTo(Context, VT);
672  break;
673  default:
674  llvm_unreachable("Type is not legal nor is it to be expanded!");
675  }
676  }
677  }
678 
679  /// Vector types are broken down into some number of legal first class types.
680  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
681  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
682  /// turns into 4 EVT::i32 values with both PPC and X86.
683  ///
684  /// This method returns the number of registers needed, and the VT for each
685  /// register. It also returns the VT and quantity of the intermediate values
686  /// before they are promoted/expanded.
687  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
688  EVT &IntermediateVT,
689  unsigned &NumIntermediates,
690  MVT &RegisterVT) const;
691 
692  /// Certain targets such as MIPS require that some types such as vectors are
693  /// always broken down into scalars in some contexts. This occurs even if the
694  /// vector type is legal.
696  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
697  unsigned &NumIntermediates, MVT &RegisterVT) const {
698  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
699  RegisterVT);
700  }
701 
702  struct IntrinsicInfo {
703  unsigned opc = 0; // target opcode
704  EVT memVT; // memory VT
705 
706  // value representing memory location
708 
709  int offset = 0; // offset off of ptrVal
710  unsigned size = 0; // the size of the memory location
711  // (taken from memVT if zero)
712  unsigned align = 1; // alignment
713 
715  IntrinsicInfo() = default;
716  };
717 
718  /// Given an intrinsic, checks if on the target the intrinsic will need to map
719  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
720  /// true and store the intrinsic information into the IntrinsicInfo that was
721  /// passed to the function.
722  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
723  MachineFunction &,
724  unsigned /*Intrinsic*/) const {
725  return false;
726  }
727 
728  /// Returns true if the target can instruction select the specified FP
729  /// immediate natively. If false, the legalizer will materialize the FP
730  /// immediate as a load from a constant pool.
731  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
732  return false;
733  }
734 
735  /// Targets can use this to indicate that they only support *some*
736  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
737  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
738  /// legal.
739  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
740  return true;
741  }
742 
743  /// Returns true if the operation can trap for the value type.
744  ///
745  /// VT must be a legal type. By default, we optimistically assume most
746  /// operations don't trap except for integer divide and remainder.
747  virtual bool canOpTrap(unsigned Op, EVT VT) const;
748 
749  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
750  /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
751  /// a VAND with a constant pool entry.
752  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
753  EVT /*VT*/) const {
754  return false;
755  }
756 
757  /// Return how this operation should be treated: either it is legal, needs to
758  /// be promoted to a larger size, needs to be expanded to some other code
759  /// sequence, or the target has a custom expander for it.
760  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
761  if (VT.isExtended()) return Expand;
762  // If a target-specific SDNode requires legalization, require the target
763  // to provide custom legalization for it.
764  if (Op >= array_lengthof(OpActions[0])) return Custom;
765  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
766  }
767 
768  /// Return true if the specified operation is legal on this target or can be
769  /// made legal with custom lowering. This is used to help guide high-level
770  /// lowering decisions.
771  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
772  return (VT == MVT::Other || isTypeLegal(VT)) &&
773  (getOperationAction(Op, VT) == Legal ||
774  getOperationAction(Op, VT) == Custom);
775  }
776 
777  /// Return true if the specified operation is legal on this target or can be
778  /// made legal using promotion. This is used to help guide high-level lowering
779  /// decisions.
780  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
781  return (VT == MVT::Other || isTypeLegal(VT)) &&
782  (getOperationAction(Op, VT) == Legal ||
783  getOperationAction(Op, VT) == Promote);
784  }
785 
786  /// Return true if the specified operation is legal on this target or can be
787  /// made legal with custom lowering or using promotion. This is used to help
788  /// guide high-level lowering decisions.
789  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
790  return (VT == MVT::Other || isTypeLegal(VT)) &&
791  (getOperationAction(Op, VT) == Legal ||
792  getOperationAction(Op, VT) == Custom ||
793  getOperationAction(Op, VT) == Promote);
794  }
795 
796  /// Return true if the operation uses custom lowering, regardless of whether
797  /// the type is legal or not.
798  bool isOperationCustom(unsigned Op, EVT VT) const {
799  return getOperationAction(Op, VT) == Custom;
800  }
801 
802  /// Return true if lowering to a jump table is allowed.
803  virtual bool areJTsAllowed(const Function *Fn) const {
804  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
805  return false;
806 
807  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
808  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
809  }
810 
811  /// Check whether the range [Low,High] fits in a machine word.
812  bool rangeFitsInWord(const APInt &Low, const APInt &High,
813  const DataLayout &DL) const {
814  // FIXME: Using the pointer type doesn't seem ideal.
815  uint64_t BW = DL.getIndexSizeInBits(0u);
816  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
817  return Range <= BW;
818  }
819 
820  /// Return true if lowering to a jump table is suitable for a set of case
821  /// clusters which may contain \p NumCases cases, \p Range range of values.
822  /// FIXME: This function check the maximum table size and density, but the
823  /// minimum size is not checked. It would be nice if the minimum size is
824  /// also combined within this function. Currently, the minimum size check is
825  /// performed in findJumpTable() in SelectionDAGBuiler and
826  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
827  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
828  uint64_t Range) const {
829  const bool OptForSize = SI->getParent()->getParent()->optForSize();
830  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
831  const unsigned MaxJumpTableSize =
832  OptForSize || getMaximumJumpTableSize() == 0
833  ? UINT_MAX
834  : getMaximumJumpTableSize();
835  // Check whether a range of clusters is dense enough for a jump table.
836  if (Range <= MaxJumpTableSize &&
837  (NumCases * 100 >= Range * MinDensity)) {
838  return true;
839  }
840  return false;
841  }
842 
843  /// Return true if lowering to a bit test is suitable for a set of case
844  /// clusters which contains \p NumDests unique destinations, \p Low and
845  /// \p High as its lowest and highest case values, and expects \p NumCmps
846  /// case value comparisons. Check if the number of destinations, comparison
847  /// metric, and range are all suitable.
848  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
849  const APInt &Low, const APInt &High,
850  const DataLayout &DL) const {
851  // FIXME: I don't think NumCmps is the correct metric: a single case and a
852  // range of cases both require only one branch to lower. Just looking at the
853  // number of clusters and destinations should be enough to decide whether to
854  // build bit tests.
855 
856  // To lower a range with bit tests, the range must fit the bitwidth of a
857  // machine word.
858  if (!rangeFitsInWord(Low, High, DL))
859  return false;
860 
861  // Decide whether it's profitable to lower this range with bit tests. Each
862  // destination requires a bit test and branch, and there is an overall range
863  // check branch. For a small number of clusters, separate comparisons might
864  // be cheaper, and for many destinations, splitting the range might be
865  // better.
866  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
867  (NumDests == 3 && NumCmps >= 6);
868  }
869 
870  /// Return true if the specified operation is illegal on this target or
871  /// unlikely to be made legal with custom lowering. This is used to help guide
872  /// high-level lowering decisions.
873  bool isOperationExpand(unsigned Op, EVT VT) const {
874  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
875  }
876 
877  /// Return true if the specified operation is legal on this target.
878  bool isOperationLegal(unsigned Op, EVT VT) const {
879  return (VT == MVT::Other || isTypeLegal(VT)) &&
880  getOperationAction(Op, VT) == Legal;
881  }
882 
883  /// Return how this load with extension should be treated: either it is legal,
884  /// needs to be promoted to a larger size, needs to be expanded to some other
885  /// code sequence, or the target has a custom expander for it.
886  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
887  EVT MemVT) const {
888  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
889  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
890  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
891  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
892  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
893  unsigned Shift = 4 * ExtType;
894  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
895  }
896 
897  /// Return true if the specified load with extension is legal on this target.
898  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
899  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
900  }
901 
902  /// Return true if the specified load with extension is legal or custom
903  /// on this target.
904  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
905  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
906  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
907  }
908 
909  /// Return how this store with truncation should be treated: either it is
910  /// legal, needs to be promoted to a larger size, needs to be expanded to some
911  /// other code sequence, or the target has a custom expander for it.
913  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
914  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
915  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
917  "Table isn't big enough!");
918  return TruncStoreActions[ValI][MemI];
919  }
920 
921  /// Return true if the specified store with truncation is legal on this
922  /// target.
923  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
924  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
925  }
926 
927  /// Return true if the specified store with truncation has solution on this
928  /// target.
929  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
930  return isTypeLegal(ValVT) &&
931  (getTruncStoreAction(ValVT, MemVT) == Legal ||
932  getTruncStoreAction(ValVT, MemVT) == Custom);
933  }
934 
935  /// Return how the indexed load should be treated: either it is legal, needs
936  /// to be promoted to a larger size, needs to be expanded to some other code
937  /// sequence, or the target has a custom expander for it.
939  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
940  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
941  "Table isn't big enough!");
942  unsigned Ty = (unsigned)VT.SimpleTy;
943  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
944  }
945 
946  /// Return true if the specified indexed load is legal on this target.
947  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
948  return VT.isSimple() &&
949  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
950  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
951  }
952 
953  /// Return how the indexed store should be treated: either it is legal, needs
954  /// to be promoted to a larger size, needs to be expanded to some other code
955  /// sequence, or the target has a custom expander for it.
957  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
958  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
959  "Table isn't big enough!");
960  unsigned Ty = (unsigned)VT.SimpleTy;
961  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
962  }
963 
964  /// Return true if the specified indexed load is legal on this target.
965  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
966  return VT.isSimple() &&
967  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
968  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
969  }
970 
971  /// Return how the condition code should be treated: either it is legal, needs
972  /// to be expanded to some other code sequence, or the target has a custom
973  /// expander for it.
976  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
977  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
978  "Table isn't big enough!");
979  // See setCondCodeAction for how this is encoded.
980  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
981  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
982  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
983  assert(Action != Promote && "Can't promote condition code!");
984  return Action;
985  }
986 
987  /// Return true if the specified condition code is legal on this target.
988  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
989  return
990  getCondCodeAction(CC, VT) == Legal ||
991  getCondCodeAction(CC, VT) == Custom;
992  }
993 
994  /// If the action for this operation is to promote, this method returns the
995  /// ValueType to promote to.
996  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
997  assert(getOperationAction(Op, VT) == Promote &&
998  "This operation isn't promoted!");
999 
1000  // See if this has an explicit type specified.
1001  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1002  MVT::SimpleValueType>::const_iterator PTTI =
1003  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1004  if (PTTI != PromoteToType.end()) return PTTI->second;
1005 
1006  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1007  "Cannot autopromote this type, add it with AddPromotedToType.");
1008 
1009  MVT NVT = VT;
1010  do {
1011  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1012  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1013  "Didn't find type to promote to!");
1014  } while (!isTypeLegal(NVT) ||
1015  getOperationAction(Op, NVT) == Promote);
1016  return NVT;
1017  }
1018 
1019  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1020  /// operations except for the pointer size. If AllowUnknown is true, this
1021  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1022  /// otherwise it will assert.
1024  bool AllowUnknown = false) const {
1025  // Lower scalar pointers to native pointer types.
1026  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1027  return getPointerTy(DL, PTy->getAddressSpace());
1028 
1029  if (Ty->isVectorTy()) {
1030  VectorType *VTy = cast<VectorType>(Ty);
1031  Type *Elm = VTy->getElementType();
1032  // Lower vectors of pointers to native pointer types.
1033  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1034  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1035  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1036  }
1037 
1038  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1039  VTy->getNumElements());
1040  }
1041  return EVT::getEVT(Ty, AllowUnknown);
1042  }
1043 
1044  /// Return the MVT corresponding to this LLVM type. See getValueType.
1046  bool AllowUnknown = false) const {
1047  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1048  }
1049 
1050  /// Return the desired alignment for ByVal or InAlloca aggregate function
1051  /// arguments in the caller parameter area. This is the actual alignment, not
1052  /// its logarithm.
1053  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1054 
1055  /// Return the type of registers that this ValueType will eventually require.
1057  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1058  return RegisterTypeForVT[VT.SimpleTy];
1059  }
1060 
1061  /// Return the type of registers that this ValueType will eventually require.
1062  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1063  if (VT.isSimple()) {
1064  assert((unsigned)VT.getSimpleVT().SimpleTy <
1065  array_lengthof(RegisterTypeForVT));
1066  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1067  }
1068  if (VT.isVector()) {
1069  EVT VT1;
1070  MVT RegisterVT;
1071  unsigned NumIntermediates;
1072  (void)getVectorTypeBreakdown(Context, VT, VT1,
1073  NumIntermediates, RegisterVT);
1074  return RegisterVT;
1075  }
1076  if (VT.isInteger()) {
1077  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1078  }
1079  llvm_unreachable("Unsupported extended type!");
1080  }
1081 
1082  /// Return the number of registers that this ValueType will eventually
1083  /// require.
1084  ///
1085  /// This is one for any types promoted to live in larger registers, but may be
1086  /// more than one for types (like i64) that are split into pieces. For types
1087  /// like i140, which are first promoted then expanded, it is the number of
1088  /// registers needed to hold all the bits of the original type. For an i140
1089  /// on a 32 bit machine this means 5 registers.
1090  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1091  if (VT.isSimple()) {
1092  assert((unsigned)VT.getSimpleVT().SimpleTy <
1093  array_lengthof(NumRegistersForVT));
1094  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1095  }
1096  if (VT.isVector()) {
1097  EVT VT1;
1098  MVT VT2;
1099  unsigned NumIntermediates;
1100  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1101  }
1102  if (VT.isInteger()) {
1103  unsigned BitWidth = VT.getSizeInBits();
1104  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1105  return (BitWidth + RegWidth - 1) / RegWidth;
1106  }
1107  llvm_unreachable("Unsupported extended type!");
1108  }
1109 
1110  /// Certain combinations of ABIs, Targets and features require that types
1111  /// are legal for some operations and not for other operations.
1112  /// For MIPS all vector types must be passed through the integer register set.
1114  return getRegisterType(VT);
1115  }
1116 
1118  EVT VT) const {
1119  return getRegisterType(Context, VT);
1120  }
1121 
1122  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1123  /// this occurs when a vector type is used, as vector are passed through the
1124  /// integer register set.
1125  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1126  EVT VT) const {
1127  return getNumRegisters(Context, VT);
1128  }
1129 
1130  /// Certain targets have context senstive alignment requirements, where one
1131  /// type has the alignment requirement of another type.
1132  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1133  DataLayout DL) const {
1134  return DL.getABITypeAlignment(ArgTy);
1135  }
1136 
1137  /// If true, then instruction selection should seek to shrink the FP constant
1138  /// of the specified type to a smaller type in order to save space and / or
1139  /// reduce runtime.
1140  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1141 
1142  // Return true if it is profitable to reduce the given load node to a smaller
1143  // type.
1144  //
1145  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1147  ISD::LoadExtType ExtTy,
1148  EVT NewVT) const {
1149  return true;
1150  }
1151 
1152  /// When splitting a value of the specified type into parts, does the Lo
1153  /// or Hi part come first? This usually follows the endianness, except
1154  /// for ppcf128, where the Hi part always comes first.
1155  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1156  return DL.isBigEndian() || VT == MVT::ppcf128;
1157  }
1158 
1159  /// If true, the target has custom DAG combine transformations that it can
1160  /// perform for the specified node.
1162  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1163  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1164  }
1165 
1166  unsigned getGatherAllAliasesMaxDepth() const {
1167  return GatherAllAliasesMaxDepth;
1168  }
1169 
1170  /// Returns the size of the platform's va_list object.
1171  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1172  return getPointerTy(DL).getSizeInBits();
1173  }
1174 
1175  /// \brief Get maximum # of store operations permitted for llvm.memset
1176  ///
1177  /// This function returns the maximum number of store operations permitted
1178  /// to replace a call to llvm.memset. The value is set by the target at the
1179  /// performance threshold for such a replacement. If OptSize is true,
1180  /// return the limit for functions that have OptSize attribute.
1181  unsigned getMaxStoresPerMemset(bool OptSize) const {
1182  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1183  }
1184 
1185  /// \brief Get maximum # of store operations permitted for llvm.memcpy
1186  ///
1187  /// This function returns the maximum number of store operations permitted
1188  /// to replace a call to llvm.memcpy. The value is set by the target at the
1189  /// performance threshold for such a replacement. If OptSize is true,
1190  /// return the limit for functions that have OptSize attribute.
1191  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1192  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1193  }
1194 
1195  /// Get maximum # of load operations permitted for memcmp
1196  ///
1197  /// This function returns the maximum number of load operations permitted
1198  /// to replace a call to memcmp. The value is set by the target at the
1199  /// performance threshold for such a replacement. If OptSize is true,
1200  /// return the limit for functions that have OptSize attribute.
1201  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1202  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1203  }
1204 
1205  /// For memcmp expansion when the memcmp result is only compared equal or
1206  /// not-equal to 0, allow up to this number of load pairs per block. As an
1207  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1208  /// a0 = load2bytes &a[0]
1209  /// b0 = load2bytes &b[0]
1210  /// a2 = load1byte &a[2]
1211  /// b2 = load1byte &b[2]
1212  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1213  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1214  return 1;
1215  }
1216 
1217  /// \brief Get maximum # of store operations permitted for llvm.memmove
1218  ///
1219  /// This function returns the maximum number of store operations permitted
1220  /// to replace a call to llvm.memmove. The value is set by the target at the
1221  /// performance threshold for such a replacement. If OptSize is true,
1222  /// return the limit for functions that have OptSize attribute.
1223  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1224  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1225  }
1226 
1227  /// \brief Determine if the target supports unaligned memory accesses.
1228  ///
1229  /// This function returns true if the target allows unaligned memory accesses
1230  /// of the specified type in the given address space. If true, it also returns
1231  /// whether the unaligned memory access is "fast" in the last argument by
1232  /// reference. This is used, for example, in situations where an array
1233  /// copy/move/set is converted to a sequence of store operations. Its use
1234  /// helps to ensure that such replacements don't generate code that causes an
1235  /// alignment error (trap) on the target machine.
1237  unsigned AddrSpace = 0,
1238  unsigned Align = 1,
1239  bool * /*Fast*/ = nullptr) const {
1240  return false;
1241  }
1242 
1243  /// Return true if the target supports a memory access of this type for the
1244  /// given address space and alignment. If the access is allowed, the optional
1245  /// final parameter returns if the access is also fast (as defined by the
1246  /// target).
1247  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1248  unsigned AddrSpace = 0, unsigned Alignment = 1,
1249  bool *Fast = nullptr) const;
1250 
1251  /// Returns the target specific optimal type for load and store operations as
1252  /// a result of memset, memcpy, and memmove lowering.
1253  ///
1254  /// If DstAlign is zero that means it's safe to destination alignment can
1255  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1256  /// a need to check it against alignment requirement, probably because the
1257  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1258  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1259  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1260  /// does not need to be loaded. It returns EVT::Other if the type should be
1261  /// determined using generic target-independent logic.
1262  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1263  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1264  bool /*IsMemset*/,
1265  bool /*ZeroMemset*/,
1266  bool /*MemcpyStrSrc*/,
1267  MachineFunction &/*MF*/) const {
1268  return MVT::Other;
1269  }
1270 
1271  /// Returns true if it's safe to use load / store of the specified type to
1272  /// expand memcpy / memset inline.
1273  ///
1274  /// This is mostly true for all types except for some special cases. For
1275  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1276  /// fstpl which also does type conversion. Note the specified type doesn't
1277  /// have to be legal as the hook is used before type legalization.
1278  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1279 
1280  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1281  bool usesUnderscoreSetJmp() const {
1282  return UseUnderscoreSetJmp;
1283  }
1284 
1285  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1286  bool usesUnderscoreLongJmp() const {
1287  return UseUnderscoreLongJmp;
1288  }
1289 
1290  /// Return lower limit for number of blocks in a jump table.
1291  virtual unsigned getMinimumJumpTableEntries() const;
1292 
1293  /// Return lower limit of the density in a jump table.
1294  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1295 
1296  /// Return upper limit for number of entries in a jump table.
1297  /// Zero if no limit.
1298  unsigned getMaximumJumpTableSize() const;
1299 
1300  virtual bool isJumpTableRelative() const {
1301  return TM.isPositionIndependent();
1302  }
1303 
1304  /// If a physical register, this specifies the register that
1305  /// llvm.savestack/llvm.restorestack should save and restore.
1307  return StackPointerRegisterToSaveRestore;
1308  }
1309 
1310  /// If a physical register, this returns the register that receives the
1311  /// exception address on entry to an EH pad.
1312  virtual unsigned
1313  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1314  // 0 is guaranteed to be the NoRegister value on all targets
1315  return 0;
1316  }
1317 
1318  /// If a physical register, this returns the register that receives the
1319  /// exception typeid on entry to a landing pad.
1320  virtual unsigned
1321  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1322  // 0 is guaranteed to be the NoRegister value on all targets
1323  return 0;
1324  }
1325 
1326  virtual bool needsFixedCatchObjects() const {
1327  report_fatal_error("Funclet EH is not implemented for this target");
1328  }
1329 
1330  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1331  /// 200)
1332  unsigned getJumpBufSize() const {
1333  return JumpBufSize;
1334  }
1335 
1336  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1337  /// is 0)
1338  unsigned getJumpBufAlignment() const {
1339  return JumpBufAlignment;
1340  }
1341 
1342  /// Return the minimum stack alignment of an argument.
1343  unsigned getMinStackArgumentAlignment() const {
1344  return MinStackArgumentAlignment;
1345  }
1346 
1347  /// Return the minimum function alignment.
1348  unsigned getMinFunctionAlignment() const {
1349  return MinFunctionAlignment;
1350  }
1351 
1352  /// Return the preferred function alignment.
1353  unsigned getPrefFunctionAlignment() const {
1354  return PrefFunctionAlignment;
1355  }
1356 
1357  /// Return the preferred loop alignment.
1358  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1359  return PrefLoopAlignment;
1360  }
1361 
1362  /// If the target has a standard location for the stack protector guard,
1363  /// returns the address of that location. Otherwise, returns nullptr.
1364  /// DEPRECATED: please override useLoadStackGuardNode and customize
1365  /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1366  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1367 
1368  /// Inserts necessary declarations for SSP (stack protection) purpose.
1369  /// Should be used only when getIRStackGuard returns nullptr.
1370  virtual void insertSSPDeclarations(Module &M) const;
1371 
1372  /// Return the variable that's previously inserted by insertSSPDeclarations,
1373  /// if any, otherwise return nullptr. Should be used only when
1374  /// getIRStackGuard returns nullptr.
1375  virtual Value *getSDagStackGuard(const Module &M) const;
1376 
1377  /// If this function returns true, stack protection checks should XOR the
1378  /// frame pointer (or whichever pointer is used to address locals) into the
1379  /// stack guard value before checking it. getIRStackGuard must return nullptr
1380  /// if this returns true.
1381  virtual bool useStackGuardXorFP() const { return false; }
1382 
1383  /// If the target has a standard stack protection check function that
1384  /// performs validation and error handling, returns the function. Otherwise,
1385  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1386  /// Should be used only when getIRStackGuard returns nullptr.
1387  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1388 
1389 protected:
1390  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1391  bool UseTLS) const;
1392 
1393 public:
1394  /// Returns the target-specific address of the unsafe stack pointer.
1395  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1396 
1397  /// Returns the name of the symbol used to emit stack probes or the empty
1398  /// string if not applicable.
1400  return "";
1401  }
1402 
1403  /// Returns true if a cast between SrcAS and DestAS is a noop.
1404  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1405  return false;
1406  }
1407 
1408  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1409  /// are happy to sink it into basic blocks.
1410  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1411  return isNoopAddrSpaceCast(SrcAS, DestAS);
1412  }
1413 
1414  /// Return true if the pointer arguments to CI should be aligned by aligning
1415  /// the object whose address is being passed. If so then MinSize is set to the
1416  /// minimum size the object must be to be aligned and PrefAlign is set to the
1417  /// preferred alignment.
1418  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1419  unsigned & /*PrefAlign*/) const {
1420  return false;
1421  }
1422 
1423  //===--------------------------------------------------------------------===//
1424  /// \name Helpers for TargetTransformInfo implementations
1425  /// @{
1426 
1427  /// Get the ISD node that corresponds to the Instruction class opcode.
1428  int InstructionOpcodeToISD(unsigned Opcode) const;
1429 
1430  /// Estimate the cost of type-legalization and the legalized type.
1431  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1432  Type *Ty) const;
1433 
1434  /// @}
1435 
1436  //===--------------------------------------------------------------------===//
1437  /// \name Helpers for atomic expansion.
1438  /// @{
1439 
1440  /// Returns the maximum atomic operation size (in bits) supported by
1441  /// the backend. Atomic operations greater than this size (as well
1442  /// as ones that are not naturally aligned), will be expanded by
1443  /// AtomicExpandPass into an __atomic_* library call.
1445  return MaxAtomicSizeInBitsSupported;
1446  }
1447 
1448  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1449  /// the backend supports. Any smaller operations are widened in
1450  /// AtomicExpandPass.
1451  ///
1452  /// Note that *unlike* operations above the maximum size, atomic ops
1453  /// are still natively supported below the minimum; they just
1454  /// require a more complex expansion.
1455  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1456 
1457  /// Whether the target supports unaligned atomic operations.
1458  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1459 
1460  /// Whether AtomicExpandPass should automatically insert fences and reduce
1461  /// ordering for this atomic. This should be true for most architectures with
1462  /// weak memory ordering. Defaults to false.
1463  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1464  return false;
1465  }
1466 
1467  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1468  /// corresponding pointee type. This may entail some non-trivial operations to
1469  /// truncate or reconstruct types that will be illegal in the backend. See
1470  /// ARMISelLowering for an example implementation.
1471  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1472  AtomicOrdering Ord) const {
1473  llvm_unreachable("Load linked unimplemented on this target");
1474  }
1475 
1476  /// Perform a store-conditional operation to Addr. Return the status of the
1477  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1478  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1479  Value *Addr, AtomicOrdering Ord) const {
1480  llvm_unreachable("Store conditional unimplemented on this target");
1481  }
1482 
1483  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1484  /// It is called by AtomicExpandPass before expanding an
1485  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1486  /// if shouldInsertFencesForAtomic returns true.
1487  ///
1488  /// Inst is the original atomic instruction, prior to other expansions that
1489  /// may be performed.
1490  ///
1491  /// This function should either return a nullptr, or a pointer to an IR-level
1492  /// Instruction*. Even complex fence sequences can be represented by a
1493  /// single Instruction* through an intrinsic to be lowered later.
1494  /// Backends should override this method to produce target-specific intrinsic
1495  /// for their fences.
1496  /// FIXME: Please note that the default implementation here in terms of
1497  /// IR-level fences exists for historical/compatibility reasons and is
1498  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1499  /// consistency. For example, consider the following example:
1500  /// atomic<int> x = y = 0;
1501  /// int r1, r2, r3, r4;
1502  /// Thread 0:
1503  /// x.store(1);
1504  /// Thread 1:
1505  /// y.store(1);
1506  /// Thread 2:
1507  /// r1 = x.load();
1508  /// r2 = y.load();
1509  /// Thread 3:
1510  /// r3 = y.load();
1511  /// r4 = x.load();
1512  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1513  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1514  /// IR-level fences can prevent it.
1515  /// @{
1517  AtomicOrdering Ord) const {
1518  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1519  return Builder.CreateFence(Ord);
1520  else
1521  return nullptr;
1522  }
1523 
1525  Instruction *Inst,
1526  AtomicOrdering Ord) const {
1527  if (isAcquireOrStronger(Ord))
1528  return Builder.CreateFence(Ord);
1529  else
1530  return nullptr;
1531  }
1532  /// @}
1533 
1534  // Emits code that executes when the comparison result in the ll/sc
1535  // expansion of a cmpxchg instruction is such that the store-conditional will
1536  // not execute. This makes it possible to balance out the load-linked with
1537  // a dedicated instruction, if desired.
1538  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1539  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1540  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1541 
1542  /// Returns true if the given (atomic) store should be expanded by the
1543  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1545  return false;
1546  }
1547 
1548  /// Returns true if arguments should be sign-extended in lib calls.
1549  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1550  return IsSigned;
1551  }
1552 
1553  /// Returns how the given (atomic) load should be expanded by the
1554  /// IR-level AtomicExpand pass.
1557  }
1558 
1559  /// Returns true if the given atomic cmpxchg should be expanded by the
1560  /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1561  /// (through emitLoadLinked() and emitStoreConditional()).
1563  return false;
1564  }
1565 
1566  /// Returns how the IR-level AtomicExpand pass should expand the given
1567  /// AtomicRMW, if at all. Default is to never expand.
1570  }
1571 
1572  /// On some platforms, an AtomicRMW that never actually modifies the value
1573  /// (such as fetch_add of 0) can be turned into a fence followed by an
1574  /// atomic load. This may sound useless, but it makes it possible for the
1575  /// processor to keep the cacheline shared, dramatically improving
1576  /// performance. And such idempotent RMWs are useful for implementing some
1577  /// kinds of locks, see for example (justification + benchmarks):
1578  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1579  /// This method tries doing that transformation, returning the atomic load if
1580  /// it succeeds, and nullptr otherwise.
1581  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1582  /// another round of expansion.
1583  virtual LoadInst *
1585  return nullptr;
1586  }
1587 
1588  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1589  /// SIGN_EXTEND, or ANY_EXTEND).
1591  return ISD::ZERO_EXTEND;
1592  }
1593 
1594  /// @}
1595 
1596  /// Returns true if we should normalize
1597  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1598  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1599  /// that it saves us from materializing N0 and N1 in an integer register.
1600  /// Targets that are able to perform and/or on flags should return false here.
1602  EVT VT) const {
1603  // If a target has multiple condition registers, then it likely has logical
1604  // operations on those registers.
1605  if (hasMultipleConditionRegisters())
1606  return false;
1607  // Only do the transform if the value won't be split into multiple
1608  // registers.
1609  LegalizeTypeAction Action = getTypeAction(Context, VT);
1610  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1611  Action != TypeSplitVector;
1612  }
1613 
1614  /// Return true if a select of constants (select Cond, C1, C2) should be
1615  /// transformed into simple math ops with the condition value. For example:
1616  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1617  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1618  return false;
1619  }
1620 
1621  //===--------------------------------------------------------------------===//
1622  // TargetLowering Configuration Methods - These methods should be invoked by
1623  // the derived class constructor to configure this object for the target.
1624  //
1625 protected:
1626  /// Specify how the target extends the result of integer and floating point
1627  /// boolean values from i1 to a wider type. See getBooleanContents.
1629  BooleanContents = Ty;
1630  BooleanFloatContents = Ty;
1631  }
1632 
1633  /// Specify how the target extends the result of integer and floating point
1634  /// boolean values from i1 to a wider type. See getBooleanContents.
1636  BooleanContents = IntTy;
1637  BooleanFloatContents = FloatTy;
1638  }
1639 
1640  /// Specify how the target extends the result of a vector boolean value from a
1641  /// vector of i1 to a wider type. See getBooleanContents.
1643  BooleanVectorContents = Ty;
1644  }
1645 
1646  /// Specify the target scheduling preference.
1648  SchedPreferenceInfo = Pref;
1649  }
1650 
1651  /// Indicate whether this target prefers to use _setjmp to implement
1652  /// llvm.setjmp or the version without _. Defaults to false.
1653  void setUseUnderscoreSetJmp(bool Val) {
1654  UseUnderscoreSetJmp = Val;
1655  }
1656 
1657  /// Indicate whether this target prefers to use _longjmp to implement
1658  /// llvm.longjmp or the version without _. Defaults to false.
1659  void setUseUnderscoreLongJmp(bool Val) {
1660  UseUnderscoreLongJmp = Val;
1661  }
1662 
1663  /// Indicate the minimum number of blocks to generate jump tables.
1664  void setMinimumJumpTableEntries(unsigned Val);
1665 
1666  /// Indicate the maximum number of entries in jump tables.
1667  /// Set to zero to generate unlimited jump tables.
1668  void setMaximumJumpTableSize(unsigned);
1669 
1670  /// If set to a physical register, this specifies the register that
1671  /// llvm.savestack/llvm.restorestack should save and restore.
1673  StackPointerRegisterToSaveRestore = R;
1674  }
1675 
1676  /// Tells the code generator that the target has multiple (allocatable)
1677  /// condition registers that can be used to store the results of comparisons
1678  /// for use by selects and conditional branches. With multiple condition
1679  /// registers, the code generator will not aggressively sink comparisons into
1680  /// the blocks of their users.
1681  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1682  HasMultipleConditionRegisters = hasManyRegs;
1683  }
1684 
1685  /// Tells the code generator that the target has BitExtract instructions.
1686  /// The code generator will aggressively sink "shift"s into the blocks of
1687  /// their users if the users will generate "and" instructions which can be
1688  /// combined with "shift" to BitExtract instructions.
1689  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1690  HasExtractBitsInsn = hasExtractInsn;
1691  }
1692 
1693  /// Tells the code generator not to expand logic operations on comparison
1694  /// predicates into separate sequences that increase the amount of flow
1695  /// control.
1696  void setJumpIsExpensive(bool isExpensive = true);
1697 
1698  /// Tells the code generator that this target supports floating point
1699  /// exceptions and cares about preserving floating point exception behavior.
1700  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1701  HasFloatingPointExceptions = FPExceptions;
1702  }
1703 
1704  /// Tells the code generator which bitwidths to bypass.
1705  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1706  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1707  }
1708 
1709  /// Add the specified register class as an available regclass for the
1710  /// specified value type. This indicates the selector can handle values of
1711  /// that class natively.
1713  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1714  RegClassForVT[VT.SimpleTy] = RC;
1715  }
1716 
1717  /// Return the largest legal super-reg register class of the register class
1718  /// for the specified type and its associated "cost".
1719  virtual std::pair<const TargetRegisterClass *, uint8_t>
1720  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1721 
1722  /// Once all of the register classes are added, this allows us to compute
1723  /// derived properties we expose.
1724  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1725 
1726  /// Indicate that the specified operation does not work with the specified
1727  /// type and indicate what to do about it. Note that VT may refer to either
1728  /// the type of a result or that of an operand of Op.
1729  void setOperationAction(unsigned Op, MVT VT,
1730  LegalizeAction Action) {
1731  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1732  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1733  }
1734 
1735  /// Indicate that the specified load with extension does not work with the
1736  /// specified type and indicate what to do about it.
1737  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1738  LegalizeAction Action) {
1739  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1740  MemVT.isValid() && "Table isn't big enough!");
1741  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1742  unsigned Shift = 4 * ExtType;
1743  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1744  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1745  }
1746 
1747  /// Indicate that the specified truncating store does not work with the
1748  /// specified type and indicate what to do about it.
1749  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1750  LegalizeAction Action) {
1751  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1752  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1753  }
1754 
1755  /// Indicate that the specified indexed load does or does not work with the
1756  /// specified type and indicate what to do abort it.
1757  ///
1758  /// NOTE: All indexed mode loads are initialized to Expand in
1759  /// TargetLowering.cpp
1760  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1761  LegalizeAction Action) {
1762  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1763  (unsigned)Action < 0xf && "Table isn't big enough!");
1764  // Load action are kept in the upper half.
1765  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1766  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1767  }
1768 
1769  /// Indicate that the specified indexed store does or does not work with the
1770  /// specified type and indicate what to do about it.
1771  ///
1772  /// NOTE: All indexed mode stores are initialized to Expand in
1773  /// TargetLowering.cpp
1774  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1775  LegalizeAction Action) {
1776  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1777  (unsigned)Action < 0xf && "Table isn't big enough!");
1778  // Store action are kept in the lower half.
1779  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1780  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1781  }
1782 
1783  /// Indicate that the specified condition code is or isn't supported on the
1784  /// target and indicate what to do about it.
1786  LegalizeAction Action) {
1787  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1788  "Table isn't big enough!");
1789  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1790  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1791  /// value and the upper 29 bits index into the second dimension of the array
1792  /// to select what 32-bit value to use.
1793  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1794  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1795  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1796  }
1797 
1798  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1799  /// to trying a larger integer/fp until it can find one that works. If that
1800  /// default is insufficient, this method can be used by the target to override
1801  /// the default.
1802  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1803  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1804  }
1805 
1806  /// Convenience method to set an operation to Promote and specify the type
1807  /// in a single call.
1808  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1809  setOperationAction(Opc, OrigVT, Promote);
1810  AddPromotedToType(Opc, OrigVT, DestVT);
1811  }
1812 
1813  /// Targets should invoke this method for each target independent node that
1814  /// they want to provide a custom DAG combiner for by implementing the
1815  /// PerformDAGCombine virtual method.
1817  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1818  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1819  }
1820 
1821  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1822  void setJumpBufSize(unsigned Size) {
1823  JumpBufSize = Size;
1824  }
1825 
1826  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1827  /// 0
1828  void setJumpBufAlignment(unsigned Align) {
1829  JumpBufAlignment = Align;
1830  }
1831 
1832  /// Set the target's minimum function alignment (in log2(bytes))
1834  MinFunctionAlignment = Align;
1835  }
1836 
1837  /// Set the target's preferred function alignment. This should be set if
1838  /// there is a performance benefit to higher-than-minimum alignment (in
1839  /// log2(bytes))
1841  PrefFunctionAlignment = Align;
1842  }
1843 
1844  /// Set the target's preferred loop alignment. Default alignment is zero, it
1845  /// means the target does not care about loop alignment. The alignment is
1846  /// specified in log2(bytes). The target may also override
1847  /// getPrefLoopAlignment to provide per-loop values.
1848  void setPrefLoopAlignment(unsigned Align) {
1849  PrefLoopAlignment = Align;
1850  }
1851 
1852  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1854  MinStackArgumentAlignment = Align;
1855  }
1856 
1857  /// Set the maximum atomic operation size supported by the
1858  /// backend. Atomic operations greater than this size (as well as
1859  /// ones that are not naturally aligned), will be expanded by
1860  /// AtomicExpandPass into an __atomic_* library call.
1861  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1862  MaxAtomicSizeInBitsSupported = SizeInBits;
1863  }
1864 
1865  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1866  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1867  MinCmpXchgSizeInBits = SizeInBits;
1868  }
1869 
1870  /// Sets whether unaligned atomic operations are supported.
1871  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1872  SupportsUnalignedAtomics = UnalignedSupported;
1873  }
1874 
1875 public:
1876  //===--------------------------------------------------------------------===//
1877  // Addressing mode description hooks (used by LSR etc).
1878  //
1879 
1880  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1881  /// instructions reading the address. This allows as much computation as
1882  /// possible to be done in the address mode for that operand. This hook lets
1883  /// targets also pass back when this should be done on intrinsics which
1884  /// load/store.
1885  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1886  SmallVectorImpl<Value*> &/*Ops*/,
1887  Type *&/*AccessTy*/) const {
1888  return false;
1889  }
1890 
1891  /// This represents an addressing mode of:
1892  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1893  /// If BaseGV is null, there is no BaseGV.
1894  /// If BaseOffs is zero, there is no base offset.
1895  /// If HasBaseReg is false, there is no base register.
1896  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1897  /// no scale.
1898  struct AddrMode {
1899  GlobalValue *BaseGV = nullptr;
1900  int64_t BaseOffs = 0;
1901  bool HasBaseReg = false;
1902  int64_t Scale = 0;
1903  AddrMode() = default;
1904  };
1905 
1906  /// Return true if the addressing mode represented by AM is legal for this
1907  /// target, for a load/store of the specified type.
1908  ///
1909  /// The type may be VoidTy, in which case only return true if the addressing
1910  /// mode is legal for a load/store of any legal type. TODO: Handle
1911  /// pre/postinc as well.
1912  ///
1913  /// If the address space cannot be determined, it will be -1.
1914  ///
1915  /// TODO: Remove default argument
1916  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1917  Type *Ty, unsigned AddrSpace,
1918  Instruction *I = nullptr) const;
1919 
1920  /// \brief Return the cost of the scaling factor used in the addressing mode
1921  /// represented by AM for this target, for a load/store of the specified type.
1922  ///
1923  /// If the AM is supported, the return value must be >= 0.
1924  /// If the AM is not supported, it returns a negative value.
1925  /// TODO: Handle pre/postinc as well.
1926  /// TODO: Remove default argument
1927  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1928  Type *Ty, unsigned AS = 0) const {
1929  // Default: assume that any scaling factor used in a legal AM is free.
1930  if (isLegalAddressingMode(DL, AM, Ty, AS))
1931  return 0;
1932  return -1;
1933  }
1934 
1935  /// Return true if the specified immediate is legal icmp immediate, that is
1936  /// the target has icmp instructions which can compare a register against the
1937  /// immediate without having to materialize the immediate into a register.
1938  virtual bool isLegalICmpImmediate(int64_t) const {
1939  return true;
1940  }
1941 
1942  /// Return true if the specified immediate is legal add immediate, that is the
1943  /// target has add instructions which can add a register with the immediate
1944  /// without having to materialize the immediate into a register.
1945  virtual bool isLegalAddImmediate(int64_t) const {
1946  return true;
1947  }
1948 
1949  /// Return true if it's significantly cheaper to shift a vector by a uniform
1950  /// scalar than by an amount which will vary across each lane. On x86, for
1951  /// example, there is a "psllw" instruction for the former case, but no simple
1952  /// instruction for a general "a << b" operation on vectors.
1953  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1954  return false;
1955  }
1956 
1957  /// Returns true if the opcode is a commutative binary operation.
1958  virtual bool isCommutativeBinOp(unsigned Opcode) const {
1959  // FIXME: This should get its info from the td file.
1960  switch (Opcode) {
1961  case ISD::ADD:
1962  case ISD::SMIN:
1963  case ISD::SMAX:
1964  case ISD::UMIN:
1965  case ISD::UMAX:
1966  case ISD::MUL:
1967  case ISD::MULHU:
1968  case ISD::MULHS:
1969  case ISD::SMUL_LOHI:
1970  case ISD::UMUL_LOHI:
1971  case ISD::FADD:
1972  case ISD::FMUL:
1973  case ISD::AND:
1974  case ISD::OR:
1975  case ISD::XOR:
1976  case ISD::SADDO:
1977  case ISD::UADDO:
1978  case ISD::ADDC:
1979  case ISD::ADDE:
1980  case ISD::FMINNUM:
1981  case ISD::FMAXNUM:
1982  case ISD::FMINNAN:
1983  case ISD::FMAXNAN:
1984  return true;
1985  default: return false;
1986  }
1987  }
1988 
1989  /// Return true if it's free to truncate a value of type FromTy to type
1990  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1991  /// by referencing its sub-register AX.
1992  /// Targets must return false when FromTy <= ToTy.
1993  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1994  return false;
1995  }
1996 
1997  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1998  /// whether a call is in tail position. Typically this means that both results
1999  /// would be assigned to the same register or stack slot, but it could mean
2000  /// the target performs adequate checks of its own before proceeding with the
2001  /// tail call. Targets must return false when FromTy <= ToTy.
2002  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2003  return false;
2004  }
2005 
2006  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2007  return false;
2008  }
2009 
2010  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2011 
2012  /// Return true if the extension represented by \p I is free.
2013  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2014  /// this method can use the context provided by \p I to decide
2015  /// whether or not \p I is free.
2016  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2017  /// In other words, if is[Z|FP]Free returns true, then this method
2018  /// returns true as well. The converse is not true.
2019  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2020  /// \pre \p I must be a sign, zero, or fp extension.
2021  bool isExtFree(const Instruction *I) const {
2022  switch (I->getOpcode()) {
2023  case Instruction::FPExt:
2024  if (isFPExtFree(EVT::getEVT(I->getType()),
2025  EVT::getEVT(I->getOperand(0)->getType())))
2026  return true;
2027  break;
2028  case Instruction::ZExt:
2029  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2030  return true;
2031  break;
2032  case Instruction::SExt:
2033  break;
2034  default:
2035  llvm_unreachable("Instruction is not an extension");
2036  }
2037  return isExtFreeImpl(I);
2038  }
2039 
2040  /// Return true if \p Load and \p Ext can form an ExtLoad.
2041  /// For example, in AArch64
2042  /// %L = load i8, i8* %ptr
2043  /// %E = zext i8 %L to i32
2044  /// can be lowered into one load instruction
2045  /// ldrb w0, [x0]
2046  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2047  const DataLayout &DL) const {
2048  EVT VT = getValueType(DL, Ext->getType());
2049  EVT LoadVT = getValueType(DL, Load->getType());
2050 
2051  // If the load has other users and the truncate is not free, the ext
2052  // probably isn't free.
2053  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2054  !isTruncateFree(Ext->getType(), Load->getType()))
2055  return false;
2056 
2057  // Check whether the target supports casts folded into loads.
2058  unsigned LType;
2059  if (isa<ZExtInst>(Ext))
2060  LType = ISD::ZEXTLOAD;
2061  else {
2062  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2063  LType = ISD::SEXTLOAD;
2064  }
2065 
2066  return isLoadExtLegal(LType, VT, LoadVT);
2067  }
2068 
2069  /// Return true if any actual instruction that defines a value of type FromTy
2070  /// implicitly zero-extends the value to ToTy in the result register.
2071  ///
2072  /// The function should return true when it is likely that the truncate can
2073  /// be freely folded with an instruction defining a value of FromTy. If
2074  /// the defining instruction is unknown (because you're looking at a
2075  /// function argument, PHI, etc.) then the target may require an
2076  /// explicit truncate, which is not necessarily free, but this function
2077  /// does not deal with those cases.
2078  /// Targets must return false when FromTy >= ToTy.
2079  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2080  return false;
2081  }
2082 
2083  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2084  return false;
2085  }
2086 
2087  /// Return true if the target supplies and combines to a paired load
2088  /// two loaded values of type LoadedType next to each other in memory.
2089  /// RequiredAlignment gives the minimal alignment constraints that must be met
2090  /// to be able to select this paired load.
2091  ///
2092  /// This information is *not* used to generate actual paired loads, but it is
2093  /// used to generate a sequence of loads that is easier to combine into a
2094  /// paired load.
2095  /// For instance, something like this:
2096  /// a = load i64* addr
2097  /// b = trunc i64 a to i32
2098  /// c = lshr i64 a, 32
2099  /// d = trunc i64 c to i32
2100  /// will be optimized into:
2101  /// b = load i32* addr1
2102  /// d = load i32* addr2
2103  /// Where addr1 = addr2 +/- sizeof(i32).
2104  ///
2105  /// In other words, unless the target performs a post-isel load combining,
2106  /// this information should not be provided because it will generate more
2107  /// loads.
2108  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2109  unsigned & /*RequiredAlignment*/) const {
2110  return false;
2111  }
2112 
2113  /// \brief Get the maximum supported factor for interleaved memory accesses.
2114  /// Default to be the minimum interleave factor: 2.
2115  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2116 
2117  /// \brief Lower an interleaved load to target specific intrinsics. Return
2118  /// true on success.
2119  ///
2120  /// \p LI is the vector load instruction.
2121  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2122  /// \p Indices is the corresponding indices for each shufflevector.
2123  /// \p Factor is the interleave factor.
2124  virtual bool lowerInterleavedLoad(LoadInst *LI,
2126  ArrayRef<unsigned> Indices,
2127  unsigned Factor) const {
2128  return false;
2129  }
2130 
2131  /// \brief Lower an interleaved store to target specific intrinsics. Return
2132  /// true on success.
2133  ///
2134  /// \p SI is the vector store instruction.
2135  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2136  /// \p Factor is the interleave factor.
2138  unsigned Factor) const {
2139  return false;
2140  }
2141 
2142  /// Return true if zero-extending the specific node Val to type VT2 is free
2143  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2144  /// because it's folded such as X86 zero-extending loads).
2145  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2146  return isZExtFree(Val.getValueType(), VT2);
2147  }
2148 
2149  /// Return true if an fpext operation is free (for instance, because
2150  /// single-precision floating-point numbers are implicitly extended to
2151  /// double-precision).
2152  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2153  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2154  "invalid fpext types");
2155  return false;
2156  }
2157 
2158  /// Return true if an fpext operation input to an \p Opcode operation is free
2159  /// (for instance, because half-precision floating-point numbers are
2160  /// implicitly extended to float-precision) for an FMA instruction.
2161  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2162  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2163  "invalid fpext types");
2164  return isFPExtFree(DestVT, SrcVT);
2165  }
2166 
2167  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2168  /// extend node) is profitable.
2169  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2170 
2171  /// Return true if an fneg operation is free to the point where it is never
2172  /// worthwhile to replace it with a bitwise operation.
2173  virtual bool isFNegFree(EVT VT) const {
2174  assert(VT.isFloatingPoint());
2175  return false;
2176  }
2177 
2178  /// Return true if an fabs operation is free to the point where it is never
2179  /// worthwhile to replace it with a bitwise operation.
2180  virtual bool isFAbsFree(EVT VT) const {
2181  assert(VT.isFloatingPoint());
2182  return false;
2183  }
2184 
2185  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2186  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2187  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2188  ///
2189  /// NOTE: This may be called before legalization on types for which FMAs are
2190  /// not legal, but should return true if those types will eventually legalize
2191  /// to types that support FMAs. After legalization, it will only be called on
2192  /// types that support FMAs (via Legal or Custom actions)
2193  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2194  return false;
2195  }
2196 
2197  /// Return true if it's profitable to narrow operations of type VT1 to
2198  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2199  /// i32 to i16.
2200  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2201  return false;
2202  }
2203 
2204  /// \brief Return true if it is beneficial to convert a load of a constant to
2205  /// just the constant itself.
2206  /// On some targets it might be more efficient to use a combination of
2207  /// arithmetic instructions to materialize the constant instead of loading it
2208  /// from a constant pool.
2209  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2210  Type *Ty) const {
2211  return false;
2212  }
2213 
2214  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2215  /// from this source type with this index. This is needed because
2216  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2217  /// the first element, and only the target knows which lowering is cheap.
2218  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2219  unsigned Index) const {
2220  return false;
2221  }
2222 
2223  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2224  // even if the vector itself has multiple uses.
2225  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2226  return false;
2227  }
2228 
2229  //===--------------------------------------------------------------------===//
2230  // Runtime Library hooks
2231  //
2232 
2233  /// Rename the default libcall routine name for the specified libcall.
2234  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2235  LibcallRoutineNames[Call] = Name;
2236  }
2237 
2238  /// Get the libcall routine name for the specified libcall.
2239  const char *getLibcallName(RTLIB::Libcall Call) const {
2240  return LibcallRoutineNames[Call];
2241  }
2242 
2243  /// Override the default CondCode to be used to test the result of the
2244  /// comparison libcall against zero.
2246  CmpLibcallCCs[Call] = CC;
2247  }
2248 
2249  /// Get the CondCode that's to be used to test the result of the comparison
2250  /// libcall against zero.
2252  return CmpLibcallCCs[Call];
2253  }
2254 
2255  /// Set the CallingConv that should be used for the specified libcall.
2257  LibcallCallingConvs[Call] = CC;
2258  }
2259 
2260  /// Get the CallingConv that should be used for the specified libcall.
2262  return LibcallCallingConvs[Call];
2263  }
2264 
2265  /// Execute target specific actions to finalize target lowering.
2266  /// This is used to set extra flags in MachineFrameInformation and freezing
2267  /// the set of reserved registers.
2268  /// The default implementation just freezes the set of reserved registers.
2269  virtual void finalizeLowering(MachineFunction &MF) const;
2270 
2271 private:
2272  const TargetMachine &TM;
2273 
2274  /// Tells the code generator that the target has multiple (allocatable)
2275  /// condition registers that can be used to store the results of comparisons
2276  /// for use by selects and conditional branches. With multiple condition
2277  /// registers, the code generator will not aggressively sink comparisons into
2278  /// the blocks of their users.
2279  bool HasMultipleConditionRegisters;
2280 
2281  /// Tells the code generator that the target has BitExtract instructions.
2282  /// The code generator will aggressively sink "shift"s into the blocks of
2283  /// their users if the users will generate "and" instructions which can be
2284  /// combined with "shift" to BitExtract instructions.
2285  bool HasExtractBitsInsn;
2286 
2287  /// Tells the code generator to bypass slow divide or remainder
2288  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2289  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2290  /// div/rem when the operands are positive and less than 256.
2291  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2292 
2293  /// Tells the code generator that it shouldn't generate extra flow control
2294  /// instructions and should attempt to combine flow control instructions via
2295  /// predication.
2296  bool JumpIsExpensive;
2297 
2298  /// Whether the target supports or cares about preserving floating point
2299  /// exception behavior.
2300  bool HasFloatingPointExceptions;
2301 
2302  /// This target prefers to use _setjmp to implement llvm.setjmp.
2303  ///
2304  /// Defaults to false.
2305  bool UseUnderscoreSetJmp;
2306 
2307  /// This target prefers to use _longjmp to implement llvm.longjmp.
2308  ///
2309  /// Defaults to false.
2310  bool UseUnderscoreLongJmp;
2311 
2312  /// Information about the contents of the high-bits in boolean values held in
2313  /// a type wider than i1. See getBooleanContents.
2314  BooleanContent BooleanContents;
2315 
2316  /// Information about the contents of the high-bits in boolean values held in
2317  /// a type wider than i1. See getBooleanContents.
2318  BooleanContent BooleanFloatContents;
2319 
2320  /// Information about the contents of the high-bits in boolean vector values
2321  /// when the element type is wider than i1. See getBooleanContents.
2322  BooleanContent BooleanVectorContents;
2323 
2324  /// The target scheduling preference: shortest possible total cycles or lowest
2325  /// register usage.
2326  Sched::Preference SchedPreferenceInfo;
2327 
2328  /// The size, in bytes, of the target's jmp_buf buffers
2329  unsigned JumpBufSize;
2330 
2331  /// The alignment, in bytes, of the target's jmp_buf buffers
2332  unsigned JumpBufAlignment;
2333 
2334  /// The minimum alignment that any argument on the stack needs to have.
2335  unsigned MinStackArgumentAlignment;
2336 
2337  /// The minimum function alignment (used when optimizing for size, and to
2338  /// prevent explicitly provided alignment from leading to incorrect code).
2339  unsigned MinFunctionAlignment;
2340 
2341  /// The preferred function alignment (used when alignment unspecified and
2342  /// optimizing for speed).
2343  unsigned PrefFunctionAlignment;
2344 
2345  /// The preferred loop alignment.
2346  unsigned PrefLoopAlignment;
2347 
2348  /// Size in bits of the maximum atomics size the backend supports.
2349  /// Accesses larger than this will be expanded by AtomicExpandPass.
2350  unsigned MaxAtomicSizeInBitsSupported;
2351 
2352  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2353  /// backend supports.
2354  unsigned MinCmpXchgSizeInBits;
2355 
2356  /// This indicates if the target supports unaligned atomic operations.
2357  bool SupportsUnalignedAtomics;
2358 
2359  /// If set to a physical register, this specifies the register that
2360  /// llvm.savestack/llvm.restorestack should save and restore.
2361  unsigned StackPointerRegisterToSaveRestore;
2362 
2363  /// This indicates the default register class to use for each ValueType the
2364  /// target supports natively.
2365  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2366  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2367  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2368 
2369  /// This indicates the "representative" register class to use for each
2370  /// ValueType the target supports natively. This information is used by the
2371  /// scheduler to track register pressure. By default, the representative
2372  /// register class is the largest legal super-reg register class of the
2373  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2374  /// representative class would be GR32.
2375  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2376 
2377  /// This indicates the "cost" of the "representative" register class for each
2378  /// ValueType. The cost is used by the scheduler to approximate register
2379  /// pressure.
2380  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2381 
2382  /// For any value types we are promoting or expanding, this contains the value
2383  /// type that we are changing to. For Expanded types, this contains one step
2384  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2385  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2386  /// the same type (e.g. i32 -> i32).
2387  MVT TransformToType[MVT::LAST_VALUETYPE];
2388 
2389  /// For each operation and each value type, keep a LegalizeAction that
2390  /// indicates how instruction selection should deal with the operation. Most
2391  /// operations are Legal (aka, supported natively by the target), but
2392  /// operations that are not should be described. Note that operations on
2393  /// non-legal value types are not described here.
2395 
2396  /// For each load extension type and each value type, keep a LegalizeAction
2397  /// that indicates how instruction selection should deal with a load of a
2398  /// specific value type and extension type. Uses 4-bits to store the action
2399  /// for each of the 4 load ext types.
2400  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2401 
2402  /// For each value type pair keep a LegalizeAction that indicates whether a
2403  /// truncating store of a specific value type and truncating type is legal.
2405 
2406  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2407  /// that indicates how instruction selection should deal with the load /
2408  /// store.
2409  ///
2410  /// The first dimension is the value_type for the reference. The second
2411  /// dimension represents the various modes for load store.
2412  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2413 
2414  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2415  /// indicates how instruction selection should deal with the condition code.
2416  ///
2417  /// Because each CC action takes up 4 bits, we need to have the array size be
2418  /// large enough to fit all of the value types. This can be done by rounding
2419  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2420  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2421 
2422 protected:
2424 
2425 private:
2426  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2427 
2428  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2429  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2430  /// array.
2431  unsigned char
2432  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2433 
2434  /// For operations that must be promoted to a specific type, this holds the
2435  /// destination type. This map should be sparse, so don't hold it as an
2436  /// array.
2437  ///
2438  /// Targets add entries to this map with AddPromotedToType(..), clients access
2439  /// this with getTypeToPromoteTo(..).
2440  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2441  PromoteToType;
2442 
2443  /// Stores the name each libcall.
2444  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2445 
2446  /// The ISD::CondCode that should be used to test the result of each of the
2447  /// comparison libcall against zero.
2448  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2449 
2450  /// Stores the CallingConv that should be used for each libcall.
2451  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2452 
2453  /// Set default libcall names and calling conventions.
2454  void InitLibcalls(const Triple &TT);
2455 
2456 protected:
2457  /// Return true if the extension represented by \p I is free.
2458  /// \pre \p I is a sign, zero, or fp extension and
2459  /// is[Z|FP]ExtFree of the related types is not true.
2460  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2461 
2462  /// Depth that GatherAllAliases should should continue looking for chain
2463  /// dependencies when trying to find a more preferable chain. As an
2464  /// approximation, this should be more than the number of consecutive stores
2465  /// expected to be merged.
2467 
2468  /// \brief Specify maximum number of store instructions per memset call.
2469  ///
2470  /// When lowering \@llvm.memset this field specifies the maximum number of
2471  /// store operations that may be substituted for the call to memset. Targets
2472  /// must set this value based on the cost threshold for that target. Targets
2473  /// should assume that the memset will be done using as many of the largest
2474  /// store operations first, followed by smaller ones, if necessary, per
2475  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2476  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2477  /// store. This only applies to setting a constant array of a constant size.
2479 
2480  /// Maximum number of stores operations that may be substituted for the call
2481  /// to memset, used for functions with OptSize attribute.
2483 
2484  /// \brief Specify maximum bytes of store instructions per memcpy call.
2485  ///
2486  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2487  /// store operations that may be substituted for a call to memcpy. Targets
2488  /// must set this value based on the cost threshold for that target. Targets
2489  /// should assume that the memcpy will be done using as many of the largest
2490  /// store operations first, followed by smaller ones, if necessary, per
2491  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2492  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2493  /// and one 1-byte store. This only applies to copying a constant array of
2494  /// constant size.
2496 
2497  /// Maximum number of store operations that may be substituted for a call to
2498  /// memcpy, used for functions with OptSize attribute.
2502 
2503  /// \brief Specify maximum bytes of store instructions per memmove call.
2504  ///
2505  /// When lowering \@llvm.memmove this field specifies the maximum number of
2506  /// store instructions that may be substituted for a call to memmove. Targets
2507  /// must set this value based on the cost threshold for that target. Targets
2508  /// should assume that the memmove will be done using as many of the largest
2509  /// store operations first, followed by smaller ones, if necessary, per
2510  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2511  /// with 8-bit alignment would result in nine 1-byte stores. This only
2512  /// applies to copying a constant array of constant size.
2514 
2515  /// Maximum number of store instructions that may be substituted for a call to
2516  /// memmove, used for functions with OptSize attribute.
2518 
2519  /// Tells the code generator that select is more expensive than a branch if
2520  /// the branch is usually predicted right.
2522 
2523  /// \see enableExtLdPromotion.
2525 
2526  /// Return true if the value types that can be represented by the specified
2527  /// register class are all legal.
2528  bool isLegalRC(const TargetRegisterInfo &TRI,
2529  const TargetRegisterClass &RC) const;
2530 
2531  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2532  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2533  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2534  MachineBasicBlock *MBB) const;
2535 
2536  /// Replace/modify the XRay custom event operands with target-dependent
2537  /// details.
2538  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2539  MachineBasicBlock *MBB) const;
2540 };
2541 
2542 /// This class defines information used to lower LLVM code to legal SelectionDAG
2543 /// operators that the target instruction selector can accept natively.
2544 ///
2545 /// This class also defines callbacks that targets must implement to lower
2546 /// target-specific constructs to SelectionDAG operators.
2548 public:
2549  struct DAGCombinerInfo;
2550 
2551  TargetLowering(const TargetLowering &) = delete;
2552  TargetLowering &operator=(const TargetLowering &) = delete;
2553 
2554  /// NOTE: The TargetMachine owns TLOF.
2555  explicit TargetLowering(const TargetMachine &TM);
2556 
2557  bool isPositionIndependent() const;
2558 
2559  /// Returns true by value, base pointer and offset pointer and addressing mode
2560  /// by reference if the node's address can be legally represented as
2561  /// pre-indexed load / store address.
2562  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2563  SDValue &/*Offset*/,
2564  ISD::MemIndexedMode &/*AM*/,
2565  SelectionDAG &/*DAG*/) const {
2566  return false;
2567  }
2568 
2569  /// Returns true by value, base pointer and offset pointer and addressing mode
2570  /// by reference if this node can be combined with a load / store to form a
2571  /// post-indexed load / store.
2572  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2573  SDValue &/*Base*/,
2574  SDValue &/*Offset*/,
2575  ISD::MemIndexedMode &/*AM*/,
2576  SelectionDAG &/*DAG*/) const {
2577  return false;
2578  }
2579 
2580  /// Return the entry encoding for a jump table in the current function. The
2581  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2582  virtual unsigned getJumpTableEncoding() const;
2583 
2584  virtual const MCExpr *
2586  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2587  MCContext &/*Ctx*/) const {
2588  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2589  }
2590 
2591  /// Returns relocation base for the given PIC jumptable.
2592  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2593  SelectionDAG &DAG) const;
2594 
2595  /// This returns the relocation base for the given PIC jumptable, the same as
2596  /// getPICJumpTableRelocBase, but as an MCExpr.
2597  virtual const MCExpr *
2598  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2599  unsigned JTI, MCContext &Ctx) const;
2600 
2601  /// Return true if folding a constant offset with the given GlobalAddress is
2602  /// legal. It is frequently not legal in PIC relocation models.
2603  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2604 
2605  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2606  SDValue &Chain) const;
2607 
2608  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2609  SDValue &NewRHS, ISD::CondCode &CCCode,
2610  const SDLoc &DL) const;
2611 
2612  /// Returns a pair of (return value, chain).
2613  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2614  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2615  EVT RetVT, ArrayRef<SDValue> Ops,
2616  bool isSigned, const SDLoc &dl,
2617  bool doesNotReturn = false,
2618  bool isReturnValueUsed = true) const;
2619 
2620  /// Check whether parameters to a call that are passed in callee saved
2621  /// registers are the same as from the calling function. This needs to be
2622  /// checked for tail call eligibility.
2623  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2624  const uint32_t *CallerPreservedMask,
2625  const SmallVectorImpl<CCValAssign> &ArgLocs,
2626  const SmallVectorImpl<SDValue> &OutVals) const;
2627 
2628  //===--------------------------------------------------------------------===//
2629  // TargetLowering Optimization Methods
2630  //
2631 
2632  /// A convenience struct that encapsulates a DAG, and two SDValues for
2633  /// returning information from TargetLowering to its clients that want to
2634  /// combine.
2637  bool LegalTys;
2638  bool LegalOps;
2641 
2643  bool LT, bool LO) :
2644  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2645 
2646  bool LegalTypes() const { return LegalTys; }
2647  bool LegalOperations() const { return LegalOps; }
2648 
2650  Old = O;
2651  New = N;
2652  return true;
2653  }
2654  };
2655 
2656  /// Check to see if the specified operand of the specified instruction is a
2657  /// constant integer. If so, check to see if there are any bits set in the
2658  /// constant that are not demanded. If so, shrink the constant and return
2659  /// true.
2660  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2661  TargetLoweringOpt &TLO) const;
2662 
2663  // Target hook to do target-specific const optimization, which is called by
2664  // ShrinkDemandedConstant. This function should return true if the target
2665  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2666  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2667  TargetLoweringOpt &TLO) const {
2668  return false;
2669  }
2670 
2671  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2672  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2673  /// generalized for targets with other types of implicit widening casts.
2674  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2675  TargetLoweringOpt &TLO) const;
2676 
2677  /// Helper for SimplifyDemandedBits that can simplify an operation with
2678  /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2679  /// then updates \p User with the simplified version. No other uses of
2680  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2681  /// function behaves exactly like function SimplifyDemandedBits declared
2682  /// below except that it also updates the DAG by calling
2683  /// DCI.CommitTargetLoweringOpt.
2684  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2685  DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2686 
2687  /// Look at Op. At this point, we know that only the DemandedMask bits of the
2688  /// result of Op are ever used downstream. If we can use this information to
2689  /// simplify Op, create a new simplified DAG node and return true, returning
2690  /// the original and new nodes in Old and New. Otherwise, analyze the
2691  /// expression and return a mask of KnownOne and KnownZero bits for the
2692  /// expression (used to simplify the caller). The KnownZero/One bits may only
2693  /// be accurate for those bits in the DemandedMask.
2694  /// \p AssumeSingleUse When this parameter is true, this function will
2695  /// attempt to simplify \p Op even if there are multiple uses.
2696  /// Callers are responsible for correctly updating the DAG based on the
2697  /// results of this function, because simply replacing replacing TLO.Old
2698  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2699  /// has multiple uses.
2700  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2701  KnownBits &Known,
2702  TargetLoweringOpt &TLO,
2703  unsigned Depth = 0,
2704  bool AssumeSingleUse = false) const;
2705 
2706  /// Helper wrapper around SimplifyDemandedBits
2707  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2708  DAGCombinerInfo &DCI) const;
2709 
2710  /// Look at Vector Op. At this point, we know that only the DemandedElts
2711  /// elements of the result of Op are ever used downstream. If we can use
2712  /// this information to simplify Op, create a new simplified DAG node and
2713  /// return true, storing the original and new nodes in TLO.
2714  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2715  /// KnownZero elements for the expression (used to simplify the caller).
2716  /// The KnownUndef/Zero elements may only be accurate for those bits
2717  /// in the DemandedMask.
2718  /// \p AssumeSingleUse When this parameter is true, this function will
2719  /// attempt to simplify \p Op even if there are multiple uses.
2720  /// Callers are responsible for correctly updating the DAG based on the
2721  /// results of this function, because simply replacing replacing TLO.Old
2722  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2723  /// has multiple uses.
2724  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2725  APInt &KnownUndef, APInt &KnownZero,
2726  TargetLoweringOpt &TLO, unsigned Depth = 0,
2727  bool AssumeSingleUse = false) const;
2728 
2729  /// Helper wrapper around SimplifyDemandedVectorElts
2730  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2731  APInt &KnownUndef, APInt &KnownZero,
2732  DAGCombinerInfo &DCI) const;
2733 
2734  /// Determine which of the bits specified in Mask are known to be either zero
2735  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2736  /// argument allows us to only collect the known bits that are shared by the
2737  /// requested vector elements.
2738  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2739  KnownBits &Known,
2740  const APInt &DemandedElts,
2741  const SelectionDAG &DAG,
2742  unsigned Depth = 0) const;
2743 
2744  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2745  /// Default implementation computes low bits based on alignment
2746  /// information. This should preserve known bits passed into it.
2747  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2748  KnownBits &Known,
2749  const APInt &DemandedElts,
2750  const SelectionDAG &DAG,
2751  unsigned Depth = 0) const;
2752 
2753  /// This method can be implemented by targets that want to expose additional
2754  /// information about sign bits to the DAG Combiner. The DemandedElts
2755  /// argument allows us to only collect the minimum sign bits that are shared
2756  /// by the requested vector elements.
2757  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2758  const APInt &DemandedElts,
2759  const SelectionDAG &DAG,
2760  unsigned Depth = 0) const;
2761 
2762  /// Attempt to simplify any target nodes based on the demanded vector
2763  /// elements, returning true on success. Otherwise, analyze the expression and
2764  /// return a mask of KnownUndef and KnownZero elements for the expression
2765  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2766  /// accurate for those bits in the DemandedMask
2767  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2768  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2769  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2770 
2772  void *DC; // The DAG Combiner object.
2775 
2776  public:
2778 
2779  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2780  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2781 
2782  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2783  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2785  return Level == AfterLegalizeDAG;
2786  }
2788  bool isCalledByLegalizer() const { return CalledByLegalizer; }
2789 
2790  void AddToWorklist(SDNode *N);
2791  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2792  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2793  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2794 
2795  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2796  };
2797 
2798  /// Return if the N is a constant or constant vector equal to the true value
2799  /// from getBooleanContents().
2800  bool isConstTrueVal(const SDNode *N) const;
2801 
2802  /// Return if the N is a constant or constant vector equal to the false value
2803  /// from getBooleanContents().
2804  bool isConstFalseVal(const SDNode *N) const;
2805 
2806  /// Return if \p N is a True value when extended to \p VT.
2807  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2808 
2809  /// Try to simplify a setcc built with the specified operands and cc. If it is
2810  /// unable to simplify it, return a null SDValue.
2811  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2812  bool foldBooleans, DAGCombinerInfo &DCI,
2813  const SDLoc &dl) const;
2814 
2815  // For targets which wrap address, unwrap for analysis.
2816  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2817 
2818  /// Returns true (and the GlobalValue and the offset) if the node is a
2819  /// GlobalAddress + offset.
2820  virtual bool
2821  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2822 
2823  /// This method will be invoked for all target nodes and for any
2824  /// target-independent nodes that the target has registered with invoke it
2825  /// for.
2826  ///
2827  /// The semantics are as follows:
2828  /// Return Value:
2829  /// SDValue.Val == 0 - No change was made
2830  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2831  /// otherwise - N should be replaced by the returned Operand.
2832  ///
2833  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2834  /// more complex transformations.
2835  ///
2836  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2837 
2838  /// Return true if it is profitable to move a following shift through this
2839  // node, adjusting any immediate operands as necessary to preserve semantics.
2840  // This transformation may not be desirable if it disrupts a particularly
2841  // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2842  // By default, it returns true.
2843  virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2844  return true;
2845  }
2846 
2847  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2848  // to a shuffle and a truncate.
2849  // Example of such a combine:
2850  // v4i32 build_vector((extract_elt V, 1),
2851  // (extract_elt V, 3),
2852  // (extract_elt V, 5),
2853  // (extract_elt V, 7))
2854  // -->
2855  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2857  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2858  return false;
2859  }
2860 
2861  /// Return true if the target has native support for the specified value type
2862  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2863  /// i16 is legal, but undesirable since i16 instruction encodings are longer
2864  /// and some i16 instructions are slow.
2865  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2866  // By default, assume all legal types are desirable.
2867  return isTypeLegal(VT);
2868  }
2869 
2870  /// Return true if it is profitable for dag combiner to transform a floating
2871  /// point op of specified opcode to a equivalent op of an integer
2872  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2873  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2874  EVT /*VT*/) const {
2875  return false;
2876  }
2877 
2878  /// This method query the target whether it is beneficial for dag combiner to
2879  /// promote the specified node. If true, it should return the desired
2880  /// promotion type by reference.
2881  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2882  return false;
2883  }
2884 
2885  /// Return true if the target supports swifterror attribute. It optimizes
2886  /// loads and stores to reading and writing a specific register.
2887  virtual bool supportSwiftError() const {
2888  return false;
2889  }
2890 
2891  /// Return true if the target supports that a subset of CSRs for the given
2892  /// machine function is handled explicitly via copies.
2893  virtual bool supportSplitCSR(MachineFunction *MF) const {
2894  return false;
2895  }
2896 
2897  /// Perform necessary initialization to handle a subset of CSRs explicitly
2898  /// via copies. This function is called at the beginning of instruction
2899  /// selection.
2900  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2901  llvm_unreachable("Not Implemented");
2902  }
2903 
2904  /// Insert explicit copies in entry and exit blocks. We copy a subset of
2905  /// CSRs to virtual registers in the entry block, and copy them back to
2906  /// physical registers in the exit blocks. This function is called at the end
2907  /// of instruction selection.
2908  virtual void insertCopiesSplitCSR(
2909  MachineBasicBlock *Entry,
2910  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2911  llvm_unreachable("Not Implemented");
2912  }
2913 
2914  //===--------------------------------------------------------------------===//
2915  // Lowering methods - These methods must be implemented by targets so that
2916  // the SelectionDAGBuilder code knows how to lower these.
2917  //
2918 
2919  /// This hook must be implemented to lower the incoming (formal) arguments,
2920  /// described by the Ins array, into the specified DAG. The implementation
2921  /// should fill in the InVals array with legal-type argument values, and
2922  /// return the resulting token chain value.
2924  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2925  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
2926  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
2927  llvm_unreachable("Not Implemented");
2928  }
2929 
2930  /// This structure contains all information that is necessary for lowering
2931  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2932  /// needs to lower a call, and targets will see this struct in their LowerCall
2933  /// implementation.
2936  Type *RetTy = nullptr;
2937  bool RetSExt : 1;
2938  bool RetZExt : 1;
2939  bool IsVarArg : 1;
2940  bool IsInReg : 1;
2941  bool DoesNotReturn : 1;
2943  bool IsConvergent : 1;
2944  bool IsPatchPoint : 1;
2945 
2946  // IsTailCall should be modified by implementations of
2947  // TargetLowering::LowerCall that perform tail call conversions.
2948  bool IsTailCall = false;
2949 
2950  // Is Call lowering done post SelectionDAG type legalization.
2951  bool IsPostTypeLegalization = false;
2952 
2953  unsigned NumFixedArgs = -1;
2956  ArgListTy Args;
2964 
2966  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
2967  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
2968  IsPatchPoint(false), DAG(DAG) {}
2969 
2971  DL = dl;
2972  return *this;
2973  }
2974 
2976  Chain = InChain;
2977  return *this;
2978  }
2979 
2980  // setCallee with target/module-specific attributes
2982  SDValue Target, ArgListTy &&ArgsList) {
2983  RetTy = ResultType;
2984  Callee = Target;
2985  CallConv = CC;
2986  NumFixedArgs = ArgsList.size();
2987  Args = std::move(ArgsList);
2988 
2990  &(DAG.getMachineFunction()), CC, Args);
2991  return *this;
2992  }
2993 
2995  SDValue Target, ArgListTy &&ArgsList) {
2996  RetTy = ResultType;
2997  Callee = Target;
2998  CallConv = CC;
2999  NumFixedArgs = ArgsList.size();
3000  Args = std::move(ArgsList);
3001  return *this;
3002  }
3003 
3005  SDValue Target, ArgListTy &&ArgsList,
3006  ImmutableCallSite Call) {
3007  RetTy = ResultType;
3008 
3009  IsInReg = Call.hasRetAttr(Attribute::InReg);
3010  DoesNotReturn =
3011  Call.doesNotReturn() ||
3012  (!Call.isInvoke() &&
3013  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3014  IsVarArg = FTy->isVarArg();
3015  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3016  RetSExt = Call.hasRetAttr(Attribute::SExt);
3017  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3018 
3019  Callee = Target;
3020 
3021  CallConv = Call.getCallingConv();
3022  NumFixedArgs = FTy->getNumParams();
3023  Args = std::move(ArgsList);
3024 
3025  CS = Call;
3026 
3027  return *this;
3028  }
3029 
3031  IsInReg = Value;
3032  return *this;
3033  }
3034 
3036  DoesNotReturn = Value;
3037  return *this;
3038  }
3039 
3041  IsVarArg = Value;
3042  return *this;
3043  }
3044 
3046  IsTailCall = Value;
3047  return *this;
3048  }
3049 
3051  IsReturnValueUsed = !Value;
3052  return *this;
3053  }
3054 
3056  IsConvergent = Value;
3057  return *this;
3058  }
3059 
3061  RetSExt = Value;
3062  return *this;
3063  }
3064 
3066  RetZExt = Value;
3067  return *this;
3068  }
3069 
3071  IsPatchPoint = Value;
3072  return *this;
3073  }
3074 
3076  IsPostTypeLegalization = Value;
3077  return *this;
3078  }
3079 
3080  ArgListTy &getArgs() {
3081  return Args;
3082  }
3083  };
3084 
3085  /// This function lowers an abstract call to a function into an actual call.
3086  /// This returns a pair of operands. The first element is the return value
3087  /// for the function (if RetTy is not VoidTy). The second element is the
3088  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3089  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3090 
3091  /// This hook must be implemented to lower calls into the specified
3092  /// DAG. The outgoing arguments to the call are described by the Outs array,
3093  /// and the values to be returned by the call are described by the Ins
3094  /// array. The implementation should fill in the InVals array with legal-type
3095  /// return values from the call, and return the resulting token chain value.
3096  virtual SDValue
3098  SmallVectorImpl<SDValue> &/*InVals*/) const {
3099  llvm_unreachable("Not Implemented");
3100  }
3101 
3102  /// Target-specific cleanup for formal ByVal parameters.
3103  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3104 
3105  /// This hook should be implemented to check whether the return values
3106  /// described by the Outs array can fit into the return registers. If false
3107  /// is returned, an sret-demotion is performed.
3108  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3109  MachineFunction &/*MF*/, bool /*isVarArg*/,
3110  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3111  LLVMContext &/*Context*/) const
3112  {
3113  // Return true by default to get preexisting behavior.
3114  return true;
3115  }
3116 
3117  /// This hook must be implemented to lower outgoing return values, described
3118  /// by the Outs array, into the specified DAG. The implementation should
3119  /// return the resulting token chain value.
3120  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3121  bool /*isVarArg*/,
3122  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3123  const SmallVectorImpl<SDValue> & /*OutVals*/,
3124  const SDLoc & /*dl*/,
3125  SelectionDAG & /*DAG*/) const {
3126  llvm_unreachable("Not Implemented");
3127  }
3128 
3129  /// Return true if result of the specified node is used by a return node
3130  /// only. It also compute and return the input chain for the tail call.
3131  ///
3132  /// This is used to determine whether it is possible to codegen a libcall as
3133  /// tail call at legalization time.
3134  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3135  return false;
3136  }
3137 
3138  /// Return true if the target may be able emit the call instruction as a tail
3139  /// call. This is used by optimization passes to determine if it's profitable
3140  /// to duplicate return instructions to enable tailcall optimization.
3141  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3142  return false;
3143  }
3144 
3145  /// Return the builtin name for the __builtin___clear_cache intrinsic
3146  /// Default is to invoke the clear cache library call
3147  virtual const char * getClearCacheBuiltinName() const {
3148  return "__clear_cache";
3149  }
3150 
3151  /// Return the register ID of the name passed in. Used by named register
3152  /// global variables extension. There is no target-independent behaviour
3153  /// so the default action is to bail.
3154  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3155  SelectionDAG &DAG) const {
3156  report_fatal_error("Named registers not implemented for this target");
3157  }
3158 
3159  /// Return the type that should be used to zero or sign extend a
3160  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3161  /// require the return type to be promoted, but this is not true all the time,
3162  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3163  /// conventions. The frontend should handle this and include all of the
3164  /// necessary information.
3166  ISD::NodeType /*ExtendKind*/) const {
3167  EVT MinVT = getRegisterType(Context, MVT::i32);
3168  return VT.bitsLT(MinVT) ? MinVT : VT;
3169  }
3170 
3171  /// For some targets, an LLVM struct type must be broken down into multiple
3172  /// simple types, but the calling convention specifies that the entire struct
3173  /// must be passed in a block of consecutive registers.
3174  virtual bool
3176  bool isVarArg) const {
3177  return false;
3178  }
3179 
3180  /// Returns a 0 terminated array of registers that can be safely used as
3181  /// scratch registers.
3182  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3183  return nullptr;
3184  }
3185 
3186  /// This callback is used to prepare for a volatile or atomic load.
3187  /// It takes a chain node as input and returns the chain for the load itself.
3188  ///
3189  /// Having a callback like this is necessary for targets like SystemZ,
3190  /// which allows a CPU to reuse the result of a previous load indefinitely,
3191  /// even if a cache-coherent store is performed by another CPU. The default
3192  /// implementation does nothing.
3194  SelectionDAG &DAG) const {
3195  return Chain;
3196  }
3197 
3198  /// This callback is used to inspect load/store instructions and add
3199  /// target-specific MachineMemOperand flags to them. The default
3200  /// implementation does nothing.
3203  }
3204 
3205  /// This callback is invoked by the type legalizer to legalize nodes with an
3206  /// illegal operand type but legal result types. It replaces the
3207  /// LowerOperation callback in the type Legalizer. The reason we can not do
3208  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3209  /// use this callback.
3210  ///
3211  /// TODO: Consider merging with ReplaceNodeResults.
3212  ///
3213  /// The target places new result values for the node in Results (their number
3214  /// and types must exactly match those of the original return values of
3215  /// the node), or leaves Results empty, which indicates that the node is not
3216  /// to be custom lowered after all.
3217  /// The default implementation calls LowerOperation.
3218  virtual void LowerOperationWrapper(SDNode *N,
3220  SelectionDAG &DAG) const;
3221 
3222  /// This callback is invoked for operations that are unsupported by the
3223  /// target, which are registered to use 'custom' lowering, and whose defined
3224  /// values are all legal. If the target has no operations that require custom
3225  /// lowering, it need not implement this. The default implementation of this
3226  /// aborts.
3227  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3228 
3229  /// This callback is invoked when a node result type is illegal for the
3230  /// target, and the operation was registered to use 'custom' lowering for that
3231  /// result type. The target places new result values for the node in Results
3232  /// (their number and types must exactly match those of the original return
3233  /// values of the node), or leaves Results empty, which indicates that the
3234  /// node is not to be custom lowered after all.
3235  ///
3236  /// If the target has no operations that require custom lowering, it need not
3237  /// implement this. The default implementation aborts.
3238  virtual void ReplaceNodeResults(SDNode * /*N*/,
3239  SmallVectorImpl<SDValue> &/*Results*/,
3240  SelectionDAG &/*DAG*/) const {
3241  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3242  }
3243 
3244  /// This method returns the name of a target specific DAG node.
3245  virtual const char *getTargetNodeName(unsigned Opcode) const;
3246 
3247  /// This method returns a target specific FastISel object, or null if the
3248  /// target does not support "fast" ISel.
3250  const TargetLibraryInfo *) const {
3251  return nullptr;
3252  }
3253 
3254  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3255  SelectionDAG &DAG) const;
3256 
3257  //===--------------------------------------------------------------------===//
3258  // Inline Asm Support hooks
3259  //
3260 
3261  /// This hook allows the target to expand an inline asm call to be explicit
3262  /// llvm code if it wants to. This is useful for turning simple inline asms
3263  /// into LLVM intrinsics, which gives the compiler more information about the
3264  /// behavior of the code.
3265  virtual bool ExpandInlineAsm(CallInst *) const {
3266  return false;
3267  }
3268 
3270  C_Register, // Constraint represents specific register(s).
3271  C_RegisterClass, // Constraint represents any of register(s) in class.
3272  C_Memory, // Memory constraint.
3273  C_Other, // Something else.
3274  C_Unknown // Unsupported constraint.
3275  };
3276 
3278  // Generic weights.
3279  CW_Invalid = -1, // No match.
3280  CW_Okay = 0, // Acceptable.
3281  CW_Good = 1, // Good weight.
3282  CW_Better = 2, // Better weight.
3283  CW_Best = 3, // Best weight.
3284 
3285  // Well-known weights.
3286  CW_SpecificReg = CW_Okay, // Specific register operands.
3287  CW_Register = CW_Good, // Register operands.
3288  CW_Memory = CW_Better, // Memory operands.
3289  CW_Constant = CW_Best, // Constant operand.
3290  CW_Default = CW_Okay // Default or don't know type.
3291  };
3292 
3293  /// This contains information for each constraint that we are lowering.
3295  /// This contains the actual string for the code, like "m". TargetLowering
3296  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3297  /// matches the operand.
3298  std::string ConstraintCode;
3299 
3300  /// Information about the constraint code, e.g. Register, RegisterClass,
3301  /// Memory, Other, Unknown.
3303 
3304  /// If this is the result output operand or a clobber, this is null,
3305  /// otherwise it is the incoming operand to the CallInst. This gets
3306  /// modified as the asm is processed.
3307  Value *CallOperandVal = nullptr;
3308 
3309  /// The ValueType for the operand value.
3310  MVT ConstraintVT = MVT::Other;
3311 
3312  /// Copy constructor for copying from a ConstraintInfo.
3314  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3315 
3316  /// Return true of this is an input operand that is a matching constraint
3317  /// like "4".
3318  bool isMatchingInputConstraint() const;
3319 
3320  /// If this is an input matching constraint, this method returns the output
3321  /// operand it matches.
3322  unsigned getMatchedOperand() const;
3323  };
3324 
3325  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3326 
3327  /// Split up the constraint string from the inline assembly value into the
3328  /// specific constraints and their prefixes, and also tie in the associated
3329  /// operand values. If this returns an empty vector, and if the constraint
3330  /// string itself isn't empty, there was an error parsing.
3331  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3332  const TargetRegisterInfo *TRI,
3333  ImmutableCallSite CS) const;
3334 
3335  /// Examine constraint type and operand type and determine a weight value.
3336  /// The operand object must already have been set up with the operand type.
3337  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3338  AsmOperandInfo &info, int maIndex) const;
3339 
3340  /// Examine constraint string and operand type and determine a weight value.
3341  /// The operand object must already have been set up with the operand type.
3342  virtual ConstraintWeight getSingleConstraintMatchWeight(
3343  AsmOperandInfo &info, const char *constraint) const;
3344 
3345  /// Determines the constraint code and constraint type to use for the specific
3346  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3347  /// If the actual operand being passed in is available, it can be passed in as
3348  /// Op, otherwise an empty SDValue can be passed.
3349  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3350  SDValue Op,
3351  SelectionDAG *DAG = nullptr) const;
3352 
3353  /// Given a constraint, return the type of constraint it is for this target.
3354  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3355 
3356  /// Given a physical register constraint (e.g. {edx}), return the register
3357  /// number and the register class for the register.
3358  ///
3359  /// Given a register class constraint, like 'r', if this corresponds directly
3360  /// to an LLVM register class, return a register of 0 and the register class
3361  /// pointer.
3362  ///
3363  /// This should only be used for C_Register constraints. On error, this
3364  /// returns a register number of 0 and a null register class pointer.
3365  virtual std::pair<unsigned, const TargetRegisterClass *>
3366  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3367  StringRef Constraint, MVT VT) const;
3368 
3369  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3370  if (ConstraintCode == "i")
3371  return InlineAsm::Constraint_i;
3372  else if (ConstraintCode == "m")
3373  return InlineAsm::Constraint_m;
3375  }
3376 
3377  /// Try to replace an X constraint, which matches anything, with another that
3378  /// has more specific requirements based on the type of the corresponding
3379  /// operand. This returns null if there is no replacement to make.
3380  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3381 
3382  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3383  /// add anything to Ops.
3384  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3385  std::vector<SDValue> &Ops,
3386  SelectionDAG &DAG) const;
3387 
3388  //===--------------------------------------------------------------------===//
3389  // Div utility functions
3390  //
3391  SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3392  bool IsAfterLegalization,
3393  std::vector<SDNode *> *Created) const;
3394  SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3395  bool IsAfterLegalization,
3396  std::vector<SDNode *> *Created) const;
3397 
3398  /// Targets may override this function to provide custom SDIV lowering for
3399  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3400  /// assumes SDIV is expensive and replaces it with a series of other integer
3401  /// operations.
3402  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3403  SelectionDAG &DAG,
3404  std::vector<SDNode *> *Created) const;
3405 
3406  /// Indicate whether this target prefers to combine FDIVs with the same
3407  /// divisor. If the transform should never be done, return zero. If the
3408  /// transform should be done, return the minimum number of divisor uses
3409  /// that must exist.
3410  virtual unsigned combineRepeatedFPDivisors() const {
3411  return 0;
3412  }
3413 
3414  /// Hooks for building estimates in place of slower divisions and square
3415  /// roots.
3416 
3417  /// Return either a square root or its reciprocal estimate value for the input
3418  /// operand.
3419  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3420  /// 'Enabled' as set by a potential default override attribute.
3421  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3422  /// refinement iterations required to generate a sufficient (though not
3423  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3424  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3425  /// algorithm implementation that uses either one or two constants.
3426  /// The boolean Reciprocal is used to select whether the estimate is for the
3427  /// square root of the input operand or the reciprocal of its square root.
3428  /// A target may choose to implement its own refinement within this function.
3429  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3430  /// any further refinement of the estimate.
3431  /// An empty SDValue return means no estimate sequence can be created.
3433  int Enabled, int &RefinementSteps,
3434  bool &UseOneConstNR, bool Reciprocal) const {
3435  return SDValue();
3436  }
3437 
3438  /// Return a reciprocal estimate value for the input operand.
3439  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3440  /// 'Enabled' as set by a potential default override attribute.
3441  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3442  /// refinement iterations required to generate a sufficient (though not
3443  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3444  /// A target may choose to implement its own refinement within this function.
3445  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3446  /// any further refinement of the estimate.
3447  /// An empty SDValue return means no estimate sequence can be created.
3449  int Enabled, int &RefinementSteps) const {
3450  return SDValue();
3451  }
3452 
3453  //===--------------------------------------------------------------------===//
3454  // Legalization utility functions
3455  //
3456 
3457  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3458  /// respectively, each computing an n/2-bit part of the result.
3459  /// \param Result A vector that will be filled with the parts of the result
3460  /// in little-endian order.
3461  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3462  /// if you want to control how low bits are extracted from the LHS.
3463  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3464  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3465  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3466  /// \returns true if the node has been expanded, false if it has not
3467  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3468  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3470  SDValue LL = SDValue(), SDValue LH = SDValue(),
3471  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3472 
3473  /// Expand a MUL into two nodes. One that computes the high bits of
3474  /// the result and one that computes the low bits.
3475  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3476  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3477  /// if you want to control how low bits are extracted from the LHS.
3478  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3479  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3480  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3481  /// \returns true if the node has been expanded. false if it has not
3482  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3483  SelectionDAG &DAG, MulExpansionKind Kind,
3484  SDValue LL = SDValue(), SDValue LH = SDValue(),
3485  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3486 
3487  /// Expand float(f32) to SINT(i64) conversion
3488  /// \param N Node to expand
3489  /// \param Result output after conversion
3490  /// \returns True, if the expansion was successful, false otherwise
3491  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3492 
3493  /// Turn load of vector type into a load of the individual elements.
3494  /// \param LD load to expand
3495  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3496  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3497 
3498  // Turn a store of a vector type into stores of the individual elements.
3499  /// \param ST Store with a vector value type
3500  /// \returns MERGE_VALUs of the individual store chains.
3501  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3502 
3503  /// Expands an unaligned load to 2 half-size loads for an integer, and
3504  /// possibly more for vectors.
3505  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3506  SelectionDAG &DAG) const;
3507 
3508  /// Expands an unaligned store to 2 half-size stores for integer values, and
3509  /// possibly more for vectors.
3510  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3511 
3512  /// Increments memory address \p Addr according to the type of the value
3513  /// \p DataVT that should be stored. If the data is stored in compressed
3514  /// form, the memory address should be incremented according to the number of
3515  /// the stored elements. This number is equal to the number of '1's bits
3516  /// in the \p Mask.
3517  /// \p DataVT is a vector type. \p Mask is a vector value.
3518  /// \p DataVT and \p Mask have the same number of vector elements.
3519  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3520  EVT DataVT, SelectionDAG &DAG,
3521  bool IsCompressedMemory) const;
3522 
3523  /// Get a pointer to vector element \p Idx located in memory for a vector of
3524  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3525  /// bounds the returned pointer is unspecified, but will be within the vector
3526  /// bounds.
3527  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3528  SDValue Idx) const;
3529 
3530  //===--------------------------------------------------------------------===//
3531  // Instruction Emitting Hooks
3532  //
3533 
3534  /// This method should be implemented by targets that mark instructions with
3535  /// the 'usesCustomInserter' flag. These instructions are special in various
3536  /// ways, which require special support to insert. The specified MachineInstr
3537  /// is created but not inserted into any basic blocks, and this method is
3538  /// called to expand it into a sequence of instructions, potentially also
3539  /// creating new basic blocks and control flow.
3540  /// As long as the returned basic block is different (i.e., we created a new
3541  /// one), the custom inserter is free to modify the rest of \p MBB.
3542  virtual MachineBasicBlock *
3543  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3544 
3545  /// This method should be implemented by targets that mark instructions with
3546  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3547  /// instruction selection by target hooks. e.g. To fill in optional defs for
3548  /// ARM 's' setting instructions.
3549  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3550  SDNode *Node) const;
3551 
3552  /// If this function returns true, SelectionDAGBuilder emits a
3553  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3554  virtual bool useLoadStackGuardNode() const {
3555  return false;
3556  }
3557 
3559  const SDLoc &DL) const {
3560  llvm_unreachable("not implemented for this target");
3561  }
3562 
3563  /// Lower TLS global address SDNode for target independent emulated TLS model.
3564  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3565  SelectionDAG &DAG) const;
3566 
3567  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3568  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3569  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3570  // combiner can fold the new nodes.
3571  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3572 
3573 private:
3574  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3575  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3576  const SDLoc &DL) const;
3577 };
3578 
3579 /// Given an LLVM IR type and return type attributes, compute the return value
3580 /// EVTs and flags, and optionally also the offsets, if the return value is
3581 /// being lowered to memory.
3584  const TargetLowering &TLI, const DataLayout &DL);
3585 
3586 } // end namespace llvm
3587 
3588 #endif // LLVM_CODEGEN_TARGETLOWERING_H
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
virtual MVT getRegisterTypeForCallingConv(MVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:570
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, EVT VT) const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:355
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:236
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:312
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static ISD::NodeType getExtendForContent(BooleanContent Content)
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:350
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
An instruction for reading from memory.
Definition: Instructions.h:164
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:360
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:256
void * PointerTy
Definition: GenericValue.h:22
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:497
Definition: BitVector.h:920
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:707
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:61
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:387
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:306
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:154
Class to represent pointers.
Definition: DerivedTypes.h:467
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:42
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:893
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:16
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:576
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:471
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:90
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:393
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:900
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:721
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:713
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
static bool Enabled
Definition: Statistic.cpp:51
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Class to represent vector types.
Definition: DerivedTypes.h:393
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:69
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform&#39;s va_list object.
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
LegalizeTypeAction getTypeAction(MVT VT) const
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:446
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:172
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:449
ValueTypeActionImpl ValueTypeActions
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
virtual bool needsFixedCatchObjects() const
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:573
Flags
Flags values. These may be or&#39;d together.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool useSoftFloat() const
CallLoweringInfo & setTailCall(bool Value=true)
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:606
virtual bool isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const
Similar to isShuffleMaskLegal.
Representation of each machine instruction.
Definition: MachineInstr.h:60
Basic Alias true
CallLoweringInfo & setConvergent(bool Value=true)
SmallVector< SDValue, 32 > OutVals
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, EVT VT) const
Certain targets require unusual breakdowns of certain types.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1248
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
const ValueTypeActionImpl & getValueTypeActions() const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
void setTypeAction(MVT VT, LegalizeTypeAction Action)
bool isPositionIndependent() const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const
Insert explicit copies in entry and exit blocks.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:582
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
Establish a view to a call site for examination.
Definition: CallSite.h:713
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that&#39;s to be used to test the result of the comparison libcall against zero...
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:881
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:312
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
const unsigned Kind
Multiway switch.
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void GetReturnInfo(Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
unsigned getMinFunctionAlignment() const
Return the minimum function alignment.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual unsigned getMemcmpEqZeroLoadsPerBlock() const
For memcmp expansion when the memcmp result is only compared equal or not-equal to 0...
CallLoweringInfo & setInRegister(bool Value=true)
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:372
LLVM Value Representation.
Definition: Value.h:73
void setUseUnderscoreSetJmp(bool Val)
Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _...
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
bool isOperationLegalOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal using promotion...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal on this target.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
virtual bool mergeStoresAfterLegalization() const
Allow store merging after legalization in addition to before legalization.
Type * getElementType() const
Definition: DerivedTypes.h:360
virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
IRTranslator LLVM IR MI
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:418
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
virtual bool isShuffleMaskLegal(ArrayRef< int >, EVT) const
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
Conversion operators.
Definition: ISDOpcodes.h:443
BooleanContent
Enum that describes how the target represents true/false values.
unsigned getGatherAllAliasesMaxDepth() const
bool isBigEndian() const
Definition: DataLayout.h:220
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
bool hasTargetDAGCombine(ISD::NodeType NT) const
If true, the target has custom DAG combine transformations that it can perform for the specified node...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
virtual bool hasBitPreservingFPLogic(EVT VT) const
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array...
virtual bool shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool isLegalAddImmediate(int64_t) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
virtual bool isDesirableToCommuteWithShift(const SDNode *N) const
Return true if it is profitable to move a following shift through this.
The operation is expected to be selectable directly by the target, and no transformation is necessary...
Definition: LegalizerInfo.h:42
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
bool use_empty() const
Definition: Value.h:328
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
Definition: ValueTypes.h:131
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool isOperationExpand(unsigned Op, EVT VT) const
Return true if the specified operation is illegal on this target or unlikely to be made legal with cu...
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
LegalizeTypeAction getTypeAction(MVT VT) const
virtual bool isNarrowingProfitable(EVT, EVT) const
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
virtual bool isFAbsFree(EVT VT) const
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
const BasicBlock * getParent() const
Definition: Instruction.h:67
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
virtual Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:873
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
BRIND - Indirect branch.
Definition: ISDOpcodes.h:602
This class is used to represent ISD::LOAD nodes.
bool isPredictableSelectExpensive() const
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right...
bool isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
Return true if Load and Ext can form an ExtLoad.