LLVM  7.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file describes how to lower LLVM code to machine code. This has two
12 /// main components:
13 ///
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
17 ///
18 /// In addition it has a few other components, like information about FP
19 /// immediates.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
25 
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/CallSite.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/IRBuilder.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h"
50 #include "llvm/IR/Type.h"
51 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class IntrinsicInst;
77 struct KnownBits;
78 class LLVMContext;
79 class MachineBasicBlock;
80 class MachineFunction;
81 class MachineInstr;
82 class MachineJumpTableInfo;
83 class MachineLoop;
84 class MachineRegisterInfo;
85 class MCContext;
86 class MCExpr;
87 class Module;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
91 class Value;
92 
93 namespace Sched {
94 
95  enum Preference {
96  None, // No preference
97  Source, // Follow source order.
98  RegPressure, // Scheduling for lowest register pressure.
99  Hybrid, // Scheduling for both latency and register pressure.
100  ILP, // Scheduling for ILP in low register pressure mode.
101  VLIW // Scheduling for VLIW targets.
102  };
103 
104 } // end namespace Sched
105 
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
109 public:
110  /// This enum indicates whether operations are valid for a target, and if not,
111  /// what action should be used to make them valid.
112  enum LegalizeAction : uint8_t {
113  Legal, // The target natively supports this operation.
114  Promote, // This operation should be executed in a larger type.
115  Expand, // Try to expand this to other ops, otherwise use a libcall.
116  LibCall, // Don't try to expand this to other ops, always use a libcall.
117  Custom // Use the LowerOperation hook to implement custom lowering.
118  };
119 
120  /// This enum indicates whether a types are legal for a target, and if not,
121  /// what action should be used to make them valid.
122  enum LegalizeTypeAction : uint8_t {
123  TypeLegal, // The target natively supports this type.
124  TypePromoteInteger, // Replace this integer with a larger one.
125  TypeExpandInteger, // Split this integer into two of half the size.
126  TypeSoftenFloat, // Convert this float to a same size integer type,
127  // if an operation is not supported in target HW.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
178  SDValue Node = SDValue();
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
198  };
199  using ArgListTy = std::vector<ArgListEntry>;
200 
201  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202  ArgListTy &Args) const {};
203 
205  switch (Content) {
206  case UndefinedBooleanContent:
207  // Extend by adding rubbish bits.
208  return ISD::ANY_EXTEND;
209  case ZeroOrOneBooleanContent:
210  // Extend by adding zero bits.
211  return ISD::ZERO_EXTEND;
212  case ZeroOrNegativeOneBooleanContent:
213  // Extend by copying the sign bit.
214  return ISD::SIGN_EXTEND;
215  }
216  llvm_unreachable("Invalid content kind");
217  }
218 
219  /// NOTE: The TargetMachine owns TLOF.
220  explicit TargetLoweringBase(const TargetMachine &TM);
221  TargetLoweringBase(const TargetLoweringBase &) = delete;
222  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223  virtual ~TargetLoweringBase() = default;
224 
225 protected:
226  /// Initialize all of the actions to default values.
227  void initActions();
228 
229 public:
230  const TargetMachine &getTargetMachine() const { return TM; }
231 
232  virtual bool useSoftFloat() const { return false; }
233 
234  /// Return the pointer type for the given address space, defaults to
235  /// the pointer type from the data layout.
236  /// FIXME: The default needs to be removed once all the code is updated.
237  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239  }
240 
241  /// Return the type for frame index, which is determined by
242  /// the alloca address space specified through the data layout.
243  MVT getFrameIndexTy(const DataLayout &DL) const {
244  return getPointerTy(DL, DL.getAllocaAddrSpace());
245  }
246 
247  /// Return the type for operands of fence.
248  /// TODO: Let fence operands be of i32 type and remove this.
249  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250  return getPointerTy(DL);
251  }
252 
253  /// EVT is not used in-tree, but is used by out-of-tree target.
254  /// A documentation for this function would be nice...
255  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
256 
257  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258  bool LegalTypes = true) const;
259 
260  /// Returns the type to be used for the index operand of:
261  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264  return getPointerTy(DL);
265  }
266 
267  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
268  return true;
269  }
270 
271  /// Return true if multiple condition registers are available.
273  return HasMultipleConditionRegisters;
274  }
275 
276  /// Return true if the target has BitExtract instructions.
277  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
278 
279  /// Return the preferred vector type legalization action.
282  // The default action for one element vectors is to scalarize
283  if (VT.getVectorNumElements() == 1)
284  return TypeScalarizeVector;
285  // The default action for other vectors is to promote
286  return TypePromoteInteger;
287  }
288 
289  // There are two general methods for expanding a BUILD_VECTOR node:
290  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
291  // them together.
292  // 2. Build the vector on the stack and then load it.
293  // If this function returns true, then method (1) will be used, subject to
294  // the constraint that all of the necessary shuffles are legal (as determined
295  // by isShuffleMaskLegal). If this function returns false, then method (2) is
296  // always used. The vector type, and the number of defined values, are
297  // provided.
298  virtual bool
300  unsigned DefinedValues) const {
301  return DefinedValues < 3;
302  }
303 
304  /// Return true if integer divide is usually cheaper than a sequence of
305  /// several shifts, adds, and multiplies for this target.
306  /// The definition of "cheaper" may depend on whether we're optimizing
307  /// for speed or for size.
308  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
309 
310  /// Return true if the target can handle a standalone remainder operation.
311  virtual bool hasStandaloneRem(EVT VT) const {
312  return true;
313  }
314 
315  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
316  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
317  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
318  return false;
319  }
320 
321  /// Reciprocal estimate status values used by the functions below.
322  enum ReciprocalEstimate : int {
323  Unspecified = -1,
324  Disabled = 0,
326  };
327 
328  /// Return a ReciprocalEstimate enum value for a square root of the given type
329  /// based on the function's attributes. If the operation is not overridden by
330  /// the function's attributes, "Unspecified" is returned and target defaults
331  /// are expected to be used for instruction selection.
332  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
333 
334  /// Return a ReciprocalEstimate enum value for a division of the given type
335  /// based on the function's attributes. If the operation is not overridden by
336  /// the function's attributes, "Unspecified" is returned and target defaults
337  /// are expected to be used for instruction selection.
338  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
339 
340  /// Return the refinement step count for a square root of the given type based
341  /// on the function's attributes. If the operation is not overridden by
342  /// the function's attributes, "Unspecified" is returned and target defaults
343  /// are expected to be used for instruction selection.
344  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
345 
346  /// Return the refinement step count for a division of the given type based
347  /// on the function's attributes. If the operation is not overridden by
348  /// the function's attributes, "Unspecified" is returned and target defaults
349  /// are expected to be used for instruction selection.
350  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
351 
352  /// Returns true if target has indicated at least one type should be bypassed.
353  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
354 
355  /// Returns map of slow types for division or remainder with corresponding
356  /// fast types
358  return BypassSlowDivWidths;
359  }
360 
361  /// Return true if Flow Control is an expensive operation that should be
362  /// avoided.
363  bool isJumpExpensive() const { return JumpIsExpensive; }
364 
365  /// Return true if selects are only cheaper than branches if the branch is
366  /// unlikely to be predicted right.
368  return PredictableSelectIsExpensive;
369  }
370 
371  /// If a branch or a select condition is skewed in one direction by more than
372  /// this factor, it is very likely to be predicted correctly.
373  virtual BranchProbability getPredictableBranchThreshold() const;
374 
375  /// Return true if the following transform is beneficial:
376  /// fold (conv (load x)) -> (load (conv*)x)
377  /// On architectures that don't natively support some vector loads
378  /// efficiently, casting the load to a smaller vector of larger types and
379  /// loading is more efficient, however, this can be undone by optimizations in
380  /// dag combiner.
381  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
382  EVT BitcastVT) const {
383  // Don't do if we could do an indexed load on the original type, but not on
384  // the new one.
385  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
386  return true;
387 
388  MVT LoadMVT = LoadVT.getSimpleVT();
389 
390  // Don't bother doing this if it's just going to be promoted again later, as
391  // doing so might interfere with other combines.
392  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
393  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
394  return false;
395 
396  return true;
397  }
398 
399  /// Return true if the following transform is beneficial:
400  /// (store (y (conv x)), y*)) -> (store x, (x*))
401  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
402  // Default to the same logic as loads.
403  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
404  }
405 
406  /// Return true if it is expected to be cheaper to do a store of a non-zero
407  /// vector constant with the given size and type for the address space than to
408  /// store the individual scalar element constants.
409  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
410  unsigned NumElem,
411  unsigned AddrSpace) const {
412  return false;
413  }
414 
415  /// Allow store merging after legalization in addition to before legalization.
416  /// This may catch stores that do not exist earlier (eg, stores created from
417  /// intrinsics).
418  virtual bool mergeStoresAfterLegalization() const { return true; }
419 
420  /// Returns if it's reasonable to merge stores to MemVT size.
421  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
422  const SelectionDAG &DAG) const {
423  return true;
424  }
425 
426  /// Return true if it is cheap to speculate a call to intrinsic cttz.
427  virtual bool isCheapToSpeculateCttz() const {
428  return false;
429  }
430 
431  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
432  virtual bool isCheapToSpeculateCtlz() const {
433  return false;
434  }
435 
436  /// Return true if ctlz instruction is fast.
437  virtual bool isCtlzFast() const {
438  return false;
439  }
440 
441  /// Return true if it is safe to transform an integer-domain bitwise operation
442  /// into the equivalent floating-point operation. This should be set to true
443  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
444  /// type.
445  virtual bool hasBitPreservingFPLogic(EVT VT) const {
446  return false;
447  }
448 
449  /// Return true if it is cheaper to split the store of a merged int val
450  /// from a pair of smaller values into multiple stores.
451  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
452  return false;
453  }
454 
455  /// Return if the target supports combining a
456  /// chain like:
457  /// \code
458  /// %andResult = and %val1, #mask
459  /// %icmpResult = icmp %andResult, 0
460  /// \endcode
461  /// into a single machine instruction of a form like:
462  /// \code
463  /// cc = test %register, #mask
464  /// \endcode
465  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
466  return false;
467  }
468 
469  /// Use bitwise logic to make pairs of compares more efficient. For example:
470  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
471  /// This should be true when it takes more than one instruction to lower
472  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
473  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
474  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
475  return false;
476  }
477 
478  /// Return the preferred operand type if the target has a quick way to compare
479  /// integer values of the given size. Assume that any legal integer type can
480  /// be compared efficiently. Targets may override this to allow illegal wide
481  /// types to return a vector type if there is support to compare that type.
482  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
483  MVT VT = MVT::getIntegerVT(NumBits);
484  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
485  }
486 
487  /// Return true if the target should transform:
488  /// (X & Y) == Y ---> (~X & Y) == 0
489  /// (X & Y) != Y ---> (~X & Y) != 0
490  ///
491  /// This may be profitable if the target has a bitwise and-not operation that
492  /// sets comparison flags. A target may want to limit the transformation based
493  /// on the type of Y or if Y is a constant.
494  ///
495  /// Note that the transform will not occur if Y is known to be a power-of-2
496  /// because a mask and compare of a single bit can be handled by inverting the
497  /// predicate, for example:
498  /// (X & 8) == 8 ---> (X & 8) != 0
499  virtual bool hasAndNotCompare(SDValue Y) const {
500  return false;
501  }
502 
503  /// Return true if the target has a bitwise and-not operation:
504  /// X = ~A & B
505  /// This can be used to simplify select or other instructions.
506  virtual bool hasAndNot(SDValue X) const {
507  // If the target has the more complex version of this operation, assume that
508  // it has this operation too.
509  return hasAndNotCompare(X);
510  }
511 
512  /// There are two ways to clear extreme bits (either low or high):
513  /// Mask: x & (-1 << y) (the instcombine canonical form)
514  /// Shifts: x >> y << y
515  /// Return true if the variant with 2 shifts is preferred.
516  /// Return false if there is no preference.
518  // By default, let's assume that no one prefers shifts.
519  return false;
520  }
521 
522  /// Should we tranform the IR-optimal check for whether given truncation
523  /// down into KeptBits would be truncating or not:
524  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
525  /// Into it's more traditional form:
526  /// ((%x << C) a>> C) dstcond %x
527  /// Return true if we should transform.
528  /// Return false if there is no preference.
530  unsigned KeptBits) const {
531  // By default, let's assume that no one prefers shifts.
532  return false;
533  }
534 
535  /// Return true if the target wants to use the optimization that
536  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
537  /// promotedInst1(...(promotedInstN(ext(load)))).
538  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
539 
540  /// Return true if the target can combine store(extractelement VectorTy,
541  /// Idx).
542  /// \p Cost[out] gives the cost of that transformation when this is true.
543  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
544  unsigned &Cost) const {
545  return false;
546  }
547 
548  /// Return true if target supports floating point exceptions.
550  return HasFloatingPointExceptions;
551  }
552 
553  /// Return true if target always beneficiates from combining into FMA for a
554  /// given value type. This must typically return false on targets where FMA
555  /// takes more cycles to execute than FADD.
556  virtual bool enableAggressiveFMAFusion(EVT VT) const {
557  return false;
558  }
559 
560  /// Return the ValueType of the result of SETCC operations.
561  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
562  EVT VT) const;
563 
564  /// Return the ValueType for comparison libcalls. Comparions libcalls include
565  /// floating point comparion calls, and Ordered/Unordered check calls on
566  /// floating point numbers.
567  virtual
568  MVT::SimpleValueType getCmpLibcallReturnType() const;
569 
570  /// For targets without i1 registers, this gives the nature of the high-bits
571  /// of boolean values held in types wider than i1.
572  ///
573  /// "Boolean values" are special true/false values produced by nodes like
574  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
575  /// Not to be confused with general values promoted from i1. Some cpus
576  /// distinguish between vectors of boolean and scalars; the isVec parameter
577  /// selects between the two kinds. For example on X86 a scalar boolean should
578  /// be zero extended from i1, while the elements of a vector of booleans
579  /// should be sign extended from i1.
580  ///
581  /// Some cpus also treat floating point types the same way as they treat
582  /// vectors instead of the way they treat scalars.
583  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
584  if (isVec)
585  return BooleanVectorContents;
586  return isFloat ? BooleanFloatContents : BooleanContents;
587  }
588 
590  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
591  }
592 
593  /// Return target scheduling preference.
595  return SchedPreferenceInfo;
596  }
597 
598  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
599  /// for different nodes. This function returns the preference (or none) for
600  /// the given node.
602  return Sched::None;
603  }
604 
605  /// Return the register class that should be used for the specified value
606  /// type.
607  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
608  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
609  assert(RC && "This value type is not natively supported!");
610  return RC;
611  }
612 
613  /// Return the 'representative' register class for the specified value
614  /// type.
615  ///
616  /// The 'representative' register class is the largest legal super-reg
617  /// register class for the register class of the value type. For example, on
618  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
619  /// register class is GR64 on x86_64.
620  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
621  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
622  return RC;
623  }
624 
625  /// Return the cost of the 'representative' register class for the specified
626  /// value type.
627  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
628  return RepRegClassCostForVT[VT.SimpleTy];
629  }
630 
631  /// Return true if the target has native support for the specified value type.
632  /// This means that it has a register that directly holds it without
633  /// promotions or expansions.
634  bool isTypeLegal(EVT VT) const {
635  assert(!VT.isSimple() ||
636  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
637  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
638  }
639 
641  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
642  /// that indicates how instruction selection should deal with the type.
643  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
644 
645  public:
647  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
648  TypeLegal);
649  }
650 
652  return ValueTypeActions[VT.SimpleTy];
653  }
654 
656  ValueTypeActions[VT.SimpleTy] = Action;
657  }
658  };
659 
661  return ValueTypeActions;
662  }
663 
664  /// Return how we should legalize values of this type, either it is already
665  /// legal (return 'Legal') or we need to promote it to a larger type (return
666  /// 'Promote'), or we need to expand it into multiple registers of smaller
667  /// integer type (return 'Expand'). 'Custom' is not an option.
669  return getTypeConversion(Context, VT).first;
670  }
672  return ValueTypeActions.getTypeAction(VT);
673  }
674 
675  /// For types supported by the target, this is an identity function. For
676  /// types that must be promoted to larger types, this returns the larger type
677  /// to promote to. For integer types that are larger than the largest integer
678  /// register, this contains one step in the expansion to get to the smaller
679  /// register. For illegal floating point types, this returns the integer type
680  /// to transform to.
681  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
682  return getTypeConversion(Context, VT).second;
683  }
684 
685  /// For types supported by the target, this is an identity function. For
686  /// types that must be expanded (i.e. integer types that are larger than the
687  /// largest integer register or illegal floating point types), this returns
688  /// the largest legal type it will be expanded to.
689  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
690  assert(!VT.isVector());
691  while (true) {
692  switch (getTypeAction(Context, VT)) {
693  case TypeLegal:
694  return VT;
695  case TypeExpandInteger:
696  VT = getTypeToTransformTo(Context, VT);
697  break;
698  default:
699  llvm_unreachable("Type is not legal nor is it to be expanded!");
700  }
701  }
702  }
703 
704  /// Vector types are broken down into some number of legal first class types.
705  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
706  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
707  /// turns into 4 EVT::i32 values with both PPC and X86.
708  ///
709  /// This method returns the number of registers needed, and the VT for each
710  /// register. It also returns the VT and quantity of the intermediate values
711  /// before they are promoted/expanded.
712  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
713  EVT &IntermediateVT,
714  unsigned &NumIntermediates,
715  MVT &RegisterVT) const;
716 
717  /// Certain targets such as MIPS require that some types such as vectors are
718  /// always broken down into scalars in some contexts. This occurs even if the
719  /// vector type is legal.
721  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
722  unsigned &NumIntermediates, MVT &RegisterVT) const {
723  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
724  RegisterVT);
725  }
726 
727  struct IntrinsicInfo {
728  unsigned opc = 0; // target opcode
729  EVT memVT; // memory VT
730 
731  // value representing memory location
733 
734  int offset = 0; // offset off of ptrVal
735  unsigned size = 0; // the size of the memory location
736  // (taken from memVT if zero)
737  unsigned align = 1; // alignment
738 
740  IntrinsicInfo() = default;
741  };
742 
743  /// Given an intrinsic, checks if on the target the intrinsic will need to map
744  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
745  /// true and store the intrinsic information into the IntrinsicInfo that was
746  /// passed to the function.
747  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
748  MachineFunction &,
749  unsigned /*Intrinsic*/) const {
750  return false;
751  }
752 
753  /// Returns true if the target can instruction select the specified FP
754  /// immediate natively. If false, the legalizer will materialize the FP
755  /// immediate as a load from a constant pool.
756  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
757  return false;
758  }
759 
760  /// Targets can use this to indicate that they only support *some*
761  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
762  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
763  /// legal.
764  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
765  return true;
766  }
767 
768  /// Returns true if the operation can trap for the value type.
769  ///
770  /// VT must be a legal type. By default, we optimistically assume most
771  /// operations don't trap except for integer divide and remainder.
772  virtual bool canOpTrap(unsigned Op, EVT VT) const;
773 
774  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
775  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
776  /// constant pool entry.
777  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
778  EVT /*VT*/) const {
779  return false;
780  }
781 
782  /// Return how this operation should be treated: either it is legal, needs to
783  /// be promoted to a larger size, needs to be expanded to some other code
784  /// sequence, or the target has a custom expander for it.
785  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
786  if (VT.isExtended()) return Expand;
787  // If a target-specific SDNode requires legalization, require the target
788  // to provide custom legalization for it.
789  if (Op >= array_lengthof(OpActions[0])) return Custom;
790  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
791  }
792 
794  unsigned EqOpc;
795  switch (Op) {
796  default: llvm_unreachable("Unexpected FP pseudo-opcode");
797  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
798  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
799  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
800  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
801  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
802  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
803  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
804  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
805  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
806  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
807  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
808  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
809  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
810  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
811  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
812  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
813  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
814  }
815 
816  auto Action = getOperationAction(EqOpc, VT);
817 
818  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
819  // For now, we just expand for those cases.
820  if (Action != Legal)
821  Action = Expand;
822 
823  return Action;
824  }
825 
826  /// Return true if the specified operation is legal on this target or can be
827  /// made legal with custom lowering. This is used to help guide high-level
828  /// lowering decisions.
829  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
830  return (VT == MVT::Other || isTypeLegal(VT)) &&
831  (getOperationAction(Op, VT) == Legal ||
832  getOperationAction(Op, VT) == Custom);
833  }
834 
835  /// Return true if the specified operation is legal on this target or can be
836  /// made legal using promotion. This is used to help guide high-level lowering
837  /// decisions.
838  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
839  return (VT == MVT::Other || isTypeLegal(VT)) &&
840  (getOperationAction(Op, VT) == Legal ||
841  getOperationAction(Op, VT) == Promote);
842  }
843 
844  /// Return true if the specified operation is legal on this target or can be
845  /// made legal with custom lowering or using promotion. This is used to help
846  /// guide high-level lowering decisions.
847  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
848  return (VT == MVT::Other || isTypeLegal(VT)) &&
849  (getOperationAction(Op, VT) == Legal ||
850  getOperationAction(Op, VT) == Custom ||
851  getOperationAction(Op, VT) == Promote);
852  }
853 
854  /// Return true if the operation uses custom lowering, regardless of whether
855  /// the type is legal or not.
856  bool isOperationCustom(unsigned Op, EVT VT) const {
857  return getOperationAction(Op, VT) == Custom;
858  }
859 
860  /// Return true if lowering to a jump table is allowed.
861  virtual bool areJTsAllowed(const Function *Fn) const {
862  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
863  return false;
864 
865  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
866  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
867  }
868 
869  /// Check whether the range [Low,High] fits in a machine word.
870  bool rangeFitsInWord(const APInt &Low, const APInt &High,
871  const DataLayout &DL) const {
872  // FIXME: Using the pointer type doesn't seem ideal.
873  uint64_t BW = DL.getIndexSizeInBits(0u);
874  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
875  return Range <= BW;
876  }
877 
878  /// Return true if lowering to a jump table is suitable for a set of case
879  /// clusters which may contain \p NumCases cases, \p Range range of values.
880  /// FIXME: This function check the maximum table size and density, but the
881  /// minimum size is not checked. It would be nice if the minimum size is
882  /// also combined within this function. Currently, the minimum size check is
883  /// performed in findJumpTable() in SelectionDAGBuiler and
884  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
885  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
886  uint64_t Range) const {
887  const bool OptForSize = SI->getParent()->getParent()->optForSize();
888  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
889  const unsigned MaxJumpTableSize =
890  OptForSize || getMaximumJumpTableSize() == 0
891  ? UINT_MAX
892  : getMaximumJumpTableSize();
893  // Check whether a range of clusters is dense enough for a jump table.
894  if (Range <= MaxJumpTableSize &&
895  (NumCases * 100 >= Range * MinDensity)) {
896  return true;
897  }
898  return false;
899  }
900 
901  /// Return true if lowering to a bit test is suitable for a set of case
902  /// clusters which contains \p NumDests unique destinations, \p Low and
903  /// \p High as its lowest and highest case values, and expects \p NumCmps
904  /// case value comparisons. Check if the number of destinations, comparison
905  /// metric, and range are all suitable.
906  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
907  const APInt &Low, const APInt &High,
908  const DataLayout &DL) const {
909  // FIXME: I don't think NumCmps is the correct metric: a single case and a
910  // range of cases both require only one branch to lower. Just looking at the
911  // number of clusters and destinations should be enough to decide whether to
912  // build bit tests.
913 
914  // To lower a range with bit tests, the range must fit the bitwidth of a
915  // machine word.
916  if (!rangeFitsInWord(Low, High, DL))
917  return false;
918 
919  // Decide whether it's profitable to lower this range with bit tests. Each
920  // destination requires a bit test and branch, and there is an overall range
921  // check branch. For a small number of clusters, separate comparisons might
922  // be cheaper, and for many destinations, splitting the range might be
923  // better.
924  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
925  (NumDests == 3 && NumCmps >= 6);
926  }
927 
928  /// Return true if the specified operation is illegal on this target or
929  /// unlikely to be made legal with custom lowering. This is used to help guide
930  /// high-level lowering decisions.
931  bool isOperationExpand(unsigned Op, EVT VT) const {
932  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
933  }
934 
935  /// Return true if the specified operation is legal on this target.
936  bool isOperationLegal(unsigned Op, EVT VT) const {
937  return (VT == MVT::Other || isTypeLegal(VT)) &&
938  getOperationAction(Op, VT) == Legal;
939  }
940 
941  /// Return how this load with extension should be treated: either it is legal,
942  /// needs to be promoted to a larger size, needs to be expanded to some other
943  /// code sequence, or the target has a custom expander for it.
944  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
945  EVT MemVT) const {
946  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
947  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
948  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
949  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
950  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
951  unsigned Shift = 4 * ExtType;
952  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
953  }
954 
955  /// Return true if the specified load with extension is legal on this target.
956  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
957  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
958  }
959 
960  /// Return true if the specified load with extension is legal or custom
961  /// on this target.
962  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
963  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
964  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
965  }
966 
967  /// Return how this store with truncation should be treated: either it is
968  /// legal, needs to be promoted to a larger size, needs to be expanded to some
969  /// other code sequence, or the target has a custom expander for it.
971  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
972  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
973  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
975  "Table isn't big enough!");
976  return TruncStoreActions[ValI][MemI];
977  }
978 
979  /// Return true if the specified store with truncation is legal on this
980  /// target.
981  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
982  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
983  }
984 
985  /// Return true if the specified store with truncation has solution on this
986  /// target.
987  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
988  return isTypeLegal(ValVT) &&
989  (getTruncStoreAction(ValVT, MemVT) == Legal ||
990  getTruncStoreAction(ValVT, MemVT) == Custom);
991  }
992 
993  /// Return how the indexed load should be treated: either it is legal, needs
994  /// to be promoted to a larger size, needs to be expanded to some other code
995  /// sequence, or the target has a custom expander for it.
997  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
998  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
999  "Table isn't big enough!");
1000  unsigned Ty = (unsigned)VT.SimpleTy;
1001  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1002  }
1003 
1004  /// Return true if the specified indexed load is legal on this target.
1005  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1006  return VT.isSimple() &&
1007  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1008  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1009  }
1010 
1011  /// Return how the indexed store should be treated: either it is legal, needs
1012  /// to be promoted to a larger size, needs to be expanded to some other code
1013  /// sequence, or the target has a custom expander for it.
1015  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1016  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1017  "Table isn't big enough!");
1018  unsigned Ty = (unsigned)VT.SimpleTy;
1019  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1020  }
1021 
1022  /// Return true if the specified indexed load is legal on this target.
1023  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1024  return VT.isSimple() &&
1025  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1026  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1027  }
1028 
1029  /// Return how the condition code should be treated: either it is legal, needs
1030  /// to be expanded to some other code sequence, or the target has a custom
1031  /// expander for it.
1034  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1035  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1036  "Table isn't big enough!");
1037  // See setCondCodeAction for how this is encoded.
1038  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1039  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1040  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1041  assert(Action != Promote && "Can't promote condition code!");
1042  return Action;
1043  }
1044 
1045  /// Return true if the specified condition code is legal on this target.
1046  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1047  return getCondCodeAction(CC, VT) == Legal;
1048  }
1049 
1050  /// Return true if the specified condition code is legal or custom on this
1051  /// target.
1053  return getCondCodeAction(CC, VT) == Legal ||
1054  getCondCodeAction(CC, VT) == Custom;
1055  }
1056 
1057  /// If the action for this operation is to promote, this method returns the
1058  /// ValueType to promote to.
1059  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1060  assert(getOperationAction(Op, VT) == Promote &&
1061  "This operation isn't promoted!");
1062 
1063  // See if this has an explicit type specified.
1064  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1065  MVT::SimpleValueType>::const_iterator PTTI =
1066  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1067  if (PTTI != PromoteToType.end()) return PTTI->second;
1068 
1069  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1070  "Cannot autopromote this type, add it with AddPromotedToType.");
1071 
1072  MVT NVT = VT;
1073  do {
1074  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1075  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1076  "Didn't find type to promote to!");
1077  } while (!isTypeLegal(NVT) ||
1078  getOperationAction(Op, NVT) == Promote);
1079  return NVT;
1080  }
1081 
1082  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1083  /// operations except for the pointer size. If AllowUnknown is true, this
1084  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1085  /// otherwise it will assert.
1087  bool AllowUnknown = false) const {
1088  // Lower scalar pointers to native pointer types.
1089  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1090  return getPointerTy(DL, PTy->getAddressSpace());
1091 
1092  if (Ty->isVectorTy()) {
1093  VectorType *VTy = cast<VectorType>(Ty);
1094  Type *Elm = VTy->getElementType();
1095  // Lower vectors of pointers to native pointer types.
1096  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1097  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1098  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1099  }
1100 
1101  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1102  VTy->getNumElements());
1103  }
1104  return EVT::getEVT(Ty, AllowUnknown);
1105  }
1106 
1107  /// Return the MVT corresponding to this LLVM type. See getValueType.
1109  bool AllowUnknown = false) const {
1110  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1111  }
1112 
1113  /// Return the desired alignment for ByVal or InAlloca aggregate function
1114  /// arguments in the caller parameter area. This is the actual alignment, not
1115  /// its logarithm.
1116  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1117 
1118  /// Return the type of registers that this ValueType will eventually require.
1120  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1121  return RegisterTypeForVT[VT.SimpleTy];
1122  }
1123 
1124  /// Return the type of registers that this ValueType will eventually require.
1125  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1126  if (VT.isSimple()) {
1127  assert((unsigned)VT.getSimpleVT().SimpleTy <
1128  array_lengthof(RegisterTypeForVT));
1129  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1130  }
1131  if (VT.isVector()) {
1132  EVT VT1;
1133  MVT RegisterVT;
1134  unsigned NumIntermediates;
1135  (void)getVectorTypeBreakdown(Context, VT, VT1,
1136  NumIntermediates, RegisterVT);
1137  return RegisterVT;
1138  }
1139  if (VT.isInteger()) {
1140  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1141  }
1142  llvm_unreachable("Unsupported extended type!");
1143  }
1144 
1145  /// Return the number of registers that this ValueType will eventually
1146  /// require.
1147  ///
1148  /// This is one for any types promoted to live in larger registers, but may be
1149  /// more than one for types (like i64) that are split into pieces. For types
1150  /// like i140, which are first promoted then expanded, it is the number of
1151  /// registers needed to hold all the bits of the original type. For an i140
1152  /// on a 32 bit machine this means 5 registers.
1153  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1154  if (VT.isSimple()) {
1155  assert((unsigned)VT.getSimpleVT().SimpleTy <
1156  array_lengthof(NumRegistersForVT));
1157  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1158  }
1159  if (VT.isVector()) {
1160  EVT VT1;
1161  MVT VT2;
1162  unsigned NumIntermediates;
1163  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1164  }
1165  if (VT.isInteger()) {
1166  unsigned BitWidth = VT.getSizeInBits();
1167  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1168  return (BitWidth + RegWidth - 1) / RegWidth;
1169  }
1170  llvm_unreachable("Unsupported extended type!");
1171  }
1172 
1173  /// Certain combinations of ABIs, Targets and features require that types
1174  /// are legal for some operations and not for other operations.
1175  /// For MIPS all vector types must be passed through the integer register set.
1177  EVT VT) const {
1178  return getRegisterType(Context, VT);
1179  }
1180 
1181  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1182  /// this occurs when a vector type is used, as vector are passed through the
1183  /// integer register set.
1184  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1185  EVT VT) const {
1186  return getNumRegisters(Context, VT);
1187  }
1188 
1189  /// Certain targets have context senstive alignment requirements, where one
1190  /// type has the alignment requirement of another type.
1191  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1192  DataLayout DL) const {
1193  return DL.getABITypeAlignment(ArgTy);
1194  }
1195 
1196  /// If true, then instruction selection should seek to shrink the FP constant
1197  /// of the specified type to a smaller type in order to save space and / or
1198  /// reduce runtime.
1199  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1200 
1201  // Return true if it is profitable to reduce the given load node to a smaller
1202  // type.
1203  //
1204  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1206  ISD::LoadExtType ExtTy,
1207  EVT NewVT) const {
1208  return true;
1209  }
1210 
1211  /// When splitting a value of the specified type into parts, does the Lo
1212  /// or Hi part come first? This usually follows the endianness, except
1213  /// for ppcf128, where the Hi part always comes first.
1214  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1215  return DL.isBigEndian() || VT == MVT::ppcf128;
1216  }
1217 
1218  /// If true, the target has custom DAG combine transformations that it can
1219  /// perform for the specified node.
1221  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1222  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1223  }
1224 
1225  unsigned getGatherAllAliasesMaxDepth() const {
1226  return GatherAllAliasesMaxDepth;
1227  }
1228 
1229  /// Returns the size of the platform's va_list object.
1230  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1231  return getPointerTy(DL).getSizeInBits();
1232  }
1233 
1234  /// Get maximum # of store operations permitted for llvm.memset
1235  ///
1236  /// This function returns the maximum number of store operations permitted
1237  /// to replace a call to llvm.memset. The value is set by the target at the
1238  /// performance threshold for such a replacement. If OptSize is true,
1239  /// return the limit for functions that have OptSize attribute.
1240  unsigned getMaxStoresPerMemset(bool OptSize) const {
1241  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1242  }
1243 
1244  /// Get maximum # of store operations permitted for llvm.memcpy
1245  ///
1246  /// This function returns the maximum number of store operations permitted
1247  /// to replace a call to llvm.memcpy. The value is set by the target at the
1248  /// performance threshold for such a replacement. If OptSize is true,
1249  /// return the limit for functions that have OptSize attribute.
1250  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1251  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1252  }
1253 
1254  /// \brief Get maximum # of store operations to be glued together
1255  ///
1256  /// This function returns the maximum number of store operations permitted
1257  /// to glue together during lowering of llvm.memcpy. The value is set by
1258  // the target at the performance threshold for such a replacement.
1259  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1260  return MaxGluedStoresPerMemcpy;
1261  }
1262 
1263  /// Get maximum # of load operations permitted for memcmp
1264  ///
1265  /// This function returns the maximum number of load operations permitted
1266  /// to replace a call to memcmp. The value is set by the target at the
1267  /// performance threshold for such a replacement. If OptSize is true,
1268  /// return the limit for functions that have OptSize attribute.
1269  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1270  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1271  }
1272 
1273  /// For memcmp expansion when the memcmp result is only compared equal or
1274  /// not-equal to 0, allow up to this number of load pairs per block. As an
1275  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1276  /// a0 = load2bytes &a[0]
1277  /// b0 = load2bytes &b[0]
1278  /// a2 = load1byte &a[2]
1279  /// b2 = load1byte &b[2]
1280  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1281  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1282  return 1;
1283  }
1284 
1285  /// Get maximum # of store operations permitted for llvm.memmove
1286  ///
1287  /// This function returns the maximum number of store operations permitted
1288  /// to replace a call to llvm.memmove. The value is set by the target at the
1289  /// performance threshold for such a replacement. If OptSize is true,
1290  /// return the limit for functions that have OptSize attribute.
1291  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1292  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1293  }
1294 
1295  /// Determine if the target supports unaligned memory accesses.
1296  ///
1297  /// This function returns true if the target allows unaligned memory accesses
1298  /// of the specified type in the given address space. If true, it also returns
1299  /// whether the unaligned memory access is "fast" in the last argument by
1300  /// reference. This is used, for example, in situations where an array
1301  /// copy/move/set is converted to a sequence of store operations. Its use
1302  /// helps to ensure that such replacements don't generate code that causes an
1303  /// alignment error (trap) on the target machine.
1305  unsigned AddrSpace = 0,
1306  unsigned Align = 1,
1307  bool * /*Fast*/ = nullptr) const {
1308  return false;
1309  }
1310 
1311  /// Return true if the target supports a memory access of this type for the
1312  /// given address space and alignment. If the access is allowed, the optional
1313  /// final parameter returns if the access is also fast (as defined by the
1314  /// target).
1315  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1316  unsigned AddrSpace = 0, unsigned Alignment = 1,
1317  bool *Fast = nullptr) const;
1318 
1319  /// Returns the target specific optimal type for load and store operations as
1320  /// a result of memset, memcpy, and memmove lowering.
1321  ///
1322  /// If DstAlign is zero that means it's safe to destination alignment can
1323  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1324  /// a need to check it against alignment requirement, probably because the
1325  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1326  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1327  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1328  /// does not need to be loaded. It returns EVT::Other if the type should be
1329  /// determined using generic target-independent logic.
1330  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1331  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1332  bool /*IsMemset*/,
1333  bool /*ZeroMemset*/,
1334  bool /*MemcpyStrSrc*/,
1335  MachineFunction &/*MF*/) const {
1336  return MVT::Other;
1337  }
1338 
1339  /// Returns true if it's safe to use load / store of the specified type to
1340  /// expand memcpy / memset inline.
1341  ///
1342  /// This is mostly true for all types except for some special cases. For
1343  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1344  /// fstpl which also does type conversion. Note the specified type doesn't
1345  /// have to be legal as the hook is used before type legalization.
1346  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1347 
1348  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1349  bool usesUnderscoreSetJmp() const {
1350  return UseUnderscoreSetJmp;
1351  }
1352 
1353  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1354  bool usesUnderscoreLongJmp() const {
1355  return UseUnderscoreLongJmp;
1356  }
1357 
1358  /// Return lower limit for number of blocks in a jump table.
1359  virtual unsigned getMinimumJumpTableEntries() const;
1360 
1361  /// Return lower limit of the density in a jump table.
1362  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1363 
1364  /// Return upper limit for number of entries in a jump table.
1365  /// Zero if no limit.
1366  unsigned getMaximumJumpTableSize() const;
1367 
1368  virtual bool isJumpTableRelative() const {
1369  return TM.isPositionIndependent();
1370  }
1371 
1372  /// If a physical register, this specifies the register that
1373  /// llvm.savestack/llvm.restorestack should save and restore.
1375  return StackPointerRegisterToSaveRestore;
1376  }
1377 
1378  /// If a physical register, this returns the register that receives the
1379  /// exception address on entry to an EH pad.
1380  virtual unsigned
1381  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1382  // 0 is guaranteed to be the NoRegister value on all targets
1383  return 0;
1384  }
1385 
1386  /// If a physical register, this returns the register that receives the
1387  /// exception typeid on entry to a landing pad.
1388  virtual unsigned
1389  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1390  // 0 is guaranteed to be the NoRegister value on all targets
1391  return 0;
1392  }
1393 
1394  virtual bool needsFixedCatchObjects() const {
1395  report_fatal_error("Funclet EH is not implemented for this target");
1396  }
1397 
1398  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1399  /// 200)
1400  unsigned getJumpBufSize() const {
1401  return JumpBufSize;
1402  }
1403 
1404  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1405  /// is 0)
1406  unsigned getJumpBufAlignment() const {
1407  return JumpBufAlignment;
1408  }
1409 
1410  /// Return the minimum stack alignment of an argument.
1411  unsigned getMinStackArgumentAlignment() const {
1412  return MinStackArgumentAlignment;
1413  }
1414 
1415  /// Return the minimum function alignment.
1416  unsigned getMinFunctionAlignment() const {
1417  return MinFunctionAlignment;
1418  }
1419 
1420  /// Return the preferred function alignment.
1421  unsigned getPrefFunctionAlignment() const {
1422  return PrefFunctionAlignment;
1423  }
1424 
1425  /// Return the preferred loop alignment.
1426  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1427  return PrefLoopAlignment;
1428  }
1429 
1430  /// If the target has a standard location for the stack protector guard,
1431  /// returns the address of that location. Otherwise, returns nullptr.
1432  /// DEPRECATED: please override useLoadStackGuardNode and customize
1433  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1434  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1435 
1436  /// Inserts necessary declarations for SSP (stack protection) purpose.
1437  /// Should be used only when getIRStackGuard returns nullptr.
1438  virtual void insertSSPDeclarations(Module &M) const;
1439 
1440  /// Return the variable that's previously inserted by insertSSPDeclarations,
1441  /// if any, otherwise return nullptr. Should be used only when
1442  /// getIRStackGuard returns nullptr.
1443  virtual Value *getSDagStackGuard(const Module &M) const;
1444 
1445  /// If this function returns true, stack protection checks should XOR the
1446  /// frame pointer (or whichever pointer is used to address locals) into the
1447  /// stack guard value before checking it. getIRStackGuard must return nullptr
1448  /// if this returns true.
1449  virtual bool useStackGuardXorFP() const { return false; }
1450 
1451  /// If the target has a standard stack protection check function that
1452  /// performs validation and error handling, returns the function. Otherwise,
1453  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1454  /// Should be used only when getIRStackGuard returns nullptr.
1455  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1456 
1457 protected:
1458  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1459  bool UseTLS) const;
1460 
1461 public:
1462  /// Returns the target-specific address of the unsafe stack pointer.
1463  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1464 
1465  /// Returns the name of the symbol used to emit stack probes or the empty
1466  /// string if not applicable.
1468  return "";
1469  }
1470 
1471  /// Returns true if a cast between SrcAS and DestAS is a noop.
1472  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1473  return false;
1474  }
1475 
1476  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1477  /// are happy to sink it into basic blocks.
1478  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1479  return isNoopAddrSpaceCast(SrcAS, DestAS);
1480  }
1481 
1482  /// Return true if the pointer arguments to CI should be aligned by aligning
1483  /// the object whose address is being passed. If so then MinSize is set to the
1484  /// minimum size the object must be to be aligned and PrefAlign is set to the
1485  /// preferred alignment.
1486  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1487  unsigned & /*PrefAlign*/) const {
1488  return false;
1489  }
1490 
1491  //===--------------------------------------------------------------------===//
1492  /// \name Helpers for TargetTransformInfo implementations
1493  /// @{
1494 
1495  /// Get the ISD node that corresponds to the Instruction class opcode.
1496  int InstructionOpcodeToISD(unsigned Opcode) const;
1497 
1498  /// Estimate the cost of type-legalization and the legalized type.
1499  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1500  Type *Ty) const;
1501 
1502  /// @}
1503 
1504  //===--------------------------------------------------------------------===//
1505  /// \name Helpers for atomic expansion.
1506  /// @{
1507 
1508  /// Returns the maximum atomic operation size (in bits) supported by
1509  /// the backend. Atomic operations greater than this size (as well
1510  /// as ones that are not naturally aligned), will be expanded by
1511  /// AtomicExpandPass into an __atomic_* library call.
1513  return MaxAtomicSizeInBitsSupported;
1514  }
1515 
1516  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1517  /// the backend supports. Any smaller operations are widened in
1518  /// AtomicExpandPass.
1519  ///
1520  /// Note that *unlike* operations above the maximum size, atomic ops
1521  /// are still natively supported below the minimum; they just
1522  /// require a more complex expansion.
1523  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1524 
1525  /// Whether the target supports unaligned atomic operations.
1526  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1527 
1528  /// Whether AtomicExpandPass should automatically insert fences and reduce
1529  /// ordering for this atomic. This should be true for most architectures with
1530  /// weak memory ordering. Defaults to false.
1531  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1532  return false;
1533  }
1534 
1535  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1536  /// corresponding pointee type. This may entail some non-trivial operations to
1537  /// truncate or reconstruct types that will be illegal in the backend. See
1538  /// ARMISelLowering for an example implementation.
1539  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1540  AtomicOrdering Ord) const {
1541  llvm_unreachable("Load linked unimplemented on this target");
1542  }
1543 
1544  /// Perform a store-conditional operation to Addr. Return the status of the
1545  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1546  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1547  Value *Addr, AtomicOrdering Ord) const {
1548  llvm_unreachable("Store conditional unimplemented on this target");
1549  }
1550 
1551  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1552  /// It is called by AtomicExpandPass before expanding an
1553  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1554  /// if shouldInsertFencesForAtomic returns true.
1555  ///
1556  /// Inst is the original atomic instruction, prior to other expansions that
1557  /// may be performed.
1558  ///
1559  /// This function should either return a nullptr, or a pointer to an IR-level
1560  /// Instruction*. Even complex fence sequences can be represented by a
1561  /// single Instruction* through an intrinsic to be lowered later.
1562  /// Backends should override this method to produce target-specific intrinsic
1563  /// for their fences.
1564  /// FIXME: Please note that the default implementation here in terms of
1565  /// IR-level fences exists for historical/compatibility reasons and is
1566  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1567  /// consistency. For example, consider the following example:
1568  /// atomic<int> x = y = 0;
1569  /// int r1, r2, r3, r4;
1570  /// Thread 0:
1571  /// x.store(1);
1572  /// Thread 1:
1573  /// y.store(1);
1574  /// Thread 2:
1575  /// r1 = x.load();
1576  /// r2 = y.load();
1577  /// Thread 3:
1578  /// r3 = y.load();
1579  /// r4 = x.load();
1580  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1581  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1582  /// IR-level fences can prevent it.
1583  /// @{
1585  AtomicOrdering Ord) const {
1586  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1587  return Builder.CreateFence(Ord);
1588  else
1589  return nullptr;
1590  }
1591 
1593  Instruction *Inst,
1594  AtomicOrdering Ord) const {
1595  if (isAcquireOrStronger(Ord))
1596  return Builder.CreateFence(Ord);
1597  else
1598  return nullptr;
1599  }
1600  /// @}
1601 
1602  // Emits code that executes when the comparison result in the ll/sc
1603  // expansion of a cmpxchg instruction is such that the store-conditional will
1604  // not execute. This makes it possible to balance out the load-linked with
1605  // a dedicated instruction, if desired.
1606  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1607  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1608  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1609 
1610  /// Returns true if the given (atomic) store should be expanded by the
1611  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1613  return false;
1614  }
1615 
1616  /// Returns true if arguments should be sign-extended in lib calls.
1617  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1618  return IsSigned;
1619  }
1620 
1621  /// Returns how the given (atomic) load should be expanded by the
1622  /// IR-level AtomicExpand pass.
1625  }
1626 
1627  /// Returns true if the given atomic cmpxchg should be expanded by the
1628  /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1629  /// (through emitLoadLinked() and emitStoreConditional()).
1631  return false;
1632  }
1633 
1634  /// Returns how the IR-level AtomicExpand pass should expand the given
1635  /// AtomicRMW, if at all. Default is to never expand.
1638  }
1639 
1640  /// On some platforms, an AtomicRMW that never actually modifies the value
1641  /// (such as fetch_add of 0) can be turned into a fence followed by an
1642  /// atomic load. This may sound useless, but it makes it possible for the
1643  /// processor to keep the cacheline shared, dramatically improving
1644  /// performance. And such idempotent RMWs are useful for implementing some
1645  /// kinds of locks, see for example (justification + benchmarks):
1646  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1647  /// This method tries doing that transformation, returning the atomic load if
1648  /// it succeeds, and nullptr otherwise.
1649  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1650  /// another round of expansion.
1651  virtual LoadInst *
1653  return nullptr;
1654  }
1655 
1656  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1657  /// SIGN_EXTEND, or ANY_EXTEND).
1659  return ISD::ZERO_EXTEND;
1660  }
1661 
1662  /// @}
1663 
1664  /// Returns true if we should normalize
1665  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1666  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1667  /// that it saves us from materializing N0 and N1 in an integer register.
1668  /// Targets that are able to perform and/or on flags should return false here.
1670  EVT VT) const {
1671  // If a target has multiple condition registers, then it likely has logical
1672  // operations on those registers.
1673  if (hasMultipleConditionRegisters())
1674  return false;
1675  // Only do the transform if the value won't be split into multiple
1676  // registers.
1677  LegalizeTypeAction Action = getTypeAction(Context, VT);
1678  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1679  Action != TypeSplitVector;
1680  }
1681 
1682  /// Return true if a select of constants (select Cond, C1, C2) should be
1683  /// transformed into simple math ops with the condition value. For example:
1684  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1685  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1686  return false;
1687  }
1688 
1689  //===--------------------------------------------------------------------===//
1690  // TargetLowering Configuration Methods - These methods should be invoked by
1691  // the derived class constructor to configure this object for the target.
1692  //
1693 protected:
1694  /// Specify how the target extends the result of integer and floating point
1695  /// boolean values from i1 to a wider type. See getBooleanContents.
1697  BooleanContents = Ty;
1698  BooleanFloatContents = Ty;
1699  }
1700 
1701  /// Specify how the target extends the result of integer and floating point
1702  /// boolean values from i1 to a wider type. See getBooleanContents.
1704  BooleanContents = IntTy;
1705  BooleanFloatContents = FloatTy;
1706  }
1707 
1708  /// Specify how the target extends the result of a vector boolean value from a
1709  /// vector of i1 to a wider type. See getBooleanContents.
1711  BooleanVectorContents = Ty;
1712  }
1713 
1714  /// Specify the target scheduling preference.
1716  SchedPreferenceInfo = Pref;
1717  }
1718 
1719  /// Indicate whether this target prefers to use _setjmp to implement
1720  /// llvm.setjmp or the version without _. Defaults to false.
1721  void setUseUnderscoreSetJmp(bool Val) {
1722  UseUnderscoreSetJmp = Val;
1723  }
1724 
1725  /// Indicate whether this target prefers to use _longjmp to implement
1726  /// llvm.longjmp or the version without _. Defaults to false.
1727  void setUseUnderscoreLongJmp(bool Val) {
1728  UseUnderscoreLongJmp = Val;
1729  }
1730 
1731  /// Indicate the minimum number of blocks to generate jump tables.
1732  void setMinimumJumpTableEntries(unsigned Val);
1733 
1734  /// Indicate the maximum number of entries in jump tables.
1735  /// Set to zero to generate unlimited jump tables.
1736  void setMaximumJumpTableSize(unsigned);
1737 
1738  /// If set to a physical register, this specifies the register that
1739  /// llvm.savestack/llvm.restorestack should save and restore.
1741  StackPointerRegisterToSaveRestore = R;
1742  }
1743 
1744  /// Tells the code generator that the target has multiple (allocatable)
1745  /// condition registers that can be used to store the results of comparisons
1746  /// for use by selects and conditional branches. With multiple condition
1747  /// registers, the code generator will not aggressively sink comparisons into
1748  /// the blocks of their users.
1749  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1750  HasMultipleConditionRegisters = hasManyRegs;
1751  }
1752 
1753  /// Tells the code generator that the target has BitExtract instructions.
1754  /// The code generator will aggressively sink "shift"s into the blocks of
1755  /// their users if the users will generate "and" instructions which can be
1756  /// combined with "shift" to BitExtract instructions.
1757  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1758  HasExtractBitsInsn = hasExtractInsn;
1759  }
1760 
1761  /// Tells the code generator not to expand logic operations on comparison
1762  /// predicates into separate sequences that increase the amount of flow
1763  /// control.
1764  void setJumpIsExpensive(bool isExpensive = true);
1765 
1766  /// Tells the code generator that this target supports floating point
1767  /// exceptions and cares about preserving floating point exception behavior.
1768  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1769  HasFloatingPointExceptions = FPExceptions;
1770  }
1771 
1772  /// Tells the code generator which bitwidths to bypass.
1773  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1774  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1775  }
1776 
1777  /// Add the specified register class as an available regclass for the
1778  /// specified value type. This indicates the selector can handle values of
1779  /// that class natively.
1781  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1782  RegClassForVT[VT.SimpleTy] = RC;
1783  }
1784 
1785  /// Return the largest legal super-reg register class of the register class
1786  /// for the specified type and its associated "cost".
1787  virtual std::pair<const TargetRegisterClass *, uint8_t>
1788  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1789 
1790  /// Once all of the register classes are added, this allows us to compute
1791  /// derived properties we expose.
1792  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1793 
1794  /// Indicate that the specified operation does not work with the specified
1795  /// type and indicate what to do about it. Note that VT may refer to either
1796  /// the type of a result or that of an operand of Op.
1797  void setOperationAction(unsigned Op, MVT VT,
1798  LegalizeAction Action) {
1799  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1800  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1801  }
1802 
1803  /// Indicate that the specified load with extension does not work with the
1804  /// specified type and indicate what to do about it.
1805  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1806  LegalizeAction Action) {
1807  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1808  MemVT.isValid() && "Table isn't big enough!");
1809  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1810  unsigned Shift = 4 * ExtType;
1811  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1812  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1813  }
1814 
1815  /// Indicate that the specified truncating store does not work with the
1816  /// specified type and indicate what to do about it.
1817  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1818  LegalizeAction Action) {
1819  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1820  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1821  }
1822 
1823  /// Indicate that the specified indexed load does or does not work with the
1824  /// specified type and indicate what to do abort it.
1825  ///
1826  /// NOTE: All indexed mode loads are initialized to Expand in
1827  /// TargetLowering.cpp
1828  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1829  LegalizeAction Action) {
1830  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1831  (unsigned)Action < 0xf && "Table isn't big enough!");
1832  // Load action are kept in the upper half.
1833  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1834  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1835  }
1836 
1837  /// Indicate that the specified indexed store does or does not work with the
1838  /// specified type and indicate what to do about it.
1839  ///
1840  /// NOTE: All indexed mode stores are initialized to Expand in
1841  /// TargetLowering.cpp
1842  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1843  LegalizeAction Action) {
1844  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1845  (unsigned)Action < 0xf && "Table isn't big enough!");
1846  // Store action are kept in the lower half.
1847  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1848  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1849  }
1850 
1851  /// Indicate that the specified condition code is or isn't supported on the
1852  /// target and indicate what to do about it.
1854  LegalizeAction Action) {
1855  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1856  "Table isn't big enough!");
1857  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1858  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1859  /// value and the upper 29 bits index into the second dimension of the array
1860  /// to select what 32-bit value to use.
1861  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1862  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1863  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1864  }
1865 
1866  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1867  /// to trying a larger integer/fp until it can find one that works. If that
1868  /// default is insufficient, this method can be used by the target to override
1869  /// the default.
1870  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1871  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1872  }
1873 
1874  /// Convenience method to set an operation to Promote and specify the type
1875  /// in a single call.
1876  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1877  setOperationAction(Opc, OrigVT, Promote);
1878  AddPromotedToType(Opc, OrigVT, DestVT);
1879  }
1880 
1881  /// Targets should invoke this method for each target independent node that
1882  /// they want to provide a custom DAG combiner for by implementing the
1883  /// PerformDAGCombine virtual method.
1885  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1886  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1887  }
1888 
1889  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1890  void setJumpBufSize(unsigned Size) {
1891  JumpBufSize = Size;
1892  }
1893 
1894  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1895  /// 0
1896  void setJumpBufAlignment(unsigned Align) {
1897  JumpBufAlignment = Align;
1898  }
1899 
1900  /// Set the target's minimum function alignment (in log2(bytes))
1902  MinFunctionAlignment = Align;
1903  }
1904 
1905  /// Set the target's preferred function alignment. This should be set if
1906  /// there is a performance benefit to higher-than-minimum alignment (in
1907  /// log2(bytes))
1909  PrefFunctionAlignment = Align;
1910  }
1911 
1912  /// Set the target's preferred loop alignment. Default alignment is zero, it
1913  /// means the target does not care about loop alignment. The alignment is
1914  /// specified in log2(bytes). The target may also override
1915  /// getPrefLoopAlignment to provide per-loop values.
1916  void setPrefLoopAlignment(unsigned Align) {
1917  PrefLoopAlignment = Align;
1918  }
1919 
1920  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1922  MinStackArgumentAlignment = Align;
1923  }
1924 
1925  /// Set the maximum atomic operation size supported by the
1926  /// backend. Atomic operations greater than this size (as well as
1927  /// ones that are not naturally aligned), will be expanded by
1928  /// AtomicExpandPass into an __atomic_* library call.
1929  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1930  MaxAtomicSizeInBitsSupported = SizeInBits;
1931  }
1932 
1933  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1934  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1935  MinCmpXchgSizeInBits = SizeInBits;
1936  }
1937 
1938  /// Sets whether unaligned atomic operations are supported.
1939  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1940  SupportsUnalignedAtomics = UnalignedSupported;
1941  }
1942 
1943 public:
1944  //===--------------------------------------------------------------------===//
1945  // Addressing mode description hooks (used by LSR etc).
1946  //
1947 
1948  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1949  /// instructions reading the address. This allows as much computation as
1950  /// possible to be done in the address mode for that operand. This hook lets
1951  /// targets also pass back when this should be done on intrinsics which
1952  /// load/store.
1953  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1954  SmallVectorImpl<Value*> &/*Ops*/,
1955  Type *&/*AccessTy*/) const {
1956  return false;
1957  }
1958 
1959  /// This represents an addressing mode of:
1960  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1961  /// If BaseGV is null, there is no BaseGV.
1962  /// If BaseOffs is zero, there is no base offset.
1963  /// If HasBaseReg is false, there is no base register.
1964  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1965  /// no scale.
1966  struct AddrMode {
1967  GlobalValue *BaseGV = nullptr;
1968  int64_t BaseOffs = 0;
1969  bool HasBaseReg = false;
1970  int64_t Scale = 0;
1971  AddrMode() = default;
1972  };
1973 
1974  /// Return true if the addressing mode represented by AM is legal for this
1975  /// target, for a load/store of the specified type.
1976  ///
1977  /// The type may be VoidTy, in which case only return true if the addressing
1978  /// mode is legal for a load/store of any legal type. TODO: Handle
1979  /// pre/postinc as well.
1980  ///
1981  /// If the address space cannot be determined, it will be -1.
1982  ///
1983  /// TODO: Remove default argument
1984  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1985  Type *Ty, unsigned AddrSpace,
1986  Instruction *I = nullptr) const;
1987 
1988  /// Return the cost of the scaling factor used in the addressing mode
1989  /// represented by AM for this target, for a load/store of the specified type.
1990  ///
1991  /// If the AM is supported, the return value must be >= 0.
1992  /// If the AM is not supported, it returns a negative value.
1993  /// TODO: Handle pre/postinc as well.
1994  /// TODO: Remove default argument
1995  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1996  Type *Ty, unsigned AS = 0) const {
1997  // Default: assume that any scaling factor used in a legal AM is free.
1998  if (isLegalAddressingMode(DL, AM, Ty, AS))
1999  return 0;
2000  return -1;
2001  }
2002 
2003  /// Return true if the specified immediate is legal icmp immediate, that is
2004  /// the target has icmp instructions which can compare a register against the
2005  /// immediate without having to materialize the immediate into a register.
2006  virtual bool isLegalICmpImmediate(int64_t) const {
2007  return true;
2008  }
2009 
2010  /// Return true if the specified immediate is legal add immediate, that is the
2011  /// target has add instructions which can add a register with the immediate
2012  /// without having to materialize the immediate into a register.
2013  virtual bool isLegalAddImmediate(int64_t) const {
2014  return true;
2015  }
2016 
2017  /// Return true if it's significantly cheaper to shift a vector by a uniform
2018  /// scalar than by an amount which will vary across each lane. On x86, for
2019  /// example, there is a "psllw" instruction for the former case, but no simple
2020  /// instruction for a general "a << b" operation on vectors.
2021  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2022  return false;
2023  }
2024 
2025  /// Returns true if the opcode is a commutative binary operation.
2026  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2027  // FIXME: This should get its info from the td file.
2028  switch (Opcode) {
2029  case ISD::ADD:
2030  case ISD::SMIN:
2031  case ISD::SMAX:
2032  case ISD::UMIN:
2033  case ISD::UMAX:
2034  case ISD::MUL:
2035  case ISD::MULHU:
2036  case ISD::MULHS:
2037  case ISD::SMUL_LOHI:
2038  case ISD::UMUL_LOHI:
2039  case ISD::FADD:
2040  case ISD::FMUL:
2041  case ISD::AND:
2042  case ISD::OR:
2043  case ISD::XOR:
2044  case ISD::SADDO:
2045  case ISD::UADDO:
2046  case ISD::ADDC:
2047  case ISD::ADDE:
2048  case ISD::FMINNUM:
2049  case ISD::FMAXNUM:
2050  case ISD::FMINNAN:
2051  case ISD::FMAXNAN:
2052  return true;
2053  default: return false;
2054  }
2055  }
2056 
2057  /// Return true if it's free to truncate a value of type FromTy to type
2058  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2059  /// by referencing its sub-register AX.
2060  /// Targets must return false when FromTy <= ToTy.
2061  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2062  return false;
2063  }
2064 
2065  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2066  /// whether a call is in tail position. Typically this means that both results
2067  /// would be assigned to the same register or stack slot, but it could mean
2068  /// the target performs adequate checks of its own before proceeding with the
2069  /// tail call. Targets must return false when FromTy <= ToTy.
2070  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2071  return false;
2072  }
2073 
2074  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2075  return false;
2076  }
2077 
2078  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2079 
2080  /// Return true if the extension represented by \p I is free.
2081  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2082  /// this method can use the context provided by \p I to decide
2083  /// whether or not \p I is free.
2084  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2085  /// In other words, if is[Z|FP]Free returns true, then this method
2086  /// returns true as well. The converse is not true.
2087  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2088  /// \pre \p I must be a sign, zero, or fp extension.
2089  bool isExtFree(const Instruction *I) const {
2090  switch (I->getOpcode()) {
2091  case Instruction::FPExt:
2092  if (isFPExtFree(EVT::getEVT(I->getType()),
2093  EVT::getEVT(I->getOperand(0)->getType())))
2094  return true;
2095  break;
2096  case Instruction::ZExt:
2097  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2098  return true;
2099  break;
2100  case Instruction::SExt:
2101  break;
2102  default:
2103  llvm_unreachable("Instruction is not an extension");
2104  }
2105  return isExtFreeImpl(I);
2106  }
2107 
2108  /// Return true if \p Load and \p Ext can form an ExtLoad.
2109  /// For example, in AArch64
2110  /// %L = load i8, i8* %ptr
2111  /// %E = zext i8 %L to i32
2112  /// can be lowered into one load instruction
2113  /// ldrb w0, [x0]
2114  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2115  const DataLayout &DL) const {
2116  EVT VT = getValueType(DL, Ext->getType());
2117  EVT LoadVT = getValueType(DL, Load->getType());
2118 
2119  // If the load has other users and the truncate is not free, the ext
2120  // probably isn't free.
2121  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2122  !isTruncateFree(Ext->getType(), Load->getType()))
2123  return false;
2124 
2125  // Check whether the target supports casts folded into loads.
2126  unsigned LType;
2127  if (isa<ZExtInst>(Ext))
2128  LType = ISD::ZEXTLOAD;
2129  else {
2130  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2131  LType = ISD::SEXTLOAD;
2132  }
2133 
2134  return isLoadExtLegal(LType, VT, LoadVT);
2135  }
2136 
2137  /// Return true if any actual instruction that defines a value of type FromTy
2138  /// implicitly zero-extends the value to ToTy in the result register.
2139  ///
2140  /// The function should return true when it is likely that the truncate can
2141  /// be freely folded with an instruction defining a value of FromTy. If
2142  /// the defining instruction is unknown (because you're looking at a
2143  /// function argument, PHI, etc.) then the target may require an
2144  /// explicit truncate, which is not necessarily free, but this function
2145  /// does not deal with those cases.
2146  /// Targets must return false when FromTy >= ToTy.
2147  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2148  return false;
2149  }
2150 
2151  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2152  return false;
2153  }
2154 
2155  /// Return true if the target supplies and combines to a paired load
2156  /// two loaded values of type LoadedType next to each other in memory.
2157  /// RequiredAlignment gives the minimal alignment constraints that must be met
2158  /// to be able to select this paired load.
2159  ///
2160  /// This information is *not* used to generate actual paired loads, but it is
2161  /// used to generate a sequence of loads that is easier to combine into a
2162  /// paired load.
2163  /// For instance, something like this:
2164  /// a = load i64* addr
2165  /// b = trunc i64 a to i32
2166  /// c = lshr i64 a, 32
2167  /// d = trunc i64 c to i32
2168  /// will be optimized into:
2169  /// b = load i32* addr1
2170  /// d = load i32* addr2
2171  /// Where addr1 = addr2 +/- sizeof(i32).
2172  ///
2173  /// In other words, unless the target performs a post-isel load combining,
2174  /// this information should not be provided because it will generate more
2175  /// loads.
2176  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2177  unsigned & /*RequiredAlignment*/) const {
2178  return false;
2179  }
2180 
2181  /// Return true if the target has a vector blend instruction.
2182  virtual bool hasVectorBlend() const { return false; }
2183 
2184  /// Get the maximum supported factor for interleaved memory accesses.
2185  /// Default to be the minimum interleave factor: 2.
2186  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2187 
2188  /// Lower an interleaved load to target specific intrinsics. Return
2189  /// true on success.
2190  ///
2191  /// \p LI is the vector load instruction.
2192  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2193  /// \p Indices is the corresponding indices for each shufflevector.
2194  /// \p Factor is the interleave factor.
2195  virtual bool lowerInterleavedLoad(LoadInst *LI,
2197  ArrayRef<unsigned> Indices,
2198  unsigned Factor) const {
2199  return false;
2200  }
2201 
2202  /// Lower an interleaved store to target specific intrinsics. Return
2203  /// true on success.
2204  ///
2205  /// \p SI is the vector store instruction.
2206  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2207  /// \p Factor is the interleave factor.
2209  unsigned Factor) const {
2210  return false;
2211  }
2212 
2213  /// Return true if zero-extending the specific node Val to type VT2 is free
2214  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2215  /// because it's folded such as X86 zero-extending loads).
2216  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2217  return isZExtFree(Val.getValueType(), VT2);
2218  }
2219 
2220  /// Return true if an fpext operation is free (for instance, because
2221  /// single-precision floating-point numbers are implicitly extended to
2222  /// double-precision).
2223  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2224  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2225  "invalid fpext types");
2226  return false;
2227  }
2228 
2229  /// Return true if an fpext operation input to an \p Opcode operation is free
2230  /// (for instance, because half-precision floating-point numbers are
2231  /// implicitly extended to float-precision) for an FMA instruction.
2232  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2233  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2234  "invalid fpext types");
2235  return isFPExtFree(DestVT, SrcVT);
2236  }
2237 
2238  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2239  /// extend node) is profitable.
2240  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2241 
2242  /// Return true if an fneg operation is free to the point where it is never
2243  /// worthwhile to replace it with a bitwise operation.
2244  virtual bool isFNegFree(EVT VT) const {
2245  assert(VT.isFloatingPoint());
2246  return false;
2247  }
2248 
2249  /// Return true if an fabs operation is free to the point where it is never
2250  /// worthwhile to replace it with a bitwise operation.
2251  virtual bool isFAbsFree(EVT VT) const {
2252  assert(VT.isFloatingPoint());
2253  return false;
2254  }
2255 
2256  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2257  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2258  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2259  ///
2260  /// NOTE: This may be called before legalization on types for which FMAs are
2261  /// not legal, but should return true if those types will eventually legalize
2262  /// to types that support FMAs. After legalization, it will only be called on
2263  /// types that support FMAs (via Legal or Custom actions)
2264  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2265  return false;
2266  }
2267 
2268  /// Return true if it's profitable to narrow operations of type VT1 to
2269  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2270  /// i32 to i16.
2271  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2272  return false;
2273  }
2274 
2275  /// Return true if it is beneficial to convert a load of a constant to
2276  /// just the constant itself.
2277  /// On some targets it might be more efficient to use a combination of
2278  /// arithmetic instructions to materialize the constant instead of loading it
2279  /// from a constant pool.
2280  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2281  Type *Ty) const {
2282  return false;
2283  }
2284 
2285  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2286  /// from this source type with this index. This is needed because
2287  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2288  /// the first element, and only the target knows which lowering is cheap.
2289  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2290  unsigned Index) const {
2291  return false;
2292  }
2293 
2294  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2295  // even if the vector itself has multiple uses.
2296  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2297  return false;
2298  }
2299 
2300  // Return true if CodeGenPrepare should consider splitting large offset of a
2301  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2302  // same blocks of its users.
2303  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2304 
2305  //===--------------------------------------------------------------------===//
2306  // Runtime Library hooks
2307  //
2308 
2309  /// Rename the default libcall routine name for the specified libcall.
2310  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2311  LibcallRoutineNames[Call] = Name;
2312  }
2313 
2314  /// Get the libcall routine name for the specified libcall.
2315  const char *getLibcallName(RTLIB::Libcall Call) const {
2316  return LibcallRoutineNames[Call];
2317  }
2318 
2319  /// Override the default CondCode to be used to test the result of the
2320  /// comparison libcall against zero.
2322  CmpLibcallCCs[Call] = CC;
2323  }
2324 
2325  /// Get the CondCode that's to be used to test the result of the comparison
2326  /// libcall against zero.
2328  return CmpLibcallCCs[Call];
2329  }
2330 
2331  /// Set the CallingConv that should be used for the specified libcall.
2333  LibcallCallingConvs[Call] = CC;
2334  }
2335 
2336  /// Get the CallingConv that should be used for the specified libcall.
2338  return LibcallCallingConvs[Call];
2339  }
2340 
2341  /// Execute target specific actions to finalize target lowering.
2342  /// This is used to set extra flags in MachineFrameInformation and freezing
2343  /// the set of reserved registers.
2344  /// The default implementation just freezes the set of reserved registers.
2345  virtual void finalizeLowering(MachineFunction &MF) const;
2346 
2347 private:
2348  const TargetMachine &TM;
2349 
2350  /// Tells the code generator that the target has multiple (allocatable)
2351  /// condition registers that can be used to store the results of comparisons
2352  /// for use by selects and conditional branches. With multiple condition
2353  /// registers, the code generator will not aggressively sink comparisons into
2354  /// the blocks of their users.
2355  bool HasMultipleConditionRegisters;
2356 
2357  /// Tells the code generator that the target has BitExtract instructions.
2358  /// The code generator will aggressively sink "shift"s into the blocks of
2359  /// their users if the users will generate "and" instructions which can be
2360  /// combined with "shift" to BitExtract instructions.
2361  bool HasExtractBitsInsn;
2362 
2363  /// Tells the code generator to bypass slow divide or remainder
2364  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2365  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2366  /// div/rem when the operands are positive and less than 256.
2367  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2368 
2369  /// Tells the code generator that it shouldn't generate extra flow control
2370  /// instructions and should attempt to combine flow control instructions via
2371  /// predication.
2372  bool JumpIsExpensive;
2373 
2374  /// Whether the target supports or cares about preserving floating point
2375  /// exception behavior.
2376  bool HasFloatingPointExceptions;
2377 
2378  /// This target prefers to use _setjmp to implement llvm.setjmp.
2379  ///
2380  /// Defaults to false.
2381  bool UseUnderscoreSetJmp;
2382 
2383  /// This target prefers to use _longjmp to implement llvm.longjmp.
2384  ///
2385  /// Defaults to false.
2386  bool UseUnderscoreLongJmp;
2387 
2388  /// Information about the contents of the high-bits in boolean values held in
2389  /// a type wider than i1. See getBooleanContents.
2390  BooleanContent BooleanContents;
2391 
2392  /// Information about the contents of the high-bits in boolean values held in
2393  /// a type wider than i1. See getBooleanContents.
2394  BooleanContent BooleanFloatContents;
2395 
2396  /// Information about the contents of the high-bits in boolean vector values
2397  /// when the element type is wider than i1. See getBooleanContents.
2398  BooleanContent BooleanVectorContents;
2399 
2400  /// The target scheduling preference: shortest possible total cycles or lowest
2401  /// register usage.
2402  Sched::Preference SchedPreferenceInfo;
2403 
2404  /// The size, in bytes, of the target's jmp_buf buffers
2405  unsigned JumpBufSize;
2406 
2407  /// The alignment, in bytes, of the target's jmp_buf buffers
2408  unsigned JumpBufAlignment;
2409 
2410  /// The minimum alignment that any argument on the stack needs to have.
2411  unsigned MinStackArgumentAlignment;
2412 
2413  /// The minimum function alignment (used when optimizing for size, and to
2414  /// prevent explicitly provided alignment from leading to incorrect code).
2415  unsigned MinFunctionAlignment;
2416 
2417  /// The preferred function alignment (used when alignment unspecified and
2418  /// optimizing for speed).
2419  unsigned PrefFunctionAlignment;
2420 
2421  /// The preferred loop alignment.
2422  unsigned PrefLoopAlignment;
2423 
2424  /// Size in bits of the maximum atomics size the backend supports.
2425  /// Accesses larger than this will be expanded by AtomicExpandPass.
2426  unsigned MaxAtomicSizeInBitsSupported;
2427 
2428  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2429  /// backend supports.
2430  unsigned MinCmpXchgSizeInBits;
2431 
2432  /// This indicates if the target supports unaligned atomic operations.
2433  bool SupportsUnalignedAtomics;
2434 
2435  /// If set to a physical register, this specifies the register that
2436  /// llvm.savestack/llvm.restorestack should save and restore.
2437  unsigned StackPointerRegisterToSaveRestore;
2438 
2439  /// This indicates the default register class to use for each ValueType the
2440  /// target supports natively.
2441  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2442  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2443  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2444 
2445  /// This indicates the "representative" register class to use for each
2446  /// ValueType the target supports natively. This information is used by the
2447  /// scheduler to track register pressure. By default, the representative
2448  /// register class is the largest legal super-reg register class of the
2449  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2450  /// representative class would be GR32.
2451  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2452 
2453  /// This indicates the "cost" of the "representative" register class for each
2454  /// ValueType. The cost is used by the scheduler to approximate register
2455  /// pressure.
2456  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2457 
2458  /// For any value types we are promoting or expanding, this contains the value
2459  /// type that we are changing to. For Expanded types, this contains one step
2460  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2461  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2462  /// the same type (e.g. i32 -> i32).
2463  MVT TransformToType[MVT::LAST_VALUETYPE];
2464 
2465  /// For each operation and each value type, keep a LegalizeAction that
2466  /// indicates how instruction selection should deal with the operation. Most
2467  /// operations are Legal (aka, supported natively by the target), but
2468  /// operations that are not should be described. Note that operations on
2469  /// non-legal value types are not described here.
2471 
2472  /// For each load extension type and each value type, keep a LegalizeAction
2473  /// that indicates how instruction selection should deal with a load of a
2474  /// specific value type and extension type. Uses 4-bits to store the action
2475  /// for each of the 4 load ext types.
2476  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2477 
2478  /// For each value type pair keep a LegalizeAction that indicates whether a
2479  /// truncating store of a specific value type and truncating type is legal.
2481 
2482  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2483  /// that indicates how instruction selection should deal with the load /
2484  /// store.
2485  ///
2486  /// The first dimension is the value_type for the reference. The second
2487  /// dimension represents the various modes for load store.
2488  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2489 
2490  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2491  /// indicates how instruction selection should deal with the condition code.
2492  ///
2493  /// Because each CC action takes up 4 bits, we need to have the array size be
2494  /// large enough to fit all of the value types. This can be done by rounding
2495  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2496  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2497 
2498 protected:
2500 
2501 private:
2502  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2503 
2504  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2505  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2506  /// array.
2507  unsigned char
2508  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2509 
2510  /// For operations that must be promoted to a specific type, this holds the
2511  /// destination type. This map should be sparse, so don't hold it as an
2512  /// array.
2513  ///
2514  /// Targets add entries to this map with AddPromotedToType(..), clients access
2515  /// this with getTypeToPromoteTo(..).
2516  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2517  PromoteToType;
2518 
2519  /// Stores the name each libcall.
2520  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2521 
2522  /// The ISD::CondCode that should be used to test the result of each of the
2523  /// comparison libcall against zero.
2524  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2525 
2526  /// Stores the CallingConv that should be used for each libcall.
2527  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2528 
2529  /// Set default libcall names and calling conventions.
2530  void InitLibcalls(const Triple &TT);
2531 
2532 protected:
2533  /// Return true if the extension represented by \p I is free.
2534  /// \pre \p I is a sign, zero, or fp extension and
2535  /// is[Z|FP]ExtFree of the related types is not true.
2536  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2537 
2538  /// Depth that GatherAllAliases should should continue looking for chain
2539  /// dependencies when trying to find a more preferable chain. As an
2540  /// approximation, this should be more than the number of consecutive stores
2541  /// expected to be merged.
2543 
2544  /// Specify maximum number of store instructions per memset call.
2545  ///
2546  /// When lowering \@llvm.memset this field specifies the maximum number of
2547  /// store operations that may be substituted for the call to memset. Targets
2548  /// must set this value based on the cost threshold for that target. Targets
2549  /// should assume that the memset will be done using as many of the largest
2550  /// store operations first, followed by smaller ones, if necessary, per
2551  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2552  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2553  /// store. This only applies to setting a constant array of a constant size.
2555 
2556  /// Maximum number of stores operations that may be substituted for the call
2557  /// to memset, used for functions with OptSize attribute.
2559 
2560  /// Specify maximum bytes of store instructions per memcpy call.
2561  ///
2562  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2563  /// store operations that may be substituted for a call to memcpy. Targets
2564  /// must set this value based on the cost threshold for that target. Targets
2565  /// should assume that the memcpy will be done using as many of the largest
2566  /// store operations first, followed by smaller ones, if necessary, per
2567  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2568  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2569  /// and one 1-byte store. This only applies to copying a constant array of
2570  /// constant size.
2572 
2573 
2574  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2575  ///
2576  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2577  /// of store instructions to keep together. This helps in pairing and
2578  // vectorization later on.
2579  unsigned MaxGluedStoresPerMemcpy = 0;
2580 
2581  /// Maximum number of store operations that may be substituted for a call to
2582  /// memcpy, used for functions with OptSize attribute.
2586 
2587  /// Specify maximum bytes of store instructions per memmove call.
2588  ///
2589  /// When lowering \@llvm.memmove this field specifies the maximum number of
2590  /// store instructions that may be substituted for a call to memmove. Targets
2591  /// must set this value based on the cost threshold for that target. Targets
2592  /// should assume that the memmove will be done using as many of the largest
2593  /// store operations first, followed by smaller ones, if necessary, per
2594  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2595  /// with 8-bit alignment would result in nine 1-byte stores. This only
2596  /// applies to copying a constant array of constant size.
2598 
2599  /// Maximum number of store instructions that may be substituted for a call to
2600  /// memmove, used for functions with OptSize attribute.
2602 
2603  /// Tells the code generator that select is more expensive than a branch if
2604  /// the branch is usually predicted right.
2606 
2607  /// \see enableExtLdPromotion.
2609 
2610  /// Return true if the value types that can be represented by the specified
2611  /// register class are all legal.
2612  bool isLegalRC(const TargetRegisterInfo &TRI,
2613  const TargetRegisterClass &RC) const;
2614 
2615  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2616  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2617  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2618  MachineBasicBlock *MBB) const;
2619 
2620  /// Replace/modify the XRay custom event operands with target-dependent
2621  /// details.
2622  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2623  MachineBasicBlock *MBB) const;
2624 
2625  /// Replace/modify the XRay typed event operands with target-dependent
2626  /// details.
2627  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2628  MachineBasicBlock *MBB) const;
2629 };
2630 
2631 /// This class defines information used to lower LLVM code to legal SelectionDAG
2632 /// operators that the target instruction selector can accept natively.
2633 ///
2634 /// This class also defines callbacks that targets must implement to lower
2635 /// target-specific constructs to SelectionDAG operators.
2637 public:
2638  struct DAGCombinerInfo;
2639 
2640  TargetLowering(const TargetLowering &) = delete;
2641  TargetLowering &operator=(const TargetLowering &) = delete;
2642 
2643  /// NOTE: The TargetMachine owns TLOF.
2644  explicit TargetLowering(const TargetMachine &TM);
2645 
2646  bool isPositionIndependent() const;
2647 
2648  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2649  FunctionLoweringInfo *FLI,
2650  DivergenceAnalysis *DA) const {
2651  return false;
2652  }
2653 
2654  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2655  return false;
2656  }
2657 
2658  /// Returns true by value, base pointer and offset pointer and addressing mode
2659  /// by reference if the node's address can be legally represented as
2660  /// pre-indexed load / store address.
2661  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2662  SDValue &/*Offset*/,
2663  ISD::MemIndexedMode &/*AM*/,
2664  SelectionDAG &/*DAG*/) const {
2665  return false;
2666  }
2667 
2668  /// Returns true by value, base pointer and offset pointer and addressing mode
2669  /// by reference if this node can be combined with a load / store to form a
2670  /// post-indexed load / store.
2671  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2672  SDValue &/*Base*/,
2673  SDValue &/*Offset*/,
2674  ISD::MemIndexedMode &/*AM*/,
2675  SelectionDAG &/*DAG*/) const {
2676  return false;
2677  }
2678 
2679  /// Return the entry encoding for a jump table in the current function. The
2680  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2681  virtual unsigned getJumpTableEncoding() const;
2682 
2683  virtual const MCExpr *
2685  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2686  MCContext &/*Ctx*/) const {
2687  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2688  }
2689 
2690  /// Returns relocation base for the given PIC jumptable.
2691  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2692  SelectionDAG &DAG) const;
2693 
2694  /// This returns the relocation base for the given PIC jumptable, the same as
2695  /// getPICJumpTableRelocBase, but as an MCExpr.
2696  virtual const MCExpr *
2697  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2698  unsigned JTI, MCContext &Ctx) const;
2699 
2700  /// Return true if folding a constant offset with the given GlobalAddress is
2701  /// legal. It is frequently not legal in PIC relocation models.
2702  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2703 
2704  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2705  SDValue &Chain) const;
2706 
2707  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2708  SDValue &NewRHS, ISD::CondCode &CCCode,
2709  const SDLoc &DL) const;
2710 
2711  /// Returns a pair of (return value, chain).
2712  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2713  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2714  EVT RetVT, ArrayRef<SDValue> Ops,
2715  bool isSigned, const SDLoc &dl,
2716  bool doesNotReturn = false,
2717  bool isReturnValueUsed = true) const;
2718 
2719  /// Check whether parameters to a call that are passed in callee saved
2720  /// registers are the same as from the calling function. This needs to be
2721  /// checked for tail call eligibility.
2722  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2723  const uint32_t *CallerPreservedMask,
2724  const SmallVectorImpl<CCValAssign> &ArgLocs,
2725  const SmallVectorImpl<SDValue> &OutVals) const;
2726 
2727  //===--------------------------------------------------------------------===//
2728  // TargetLowering Optimization Methods
2729  //
2730 
2731  /// A convenience struct that encapsulates a DAG, and two SDValues for
2732  /// returning information from TargetLowering to its clients that want to
2733  /// combine.
2736  bool LegalTys;
2737  bool LegalOps;
2740 
2742  bool LT, bool LO) :
2743  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2744 
2745  bool LegalTypes() const { return LegalTys; }
2746  bool LegalOperations() const { return LegalOps; }
2747 
2749  Old = O;
2750  New = N;
2751  return true;
2752  }
2753  };
2754 
2755  /// Check to see if the specified operand of the specified instruction is a
2756  /// constant integer. If so, check to see if there are any bits set in the
2757  /// constant that are not demanded. If so, shrink the constant and return
2758  /// true.
2759  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2760  TargetLoweringOpt &TLO) const;
2761 
2762  // Target hook to do target-specific const optimization, which is called by
2763  // ShrinkDemandedConstant. This function should return true if the target
2764  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2765  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2766  TargetLoweringOpt &TLO) const {
2767  return false;
2768  }
2769 
2770  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2771  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2772  /// generalized for targets with other types of implicit widening casts.
2773  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2774  TargetLoweringOpt &TLO) const;
2775 
2776  /// Helper for SimplifyDemandedBits that can simplify an operation with
2777  /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2778  /// then updates \p User with the simplified version. No other uses of
2779  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2780  /// function behaves exactly like function SimplifyDemandedBits declared
2781  /// below except that it also updates the DAG by calling
2782  /// DCI.CommitTargetLoweringOpt.
2783  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2784  DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2785 
2786  /// Look at Op. At this point, we know that only the DemandedMask bits of the
2787  /// result of Op are ever used downstream. If we can use this information to
2788  /// simplify Op, create a new simplified DAG node and return true, returning
2789  /// the original and new nodes in Old and New. Otherwise, analyze the
2790  /// expression and return a mask of KnownOne and KnownZero bits for the
2791  /// expression (used to simplify the caller). The KnownZero/One bits may only
2792  /// be accurate for those bits in the DemandedMask.
2793  /// \p AssumeSingleUse When this parameter is true, this function will
2794  /// attempt to simplify \p Op even if there are multiple uses.
2795  /// Callers are responsible for correctly updating the DAG based on the
2796  /// results of this function, because simply replacing replacing TLO.Old
2797  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2798  /// has multiple uses.
2799  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2800  KnownBits &Known,
2801  TargetLoweringOpt &TLO,
2802  unsigned Depth = 0,
2803  bool AssumeSingleUse = false) const;
2804 
2805  /// Helper wrapper around SimplifyDemandedBits
2806  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2807  DAGCombinerInfo &DCI) const;
2808 
2809  /// Look at Vector Op. At this point, we know that only the DemandedElts
2810  /// elements of the result of Op are ever used downstream. If we can use
2811  /// this information to simplify Op, create a new simplified DAG node and
2812  /// return true, storing the original and new nodes in TLO.
2813  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2814  /// KnownZero elements for the expression (used to simplify the caller).
2815  /// The KnownUndef/Zero elements may only be accurate for those bits
2816  /// in the DemandedMask.
2817  /// \p AssumeSingleUse When this parameter is true, this function will
2818  /// attempt to simplify \p Op even if there are multiple uses.
2819  /// Callers are responsible for correctly updating the DAG based on the
2820  /// results of this function, because simply replacing replacing TLO.Old
2821  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2822  /// has multiple uses.
2823  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2824  APInt &KnownUndef, APInt &KnownZero,
2825  TargetLoweringOpt &TLO, unsigned Depth = 0,
2826  bool AssumeSingleUse = false) const;
2827 
2828  /// Helper wrapper around SimplifyDemandedVectorElts
2829  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2830  APInt &KnownUndef, APInt &KnownZero,
2831  DAGCombinerInfo &DCI) const;
2832 
2833  /// Determine which of the bits specified in Mask are known to be either zero
2834  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2835  /// argument allows us to only collect the known bits that are shared by the
2836  /// requested vector elements.
2837  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2838  KnownBits &Known,
2839  const APInt &DemandedElts,
2840  const SelectionDAG &DAG,
2841  unsigned Depth = 0) const;
2842 
2843  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2844  /// Default implementation computes low bits based on alignment
2845  /// information. This should preserve known bits passed into it.
2846  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2847  KnownBits &Known,
2848  const APInt &DemandedElts,
2849  const SelectionDAG &DAG,
2850  unsigned Depth = 0) const;
2851 
2852  /// This method can be implemented by targets that want to expose additional
2853  /// information about sign bits to the DAG Combiner. The DemandedElts
2854  /// argument allows us to only collect the minimum sign bits that are shared
2855  /// by the requested vector elements.
2856  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2857  const APInt &DemandedElts,
2858  const SelectionDAG &DAG,
2859  unsigned Depth = 0) const;
2860 
2861  /// Attempt to simplify any target nodes based on the demanded vector
2862  /// elements, returning true on success. Otherwise, analyze the expression and
2863  /// return a mask of KnownUndef and KnownZero elements for the expression
2864  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2865  /// accurate for those bits in the DemandedMask
2866  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2867  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2868  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2869 
2871  void *DC; // The DAG Combiner object.
2874 
2875  public:
2877 
2878  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2879  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2880 
2881  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2882  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2883  bool isAfterLegalizeDAG() const {
2884  return Level == AfterLegalizeDAG;
2885  }
2887  bool isCalledByLegalizer() const { return CalledByLegalizer; }
2888 
2889  void AddToWorklist(SDNode *N);
2890  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2891  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2892  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2893 
2894  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2895  };
2896 
2897  /// Return if the N is a constant or constant vector equal to the true value
2898  /// from getBooleanContents().
2899  bool isConstTrueVal(const SDNode *N) const;
2900 
2901  /// Return if the N is a constant or constant vector equal to the false value
2902  /// from getBooleanContents().
2903  bool isConstFalseVal(const SDNode *N) const;
2904 
2905  /// Return if \p N is a True value when extended to \p VT.
2906  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
2907 
2908  /// Try to simplify a setcc built with the specified operands and cc. If it is
2909  /// unable to simplify it, return a null SDValue.
2910  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2911  bool foldBooleans, DAGCombinerInfo &DCI,
2912  const SDLoc &dl) const;
2913 
2914  // For targets which wrap address, unwrap for analysis.
2915  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2916 
2917  /// Returns true (and the GlobalValue and the offset) if the node is a
2918  /// GlobalAddress + offset.
2919  virtual bool
2920  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2921 
2922  /// This method will be invoked for all target nodes and for any
2923  /// target-independent nodes that the target has registered with invoke it
2924  /// for.
2925  ///
2926  /// The semantics are as follows:
2927  /// Return Value:
2928  /// SDValue.Val == 0 - No change was made
2929  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2930  /// otherwise - N should be replaced by the returned Operand.
2931  ///
2932  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2933  /// more complex transformations.
2934  ///
2935  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2936 
2937  /// Return true if it is profitable to move a following shift through this
2938  // node, adjusting any immediate operands as necessary to preserve semantics.
2939  // This transformation may not be desirable if it disrupts a particularly
2940  // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2941  // By default, it returns true.
2942  virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2943  return true;
2944  }
2945 
2946  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2947  // to a shuffle and a truncate.
2948  // Example of such a combine:
2949  // v4i32 build_vector((extract_elt V, 1),
2950  // (extract_elt V, 3),
2951  // (extract_elt V, 5),
2952  // (extract_elt V, 7))
2953  // -->
2954  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2956  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2957  return false;
2958  }
2959 
2960  /// Return true if the target has native support for the specified value type
2961  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2962  /// i16 is legal, but undesirable since i16 instruction encodings are longer
2963  /// and some i16 instructions are slow.
2964  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2965  // By default, assume all legal types are desirable.
2966  return isTypeLegal(VT);
2967  }
2968 
2969  /// Return true if it is profitable for dag combiner to transform a floating
2970  /// point op of specified opcode to a equivalent op of an integer
2971  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2972  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2973  EVT /*VT*/) const {
2974  return false;
2975  }
2976 
2977  /// This method query the target whether it is beneficial for dag combiner to
2978  /// promote the specified node. If true, it should return the desired
2979  /// promotion type by reference.
2980  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2981  return false;
2982  }
2983 
2984  /// Return true if the target supports swifterror attribute. It optimizes
2985  /// loads and stores to reading and writing a specific register.
2986  virtual bool supportSwiftError() const {
2987  return false;
2988  }
2989 
2990  /// Return true if the target supports that a subset of CSRs for the given
2991  /// machine function is handled explicitly via copies.
2992  virtual bool supportSplitCSR(MachineFunction *MF) const {
2993  return false;
2994  }
2995 
2996  /// Perform necessary initialization to handle a subset of CSRs explicitly
2997  /// via copies. This function is called at the beginning of instruction
2998  /// selection.
2999  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3000  llvm_unreachable("Not Implemented");
3001  }
3002 
3003  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3004  /// CSRs to virtual registers in the entry block, and copy them back to
3005  /// physical registers in the exit blocks. This function is called at the end
3006  /// of instruction selection.
3007  virtual void insertCopiesSplitCSR(
3008  MachineBasicBlock *Entry,
3009  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3010  llvm_unreachable("Not Implemented");
3011  }
3012 
3013  //===--------------------------------------------------------------------===//
3014  // Lowering methods - These methods must be implemented by targets so that
3015  // the SelectionDAGBuilder code knows how to lower these.
3016  //
3017 
3018  /// This hook must be implemented to lower the incoming (formal) arguments,
3019  /// described by the Ins array, into the specified DAG. The implementation
3020  /// should fill in the InVals array with legal-type argument values, and
3021  /// return the resulting token chain value.
3023  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3024  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3025  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3026  llvm_unreachable("Not Implemented");
3027  }
3028 
3029  /// This structure contains all information that is necessary for lowering
3030  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3031  /// needs to lower a call, and targets will see this struct in their LowerCall
3032  /// implementation.
3035  Type *RetTy = nullptr;
3036  bool RetSExt : 1;
3037  bool RetZExt : 1;
3038  bool IsVarArg : 1;
3039  bool IsInReg : 1;
3040  bool DoesNotReturn : 1;
3042  bool IsConvergent : 1;
3043  bool IsPatchPoint : 1;
3044 
3045  // IsTailCall should be modified by implementations of
3046  // TargetLowering::LowerCall that perform tail call conversions.
3047  bool IsTailCall = false;
3048 
3049  // Is Call lowering done post SelectionDAG type legalization.
3050  bool IsPostTypeLegalization = false;
3051 
3052  unsigned NumFixedArgs = -1;
3055  ArgListTy Args;
3063 
3065  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3066  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3067  IsPatchPoint(false), DAG(DAG) {}
3068 
3070  DL = dl;
3071  return *this;
3072  }
3073 
3075  Chain = InChain;
3076  return *this;
3077  }
3078 
3079  // setCallee with target/module-specific attributes
3081  SDValue Target, ArgListTy &&ArgsList) {
3082  RetTy = ResultType;
3083  Callee = Target;
3084  CallConv = CC;
3085  NumFixedArgs = ArgsList.size();
3086  Args = std::move(ArgsList);
3087 
3089  &(DAG.getMachineFunction()), CC, Args);
3090  return *this;
3091  }
3092 
3094  SDValue Target, ArgListTy &&ArgsList) {
3095  RetTy = ResultType;
3096  Callee = Target;
3097  CallConv = CC;
3098  NumFixedArgs = ArgsList.size();
3099  Args = std::move(ArgsList);
3100  return *this;
3101  }
3102 
3104  SDValue Target, ArgListTy &&ArgsList,
3105  ImmutableCallSite Call) {
3106  RetTy = ResultType;
3107 
3108  IsInReg = Call.hasRetAttr(Attribute::InReg);
3109  DoesNotReturn =
3110  Call.doesNotReturn() ||
3111  (!Call.isInvoke() &&
3112  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3113  IsVarArg = FTy->isVarArg();
3114  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3115  RetSExt = Call.hasRetAttr(Attribute::SExt);
3116  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3117 
3118  Callee = Target;
3119 
3120  CallConv = Call.getCallingConv();
3121  NumFixedArgs = FTy->getNumParams();
3122  Args = std::move(ArgsList);
3123 
3124  CS = Call;
3125 
3126  return *this;
3127  }
3128 
3130  IsInReg = Value;
3131  return *this;
3132  }
3133 
3135  DoesNotReturn = Value;
3136  return *this;
3137  }
3138 
3140  IsVarArg = Value;
3141  return *this;
3142  }
3143 
3145  IsTailCall = Value;
3146  return *this;
3147  }
3148 
3150  IsReturnValueUsed = !Value;
3151  return *this;
3152  }
3153 
3155  IsConvergent = Value;
3156  return *this;
3157  }
3158 
3160  RetSExt = Value;
3161  return *this;
3162  }
3163 
3165  RetZExt = Value;
3166  return *this;
3167  }
3168 
3170  IsPatchPoint = Value;
3171  return *this;
3172  }
3173 
3175  IsPostTypeLegalization = Value;
3176  return *this;
3177  }
3178 
3179  ArgListTy &getArgs() {
3180  return Args;
3181  }
3182  };
3183 
3184  /// This function lowers an abstract call to a function into an actual call.
3185  /// This returns a pair of operands. The first element is the return value
3186  /// for the function (if RetTy is not VoidTy). The second element is the
3187  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3188  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3189 
3190  /// This hook must be implemented to lower calls into the specified
3191  /// DAG. The outgoing arguments to the call are described by the Outs array,
3192  /// and the values to be returned by the call are described by the Ins
3193  /// array. The implementation should fill in the InVals array with legal-type
3194  /// return values from the call, and return the resulting token chain value.
3195  virtual SDValue
3197  SmallVectorImpl<SDValue> &/*InVals*/) const {
3198  llvm_unreachable("Not Implemented");
3199  }
3200 
3201  /// Target-specific cleanup for formal ByVal parameters.
3202  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3203 
3204  /// This hook should be implemented to check whether the return values
3205  /// described by the Outs array can fit into the return registers. If false
3206  /// is returned, an sret-demotion is performed.
3207  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3208  MachineFunction &/*MF*/, bool /*isVarArg*/,
3209  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3210  LLVMContext &/*Context*/) const
3211  {
3212  // Return true by default to get preexisting behavior.
3213  return true;
3214  }
3215 
3216  /// This hook must be implemented to lower outgoing return values, described
3217  /// by the Outs array, into the specified DAG. The implementation should
3218  /// return the resulting token chain value.
3219  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3220  bool /*isVarArg*/,
3221  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3222  const SmallVectorImpl<SDValue> & /*OutVals*/,
3223  const SDLoc & /*dl*/,
3224  SelectionDAG & /*DAG*/) const {
3225  llvm_unreachable("Not Implemented");
3226  }
3227 
3228  /// Return true if result of the specified node is used by a return node
3229  /// only. It also compute and return the input chain for the tail call.
3230  ///
3231  /// This is used to determine whether it is possible to codegen a libcall as
3232  /// tail call at legalization time.
3233  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3234  return false;
3235  }
3236 
3237  /// Return true if the target may be able emit the call instruction as a tail
3238  /// call. This is used by optimization passes to determine if it's profitable
3239  /// to duplicate return instructions to enable tailcall optimization.
3240  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3241  return false;
3242  }
3243 
3244  /// Return the builtin name for the __builtin___clear_cache intrinsic
3245  /// Default is to invoke the clear cache library call
3246  virtual const char * getClearCacheBuiltinName() const {
3247  return "__clear_cache";
3248  }
3249 
3250  /// Return the register ID of the name passed in. Used by named register
3251  /// global variables extension. There is no target-independent behaviour
3252  /// so the default action is to bail.
3253  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3254  SelectionDAG &DAG) const {
3255  report_fatal_error("Named registers not implemented for this target");
3256  }
3257 
3258  /// Return the type that should be used to zero or sign extend a
3259  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3260  /// require the return type to be promoted, but this is not true all the time,
3261  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3262  /// conventions. The frontend should handle this and include all of the
3263  /// necessary information.
3265  ISD::NodeType /*ExtendKind*/) const {
3266  EVT MinVT = getRegisterType(Context, MVT::i32);
3267  return VT.bitsLT(MinVT) ? MinVT : VT;
3268  }
3269 
3270  /// For some targets, an LLVM struct type must be broken down into multiple
3271  /// simple types, but the calling convention specifies that the entire struct
3272  /// must be passed in a block of consecutive registers.
3273  virtual bool
3275  bool isVarArg) const {
3276  return false;
3277  }
3278 
3279  /// Returns a 0 terminated array of registers that can be safely used as
3280  /// scratch registers.
3281  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3282  return nullptr;
3283  }
3284 
3285  /// This callback is used to prepare for a volatile or atomic load.
3286  /// It takes a chain node as input and returns the chain for the load itself.
3287  ///
3288  /// Having a callback like this is necessary for targets like SystemZ,
3289  /// which allows a CPU to reuse the result of a previous load indefinitely,
3290  /// even if a cache-coherent store is performed by another CPU. The default
3291  /// implementation does nothing.
3293  SelectionDAG &DAG) const {
3294  return Chain;
3295  }
3296 
3297  /// This callback is used to inspect load/store instructions and add
3298  /// target-specific MachineMemOperand flags to them. The default
3299  /// implementation does nothing.
3302  }
3303 
3304  /// This callback is invoked by the type legalizer to legalize nodes with an
3305  /// illegal operand type but legal result types. It replaces the
3306  /// LowerOperation callback in the type Legalizer. The reason we can not do
3307  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3308  /// use this callback.
3309  ///
3310  /// TODO: Consider merging with ReplaceNodeResults.
3311  ///
3312  /// The target places new result values for the node in Results (their number
3313  /// and types must exactly match those of the original return values of
3314  /// the node), or leaves Results empty, which indicates that the node is not
3315  /// to be custom lowered after all.
3316  /// The default implementation calls LowerOperation.
3317  virtual void LowerOperationWrapper(SDNode *N,
3319  SelectionDAG &DAG) const;
3320 
3321  /// This callback is invoked for operations that are unsupported by the
3322  /// target, which are registered to use 'custom' lowering, and whose defined
3323  /// values are all legal. If the target has no operations that require custom
3324  /// lowering, it need not implement this. The default implementation of this
3325  /// aborts.
3326  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3327 
3328  /// This callback is invoked when a node result type is illegal for the
3329  /// target, and the operation was registered to use 'custom' lowering for that
3330  /// result type. The target places new result values for the node in Results
3331  /// (their number and types must exactly match those of the original return
3332  /// values of the node), or leaves Results empty, which indicates that the
3333  /// node is not to be custom lowered after all.
3334  ///
3335  /// If the target has no operations that require custom lowering, it need not
3336  /// implement this. The default implementation aborts.
3337  virtual void ReplaceNodeResults(SDNode * /*N*/,
3338  SmallVectorImpl<SDValue> &/*Results*/,
3339  SelectionDAG &/*DAG*/) const {
3340  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3341  }
3342 
3343  /// This method returns the name of a target specific DAG node.
3344  virtual const char *getTargetNodeName(unsigned Opcode) const;
3345 
3346  /// This method returns a target specific FastISel object, or null if the
3347  /// target does not support "fast" ISel.
3349  const TargetLibraryInfo *) const {
3350  return nullptr;
3351  }
3352 
3353  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3354  SelectionDAG &DAG) const;
3355 
3356  //===--------------------------------------------------------------------===//
3357  // Inline Asm Support hooks
3358  //
3359 
3360  /// This hook allows the target to expand an inline asm call to be explicit
3361  /// llvm code if it wants to. This is useful for turning simple inline asms
3362  /// into LLVM intrinsics, which gives the compiler more information about the
3363  /// behavior of the code.
3364  virtual bool ExpandInlineAsm(CallInst *) const {
3365  return false;
3366  }
3367 
3369  C_Register, // Constraint represents specific register(s).
3370  C_RegisterClass, // Constraint represents any of register(s) in class.
3371  C_Memory, // Memory constraint.
3372  C_Other, // Something else.
3373  C_Unknown // Unsupported constraint.
3374  };
3375 
3377  // Generic weights.
3378  CW_Invalid = -1, // No match.
3379  CW_Okay = 0, // Acceptable.
3380  CW_Good = 1, // Good weight.
3381  CW_Better = 2, // Better weight.
3382  CW_Best = 3, // Best weight.
3383 
3384  // Well-known weights.
3385  CW_SpecificReg = CW_Okay, // Specific register operands.
3386  CW_Register = CW_Good, // Register operands.
3387  CW_Memory = CW_Better, // Memory operands.
3388  CW_Constant = CW_Best, // Constant operand.
3389  CW_Default = CW_Okay // Default or don't know type.
3390  };
3391 
3392  /// This contains information for each constraint that we are lowering.
3394  /// This contains the actual string for the code, like "m". TargetLowering
3395  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3396  /// matches the operand.
3397  std::string ConstraintCode;
3398 
3399  /// Information about the constraint code, e.g. Register, RegisterClass,
3400  /// Memory, Other, Unknown.
3402 
3403  /// If this is the result output operand or a clobber, this is null,
3404  /// otherwise it is the incoming operand to the CallInst. This gets
3405  /// modified as the asm is processed.
3406  Value *CallOperandVal = nullptr;
3407 
3408  /// The ValueType for the operand value.
3409  MVT ConstraintVT = MVT::Other;
3410 
3411  /// Copy constructor for copying from a ConstraintInfo.
3413  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3414 
3415  /// Return true of this is an input operand that is a matching constraint
3416  /// like "4".
3417  bool isMatchingInputConstraint() const;
3418 
3419  /// If this is an input matching constraint, this method returns the output
3420  /// operand it matches.
3421  unsigned getMatchedOperand() const;
3422  };
3423 
3424  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3425 
3426  /// Split up the constraint string from the inline assembly value into the
3427  /// specific constraints and their prefixes, and also tie in the associated
3428  /// operand values. If this returns an empty vector, and if the constraint
3429  /// string itself isn't empty, there was an error parsing.
3430  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3431  const TargetRegisterInfo *TRI,
3432  ImmutableCallSite CS) const;
3433 
3434  /// Examine constraint type and operand type and determine a weight value.
3435  /// The operand object must already have been set up with the operand type.
3436  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3437  AsmOperandInfo &info, int maIndex) const;
3438 
3439  /// Examine constraint string and operand type and determine a weight value.
3440  /// The operand object must already have been set up with the operand type.
3441  virtual ConstraintWeight getSingleConstraintMatchWeight(
3442  AsmOperandInfo &info, const char *constraint) const;
3443 
3444  /// Determines the constraint code and constraint type to use for the specific
3445  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3446  /// If the actual operand being passed in is available, it can be passed in as
3447  /// Op, otherwise an empty SDValue can be passed.
3448  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3449  SDValue Op,
3450  SelectionDAG *DAG = nullptr) const;
3451 
3452  /// Given a constraint, return the type of constraint it is for this target.
3453  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3454 
3455  /// Given a physical register constraint (e.g. {edx}), return the register
3456  /// number and the register class for the register.
3457  ///
3458  /// Given a register class constraint, like 'r', if this corresponds directly
3459  /// to an LLVM register class, return a register of 0 and the register class
3460  /// pointer.
3461  ///
3462  /// This should only be used for C_Register constraints. On error, this
3463  /// returns a register number of 0 and a null register class pointer.
3464  virtual std::pair<unsigned, const TargetRegisterClass *>
3465  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3466  StringRef Constraint, MVT VT) const;
3467 
3468  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3469  if (ConstraintCode == "i")
3470  return InlineAsm::Constraint_i;
3471  else if (ConstraintCode == "m")
3472  return InlineAsm::Constraint_m;
3474  }
3475 
3476  /// Try to replace an X constraint, which matches anything, with another that
3477  /// has more specific requirements based on the type of the corresponding
3478  /// operand. This returns null if there is no replacement to make.
3479  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3480 
3481  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3482  /// add anything to Ops.
3483  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3484  std::vector<SDValue> &Ops,
3485  SelectionDAG &DAG) const;
3486 
3487  //===--------------------------------------------------------------------===//
3488  // Div utility functions
3489  //
3490  SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3491  bool IsAfterLegalization,
3492  std::vector<SDNode *> *Created) const;
3493  SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3494  bool IsAfterLegalization,
3495  std::vector<SDNode *> *Created) const;
3496 
3497  /// Targets may override this function to provide custom SDIV lowering for
3498  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3499  /// assumes SDIV is expensive and replaces it with a series of other integer
3500  /// operations.
3501  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3502  SelectionDAG &DAG,
3503  std::vector<SDNode *> *Created) const;
3504 
3505  /// Indicate whether this target prefers to combine FDIVs with the same
3506  /// divisor. If the transform should never be done, return zero. If the
3507  /// transform should be done, return the minimum number of divisor uses
3508  /// that must exist.
3509  virtual unsigned combineRepeatedFPDivisors() const {
3510  return 0;
3511  }
3512 
3513  /// Hooks for building estimates in place of slower divisions and square
3514  /// roots.
3515 
3516  /// Return either a square root or its reciprocal estimate value for the input
3517  /// operand.
3518  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3519  /// 'Enabled' as set by a potential default override attribute.
3520  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3521  /// refinement iterations required to generate a sufficient (though not
3522  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3523  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3524  /// algorithm implementation that uses either one or two constants.
3525  /// The boolean Reciprocal is used to select whether the estimate is for the
3526  /// square root of the input operand or the reciprocal of its square root.
3527  /// A target may choose to implement its own refinement within this function.
3528  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3529  /// any further refinement of the estimate.
3530  /// An empty SDValue return means no estimate sequence can be created.
3532  int Enabled, int &RefinementSteps,
3533  bool &UseOneConstNR, bool Reciprocal) const {
3534  return SDValue();
3535  }
3536 
3537  /// Return a reciprocal estimate value for the input operand.
3538  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3539  /// 'Enabled' as set by a potential default override attribute.
3540  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3541  /// refinement iterations required to generate a sufficient (though not
3542  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3543  /// A target may choose to implement its own refinement within this function.
3544  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3545  /// any further refinement of the estimate.
3546  /// An empty SDValue return means no estimate sequence can be created.
3548  int Enabled, int &RefinementSteps) const {
3549  return SDValue();
3550  }
3551 
3552  //===--------------------------------------------------------------------===//
3553  // Legalization utility functions
3554  //
3555 
3556  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3557  /// respectively, each computing an n/2-bit part of the result.
3558  /// \param Result A vector that will be filled with the parts of the result
3559  /// in little-endian order.
3560  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3561  /// if you want to control how low bits are extracted from the LHS.
3562  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3563  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3564  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3565  /// \returns true if the node has been expanded, false if it has not
3566  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3567  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3569  SDValue LL = SDValue(), SDValue LH = SDValue(),
3570  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3571 
3572  /// Expand a MUL into two nodes. One that computes the high bits of
3573  /// the result and one that computes the low bits.
3574  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3575  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3576  /// if you want to control how low bits are extracted from the LHS.
3577  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3578  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3579  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3580  /// \returns true if the node has been expanded. false if it has not
3581  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3582  SelectionDAG &DAG, MulExpansionKind Kind,
3583  SDValue LL = SDValue(), SDValue LH = SDValue(),
3584  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3585 
3586  /// Expand float(f32) to SINT(i64) conversion
3587  /// \param N Node to expand
3588  /// \param Result output after conversion
3589  /// \returns True, if the expansion was successful, false otherwise
3590  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3591 
3592  /// Turn load of vector type into a load of the individual elements.
3593  /// \param LD load to expand
3594  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3595  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3596 
3597  // Turn a store of a vector type into stores of the individual elements.
3598  /// \param ST Store with a vector value type
3599  /// \returns MERGE_VALUs of the individual store chains.
3600  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3601 
3602  /// Expands an unaligned load to 2 half-size loads for an integer, and
3603  /// possibly more for vectors.
3604  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3605  SelectionDAG &DAG) const;
3606 
3607  /// Expands an unaligned store to 2 half-size stores for integer values, and
3608  /// possibly more for vectors.
3609  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3610 
3611  /// Increments memory address \p Addr according to the type of the value
3612  /// \p DataVT that should be stored. If the data is stored in compressed
3613  /// form, the memory address should be incremented according to the number of
3614  /// the stored elements. This number is equal to the number of '1's bits
3615  /// in the \p Mask.
3616  /// \p DataVT is a vector type. \p Mask is a vector value.
3617  /// \p DataVT and \p Mask have the same number of vector elements.
3618  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3619  EVT DataVT, SelectionDAG &DAG,
3620  bool IsCompressedMemory) const;
3621 
3622  /// Get a pointer to vector element \p Idx located in memory for a vector of
3623  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3624  /// bounds the returned pointer is unspecified, but will be within the vector
3625  /// bounds.
3626  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3627  SDValue Index) const;
3628 
3629  //===--------------------------------------------------------------------===//
3630  // Instruction Emitting Hooks
3631  //
3632 
3633  /// This method should be implemented by targets that mark instructions with
3634  /// the 'usesCustomInserter' flag. These instructions are special in various
3635  /// ways, which require special support to insert. The specified MachineInstr
3636  /// is created but not inserted into any basic blocks, and this method is
3637  /// called to expand it into a sequence of instructions, potentially also
3638  /// creating new basic blocks and control flow.
3639  /// As long as the returned basic block is different (i.e., we created a new
3640  /// one), the custom inserter is free to modify the rest of \p MBB.
3641  virtual MachineBasicBlock *
3642  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3643 
3644  /// This method should be implemented by targets that mark instructions with
3645  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3646  /// instruction selection by target hooks. e.g. To fill in optional defs for
3647  /// ARM 's' setting instructions.
3648  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3649  SDNode *Node) const;
3650 
3651  /// If this function returns true, SelectionDAGBuilder emits a
3652  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3653  virtual bool useLoadStackGuardNode() const {
3654  return false;
3655  }
3656 
3658  const SDLoc &DL) const {
3659  llvm_unreachable("not implemented for this target");
3660  }
3661 
3662  /// Lower TLS global address SDNode for target independent emulated TLS model.
3663  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3664  SelectionDAG &DAG) const;
3665 
3666  /// Expands target specific indirect branch for the case of JumpTable
3667  /// expanasion.
3669  SelectionDAG &DAG) const {
3670  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3671  }
3672 
3673  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3674  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3675  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3676  // combiner can fold the new nodes.
3677  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3678 
3679 private:
3680  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3681  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3682  const SDLoc &DL) const;
3683 
3684  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3685  SDValue N1, ISD::CondCode Cond,
3686  DAGCombinerInfo &DCI,
3687  const SDLoc &DL) const;
3688 };
3689 
3690 /// Given an LLVM IR type and return type attributes, compute the return value
3691 /// EVTs and flags, and optionally also the offsets, if the return value is
3692 /// being lowered to memory.
3695  const TargetLowering &TLI, const DataLayout &DL);
3696 
3697 } // end namespace llvm
3698 
3699 #endif // LLVM_CODEGEN_TARGETLOWERING_H
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
static MVT getIntegerVT(unsigned BitWidth)
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, DivergenceAnalysis *DA) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:829
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:250
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:563
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:365
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:273
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:241
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:312
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static ISD::NodeType getExtendForContent(BooleanContent Content)
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:266
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
An instruction for reading from memory.
Definition: Instructions.h:168
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:360
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
void * PointerTy
Definition: GenericValue.h:22
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:497
Definition: BitVector.h:921
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:731
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:63
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:310
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:911
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:170
Class to represent pointers.
Definition: DerivedTypes.h:467
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:42
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:886
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:16
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:584
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:471
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:90
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:401
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:893
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1032
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
virtual bool shouldConsiderGEPOffsetSplit() const
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
static bool Enabled
Definition: Statistic.cpp:51
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Class to represent vector types.
Definition: DerivedTypes.h:393
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:69
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform&#39;s va_list object.
virtual bool preferShiftsToClearExtremeBits(SDValue X) const
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
LegalizeTypeAction getTypeAction(MVT VT) const
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:438
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:186
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:441
ValueTypeActionImpl ValueTypeActions
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
virtual bool needsFixedCatchObjects() const
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:566
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
Flags
Flags values. These may be or&#39;d together.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool useSoftFloat() const
CallLoweringInfo & setTailCall(bool Value=true)
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:599
Representation of each machine instruction.
Definition: MachineInstr.h:60
Basic Alias true
CallLoweringInfo & setConvergent(bool Value=true)
SmallVector< SDValue, 32 > OutVals
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, EVT VT) const
Certain targets require unusual breakdowns of certain types.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1353
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
const ValueTypeActionImpl & getValueTypeActions() const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
void setTypeAction(MVT VT, LegalizeTypeAction Action)
bool isPositionIndependent() const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const
Insert explicit copies in entry and exit blocks.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:575
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
Establish a view to a call site for examination.
Definition: CallSite.h:714
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that&#39;s to be used to test the result of the comparison libcall against zero...
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:874
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:309
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
const unsigned Kind
Multiway switch.
LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void GetReturnInfo(Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
unsigned getMinFunctionAlignment() const
Return the minimum function alignment.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual unsigned getMemcmpEqZeroLoadsPerBlock() const
For memcmp expansion when the memcmp result is only compared equal or not-equal to 0...
CallLoweringInfo & setInRegister(bool Value=true)