LLVM  7.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file describes how to lower LLVM code to machine code. This has two
12 /// main components:
13 ///
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
17 ///
18 /// In addition it has a few other components, like information about FP
19 /// immediates.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
25 
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/CallSite.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/IRBuilder.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h"
50 #include "llvm/IR/Type.h"
51 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class IntrinsicInst;
77 struct KnownBits;
78 class LLVMContext;
79 class MachineBasicBlock;
80 class MachineFunction;
81 class MachineInstr;
82 class MachineJumpTableInfo;
83 class MachineLoop;
84 class MachineRegisterInfo;
85 class MCContext;
86 class MCExpr;
87 class Module;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
91 class Value;
92 
93 namespace Sched {
94 
95  enum Preference {
96  None, // No preference
97  Source, // Follow source order.
98  RegPressure, // Scheduling for lowest register pressure.
99  Hybrid, // Scheduling for both latency and register pressure.
100  ILP, // Scheduling for ILP in low register pressure mode.
101  VLIW // Scheduling for VLIW targets.
102  };
103 
104 } // end namespace Sched
105 
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
109 public:
110  /// This enum indicates whether operations are valid for a target, and if not,
111  /// what action should be used to make them valid.
112  enum LegalizeAction : uint8_t {
113  Legal, // The target natively supports this operation.
114  Promote, // This operation should be executed in a larger type.
115  Expand, // Try to expand this to other ops, otherwise use a libcall.
116  LibCall, // Don't try to expand this to other ops, always use a libcall.
117  Custom // Use the LowerOperation hook to implement custom lowering.
118  };
119 
120  /// This enum indicates whether a types are legal for a target, and if not,
121  /// what action should be used to make them valid.
122  enum LegalizeTypeAction : uint8_t {
123  TypeLegal, // The target natively supports this type.
124  TypePromoteInteger, // Replace this integer with a larger one.
125  TypeExpandInteger, // Split this integer into two of half the size.
126  TypeSoftenFloat, // Convert this float to a same size integer type,
127  // if an operation is not supported in target HW.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
178  SDValue Node = SDValue();
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
198  };
199  using ArgListTy = std::vector<ArgListEntry>;
200 
201  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202  ArgListTy &Args) const {};
203 
205  switch (Content) {
206  case UndefinedBooleanContent:
207  // Extend by adding rubbish bits.
208  return ISD::ANY_EXTEND;
209  case ZeroOrOneBooleanContent:
210  // Extend by adding zero bits.
211  return ISD::ZERO_EXTEND;
212  case ZeroOrNegativeOneBooleanContent:
213  // Extend by copying the sign bit.
214  return ISD::SIGN_EXTEND;
215  }
216  llvm_unreachable("Invalid content kind");
217  }
218 
219  /// NOTE: The TargetMachine owns TLOF.
220  explicit TargetLoweringBase(const TargetMachine &TM);
221  TargetLoweringBase(const TargetLoweringBase &) = delete;
222  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223  virtual ~TargetLoweringBase() = default;
224 
225 protected:
226  /// \brief Initialize all of the actions to default values.
227  void initActions();
228 
229 public:
230  const TargetMachine &getTargetMachine() const { return TM; }
231 
232  virtual bool useSoftFloat() const { return false; }
233 
234  /// Return the pointer type for the given address space, defaults to
235  /// the pointer type from the data layout.
236  /// FIXME: The default needs to be removed once all the code is updated.
237  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239  }
240 
241  /// Return the type for frame index, which is determined by
242  /// the alloca address space specified through the data layout.
243  MVT getFrameIndexTy(const DataLayout &DL) const {
244  return getPointerTy(DL, DL.getAllocaAddrSpace());
245  }
246 
247  /// Return the type for operands of fence.
248  /// TODO: Let fence operands be of i32 type and remove this.
249  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250  return getPointerTy(DL);
251  }
252 
253  /// EVT is not used in-tree, but is used by out-of-tree target.
254  /// A documentation for this function would be nice...
255  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
256 
257  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258  bool LegalTypes = true) const;
259 
260  /// Returns the type to be used for the index operand of:
261  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264  return getPointerTy(DL);
265  }
266 
267  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
268  return true;
269  }
270 
271  /// Return true if multiple condition registers are available.
273  return HasMultipleConditionRegisters;
274  }
275 
276  /// Return true if the target has BitExtract instructions.
277  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
278 
279  /// Return the preferred vector type legalization action.
282  // The default action for one element vectors is to scalarize
283  if (VT.getVectorNumElements() == 1)
284  return TypeScalarizeVector;
285  // The default action for other vectors is to promote
286  return TypePromoteInteger;
287  }
288 
289  // There are two general methods for expanding a BUILD_VECTOR node:
290  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
291  // them together.
292  // 2. Build the vector on the stack and then load it.
293  // If this function returns true, then method (1) will be used, subject to
294  // the constraint that all of the necessary shuffles are legal (as determined
295  // by isShuffleMaskLegal). If this function returns false, then method (2) is
296  // always used. The vector type, and the number of defined values, are
297  // provided.
298  virtual bool
300  unsigned DefinedValues) const {
301  return DefinedValues < 3;
302  }
303 
304  /// Return true if integer divide is usually cheaper than a sequence of
305  /// several shifts, adds, and multiplies for this target.
306  /// The definition of "cheaper" may depend on whether we're optimizing
307  /// for speed or for size.
308  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
309 
310  /// Return true if the target can handle a standalone remainder operation.
311  virtual bool hasStandaloneRem(EVT VT) const {
312  return true;
313  }
314 
315  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
316  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
317  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
318  return false;
319  }
320 
321  /// Reciprocal estimate status values used by the functions below.
322  enum ReciprocalEstimate : int {
323  Unspecified = -1,
324  Disabled = 0,
326  };
327 
328  /// Return a ReciprocalEstimate enum value for a square root of the given type
329  /// based on the function's attributes. If the operation is not overridden by
330  /// the function's attributes, "Unspecified" is returned and target defaults
331  /// are expected to be used for instruction selection.
332  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
333 
334  /// Return a ReciprocalEstimate enum value for a division of the given type
335  /// based on the function's attributes. If the operation is not overridden by
336  /// the function's attributes, "Unspecified" is returned and target defaults
337  /// are expected to be used for instruction selection.
338  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
339 
340  /// Return the refinement step count for a square root of the given type based
341  /// on the function's attributes. If the operation is not overridden by
342  /// the function's attributes, "Unspecified" is returned and target defaults
343  /// are expected to be used for instruction selection.
344  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
345 
346  /// Return the refinement step count for a division of the given type based
347  /// on the function's attributes. If the operation is not overridden by
348  /// the function's attributes, "Unspecified" is returned and target defaults
349  /// are expected to be used for instruction selection.
350  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
351 
352  /// Returns true if target has indicated at least one type should be bypassed.
353  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
354 
355  /// Returns map of slow types for division or remainder with corresponding
356  /// fast types
358  return BypassSlowDivWidths;
359  }
360 
361  /// Return true if Flow Control is an expensive operation that should be
362  /// avoided.
363  bool isJumpExpensive() const { return JumpIsExpensive; }
364 
365  /// Return true if selects are only cheaper than branches if the branch is
366  /// unlikely to be predicted right.
368  return PredictableSelectIsExpensive;
369  }
370 
371  /// If a branch or a select condition is skewed in one direction by more than
372  /// this factor, it is very likely to be predicted correctly.
373  virtual BranchProbability getPredictableBranchThreshold() const;
374 
375  /// Return true if the following transform is beneficial:
376  /// fold (conv (load x)) -> (load (conv*)x)
377  /// On architectures that don't natively support some vector loads
378  /// efficiently, casting the load to a smaller vector of larger types and
379  /// loading is more efficient, however, this can be undone by optimizations in
380  /// dag combiner.
381  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
382  EVT BitcastVT) const {
383  // Don't do if we could do an indexed load on the original type, but not on
384  // the new one.
385  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
386  return true;
387 
388  MVT LoadMVT = LoadVT.getSimpleVT();
389 
390  // Don't bother doing this if it's just going to be promoted again later, as
391  // doing so might interfere with other combines.
392  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
393  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
394  return false;
395 
396  return true;
397  }
398 
399  /// Return true if the following transform is beneficial:
400  /// (store (y (conv x)), y*)) -> (store x, (x*))
401  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
402  // Default to the same logic as loads.
403  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
404  }
405 
406  /// Return true if it is expected to be cheaper to do a store of a non-zero
407  /// vector constant with the given size and type for the address space than to
408  /// store the individual scalar element constants.
409  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
410  unsigned NumElem,
411  unsigned AddrSpace) const {
412  return false;
413  }
414 
415  /// Allow store merging after legalization in addition to before legalization.
416  /// This may catch stores that do not exist earlier (eg, stores created from
417  /// intrinsics).
418  virtual bool mergeStoresAfterLegalization() const { return true; }
419 
420  /// Returns if it's reasonable to merge stores to MemVT size.
421  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
422  const SelectionDAG &DAG) const {
423  return true;
424  }
425 
426  /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
427  virtual bool isCheapToSpeculateCttz() const {
428  return false;
429  }
430 
431  /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
432  virtual bool isCheapToSpeculateCtlz() const {
433  return false;
434  }
435 
436  /// \brief Return true if ctlz instruction is fast.
437  virtual bool isCtlzFast() const {
438  return false;
439  }
440 
441  /// Return true if it is safe to transform an integer-domain bitwise operation
442  /// into the equivalent floating-point operation. This should be set to true
443  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
444  /// type.
445  virtual bool hasBitPreservingFPLogic(EVT VT) const {
446  return false;
447  }
448 
449  /// \brief Return true if it is cheaper to split the store of a merged int val
450  /// from a pair of smaller values into multiple stores.
451  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
452  return false;
453  }
454 
455  /// \brief Return if the target supports combining a
456  /// chain like:
457  /// \code
458  /// %andResult = and %val1, #mask
459  /// %icmpResult = icmp %andResult, 0
460  /// \endcode
461  /// into a single machine instruction of a form like:
462  /// \code
463  /// cc = test %register, #mask
464  /// \endcode
465  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
466  return false;
467  }
468 
469  /// Use bitwise logic to make pairs of compares more efficient. For example:
470  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
471  /// This should be true when it takes more than one instruction to lower
472  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
473  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
474  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
475  return false;
476  }
477 
478  /// Return the preferred operand type if the target has a quick way to compare
479  /// integer values of the given size. Assume that any legal integer type can
480  /// be compared efficiently. Targets may override this to allow illegal wide
481  /// types to return a vector type if there is support to compare that type.
482  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
483  MVT VT = MVT::getIntegerVT(NumBits);
484  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
485  }
486 
487  /// Return true if the target should transform:
488  /// (X & Y) == Y ---> (~X & Y) == 0
489  /// (X & Y) != Y ---> (~X & Y) != 0
490  ///
491  /// This may be profitable if the target has a bitwise and-not operation that
492  /// sets comparison flags. A target may want to limit the transformation based
493  /// on the type of Y or if Y is a constant.
494  ///
495  /// Note that the transform will not occur if Y is known to be a power-of-2
496  /// because a mask and compare of a single bit can be handled by inverting the
497  /// predicate, for example:
498  /// (X & 8) == 8 ---> (X & 8) != 0
499  virtual bool hasAndNotCompare(SDValue Y) const {
500  return false;
501  }
502 
503  /// Return true if the target has a bitwise and-not operation:
504  /// X = ~A & B
505  /// This can be used to simplify select or other instructions.
506  virtual bool hasAndNot(SDValue X) const {
507  // If the target has the more complex version of this operation, assume that
508  // it has this operation too.
509  return hasAndNotCompare(X);
510  }
511 
512  /// \brief Return true if the target wants to use the optimization that
513  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
514  /// promotedInst1(...(promotedInstN(ext(load)))).
515  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
516 
517  /// Return true if the target can combine store(extractelement VectorTy,
518  /// Idx).
519  /// \p Cost[out] gives the cost of that transformation when this is true.
520  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
521  unsigned &Cost) const {
522  return false;
523  }
524 
525  /// Return true if target supports floating point exceptions.
527  return HasFloatingPointExceptions;
528  }
529 
530  /// Return true if target always beneficiates from combining into FMA for a
531  /// given value type. This must typically return false on targets where FMA
532  /// takes more cycles to execute than FADD.
533  virtual bool enableAggressiveFMAFusion(EVT VT) const {
534  return false;
535  }
536 
537  /// Return the ValueType of the result of SETCC operations.
538  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
539  EVT VT) const;
540 
541  /// Return the ValueType for comparison libcalls. Comparions libcalls include
542  /// floating point comparion calls, and Ordered/Unordered check calls on
543  /// floating point numbers.
544  virtual
545  MVT::SimpleValueType getCmpLibcallReturnType() const;
546 
547  /// For targets without i1 registers, this gives the nature of the high-bits
548  /// of boolean values held in types wider than i1.
549  ///
550  /// "Boolean values" are special true/false values produced by nodes like
551  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
552  /// Not to be confused with general values promoted from i1. Some cpus
553  /// distinguish between vectors of boolean and scalars; the isVec parameter
554  /// selects between the two kinds. For example on X86 a scalar boolean should
555  /// be zero extended from i1, while the elements of a vector of booleans
556  /// should be sign extended from i1.
557  ///
558  /// Some cpus also treat floating point types the same way as they treat
559  /// vectors instead of the way they treat scalars.
560  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
561  if (isVec)
562  return BooleanVectorContents;
563  return isFloat ? BooleanFloatContents : BooleanContents;
564  }
565 
567  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
568  }
569 
570  /// Return target scheduling preference.
572  return SchedPreferenceInfo;
573  }
574 
575  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
576  /// for different nodes. This function returns the preference (or none) for
577  /// the given node.
579  return Sched::None;
580  }
581 
582  /// Return the register class that should be used for the specified value
583  /// type.
584  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
585  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
586  assert(RC && "This value type is not natively supported!");
587  return RC;
588  }
589 
590  /// Return the 'representative' register class for the specified value
591  /// type.
592  ///
593  /// The 'representative' register class is the largest legal super-reg
594  /// register class for the register class of the value type. For example, on
595  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
596  /// register class is GR64 on x86_64.
597  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
598  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
599  return RC;
600  }
601 
602  /// Return the cost of the 'representative' register class for the specified
603  /// value type.
604  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
605  return RepRegClassCostForVT[VT.SimpleTy];
606  }
607 
608  /// Return true if the target has native support for the specified value type.
609  /// This means that it has a register that directly holds it without
610  /// promotions or expansions.
611  bool isTypeLegal(EVT VT) const {
612  assert(!VT.isSimple() ||
613  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
614  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
615  }
616 
618  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
619  /// that indicates how instruction selection should deal with the type.
620  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
621 
622  public:
624  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
625  TypeLegal);
626  }
627 
629  return ValueTypeActions[VT.SimpleTy];
630  }
631 
633  ValueTypeActions[VT.SimpleTy] = Action;
634  }
635  };
636 
638  return ValueTypeActions;
639  }
640 
641  /// Return how we should legalize values of this type, either it is already
642  /// legal (return 'Legal') or we need to promote it to a larger type (return
643  /// 'Promote'), or we need to expand it into multiple registers of smaller
644  /// integer type (return 'Expand'). 'Custom' is not an option.
646  return getTypeConversion(Context, VT).first;
647  }
649  return ValueTypeActions.getTypeAction(VT);
650  }
651 
652  /// For types supported by the target, this is an identity function. For
653  /// types that must be promoted to larger types, this returns the larger type
654  /// to promote to. For integer types that are larger than the largest integer
655  /// register, this contains one step in the expansion to get to the smaller
656  /// register. For illegal floating point types, this returns the integer type
657  /// to transform to.
658  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
659  return getTypeConversion(Context, VT).second;
660  }
661 
662  /// For types supported by the target, this is an identity function. For
663  /// types that must be expanded (i.e. integer types that are larger than the
664  /// largest integer register or illegal floating point types), this returns
665  /// the largest legal type it will be expanded to.
666  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
667  assert(!VT.isVector());
668  while (true) {
669  switch (getTypeAction(Context, VT)) {
670  case TypeLegal:
671  return VT;
672  case TypeExpandInteger:
673  VT = getTypeToTransformTo(Context, VT);
674  break;
675  default:
676  llvm_unreachable("Type is not legal nor is it to be expanded!");
677  }
678  }
679  }
680 
681  /// Vector types are broken down into some number of legal first class types.
682  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
683  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
684  /// turns into 4 EVT::i32 values with both PPC and X86.
685  ///
686  /// This method returns the number of registers needed, and the VT for each
687  /// register. It also returns the VT and quantity of the intermediate values
688  /// before they are promoted/expanded.
689  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
690  EVT &IntermediateVT,
691  unsigned &NumIntermediates,
692  MVT &RegisterVT) const;
693 
694  /// Certain targets such as MIPS require that some types such as vectors are
695  /// always broken down into scalars in some contexts. This occurs even if the
696  /// vector type is legal.
698  LLVMContext &Context, EVT VT, EVT &IntermediateVT,
699  unsigned &NumIntermediates, MVT &RegisterVT) const {
700  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
701  RegisterVT);
702  }
703 
704  struct IntrinsicInfo {
705  unsigned opc = 0; // target opcode
706  EVT memVT; // memory VT
707 
708  // value representing memory location
710 
711  int offset = 0; // offset off of ptrVal
712  unsigned size = 0; // the size of the memory location
713  // (taken from memVT if zero)
714  unsigned align = 1; // alignment
715 
717  IntrinsicInfo() = default;
718  };
719 
720  /// Given an intrinsic, checks if on the target the intrinsic will need to map
721  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
722  /// true and store the intrinsic information into the IntrinsicInfo that was
723  /// passed to the function.
724  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
725  MachineFunction &,
726  unsigned /*Intrinsic*/) const {
727  return false;
728  }
729 
730  /// Returns true if the target can instruction select the specified FP
731  /// immediate natively. If false, the legalizer will materialize the FP
732  /// immediate as a load from a constant pool.
733  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
734  return false;
735  }
736 
737  /// Targets can use this to indicate that they only support *some*
738  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
739  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
740  /// legal.
741  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
742  return true;
743  }
744 
745  /// Returns true if the operation can trap for the value type.
746  ///
747  /// VT must be a legal type. By default, we optimistically assume most
748  /// operations don't trap except for integer divide and remainder.
749  virtual bool canOpTrap(unsigned Op, EVT VT) const;
750 
751  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
752  /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
753  /// a VAND with a constant pool entry.
754  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
755  EVT /*VT*/) const {
756  return false;
757  }
758 
759  /// Return how this operation should be treated: either it is legal, needs to
760  /// be promoted to a larger size, needs to be expanded to some other code
761  /// sequence, or the target has a custom expander for it.
762  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
763  if (VT.isExtended()) return Expand;
764  // If a target-specific SDNode requires legalization, require the target
765  // to provide custom legalization for it.
766  if (Op >= array_lengthof(OpActions[0])) return Custom;
767  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
768  }
769 
770  /// Return true if the specified operation is legal on this target or can be
771  /// made legal with custom lowering. This is used to help guide high-level
772  /// lowering decisions.
773  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
774  return (VT == MVT::Other || isTypeLegal(VT)) &&
775  (getOperationAction(Op, VT) == Legal ||
776  getOperationAction(Op, VT) == Custom);
777  }
778 
779  /// Return true if the specified operation is legal on this target or can be
780  /// made legal using promotion. This is used to help guide high-level lowering
781  /// decisions.
782  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
783  return (VT == MVT::Other || isTypeLegal(VT)) &&
784  (getOperationAction(Op, VT) == Legal ||
785  getOperationAction(Op, VT) == Promote);
786  }
787 
788  /// Return true if the specified operation is legal on this target or can be
789  /// made legal with custom lowering or using promotion. This is used to help
790  /// guide high-level lowering decisions.
791  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
792  return (VT == MVT::Other || isTypeLegal(VT)) &&
793  (getOperationAction(Op, VT) == Legal ||
794  getOperationAction(Op, VT) == Custom ||
795  getOperationAction(Op, VT) == Promote);
796  }
797 
798  /// Return true if the operation uses custom lowering, regardless of whether
799  /// the type is legal or not.
800  bool isOperationCustom(unsigned Op, EVT VT) const {
801  return getOperationAction(Op, VT) == Custom;
802  }
803 
804  /// Return true if lowering to a jump table is allowed.
805  virtual bool areJTsAllowed(const Function *Fn) const {
806  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
807  return false;
808 
809  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
810  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
811  }
812 
813  /// Check whether the range [Low,High] fits in a machine word.
814  bool rangeFitsInWord(const APInt &Low, const APInt &High,
815  const DataLayout &DL) const {
816  // FIXME: Using the pointer type doesn't seem ideal.
817  uint64_t BW = DL.getIndexSizeInBits(0u);
818  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
819  return Range <= BW;
820  }
821 
822  /// Return true if lowering to a jump table is suitable for a set of case
823  /// clusters which may contain \p NumCases cases, \p Range range of values.
824  /// FIXME: This function check the maximum table size and density, but the
825  /// minimum size is not checked. It would be nice if the minimum size is
826  /// also combined within this function. Currently, the minimum size check is
827  /// performed in findJumpTable() in SelectionDAGBuiler and
828  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
829  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
830  uint64_t Range) const {
831  const bool OptForSize = SI->getParent()->getParent()->optForSize();
832  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
833  const unsigned MaxJumpTableSize =
834  OptForSize || getMaximumJumpTableSize() == 0
835  ? UINT_MAX
836  : getMaximumJumpTableSize();
837  // Check whether a range of clusters is dense enough for a jump table.
838  if (Range <= MaxJumpTableSize &&
839  (NumCases * 100 >= Range * MinDensity)) {
840  return true;
841  }
842  return false;
843  }
844 
845  /// Return true if lowering to a bit test is suitable for a set of case
846  /// clusters which contains \p NumDests unique destinations, \p Low and
847  /// \p High as its lowest and highest case values, and expects \p NumCmps
848  /// case value comparisons. Check if the number of destinations, comparison
849  /// metric, and range are all suitable.
850  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
851  const APInt &Low, const APInt &High,
852  const DataLayout &DL) const {
853  // FIXME: I don't think NumCmps is the correct metric: a single case and a
854  // range of cases both require only one branch to lower. Just looking at the
855  // number of clusters and destinations should be enough to decide whether to
856  // build bit tests.
857 
858  // To lower a range with bit tests, the range must fit the bitwidth of a
859  // machine word.
860  if (!rangeFitsInWord(Low, High, DL))
861  return false;
862 
863  // Decide whether it's profitable to lower this range with bit tests. Each
864  // destination requires a bit test and branch, and there is an overall range
865  // check branch. For a small number of clusters, separate comparisons might
866  // be cheaper, and for many destinations, splitting the range might be
867  // better.
868  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
869  (NumDests == 3 && NumCmps >= 6);
870  }
871 
872  /// Return true if the specified operation is illegal on this target or
873  /// unlikely to be made legal with custom lowering. This is used to help guide
874  /// high-level lowering decisions.
875  bool isOperationExpand(unsigned Op, EVT VT) const {
876  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
877  }
878 
879  /// Return true if the specified operation is legal on this target.
880  bool isOperationLegal(unsigned Op, EVT VT) const {
881  return (VT == MVT::Other || isTypeLegal(VT)) &&
882  getOperationAction(Op, VT) == Legal;
883  }
884 
885  /// Return how this load with extension should be treated: either it is legal,
886  /// needs to be promoted to a larger size, needs to be expanded to some other
887  /// code sequence, or the target has a custom expander for it.
888  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
889  EVT MemVT) const {
890  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
891  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
892  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
893  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
894  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
895  unsigned Shift = 4 * ExtType;
896  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
897  }
898 
899  /// Return true if the specified load with extension is legal on this target.
900  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
901  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
902  }
903 
904  /// Return true if the specified load with extension is legal or custom
905  /// on this target.
906  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
907  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
908  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
909  }
910 
911  /// Return how this store with truncation should be treated: either it is
912  /// legal, needs to be promoted to a larger size, needs to be expanded to some
913  /// other code sequence, or the target has a custom expander for it.
915  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
916  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
917  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
919  "Table isn't big enough!");
920  return TruncStoreActions[ValI][MemI];
921  }
922 
923  /// Return true if the specified store with truncation is legal on this
924  /// target.
925  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
926  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
927  }
928 
929  /// Return true if the specified store with truncation has solution on this
930  /// target.
931  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
932  return isTypeLegal(ValVT) &&
933  (getTruncStoreAction(ValVT, MemVT) == Legal ||
934  getTruncStoreAction(ValVT, MemVT) == Custom);
935  }
936 
937  /// Return how the indexed load should be treated: either it is legal, needs
938  /// to be promoted to a larger size, needs to be expanded to some other code
939  /// sequence, or the target has a custom expander for it.
941  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
942  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
943  "Table isn't big enough!");
944  unsigned Ty = (unsigned)VT.SimpleTy;
945  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
946  }
947 
948  /// Return true if the specified indexed load is legal on this target.
949  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
950  return VT.isSimple() &&
951  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
952  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
953  }
954 
955  /// Return how the indexed store should be treated: either it is legal, needs
956  /// to be promoted to a larger size, needs to be expanded to some other code
957  /// sequence, or the target has a custom expander for it.
959  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
960  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
961  "Table isn't big enough!");
962  unsigned Ty = (unsigned)VT.SimpleTy;
963  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
964  }
965 
966  /// Return true if the specified indexed load is legal on this target.
967  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
968  return VT.isSimple() &&
969  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
970  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
971  }
972 
973  /// Return how the condition code should be treated: either it is legal, needs
974  /// to be expanded to some other code sequence, or the target has a custom
975  /// expander for it.
978  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
979  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
980  "Table isn't big enough!");
981  // See setCondCodeAction for how this is encoded.
982  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
983  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
984  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
985  assert(Action != Promote && "Can't promote condition code!");
986  return Action;
987  }
988 
989  /// Return true if the specified condition code is legal on this target.
990  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
991  return getCondCodeAction(CC, VT) == Legal;
992  }
993 
994  /// Return true if the specified condition code is legal or custom on this
995  /// target.
997  return getCondCodeAction(CC, VT) == Legal ||
998  getCondCodeAction(CC, VT) == Custom;
999  }
1000 
1001  /// If the action for this operation is to promote, this method returns the
1002  /// ValueType to promote to.
1003  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1004  assert(getOperationAction(Op, VT) == Promote &&
1005  "This operation isn't promoted!");
1006 
1007  // See if this has an explicit type specified.
1008  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1009  MVT::SimpleValueType>::const_iterator PTTI =
1010  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1011  if (PTTI != PromoteToType.end()) return PTTI->second;
1012 
1013  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1014  "Cannot autopromote this type, add it with AddPromotedToType.");
1015 
1016  MVT NVT = VT;
1017  do {
1018  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1019  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1020  "Didn't find type to promote to!");
1021  } while (!isTypeLegal(NVT) ||
1022  getOperationAction(Op, NVT) == Promote);
1023  return NVT;
1024  }
1025 
1026  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1027  /// operations except for the pointer size. If AllowUnknown is true, this
1028  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1029  /// otherwise it will assert.
1031  bool AllowUnknown = false) const {
1032  // Lower scalar pointers to native pointer types.
1033  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1034  return getPointerTy(DL, PTy->getAddressSpace());
1035 
1036  if (Ty->isVectorTy()) {
1037  VectorType *VTy = cast<VectorType>(Ty);
1038  Type *Elm = VTy->getElementType();
1039  // Lower vectors of pointers to native pointer types.
1040  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1041  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1042  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1043  }
1044 
1045  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1046  VTy->getNumElements());
1047  }
1048  return EVT::getEVT(Ty, AllowUnknown);
1049  }
1050 
1051  /// Return the MVT corresponding to this LLVM type. See getValueType.
1053  bool AllowUnknown = false) const {
1054  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1055  }
1056 
1057  /// Return the desired alignment for ByVal or InAlloca aggregate function
1058  /// arguments in the caller parameter area. This is the actual alignment, not
1059  /// its logarithm.
1060  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1061 
1062  /// Return the type of registers that this ValueType will eventually require.
1064  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1065  return RegisterTypeForVT[VT.SimpleTy];
1066  }
1067 
1068  /// Return the type of registers that this ValueType will eventually require.
1069  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1070  if (VT.isSimple()) {
1071  assert((unsigned)VT.getSimpleVT().SimpleTy <
1072  array_lengthof(RegisterTypeForVT));
1073  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1074  }
1075  if (VT.isVector()) {
1076  EVT VT1;
1077  MVT RegisterVT;
1078  unsigned NumIntermediates;
1079  (void)getVectorTypeBreakdown(Context, VT, VT1,
1080  NumIntermediates, RegisterVT);
1081  return RegisterVT;
1082  }
1083  if (VT.isInteger()) {
1084  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1085  }
1086  llvm_unreachable("Unsupported extended type!");
1087  }
1088 
1089  /// Return the number of registers that this ValueType will eventually
1090  /// require.
1091  ///
1092  /// This is one for any types promoted to live in larger registers, but may be
1093  /// more than one for types (like i64) that are split into pieces. For types
1094  /// like i140, which are first promoted then expanded, it is the number of
1095  /// registers needed to hold all the bits of the original type. For an i140
1096  /// on a 32 bit machine this means 5 registers.
1097  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1098  if (VT.isSimple()) {
1099  assert((unsigned)VT.getSimpleVT().SimpleTy <
1100  array_lengthof(NumRegistersForVT));
1101  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1102  }
1103  if (VT.isVector()) {
1104  EVT VT1;
1105  MVT VT2;
1106  unsigned NumIntermediates;
1107  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1108  }
1109  if (VT.isInteger()) {
1110  unsigned BitWidth = VT.getSizeInBits();
1111  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1112  return (BitWidth + RegWidth - 1) / RegWidth;
1113  }
1114  llvm_unreachable("Unsupported extended type!");
1115  }
1116 
1117  /// Certain combinations of ABIs, Targets and features require that types
1118  /// are legal for some operations and not for other operations.
1119  /// For MIPS all vector types must be passed through the integer register set.
1121  return getRegisterType(VT);
1122  }
1123 
1125  EVT VT) const {
1126  return getRegisterType(Context, VT);
1127  }
1128 
1129  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1130  /// this occurs when a vector type is used, as vector are passed through the
1131  /// integer register set.
1132  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1133  EVT VT) const {
1134  return getNumRegisters(Context, VT);
1135  }
1136 
1137  /// Certain targets have context senstive alignment requirements, where one
1138  /// type has the alignment requirement of another type.
1139  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1140  DataLayout DL) const {
1141  return DL.getABITypeAlignment(ArgTy);
1142  }
1143 
1144  /// If true, then instruction selection should seek to shrink the FP constant
1145  /// of the specified type to a smaller type in order to save space and / or
1146  /// reduce runtime.
1147  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1148 
1149  // Return true if it is profitable to reduce the given load node to a smaller
1150  // type.
1151  //
1152  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1154  ISD::LoadExtType ExtTy,
1155  EVT NewVT) const {
1156  return true;
1157  }
1158 
1159  /// When splitting a value of the specified type into parts, does the Lo
1160  /// or Hi part come first? This usually follows the endianness, except
1161  /// for ppcf128, where the Hi part always comes first.
1162  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1163  return DL.isBigEndian() || VT == MVT::ppcf128;
1164  }
1165 
1166  /// If true, the target has custom DAG combine transformations that it can
1167  /// perform for the specified node.
1169  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1170  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1171  }
1172 
1173  unsigned getGatherAllAliasesMaxDepth() const {
1174  return GatherAllAliasesMaxDepth;
1175  }
1176 
1177  /// Returns the size of the platform's va_list object.
1178  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1179  return getPointerTy(DL).getSizeInBits();
1180  }
1181 
1182  /// \brief Get maximum # of store operations permitted for llvm.memset
1183  ///
1184  /// This function returns the maximum number of store operations permitted
1185  /// to replace a call to llvm.memset. The value is set by the target at the
1186  /// performance threshold for such a replacement. If OptSize is true,
1187  /// return the limit for functions that have OptSize attribute.
1188  unsigned getMaxStoresPerMemset(bool OptSize) const {
1189  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1190  }
1191 
1192  /// \brief Get maximum # of store operations permitted for llvm.memcpy
1193  ///
1194  /// This function returns the maximum number of store operations permitted
1195  /// to replace a call to llvm.memcpy. The value is set by the target at the
1196  /// performance threshold for such a replacement. If OptSize is true,
1197  /// return the limit for functions that have OptSize attribute.
1198  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1199  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1200  }
1201 
1202  /// Get maximum # of load operations permitted for memcmp
1203  ///
1204  /// This function returns the maximum number of load operations permitted
1205  /// to replace a call to memcmp. The value is set by the target at the
1206  /// performance threshold for such a replacement. If OptSize is true,
1207  /// return the limit for functions that have OptSize attribute.
1208  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1209  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1210  }
1211 
1212  /// For memcmp expansion when the memcmp result is only compared equal or
1213  /// not-equal to 0, allow up to this number of load pairs per block. As an
1214  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1215  /// a0 = load2bytes &a[0]
1216  /// b0 = load2bytes &b[0]
1217  /// a2 = load1byte &a[2]
1218  /// b2 = load1byte &b[2]
1219  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1220  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1221  return 1;
1222  }
1223 
1224  /// \brief Get maximum # of store operations permitted for llvm.memmove
1225  ///
1226  /// This function returns the maximum number of store operations permitted
1227  /// to replace a call to llvm.memmove. The value is set by the target at the
1228  /// performance threshold for such a replacement. If OptSize is true,
1229  /// return the limit for functions that have OptSize attribute.
1230  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1231  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1232  }
1233 
1234  /// \brief Determine if the target supports unaligned memory accesses.
1235  ///
1236  /// This function returns true if the target allows unaligned memory accesses
1237  /// of the specified type in the given address space. If true, it also returns
1238  /// whether the unaligned memory access is "fast" in the last argument by
1239  /// reference. This is used, for example, in situations where an array
1240  /// copy/move/set is converted to a sequence of store operations. Its use
1241  /// helps to ensure that such replacements don't generate code that causes an
1242  /// alignment error (trap) on the target machine.
1244  unsigned AddrSpace = 0,
1245  unsigned Align = 1,
1246  bool * /*Fast*/ = nullptr) const {
1247  return false;
1248  }
1249 
1250  /// Return true if the target supports a memory access of this type for the
1251  /// given address space and alignment. If the access is allowed, the optional
1252  /// final parameter returns if the access is also fast (as defined by the
1253  /// target).
1254  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1255  unsigned AddrSpace = 0, unsigned Alignment = 1,
1256  bool *Fast = nullptr) const;
1257 
1258  /// Returns the target specific optimal type for load and store operations as
1259  /// a result of memset, memcpy, and memmove lowering.
1260  ///
1261  /// If DstAlign is zero that means it's safe to destination alignment can
1262  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1263  /// a need to check it against alignment requirement, probably because the
1264  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1265  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1266  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1267  /// does not need to be loaded. It returns EVT::Other if the type should be
1268  /// determined using generic target-independent logic.
1269  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1270  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1271  bool /*IsMemset*/,
1272  bool /*ZeroMemset*/,
1273  bool /*MemcpyStrSrc*/,
1274  MachineFunction &/*MF*/) const {
1275  return MVT::Other;
1276  }
1277 
1278  /// Returns true if it's safe to use load / store of the specified type to
1279  /// expand memcpy / memset inline.
1280  ///
1281  /// This is mostly true for all types except for some special cases. For
1282  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1283  /// fstpl which also does type conversion. Note the specified type doesn't
1284  /// have to be legal as the hook is used before type legalization.
1285  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1286 
1287  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1288  bool usesUnderscoreSetJmp() const {
1289  return UseUnderscoreSetJmp;
1290  }
1291 
1292  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1293  bool usesUnderscoreLongJmp() const {
1294  return UseUnderscoreLongJmp;
1295  }
1296 
1297  /// Return lower limit for number of blocks in a jump table.
1298  virtual unsigned getMinimumJumpTableEntries() const;
1299 
1300  /// Return lower limit of the density in a jump table.
1301  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1302 
1303  /// Return upper limit for number of entries in a jump table.
1304  /// Zero if no limit.
1305  unsigned getMaximumJumpTableSize() const;
1306 
1307  virtual bool isJumpTableRelative() const {
1308  return TM.isPositionIndependent();
1309  }
1310 
1311  /// If a physical register, this specifies the register that
1312  /// llvm.savestack/llvm.restorestack should save and restore.
1314  return StackPointerRegisterToSaveRestore;
1315  }
1316 
1317  /// If a physical register, this returns the register that receives the
1318  /// exception address on entry to an EH pad.
1319  virtual unsigned
1320  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1321  // 0 is guaranteed to be the NoRegister value on all targets
1322  return 0;
1323  }
1324 
1325  /// If a physical register, this returns the register that receives the
1326  /// exception typeid on entry to a landing pad.
1327  virtual unsigned
1328  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1329  // 0 is guaranteed to be the NoRegister value on all targets
1330  return 0;
1331  }
1332 
1333  virtual bool needsFixedCatchObjects() const {
1334  report_fatal_error("Funclet EH is not implemented for this target");
1335  }
1336 
1337  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1338  /// 200)
1339  unsigned getJumpBufSize() const {
1340  return JumpBufSize;
1341  }
1342 
1343  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1344  /// is 0)
1345  unsigned getJumpBufAlignment() const {
1346  return JumpBufAlignment;
1347  }
1348 
1349  /// Return the minimum stack alignment of an argument.
1350  unsigned getMinStackArgumentAlignment() const {
1351  return MinStackArgumentAlignment;
1352  }
1353 
1354  /// Return the minimum function alignment.
1355  unsigned getMinFunctionAlignment() const {
1356  return MinFunctionAlignment;
1357  }
1358 
1359  /// Return the preferred function alignment.
1360  unsigned getPrefFunctionAlignment() const {
1361  return PrefFunctionAlignment;
1362  }
1363 
1364  /// Return the preferred loop alignment.
1365  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1366  return PrefLoopAlignment;
1367  }
1368 
1369  /// If the target has a standard location for the stack protector guard,
1370  /// returns the address of that location. Otherwise, returns nullptr.
1371  /// DEPRECATED: please override useLoadStackGuardNode and customize
1372  /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1373  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1374 
1375  /// Inserts necessary declarations for SSP (stack protection) purpose.
1376  /// Should be used only when getIRStackGuard returns nullptr.
1377  virtual void insertSSPDeclarations(Module &M) const;
1378 
1379  /// Return the variable that's previously inserted by insertSSPDeclarations,
1380  /// if any, otherwise return nullptr. Should be used only when
1381  /// getIRStackGuard returns nullptr.
1382  virtual Value *getSDagStackGuard(const Module &M) const;
1383 
1384  /// If this function returns true, stack protection checks should XOR the
1385  /// frame pointer (or whichever pointer is used to address locals) into the
1386  /// stack guard value before checking it. getIRStackGuard must return nullptr
1387  /// if this returns true.
1388  virtual bool useStackGuardXorFP() const { return false; }
1389 
1390  /// If the target has a standard stack protection check function that
1391  /// performs validation and error handling, returns the function. Otherwise,
1392  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1393  /// Should be used only when getIRStackGuard returns nullptr.
1394  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1395 
1396 protected:
1397  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1398  bool UseTLS) const;
1399 
1400 public:
1401  /// Returns the target-specific address of the unsafe stack pointer.
1402  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1403 
1404  /// Returns the name of the symbol used to emit stack probes or the empty
1405  /// string if not applicable.
1407  return "";
1408  }
1409 
1410  /// Returns true if a cast between SrcAS and DestAS is a noop.
1411  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1412  return false;
1413  }
1414 
1415  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1416  /// are happy to sink it into basic blocks.
1417  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1418  return isNoopAddrSpaceCast(SrcAS, DestAS);
1419  }
1420 
1421  /// Return true if the pointer arguments to CI should be aligned by aligning
1422  /// the object whose address is being passed. If so then MinSize is set to the
1423  /// minimum size the object must be to be aligned and PrefAlign is set to the
1424  /// preferred alignment.
1425  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1426  unsigned & /*PrefAlign*/) const {
1427  return false;
1428  }
1429 
1430  //===--------------------------------------------------------------------===//
1431  /// \name Helpers for TargetTransformInfo implementations
1432  /// @{
1433 
1434  /// Get the ISD node that corresponds to the Instruction class opcode.
1435  int InstructionOpcodeToISD(unsigned Opcode) const;
1436 
1437  /// Estimate the cost of type-legalization and the legalized type.
1438  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1439  Type *Ty) const;
1440 
1441  /// @}
1442 
1443  //===--------------------------------------------------------------------===//
1444  /// \name Helpers for atomic expansion.
1445  /// @{
1446 
1447  /// Returns the maximum atomic operation size (in bits) supported by
1448  /// the backend. Atomic operations greater than this size (as well
1449  /// as ones that are not naturally aligned), will be expanded by
1450  /// AtomicExpandPass into an __atomic_* library call.
1452  return MaxAtomicSizeInBitsSupported;
1453  }
1454 
1455  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1456  /// the backend supports. Any smaller operations are widened in
1457  /// AtomicExpandPass.
1458  ///
1459  /// Note that *unlike* operations above the maximum size, atomic ops
1460  /// are still natively supported below the minimum; they just
1461  /// require a more complex expansion.
1462  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1463 
1464  /// Whether the target supports unaligned atomic operations.
1465  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1466 
1467  /// Whether AtomicExpandPass should automatically insert fences and reduce
1468  /// ordering for this atomic. This should be true for most architectures with
1469  /// weak memory ordering. Defaults to false.
1470  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1471  return false;
1472  }
1473 
1474  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1475  /// corresponding pointee type. This may entail some non-trivial operations to
1476  /// truncate or reconstruct types that will be illegal in the backend. See
1477  /// ARMISelLowering for an example implementation.
1478  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1479  AtomicOrdering Ord) const {
1480  llvm_unreachable("Load linked unimplemented on this target");
1481  }
1482 
1483  /// Perform a store-conditional operation to Addr. Return the status of the
1484  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1485  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1486  Value *Addr, AtomicOrdering Ord) const {
1487  llvm_unreachable("Store conditional unimplemented on this target");
1488  }
1489 
1490  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1491  /// It is called by AtomicExpandPass before expanding an
1492  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1493  /// if shouldInsertFencesForAtomic returns true.
1494  ///
1495  /// Inst is the original atomic instruction, prior to other expansions that
1496  /// may be performed.
1497  ///
1498  /// This function should either return a nullptr, or a pointer to an IR-level
1499  /// Instruction*. Even complex fence sequences can be represented by a
1500  /// single Instruction* through an intrinsic to be lowered later.
1501  /// Backends should override this method to produce target-specific intrinsic
1502  /// for their fences.
1503  /// FIXME: Please note that the default implementation here in terms of
1504  /// IR-level fences exists for historical/compatibility reasons and is
1505  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1506  /// consistency. For example, consider the following example:
1507  /// atomic<int> x = y = 0;
1508  /// int r1, r2, r3, r4;
1509  /// Thread 0:
1510  /// x.store(1);
1511  /// Thread 1:
1512  /// y.store(1);
1513  /// Thread 2:
1514  /// r1 = x.load();
1515  /// r2 = y.load();
1516  /// Thread 3:
1517  /// r3 = y.load();
1518  /// r4 = x.load();
1519  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1520  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1521  /// IR-level fences can prevent it.
1522  /// @{
1524  AtomicOrdering Ord) const {
1525  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1526  return Builder.CreateFence(Ord);
1527  else
1528  return nullptr;
1529  }
1530 
1532  Instruction *Inst,
1533  AtomicOrdering Ord) const {
1534  if (isAcquireOrStronger(Ord))
1535  return Builder.CreateFence(Ord);
1536  else
1537  return nullptr;
1538  }
1539  /// @}
1540 
1541  // Emits code that executes when the comparison result in the ll/sc
1542  // expansion of a cmpxchg instruction is such that the store-conditional will
1543  // not execute. This makes it possible to balance out the load-linked with
1544  // a dedicated instruction, if desired.
1545  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1546  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1547  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1548 
1549  /// Returns true if the given (atomic) store should be expanded by the
1550  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1552  return false;
1553  }
1554 
1555  /// Returns true if arguments should be sign-extended in lib calls.
1556  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1557  return IsSigned;
1558  }
1559 
1560  /// Returns how the given (atomic) load should be expanded by the
1561  /// IR-level AtomicExpand pass.
1564  }
1565 
1566  /// Returns true if the given atomic cmpxchg should be expanded by the
1567  /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1568  /// (through emitLoadLinked() and emitStoreConditional()).
1570  return false;
1571  }
1572 
1573  /// Returns how the IR-level AtomicExpand pass should expand the given
1574  /// AtomicRMW, if at all. Default is to never expand.
1577  }
1578 
1579  /// On some platforms, an AtomicRMW that never actually modifies the value
1580  /// (such as fetch_add of 0) can be turned into a fence followed by an
1581  /// atomic load. This may sound useless, but it makes it possible for the
1582  /// processor to keep the cacheline shared, dramatically improving
1583  /// performance. And such idempotent RMWs are useful for implementing some
1584  /// kinds of locks, see for example (justification + benchmarks):
1585  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1586  /// This method tries doing that transformation, returning the atomic load if
1587  /// it succeeds, and nullptr otherwise.
1588  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1589  /// another round of expansion.
1590  virtual LoadInst *
1592  return nullptr;
1593  }
1594 
1595  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1596  /// SIGN_EXTEND, or ANY_EXTEND).
1598  return ISD::ZERO_EXTEND;
1599  }
1600 
1601  /// @}
1602 
1603  /// Returns true if we should normalize
1604  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1605  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1606  /// that it saves us from materializing N0 and N1 in an integer register.
1607  /// Targets that are able to perform and/or on flags should return false here.
1609  EVT VT) const {
1610  // If a target has multiple condition registers, then it likely has logical
1611  // operations on those registers.
1612  if (hasMultipleConditionRegisters())
1613  return false;
1614  // Only do the transform if the value won't be split into multiple
1615  // registers.
1616  LegalizeTypeAction Action = getTypeAction(Context, VT);
1617  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1618  Action != TypeSplitVector;
1619  }
1620 
1621  /// Return true if a select of constants (select Cond, C1, C2) should be
1622  /// transformed into simple math ops with the condition value. For example:
1623  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1624  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1625  return false;
1626  }
1627 
1628  //===--------------------------------------------------------------------===//
1629  // TargetLowering Configuration Methods - These methods should be invoked by
1630  // the derived class constructor to configure this object for the target.
1631  //
1632 protected:
1633  /// Specify how the target extends the result of integer and floating point
1634  /// boolean values from i1 to a wider type. See getBooleanContents.
1636  BooleanContents = Ty;
1637  BooleanFloatContents = Ty;
1638  }
1639 
1640  /// Specify how the target extends the result of integer and floating point
1641  /// boolean values from i1 to a wider type. See getBooleanContents.
1643  BooleanContents = IntTy;
1644  BooleanFloatContents = FloatTy;
1645  }
1646 
1647  /// Specify how the target extends the result of a vector boolean value from a
1648  /// vector of i1 to a wider type. See getBooleanContents.
1650  BooleanVectorContents = Ty;
1651  }
1652 
1653  /// Specify the target scheduling preference.
1655  SchedPreferenceInfo = Pref;
1656  }
1657 
1658  /// Indicate whether this target prefers to use _setjmp to implement
1659  /// llvm.setjmp or the version without _. Defaults to false.
1660  void setUseUnderscoreSetJmp(bool Val) {
1661  UseUnderscoreSetJmp = Val;
1662  }
1663 
1664  /// Indicate whether this target prefers to use _longjmp to implement
1665  /// llvm.longjmp or the version without _. Defaults to false.
1666  void setUseUnderscoreLongJmp(bool Val) {
1667  UseUnderscoreLongJmp = Val;
1668  }
1669 
1670  /// Indicate the minimum number of blocks to generate jump tables.
1671  void setMinimumJumpTableEntries(unsigned Val);
1672 
1673  /// Indicate the maximum number of entries in jump tables.
1674  /// Set to zero to generate unlimited jump tables.
1675  void setMaximumJumpTableSize(unsigned);
1676 
1677  /// If set to a physical register, this specifies the register that
1678  /// llvm.savestack/llvm.restorestack should save and restore.
1680  StackPointerRegisterToSaveRestore = R;
1681  }
1682 
1683  /// Tells the code generator that the target has multiple (allocatable)
1684  /// condition registers that can be used to store the results of comparisons
1685  /// for use by selects and conditional branches. With multiple condition
1686  /// registers, the code generator will not aggressively sink comparisons into
1687  /// the blocks of their users.
1688  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1689  HasMultipleConditionRegisters = hasManyRegs;
1690  }
1691 
1692  /// Tells the code generator that the target has BitExtract instructions.
1693  /// The code generator will aggressively sink "shift"s into the blocks of
1694  /// their users if the users will generate "and" instructions which can be
1695  /// combined with "shift" to BitExtract instructions.
1696  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1697  HasExtractBitsInsn = hasExtractInsn;
1698  }
1699 
1700  /// Tells the code generator not to expand logic operations on comparison
1701  /// predicates into separate sequences that increase the amount of flow
1702  /// control.
1703  void setJumpIsExpensive(bool isExpensive = true);
1704 
1705  /// Tells the code generator that this target supports floating point
1706  /// exceptions and cares about preserving floating point exception behavior.
1707  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1708  HasFloatingPointExceptions = FPExceptions;
1709  }
1710 
1711  /// Tells the code generator which bitwidths to bypass.
1712  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1713  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1714  }
1715 
1716  /// Add the specified register class as an available regclass for the
1717  /// specified value type. This indicates the selector can handle values of
1718  /// that class natively.
1720  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1721  RegClassForVT[VT.SimpleTy] = RC;
1722  }
1723 
1724  /// Return the largest legal super-reg register class of the register class
1725  /// for the specified type and its associated "cost".
1726  virtual std::pair<const TargetRegisterClass *, uint8_t>
1727  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1728 
1729  /// Once all of the register classes are added, this allows us to compute
1730  /// derived properties we expose.
1731  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1732 
1733  /// Indicate that the specified operation does not work with the specified
1734  /// type and indicate what to do about it. Note that VT may refer to either
1735  /// the type of a result or that of an operand of Op.
1736  void setOperationAction(unsigned Op, MVT VT,
1737  LegalizeAction Action) {
1738  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1739  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1740  }
1741 
1742  /// Indicate that the specified load with extension does not work with the
1743  /// specified type and indicate what to do about it.
1744  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1745  LegalizeAction Action) {
1746  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1747  MemVT.isValid() && "Table isn't big enough!");
1748  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1749  unsigned Shift = 4 * ExtType;
1750  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1751  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1752  }
1753 
1754  /// Indicate that the specified truncating store does not work with the
1755  /// specified type and indicate what to do about it.
1756  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1757  LegalizeAction Action) {
1758  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1759  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1760  }
1761 
1762  /// Indicate that the specified indexed load does or does not work with the
1763  /// specified type and indicate what to do abort it.
1764  ///
1765  /// NOTE: All indexed mode loads are initialized to Expand in
1766  /// TargetLowering.cpp
1767  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1768  LegalizeAction Action) {
1769  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1770  (unsigned)Action < 0xf && "Table isn't big enough!");
1771  // Load action are kept in the upper half.
1772  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1773  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1774  }
1775 
1776  /// Indicate that the specified indexed store does or does not work with the
1777  /// specified type and indicate what to do about it.
1778  ///
1779  /// NOTE: All indexed mode stores are initialized to Expand in
1780  /// TargetLowering.cpp
1781  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1782  LegalizeAction Action) {
1783  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1784  (unsigned)Action < 0xf && "Table isn't big enough!");
1785  // Store action are kept in the lower half.
1786  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1787  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1788  }
1789 
1790  /// Indicate that the specified condition code is or isn't supported on the
1791  /// target and indicate what to do about it.
1793  LegalizeAction Action) {
1794  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1795  "Table isn't big enough!");
1796  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1797  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1798  /// value and the upper 29 bits index into the second dimension of the array
1799  /// to select what 32-bit value to use.
1800  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1801  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1802  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1803  }
1804 
1805  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1806  /// to trying a larger integer/fp until it can find one that works. If that
1807  /// default is insufficient, this method can be used by the target to override
1808  /// the default.
1809  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1810  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1811  }
1812 
1813  /// Convenience method to set an operation to Promote and specify the type
1814  /// in a single call.
1815  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1816  setOperationAction(Opc, OrigVT, Promote);
1817  AddPromotedToType(Opc, OrigVT, DestVT);
1818  }
1819 
1820  /// Targets should invoke this method for each target independent node that
1821  /// they want to provide a custom DAG combiner for by implementing the
1822  /// PerformDAGCombine virtual method.
1824  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1825  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1826  }
1827 
1828  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1829  void setJumpBufSize(unsigned Size) {
1830  JumpBufSize = Size;
1831  }
1832 
1833  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1834  /// 0
1835  void setJumpBufAlignment(unsigned Align) {
1836  JumpBufAlignment = Align;
1837  }
1838 
1839  /// Set the target's minimum function alignment (in log2(bytes))
1841  MinFunctionAlignment = Align;
1842  }
1843 
1844  /// Set the target's preferred function alignment. This should be set if
1845  /// there is a performance benefit to higher-than-minimum alignment (in
1846  /// log2(bytes))
1848  PrefFunctionAlignment = Align;
1849  }
1850 
1851  /// Set the target's preferred loop alignment. Default alignment is zero, it
1852  /// means the target does not care about loop alignment. The alignment is
1853  /// specified in log2(bytes). The target may also override
1854  /// getPrefLoopAlignment to provide per-loop values.
1855  void setPrefLoopAlignment(unsigned Align) {
1856  PrefLoopAlignment = Align;
1857  }
1858 
1859  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1861  MinStackArgumentAlignment = Align;
1862  }
1863 
1864  /// Set the maximum atomic operation size supported by the
1865  /// backend. Atomic operations greater than this size (as well as
1866  /// ones that are not naturally aligned), will be expanded by
1867  /// AtomicExpandPass into an __atomic_* library call.
1868  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1869  MaxAtomicSizeInBitsSupported = SizeInBits;
1870  }
1871 
1872  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1873  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1874  MinCmpXchgSizeInBits = SizeInBits;
1875  }
1876 
1877  /// Sets whether unaligned atomic operations are supported.
1878  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1879  SupportsUnalignedAtomics = UnalignedSupported;
1880  }
1881 
1882 public:
1883  //===--------------------------------------------------------------------===//
1884  // Addressing mode description hooks (used by LSR etc).
1885  //
1886 
1887  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1888  /// instructions reading the address. This allows as much computation as
1889  /// possible to be done in the address mode for that operand. This hook lets
1890  /// targets also pass back when this should be done on intrinsics which
1891  /// load/store.
1892  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1893  SmallVectorImpl<Value*> &/*Ops*/,
1894  Type *&/*AccessTy*/) const {
1895  return false;
1896  }
1897 
1898  /// This represents an addressing mode of:
1899  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1900  /// If BaseGV is null, there is no BaseGV.
1901  /// If BaseOffs is zero, there is no base offset.
1902  /// If HasBaseReg is false, there is no base register.
1903  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1904  /// no scale.
1905  struct AddrMode {
1906  GlobalValue *BaseGV = nullptr;
1907  int64_t BaseOffs = 0;
1908  bool HasBaseReg = false;
1909  int64_t Scale = 0;
1910  AddrMode() = default;
1911  };
1912 
1913  /// Return true if the addressing mode represented by AM is legal for this
1914  /// target, for a load/store of the specified type.
1915  ///
1916  /// The type may be VoidTy, in which case only return true if the addressing
1917  /// mode is legal for a load/store of any legal type. TODO: Handle
1918  /// pre/postinc as well.
1919  ///
1920  /// If the address space cannot be determined, it will be -1.
1921  ///
1922  /// TODO: Remove default argument
1923  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1924  Type *Ty, unsigned AddrSpace,
1925  Instruction *I = nullptr) const;
1926 
1927  /// \brief Return the cost of the scaling factor used in the addressing mode
1928  /// represented by AM for this target, for a load/store of the specified type.
1929  ///
1930  /// If the AM is supported, the return value must be >= 0.
1931  /// If the AM is not supported, it returns a negative value.
1932  /// TODO: Handle pre/postinc as well.
1933  /// TODO: Remove default argument
1934  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1935  Type *Ty, unsigned AS = 0) const {
1936  // Default: assume that any scaling factor used in a legal AM is free.
1937  if (isLegalAddressingMode(DL, AM, Ty, AS))
1938  return 0;
1939  return -1;
1940  }
1941 
1942  /// Return true if the specified immediate is legal icmp immediate, that is
1943  /// the target has icmp instructions which can compare a register against the
1944  /// immediate without having to materialize the immediate into a register.
1945  virtual bool isLegalICmpImmediate(int64_t) const {
1946  return true;
1947  }
1948 
1949  /// Return true if the specified immediate is legal add immediate, that is the
1950  /// target has add instructions which can add a register with the immediate
1951  /// without having to materialize the immediate into a register.
1952  virtual bool isLegalAddImmediate(int64_t) const {
1953  return true;
1954  }
1955 
1956  /// Return true if it's significantly cheaper to shift a vector by a uniform
1957  /// scalar than by an amount which will vary across each lane. On x86, for
1958  /// example, there is a "psllw" instruction for the former case, but no simple
1959  /// instruction for a general "a << b" operation on vectors.
1960  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1961  return false;
1962  }
1963 
1964  /// Returns true if the opcode is a commutative binary operation.
1965  virtual bool isCommutativeBinOp(unsigned Opcode) const {
1966  // FIXME: This should get its info from the td file.
1967  switch (Opcode) {
1968  case ISD::ADD:
1969  case ISD::SMIN:
1970  case ISD::SMAX:
1971  case ISD::UMIN:
1972  case ISD::UMAX:
1973  case ISD::MUL:
1974  case ISD::MULHU:
1975  case ISD::MULHS:
1976  case ISD::SMUL_LOHI:
1977  case ISD::UMUL_LOHI:
1978  case ISD::FADD:
1979  case ISD::FMUL:
1980  case ISD::AND:
1981  case ISD::OR:
1982  case ISD::XOR:
1983  case ISD::SADDO:
1984  case ISD::UADDO:
1985  case ISD::ADDC:
1986  case ISD::ADDE:
1987  case ISD::FMINNUM:
1988  case ISD::FMAXNUM:
1989  case ISD::FMINNAN:
1990  case ISD::FMAXNAN:
1991  return true;
1992  default: return false;
1993  }
1994  }
1995 
1996  /// Return true if it's free to truncate a value of type FromTy to type
1997  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1998  /// by referencing its sub-register AX.
1999  /// Targets must return false when FromTy <= ToTy.
2000  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2001  return false;
2002  }
2003 
2004  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2005  /// whether a call is in tail position. Typically this means that both results
2006  /// would be assigned to the same register or stack slot, but it could mean
2007  /// the target performs adequate checks of its own before proceeding with the
2008  /// tail call. Targets must return false when FromTy <= ToTy.
2009  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2010  return false;
2011  }
2012 
2013  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2014  return false;
2015  }
2016 
2017  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2018 
2019  /// Return true if the extension represented by \p I is free.
2020  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2021  /// this method can use the context provided by \p I to decide
2022  /// whether or not \p I is free.
2023  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2024  /// In other words, if is[Z|FP]Free returns true, then this method
2025  /// returns true as well. The converse is not true.
2026  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2027  /// \pre \p I must be a sign, zero, or fp extension.
2028  bool isExtFree(const Instruction *I) const {
2029  switch (I->getOpcode()) {
2030  case Instruction::FPExt:
2031  if (isFPExtFree(EVT::getEVT(I->getType()),
2032  EVT::getEVT(I->getOperand(0)->getType())))
2033  return true;
2034  break;
2035  case Instruction::ZExt:
2036  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2037  return true;
2038  break;
2039  case Instruction::SExt:
2040  break;
2041  default:
2042  llvm_unreachable("Instruction is not an extension");
2043  }
2044  return isExtFreeImpl(I);
2045  }
2046 
2047  /// Return true if \p Load and \p Ext can form an ExtLoad.
2048  /// For example, in AArch64
2049  /// %L = load i8, i8* %ptr
2050  /// %E = zext i8 %L to i32
2051  /// can be lowered into one load instruction
2052  /// ldrb w0, [x0]
2053  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2054  const DataLayout &DL) const {
2055  EVT VT = getValueType(DL, Ext->getType());
2056  EVT LoadVT = getValueType(DL, Load->getType());
2057 
2058  // If the load has other users and the truncate is not free, the ext
2059  // probably isn't free.
2060  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2061  !isTruncateFree(Ext->getType(), Load->getType()))
2062  return false;
2063 
2064  // Check whether the target supports casts folded into loads.
2065  unsigned LType;
2066  if (isa<ZExtInst>(Ext))
2067  LType = ISD::ZEXTLOAD;
2068  else {
2069  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2070  LType = ISD::SEXTLOAD;
2071  }
2072 
2073  return isLoadExtLegal(LType, VT, LoadVT);
2074  }
2075 
2076  /// Return true if any actual instruction that defines a value of type FromTy
2077  /// implicitly zero-extends the value to ToTy in the result register.
2078  ///
2079  /// The function should return true when it is likely that the truncate can
2080  /// be freely folded with an instruction defining a value of FromTy. If
2081  /// the defining instruction is unknown (because you're looking at a
2082  /// function argument, PHI, etc.) then the target may require an
2083  /// explicit truncate, which is not necessarily free, but this function
2084  /// does not deal with those cases.
2085  /// Targets must return false when FromTy >= ToTy.
2086  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2087  return false;
2088  }
2089 
2090  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2091  return false;
2092  }
2093 
2094  /// Return true if the target supplies and combines to a paired load
2095  /// two loaded values of type LoadedType next to each other in memory.
2096  /// RequiredAlignment gives the minimal alignment constraints that must be met
2097  /// to be able to select this paired load.
2098  ///
2099  /// This information is *not* used to generate actual paired loads, but it is
2100  /// used to generate a sequence of loads that is easier to combine into a
2101  /// paired load.
2102  /// For instance, something like this:
2103  /// a = load i64* addr
2104  /// b = trunc i64 a to i32
2105  /// c = lshr i64 a, 32
2106  /// d = trunc i64 c to i32
2107  /// will be optimized into:
2108  /// b = load i32* addr1
2109  /// d = load i32* addr2
2110  /// Where addr1 = addr2 +/- sizeof(i32).
2111  ///
2112  /// In other words, unless the target performs a post-isel load combining,
2113  /// this information should not be provided because it will generate more
2114  /// loads.
2115  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2116  unsigned & /*RequiredAlignment*/) const {
2117  return false;
2118  }
2119 
2120  /// Return true if the target has a vector blend instruction.
2121  virtual bool hasVectorBlend() const { return false; }
2122 
2123  /// \brief Get the maximum supported factor for interleaved memory accesses.
2124  /// Default to be the minimum interleave factor: 2.
2125  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2126 
2127  /// \brief Lower an interleaved load to target specific intrinsics. Return
2128  /// true on success.
2129  ///
2130  /// \p LI is the vector load instruction.
2131  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2132  /// \p Indices is the corresponding indices for each shufflevector.
2133  /// \p Factor is the interleave factor.
2134  virtual bool lowerInterleavedLoad(LoadInst *LI,
2136  ArrayRef<unsigned> Indices,
2137  unsigned Factor) const {
2138  return false;
2139  }
2140 
2141  /// \brief Lower an interleaved store to target specific intrinsics. Return
2142  /// true on success.
2143  ///
2144  /// \p SI is the vector store instruction.
2145  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2146  /// \p Factor is the interleave factor.
2148  unsigned Factor) const {
2149  return false;
2150  }
2151 
2152  /// Return true if zero-extending the specific node Val to type VT2 is free
2153  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2154  /// because it's folded such as X86 zero-extending loads).
2155  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2156  return isZExtFree(Val.getValueType(), VT2);
2157  }
2158 
2159  /// Return true if an fpext operation is free (for instance, because
2160  /// single-precision floating-point numbers are implicitly extended to
2161  /// double-precision).
2162  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2163  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2164  "invalid fpext types");
2165  return false;
2166  }
2167 
2168  /// Return true if an fpext operation input to an \p Opcode operation is free
2169  /// (for instance, because half-precision floating-point numbers are
2170  /// implicitly extended to float-precision) for an FMA instruction.
2171  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2172  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2173  "invalid fpext types");
2174  return isFPExtFree(DestVT, SrcVT);
2175  }
2176 
2177  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2178  /// extend node) is profitable.
2179  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2180 
2181  /// Return true if an fneg operation is free to the point where it is never
2182  /// worthwhile to replace it with a bitwise operation.
2183  virtual bool isFNegFree(EVT VT) const {
2184  assert(VT.isFloatingPoint());
2185  return false;
2186  }
2187 
2188  /// Return true if an fabs operation is free to the point where it is never
2189  /// worthwhile to replace it with a bitwise operation.
2190  virtual bool isFAbsFree(EVT VT) const {
2191  assert(VT.isFloatingPoint());
2192  return false;
2193  }
2194 
2195  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2196  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2197  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2198  ///
2199  /// NOTE: This may be called before legalization on types for which FMAs are
2200  /// not legal, but should return true if those types will eventually legalize
2201  /// to types that support FMAs. After legalization, it will only be called on
2202  /// types that support FMAs (via Legal or Custom actions)
2203  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2204  return false;
2205  }
2206 
2207  /// Return true if it's profitable to narrow operations of type VT1 to
2208  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2209  /// i32 to i16.
2210  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2211  return false;
2212  }
2213 
2214  /// \brief Return true if it is beneficial to convert a load of a constant to
2215  /// just the constant itself.
2216  /// On some targets it might be more efficient to use a combination of
2217  /// arithmetic instructions to materialize the constant instead of loading it
2218  /// from a constant pool.
2219  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2220  Type *Ty) const {
2221  return false;
2222  }
2223 
2224  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2225  /// from this source type with this index. This is needed because
2226  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2227  /// the first element, and only the target knows which lowering is cheap.
2228  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2229  unsigned Index) const {
2230  return false;
2231  }
2232 
2233  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2234  // even if the vector itself has multiple uses.
2235  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2236  return false;
2237  }
2238 
2239  //===--------------------------------------------------------------------===//
2240  // Runtime Library hooks
2241  //
2242 
2243  /// Rename the default libcall routine name for the specified libcall.
2244  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2245  LibcallRoutineNames[Call] = Name;
2246  }
2247 
2248  /// Get the libcall routine name for the specified libcall.
2249  const char *getLibcallName(RTLIB::Libcall Call) const {
2250  return LibcallRoutineNames[Call];
2251  }
2252 
2253  /// Override the default CondCode to be used to test the result of the
2254  /// comparison libcall against zero.
2256  CmpLibcallCCs[Call] = CC;
2257  }
2258 
2259  /// Get the CondCode that's to be used to test the result of the comparison
2260  /// libcall against zero.
2262  return CmpLibcallCCs[Call];
2263  }
2264 
2265  /// Set the CallingConv that should be used for the specified libcall.
2267  LibcallCallingConvs[Call] = CC;
2268  }
2269 
2270  /// Get the CallingConv that should be used for the specified libcall.
2272  return LibcallCallingConvs[Call];
2273  }
2274 
2275  /// Execute target specific actions to finalize target lowering.
2276  /// This is used to set extra flags in MachineFrameInformation and freezing
2277  /// the set of reserved registers.
2278  /// The default implementation just freezes the set of reserved registers.
2279  virtual void finalizeLowering(MachineFunction &MF) const;
2280 
2281 private:
2282  const TargetMachine &TM;
2283 
2284  /// Tells the code generator that the target has multiple (allocatable)
2285  /// condition registers that can be used to store the results of comparisons
2286  /// for use by selects and conditional branches. With multiple condition
2287  /// registers, the code generator will not aggressively sink comparisons into
2288  /// the blocks of their users.
2289  bool HasMultipleConditionRegisters;
2290 
2291  /// Tells the code generator that the target has BitExtract instructions.
2292  /// The code generator will aggressively sink "shift"s into the blocks of
2293  /// their users if the users will generate "and" instructions which can be
2294  /// combined with "shift" to BitExtract instructions.
2295  bool HasExtractBitsInsn;
2296 
2297  /// Tells the code generator to bypass slow divide or remainder
2298  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2299  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2300  /// div/rem when the operands are positive and less than 256.
2301  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2302 
2303  /// Tells the code generator that it shouldn't generate extra flow control
2304  /// instructions and should attempt to combine flow control instructions via
2305  /// predication.
2306  bool JumpIsExpensive;
2307 
2308  /// Whether the target supports or cares about preserving floating point
2309  /// exception behavior.
2310  bool HasFloatingPointExceptions;
2311 
2312  /// This target prefers to use _setjmp to implement llvm.setjmp.
2313  ///
2314  /// Defaults to false.
2315  bool UseUnderscoreSetJmp;
2316 
2317  /// This target prefers to use _longjmp to implement llvm.longjmp.
2318  ///
2319  /// Defaults to false.
2320  bool UseUnderscoreLongJmp;
2321 
2322  /// Information about the contents of the high-bits in boolean values held in
2323  /// a type wider than i1. See getBooleanContents.
2324  BooleanContent BooleanContents;
2325 
2326  /// Information about the contents of the high-bits in boolean values held in
2327  /// a type wider than i1. See getBooleanContents.
2328  BooleanContent BooleanFloatContents;
2329 
2330  /// Information about the contents of the high-bits in boolean vector values
2331  /// when the element type is wider than i1. See getBooleanContents.
2332  BooleanContent BooleanVectorContents;
2333 
2334  /// The target scheduling preference: shortest possible total cycles or lowest
2335  /// register usage.
2336  Sched::Preference SchedPreferenceInfo;
2337 
2338  /// The size, in bytes, of the target's jmp_buf buffers
2339  unsigned JumpBufSize;
2340 
2341  /// The alignment, in bytes, of the target's jmp_buf buffers
2342  unsigned JumpBufAlignment;
2343 
2344  /// The minimum alignment that any argument on the stack needs to have.
2345  unsigned MinStackArgumentAlignment;
2346 
2347  /// The minimum function alignment (used when optimizing for size, and to
2348  /// prevent explicitly provided alignment from leading to incorrect code).
2349  unsigned MinFunctionAlignment;
2350 
2351  /// The preferred function alignment (used when alignment unspecified and
2352  /// optimizing for speed).
2353  unsigned PrefFunctionAlignment;
2354 
2355  /// The preferred loop alignment.
2356  unsigned PrefLoopAlignment;
2357 
2358  /// Size in bits of the maximum atomics size the backend supports.
2359  /// Accesses larger than this will be expanded by AtomicExpandPass.
2360  unsigned MaxAtomicSizeInBitsSupported;
2361 
2362  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2363  /// backend supports.
2364  unsigned MinCmpXchgSizeInBits;
2365 
2366  /// This indicates if the target supports unaligned atomic operations.
2367  bool SupportsUnalignedAtomics;
2368 
2369  /// If set to a physical register, this specifies the register that
2370  /// llvm.savestack/llvm.restorestack should save and restore.
2371  unsigned StackPointerRegisterToSaveRestore;
2372 
2373  /// This indicates the default register class to use for each ValueType the
2374  /// target supports natively.
2375  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2376  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2377  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2378 
2379  /// This indicates the "representative" register class to use for each
2380  /// ValueType the target supports natively. This information is used by the
2381  /// scheduler to track register pressure. By default, the representative
2382  /// register class is the largest legal super-reg register class of the
2383  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2384  /// representative class would be GR32.
2385  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2386 
2387  /// This indicates the "cost" of the "representative" register class for each
2388  /// ValueType. The cost is used by the scheduler to approximate register
2389  /// pressure.
2390  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2391 
2392  /// For any value types we are promoting or expanding, this contains the value
2393  /// type that we are changing to. For Expanded types, this contains one step
2394  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2395  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2396  /// the same type (e.g. i32 -> i32).
2397  MVT TransformToType[MVT::LAST_VALUETYPE];
2398 
2399  /// For each operation and each value type, keep a LegalizeAction that
2400  /// indicates how instruction selection should deal with the operation. Most
2401  /// operations are Legal (aka, supported natively by the target), but
2402  /// operations that are not should be described. Note that operations on
2403  /// non-legal value types are not described here.
2405 
2406  /// For each load extension type and each value type, keep a LegalizeAction
2407  /// that indicates how instruction selection should deal with a load of a
2408  /// specific value type and extension type. Uses 4-bits to store the action
2409  /// for each of the 4 load ext types.
2410  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2411 
2412  /// For each value type pair keep a LegalizeAction that indicates whether a
2413  /// truncating store of a specific value type and truncating type is legal.
2415 
2416  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2417  /// that indicates how instruction selection should deal with the load /
2418  /// store.
2419  ///
2420  /// The first dimension is the value_type for the reference. The second
2421  /// dimension represents the various modes for load store.
2422  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2423 
2424  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2425  /// indicates how instruction selection should deal with the condition code.
2426  ///
2427  /// Because each CC action takes up 4 bits, we need to have the array size be
2428  /// large enough to fit all of the value types. This can be done by rounding
2429  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2430  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2431 
2432 protected:
2434 
2435 private:
2436  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2437 
2438  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2439  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2440  /// array.
2441  unsigned char
2442  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2443 
2444  /// For operations that must be promoted to a specific type, this holds the
2445  /// destination type. This map should be sparse, so don't hold it as an
2446  /// array.
2447  ///
2448  /// Targets add entries to this map with AddPromotedToType(..), clients access
2449  /// this with getTypeToPromoteTo(..).
2450  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2451  PromoteToType;
2452 
2453  /// Stores the name each libcall.
2454  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2455 
2456  /// The ISD::CondCode that should be used to test the result of each of the
2457  /// comparison libcall against zero.
2458  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2459 
2460  /// Stores the CallingConv that should be used for each libcall.
2461  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2462 
2463  /// Set default libcall names and calling conventions.
2464  void InitLibcalls(const Triple &TT);
2465 
2466 protected:
2467  /// Return true if the extension represented by \p I is free.
2468  /// \pre \p I is a sign, zero, or fp extension and
2469  /// is[Z|FP]ExtFree of the related types is not true.
2470  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2471 
2472  /// Depth that GatherAllAliases should should continue looking for chain
2473  /// dependencies when trying to find a more preferable chain. As an
2474  /// approximation, this should be more than the number of consecutive stores
2475  /// expected to be merged.
2477 
2478  /// \brief Specify maximum number of store instructions per memset call.
2479  ///
2480  /// When lowering \@llvm.memset this field specifies the maximum number of
2481  /// store operations that may be substituted for the call to memset. Targets
2482  /// must set this value based on the cost threshold for that target. Targets
2483  /// should assume that the memset will be done using as many of the largest
2484  /// store operations first, followed by smaller ones, if necessary, per
2485  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2486  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2487  /// store. This only applies to setting a constant array of a constant size.
2489 
2490  /// Maximum number of stores operations that may be substituted for the call
2491  /// to memset, used for functions with OptSize attribute.
2493 
2494  /// \brief Specify maximum bytes of store instructions per memcpy call.
2495  ///
2496  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2497  /// store operations that may be substituted for a call to memcpy. Targets
2498  /// must set this value based on the cost threshold for that target. Targets
2499  /// should assume that the memcpy will be done using as many of the largest
2500  /// store operations first, followed by smaller ones, if necessary, per
2501  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2502  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2503  /// and one 1-byte store. This only applies to copying a constant array of
2504  /// constant size.
2506 
2507  /// Maximum number of store operations that may be substituted for a call to
2508  /// memcpy, used for functions with OptSize attribute.
2512 
2513  /// \brief Specify maximum bytes of store instructions per memmove call.
2514  ///
2515  /// When lowering \@llvm.memmove this field specifies the maximum number of
2516  /// store instructions that may be substituted for a call to memmove. Targets
2517  /// must set this value based on the cost threshold for that target. Targets
2518  /// should assume that the memmove will be done using as many of the largest
2519  /// store operations first, followed by smaller ones, if necessary, per
2520  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2521  /// with 8-bit alignment would result in nine 1-byte stores. This only
2522  /// applies to copying a constant array of constant size.
2524 
2525  /// Maximum number of store instructions that may be substituted for a call to
2526  /// memmove, used for functions with OptSize attribute.
2528 
2529  /// Tells the code generator that select is more expensive than a branch if
2530  /// the branch is usually predicted right.
2532 
2533  /// \see enableExtLdPromotion.
2535 
2536  /// Return true if the value types that can be represented by the specified
2537  /// register class are all legal.
2538  bool isLegalRC(const TargetRegisterInfo &TRI,
2539  const TargetRegisterClass &RC) const;
2540 
2541  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2542  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2543  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2544  MachineBasicBlock *MBB) const;
2545 
2546  /// Replace/modify the XRay custom event operands with target-dependent
2547  /// details.
2548  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2549  MachineBasicBlock *MBB) const;
2550 
2551  /// Replace/modify the XRay typed event operands with target-dependent
2552  /// details.
2553  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2554  MachineBasicBlock *MBB) const;
2555 };
2556 
2557 /// This class defines information used to lower LLVM code to legal SelectionDAG
2558 /// operators that the target instruction selector can accept natively.
2559 ///
2560 /// This class also defines callbacks that targets must implement to lower
2561 /// target-specific constructs to SelectionDAG operators.
2563 public:
2564  struct DAGCombinerInfo;
2565 
2566  TargetLowering(const TargetLowering &) = delete;
2567  TargetLowering &operator=(const TargetLowering &) = delete;
2568 
2569  /// NOTE: The TargetMachine owns TLOF.
2570  explicit TargetLowering(const TargetMachine &TM);
2571 
2572  bool isPositionIndependent() const;
2573 
2574  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2575  FunctionLoweringInfo *FLI,
2576  DivergenceAnalysis *DA) const {
2577  return false;
2578  }
2579 
2580  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2581  return false;
2582  }
2583 
2584  /// Returns true by value, base pointer and offset pointer and addressing mode
2585  /// by reference if the node's address can be legally represented as
2586  /// pre-indexed load / store address.
2587  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2588  SDValue &/*Offset*/,
2589  ISD::MemIndexedMode &/*AM*/,
2590  SelectionDAG &/*DAG*/) const {
2591  return false;
2592  }
2593 
2594  /// Returns true by value, base pointer and offset pointer and addressing mode
2595  /// by reference if this node can be combined with a load / store to form a
2596  /// post-indexed load / store.
2597  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2598  SDValue &/*Base*/,
2599  SDValue &/*Offset*/,
2600  ISD::MemIndexedMode &/*AM*/,
2601  SelectionDAG &/*DAG*/) const {
2602  return false;
2603  }
2604 
2605  /// Return the entry encoding for a jump table in the current function. The
2606  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2607  virtual unsigned getJumpTableEncoding() const;
2608 
2609  virtual const MCExpr *
2611  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2612  MCContext &/*Ctx*/) const {
2613  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2614  }
2615 
2616  /// Returns relocation base for the given PIC jumptable.
2617  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2618  SelectionDAG &DAG) const;
2619 
2620  /// This returns the relocation base for the given PIC jumptable, the same as
2621  /// getPICJumpTableRelocBase, but as an MCExpr.
2622  virtual const MCExpr *
2623  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2624  unsigned JTI, MCContext &Ctx) const;
2625 
2626  /// Return true if folding a constant offset with the given GlobalAddress is
2627  /// legal. It is frequently not legal in PIC relocation models.
2628  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2629 
2630  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2631  SDValue &Chain) const;
2632 
2633  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2634  SDValue &NewRHS, ISD::CondCode &CCCode,
2635  const SDLoc &DL) const;
2636 
2637  /// Returns a pair of (return value, chain).
2638  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2639  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2640  EVT RetVT, ArrayRef<SDValue> Ops,
2641  bool isSigned, const SDLoc &dl,
2642  bool doesNotReturn = false,
2643  bool isReturnValueUsed = true) const;
2644 
2645  /// Check whether parameters to a call that are passed in callee saved
2646  /// registers are the same as from the calling function. This needs to be
2647  /// checked for tail call eligibility.
2648  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2649  const uint32_t *CallerPreservedMask,
2650  const SmallVectorImpl<CCValAssign> &ArgLocs,
2651  const SmallVectorImpl<SDValue> &OutVals) const;
2652 
2653  //===--------------------------------------------------------------------===//
2654  // TargetLowering Optimization Methods
2655  //
2656 
2657  /// A convenience struct that encapsulates a DAG, and two SDValues for
2658  /// returning information from TargetLowering to its clients that want to
2659  /// combine.
2662  bool LegalTys;
2663  bool LegalOps;
2666 
2668  bool LT, bool LO) :
2669  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2670 
2671  bool LegalTypes() const { return LegalTys; }
2672  bool LegalOperations() const { return LegalOps; }
2673 
2675  Old = O;
2676  New = N;
2677  return true;
2678  }
2679  };
2680 
2681  /// Check to see if the specified operand of the specified instruction is a
2682  /// constant integer. If so, check to see if there are any bits set in the
2683  /// constant that are not demanded. If so, shrink the constant and return
2684  /// true.
2685  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2686  TargetLoweringOpt &TLO) const;
2687 
2688  // Target hook to do target-specific const optimization, which is called by
2689  // ShrinkDemandedConstant. This function should return true if the target
2690  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2691  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2692  TargetLoweringOpt &TLO) const {
2693  return false;
2694  }
2695 
2696  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2697  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2698  /// generalized for targets with other types of implicit widening casts.
2699  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2700  TargetLoweringOpt &TLO) const;
2701 
2702  /// Helper for SimplifyDemandedBits that can simplify an operation with
2703  /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2704  /// then updates \p User with the simplified version. No other uses of
2705  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2706  /// function behaves exactly like function SimplifyDemandedBits declared
2707  /// below except that it also updates the DAG by calling
2708  /// DCI.CommitTargetLoweringOpt.
2709  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2710  DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2711 
2712  /// Look at Op. At this point, we know that only the DemandedMask bits of the
2713  /// result of Op are ever used downstream. If we can use this information to
2714  /// simplify Op, create a new simplified DAG node and return true, returning
2715  /// the original and new nodes in Old and New. Otherwise, analyze the
2716  /// expression and return a mask of KnownOne and KnownZero bits for the
2717  /// expression (used to simplify the caller). The KnownZero/One bits may only
2718  /// be accurate for those bits in the DemandedMask.
2719  /// \p AssumeSingleUse When this parameter is true, this function will
2720  /// attempt to simplify \p Op even if there are multiple uses.
2721  /// Callers are responsible for correctly updating the DAG based on the
2722  /// results of this function, because simply replacing replacing TLO.Old
2723  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2724  /// has multiple uses.
2725  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2726  KnownBits &Known,
2727  TargetLoweringOpt &TLO,
2728  unsigned Depth = 0,
2729  bool AssumeSingleUse = false) const;
2730 
2731  /// Helper wrapper around SimplifyDemandedBits
2732  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2733  DAGCombinerInfo &DCI) const;
2734 
2735  /// Look at Vector Op. At this point, we know that only the DemandedElts
2736  /// elements of the result of Op are ever used downstream. If we can use
2737  /// this information to simplify Op, create a new simplified DAG node and
2738  /// return true, storing the original and new nodes in TLO.
2739  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2740  /// KnownZero elements for the expression (used to simplify the caller).
2741  /// The KnownUndef/Zero elements may only be accurate for those bits
2742  /// in the DemandedMask.
2743  /// \p AssumeSingleUse When this parameter is true, this function will
2744  /// attempt to simplify \p Op even if there are multiple uses.
2745  /// Callers are responsible for correctly updating the DAG based on the
2746  /// results of this function, because simply replacing replacing TLO.Old
2747  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2748  /// has multiple uses.
2749  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2750  APInt &KnownUndef, APInt &KnownZero,
2751  TargetLoweringOpt &TLO, unsigned Depth = 0,
2752  bool AssumeSingleUse = false) const;
2753 
2754  /// Helper wrapper around SimplifyDemandedVectorElts
2755  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2756  APInt &KnownUndef, APInt &KnownZero,
2757  DAGCombinerInfo &DCI) const;
2758 
2759  /// Determine which of the bits specified in Mask are known to be either zero
2760  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2761  /// argument allows us to only collect the known bits that are shared by the
2762  /// requested vector elements.
2763  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2764  KnownBits &Known,
2765  const APInt &DemandedElts,
2766  const SelectionDAG &DAG,
2767  unsigned Depth = 0) const;
2768 
2769  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2770  /// Default implementation computes low bits based on alignment
2771  /// information. This should preserve known bits passed into it.
2772  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2773  KnownBits &Known,
2774  const APInt &DemandedElts,
2775  const SelectionDAG &DAG,
2776  unsigned Depth = 0) const;
2777 
2778  /// This method can be implemented by targets that want to expose additional
2779  /// information about sign bits to the DAG Combiner. The DemandedElts
2780  /// argument allows us to only collect the minimum sign bits that are shared
2781  /// by the requested vector elements.
2782  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2783  const APInt &DemandedElts,
2784  const SelectionDAG &DAG,
2785  unsigned Depth = 0) const;
2786 
2787  /// Attempt to simplify any target nodes based on the demanded vector
2788  /// elements, returning true on success. Otherwise, analyze the expression and
2789  /// return a mask of KnownUndef and KnownZero elements for the expression
2790  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2791  /// accurate for those bits in the DemandedMask
2792  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2793  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2794  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2795 
2797  void *DC; // The DAG Combiner object.
2800 
2801  public:
2803 
2804  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2805  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2806 
2807  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2808  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2809  bool isAfterLegalizeDAG() const {
2810  return Level == AfterLegalizeDAG;
2811  }
2813  bool isCalledByLegalizer() const { return CalledByLegalizer; }
2814 
2815  void AddToWorklist(SDNode *N);
2816  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2817  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2818  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2819 
2820  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2821  };
2822 
2823  /// Return if the N is a constant or constant vector equal to the true value
2824  /// from getBooleanContents().
2825  bool isConstTrueVal(const SDNode *N) const;
2826 
2827  /// Return if the N is a constant or constant vector equal to the false value
2828  /// from getBooleanContents().
2829  bool isConstFalseVal(const SDNode *N) const;
2830 
2831  /// Return if \p N is a True value when extended to \p VT.
2832  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2833 
2834  /// Try to simplify a setcc built with the specified operands and cc. If it is
2835  /// unable to simplify it, return a null SDValue.
2836  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2837  bool foldBooleans, DAGCombinerInfo &DCI,
2838  const SDLoc &dl) const;
2839 
2840  // For targets which wrap address, unwrap for analysis.
2841  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2842 
2843  /// Returns true (and the GlobalValue and the offset) if the node is a
2844  /// GlobalAddress + offset.
2845  virtual bool
2846  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2847 
2848  /// This method will be invoked for all target nodes and for any
2849  /// target-independent nodes that the target has registered with invoke it
2850  /// for.
2851  ///
2852  /// The semantics are as follows:
2853  /// Return Value:
2854  /// SDValue.Val == 0 - No change was made
2855  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2856  /// otherwise - N should be replaced by the returned Operand.
2857  ///
2858  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2859  /// more complex transformations.
2860  ///
2861  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2862 
2863  /// Return true if it is profitable to move a following shift through this
2864  // node, adjusting any immediate operands as necessary to preserve semantics.
2865  // This transformation may not be desirable if it disrupts a particularly
2866  // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2867  // By default, it returns true.
2868  virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2869  return true;
2870  }
2871 
2872  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2873  // to a shuffle and a truncate.
2874  // Example of such a combine:
2875  // v4i32 build_vector((extract_elt V, 1),
2876  // (extract_elt V, 3),
2877  // (extract_elt V, 5),
2878  // (extract_elt V, 7))
2879  // -->
2880  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2882  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2883  return false;
2884  }
2885 
2886  /// Return true if the target has native support for the specified value type
2887  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2888  /// i16 is legal, but undesirable since i16 instruction encodings are longer
2889  /// and some i16 instructions are slow.
2890  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2891  // By default, assume all legal types are desirable.
2892  return isTypeLegal(VT);
2893  }
2894 
2895  /// Return true if it is profitable for dag combiner to transform a floating
2896  /// point op of specified opcode to a equivalent op of an integer
2897  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2898  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2899  EVT /*VT*/) const {
2900  return false;
2901  }
2902 
2903  /// This method query the target whether it is beneficial for dag combiner to
2904  /// promote the specified node. If true, it should return the desired
2905  /// promotion type by reference.
2906  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2907  return false;
2908  }
2909 
2910  /// Return true if the target supports swifterror attribute. It optimizes
2911  /// loads and stores to reading and writing a specific register.
2912  virtual bool supportSwiftError() const {
2913  return false;
2914  }
2915 
2916  /// Return true if the target supports that a subset of CSRs for the given
2917  /// machine function is handled explicitly via copies.
2918  virtual bool supportSplitCSR(MachineFunction *MF) const {
2919  return false;
2920  }
2921 
2922  /// Perform necessary initialization to handle a subset of CSRs explicitly
2923  /// via copies. This function is called at the beginning of instruction
2924  /// selection.
2925  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2926  llvm_unreachable("Not Implemented");
2927  }
2928 
2929  /// Insert explicit copies in entry and exit blocks. We copy a subset of
2930  /// CSRs to virtual registers in the entry block, and copy them back to
2931  /// physical registers in the exit blocks. This function is called at the end
2932  /// of instruction selection.
2933  virtual void insertCopiesSplitCSR(
2934  MachineBasicBlock *Entry,
2935  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2936  llvm_unreachable("Not Implemented");
2937  }
2938 
2939  //===--------------------------------------------------------------------===//
2940  // Lowering methods - These methods must be implemented by targets so that
2941  // the SelectionDAGBuilder code knows how to lower these.
2942  //
2943 
2944  /// This hook must be implemented to lower the incoming (formal) arguments,
2945  /// described by the Ins array, into the specified DAG. The implementation
2946  /// should fill in the InVals array with legal-type argument values, and
2947  /// return the resulting token chain value.
2949  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2950  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
2951  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
2952  llvm_unreachable("Not Implemented");
2953  }
2954 
2955  /// This structure contains all information that is necessary for lowering
2956  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2957  /// needs to lower a call, and targets will see this struct in their LowerCall
2958  /// implementation.
2961  Type *RetTy = nullptr;
2962  bool RetSExt : 1;
2963  bool RetZExt : 1;
2964  bool IsVarArg : 1;
2965  bool IsInReg : 1;
2966  bool DoesNotReturn : 1;
2968  bool IsConvergent : 1;
2969  bool IsPatchPoint : 1;
2970 
2971  // IsTailCall should be modified by implementations of
2972  // TargetLowering::LowerCall that perform tail call conversions.
2973  bool IsTailCall = false;
2974 
2975  // Is Call lowering done post SelectionDAG type legalization.
2976  bool IsPostTypeLegalization = false;
2977 
2978  unsigned NumFixedArgs = -1;
2981  ArgListTy Args;
2989 
2991  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
2992  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
2993  IsPatchPoint(false), DAG(DAG) {}
2994 
2996  DL = dl;
2997  return *this;
2998  }
2999 
3001  Chain = InChain;
3002  return *this;
3003  }
3004 
3005  // setCallee with target/module-specific attributes
3007  SDValue Target, ArgListTy &&ArgsList) {
3008  RetTy = ResultType;
3009  Callee = Target;
3010  CallConv = CC;
3011  NumFixedArgs = ArgsList.size();
3012  Args = std::move(ArgsList);
3013 
3015  &(DAG.getMachineFunction()), CC, Args);
3016  return *this;
3017  }
3018 
3020  SDValue Target, ArgListTy &&ArgsList) {
3021  RetTy = ResultType;
3022  Callee = Target;
3023  CallConv = CC;
3024  NumFixedArgs = ArgsList.size();
3025  Args = std::move(ArgsList);
3026  return *this;
3027  }
3028 
3030  SDValue Target, ArgListTy &&ArgsList,
3031  ImmutableCallSite Call) {
3032  RetTy = ResultType;
3033 
3034  IsInReg = Call.hasRetAttr(Attribute::InReg);
3035  DoesNotReturn =
3036  Call.doesNotReturn() ||
3037  (!Call.isInvoke() &&
3038  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3039  IsVarArg = FTy->isVarArg();
3040  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3041  RetSExt = Call.hasRetAttr(Attribute::SExt);
3042  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3043 
3044  Callee = Target;
3045 
3046  CallConv = Call.getCallingConv();
3047  NumFixedArgs = FTy->getNumParams();
3048  Args = std::move(ArgsList);
3049 
3050  CS = Call;
3051 
3052  return *this;
3053  }
3054 
3056  IsInReg = Value;
3057  return *this;
3058  }
3059 
3061  DoesNotReturn = Value;
3062  return *this;
3063  }
3064 
3066  IsVarArg = Value;
3067  return *this;
3068  }
3069 
3071  IsTailCall = Value;
3072  return *this;
3073  }
3074 
3076  IsReturnValueUsed = !Value;
3077  return *this;
3078  }
3079 
3081  IsConvergent = Value;
3082  return *this;
3083  }
3084 
3086  RetSExt = Value;
3087  return *this;
3088  }
3089 
3091  RetZExt = Value;
3092  return *this;
3093  }
3094 
3096  IsPatchPoint = Value;
3097  return *this;
3098  }
3099 
3101  IsPostTypeLegalization = Value;
3102  return *this;
3103  }
3104 
3105  ArgListTy &getArgs() {
3106  return Args;
3107  }
3108  };
3109 
3110  /// This function lowers an abstract call to a function into an actual call.
3111  /// This returns a pair of operands. The first element is the return value
3112  /// for the function (if RetTy is not VoidTy). The second element is the
3113  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3114  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3115 
3116  /// This hook must be implemented to lower calls into the specified
3117  /// DAG. The outgoing arguments to the call are described by the Outs array,
3118  /// and the values to be returned by the call are described by the Ins
3119  /// array. The implementation should fill in the InVals array with legal-type
3120  /// return values from the call, and return the resulting token chain value.
3121  virtual SDValue
3123  SmallVectorImpl<SDValue> &/*InVals*/) const {
3124  llvm_unreachable("Not Implemented");
3125  }
3126 
3127  /// Target-specific cleanup for formal ByVal parameters.
3128  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3129 
3130  /// This hook should be implemented to check whether the return values
3131  /// described by the Outs array can fit into the return registers. If false
3132  /// is returned, an sret-demotion is performed.
3133  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3134  MachineFunction &/*MF*/, bool /*isVarArg*/,
3135  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3136  LLVMContext &/*Context*/) const
3137  {
3138  // Return true by default to get preexisting behavior.
3139  return true;
3140  }
3141 
3142  /// This hook must be implemented to lower outgoing return values, described
3143  /// by the Outs array, into the specified DAG. The implementation should
3144  /// return the resulting token chain value.
3145  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3146  bool /*isVarArg*/,
3147  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3148  const SmallVectorImpl<SDValue> & /*OutVals*/,
3149  const SDLoc & /*dl*/,
3150  SelectionDAG & /*DAG*/) const {
3151  llvm_unreachable("Not Implemented");
3152  }
3153 
3154  /// Return true if result of the specified node is used by a return node
3155  /// only. It also compute and return the input chain for the tail call.
3156  ///
3157  /// This is used to determine whether it is possible to codegen a libcall as
3158  /// tail call at legalization time.
3159  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3160  return false;
3161  }
3162 
3163  /// Return true if the target may be able emit the call instruction as a tail
3164  /// call. This is used by optimization passes to determine if it's profitable
3165  /// to duplicate return instructions to enable tailcall optimization.
3166  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3167  return false;
3168  }
3169 
3170  /// Return the builtin name for the __builtin___clear_cache intrinsic
3171  /// Default is to invoke the clear cache library call
3172  virtual const char * getClearCacheBuiltinName() const {
3173  return "__clear_cache";
3174  }
3175 
3176  /// Return the register ID of the name passed in. Used by named register
3177  /// global variables extension. There is no target-independent behaviour
3178  /// so the default action is to bail.
3179  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3180  SelectionDAG &DAG) const {
3181  report_fatal_error("Named registers not implemented for this target");
3182  }
3183 
3184  /// Return the type that should be used to zero or sign extend a
3185  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3186  /// require the return type to be promoted, but this is not true all the time,
3187  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3188  /// conventions. The frontend should handle this and include all of the
3189  /// necessary information.
3191  ISD::NodeType /*ExtendKind*/) const {
3192  EVT MinVT = getRegisterType(Context, MVT::i32);
3193  return VT.bitsLT(MinVT) ? MinVT : VT;
3194  }
3195 
3196  /// For some targets, an LLVM struct type must be broken down into multiple
3197  /// simple types, but the calling convention specifies that the entire struct
3198  /// must be passed in a block of consecutive registers.
3199  virtual bool
3201  bool isVarArg) const {
3202  return false;
3203  }
3204 
3205  /// Returns a 0 terminated array of registers that can be safely used as
3206  /// scratch registers.
3207  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3208  return nullptr;
3209  }
3210 
3211  /// This callback is used to prepare for a volatile or atomic load.
3212  /// It takes a chain node as input and returns the chain for the load itself.
3213  ///
3214  /// Having a callback like this is necessary for targets like SystemZ,
3215  /// which allows a CPU to reuse the result of a previous load indefinitely,
3216  /// even if a cache-coherent store is performed by another CPU. The default
3217  /// implementation does nothing.
3219  SelectionDAG &DAG) const {
3220  return Chain;
3221  }
3222 
3223  /// This callback is used to inspect load/store instructions and add
3224  /// target-specific MachineMemOperand flags to them. The default
3225  /// implementation does nothing.
3228  }
3229 
3230  /// This callback is invoked by the type legalizer to legalize nodes with an
3231  /// illegal operand type but legal result types. It replaces the
3232  /// LowerOperation callback in the type Legalizer. The reason we can not do
3233  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3234  /// use this callback.
3235  ///
3236  /// TODO: Consider merging with ReplaceNodeResults.
3237  ///
3238  /// The target places new result values for the node in Results (their number
3239  /// and types must exactly match those of the original return values of
3240  /// the node), or leaves Results empty, which indicates that the node is not
3241  /// to be custom lowered after all.
3242  /// The default implementation calls LowerOperation.
3243  virtual void LowerOperationWrapper(SDNode *N,
3245  SelectionDAG &DAG) const;
3246 
3247  /// This callback is invoked for operations that are unsupported by the
3248  /// target, which are registered to use 'custom' lowering, and whose defined
3249  /// values are all legal. If the target has no operations that require custom
3250  /// lowering, it need not implement this. The default implementation of this
3251  /// aborts.
3252  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3253 
3254  /// This callback is invoked when a node result type is illegal for the
3255  /// target, and the operation was registered to use 'custom' lowering for that
3256  /// result type. The target places new result values for the node in Results
3257  /// (their number and types must exactly match those of the original return
3258  /// values of the node), or leaves Results empty, which indicates that the
3259  /// node is not to be custom lowered after all.
3260  ///
3261  /// If the target has no operations that require custom lowering, it need not
3262  /// implement this. The default implementation aborts.
3263  virtual void ReplaceNodeResults(SDNode * /*N*/,
3264  SmallVectorImpl<SDValue> &/*Results*/,
3265  SelectionDAG &/*DAG*/) const {
3266  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3267  }
3268 
3269  /// This method returns the name of a target specific DAG node.
3270  virtual const char *getTargetNodeName(unsigned Opcode) const;
3271 
3272  /// This method returns a target specific FastISel object, or null if the
3273  /// target does not support "fast" ISel.
3275  const TargetLibraryInfo *) const {
3276  return nullptr;
3277  }
3278 
3279  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3280  SelectionDAG &DAG) const;
3281 
3282  //===--------------------------------------------------------------------===//
3283  // Inline Asm Support hooks
3284  //
3285 
3286  /// This hook allows the target to expand an inline asm call to be explicit
3287  /// llvm code if it wants to. This is useful for turning simple inline asms
3288  /// into LLVM intrinsics, which gives the compiler more information about the
3289  /// behavior of the code.
3290  virtual bool ExpandInlineAsm(CallInst *) const {
3291  return false;
3292  }
3293 
3295  C_Register, // Constraint represents specific register(s).
3296  C_RegisterClass, // Constraint represents any of register(s) in class.
3297  C_Memory, // Memory constraint.
3298  C_Other, // Something else.
3299  C_Unknown // Unsupported constraint.
3300  };
3301 
3303  // Generic weights.
3304  CW_Invalid = -1, // No match.
3305  CW_Okay = 0, // Acceptable.
3306  CW_Good = 1, // Good weight.
3307  CW_Better = 2, // Better weight.
3308  CW_Best = 3, // Best weight.
3309 
3310  // Well-known weights.
3311  CW_SpecificReg = CW_Okay, // Specific register operands.
3312  CW_Register = CW_Good, // Register operands.
3313  CW_Memory = CW_Better, // Memory operands.
3314  CW_Constant = CW_Best, // Constant operand.
3315  CW_Default = CW_Okay // Default or don't know type.
3316  };
3317 
3318  /// This contains information for each constraint that we are lowering.
3320  /// This contains the actual string for the code, like "m". TargetLowering
3321  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3322  /// matches the operand.
3323  std::string ConstraintCode;
3324 
3325  /// Information about the constraint code, e.g. Register, RegisterClass,
3326  /// Memory, Other, Unknown.
3328 
3329  /// If this is the result output operand or a clobber, this is null,
3330  /// otherwise it is the incoming operand to the CallInst. This gets
3331  /// modified as the asm is processed.
3332  Value *CallOperandVal = nullptr;
3333 
3334  /// The ValueType for the operand value.
3335  MVT ConstraintVT = MVT::Other;
3336 
3337  /// Copy constructor for copying from a ConstraintInfo.
3339  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3340 
3341  /// Return true of this is an input operand that is a matching constraint
3342  /// like "4".
3343  bool isMatchingInputConstraint() const;
3344 
3345  /// If this is an input matching constraint, this method returns the output
3346  /// operand it matches.
3347  unsigned getMatchedOperand() const;
3348  };
3349 
3350  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3351 
3352  /// Split up the constraint string from the inline assembly value into the
3353  /// specific constraints and their prefixes, and also tie in the associated
3354  /// operand values. If this returns an empty vector, and if the constraint
3355  /// string itself isn't empty, there was an error parsing.
3356  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3357  const TargetRegisterInfo *TRI,
3358  ImmutableCallSite CS) const;
3359 
3360  /// Examine constraint type and operand type and determine a weight value.
3361  /// The operand object must already have been set up with the operand type.
3362  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3363  AsmOperandInfo &info, int maIndex) const;
3364 
3365  /// Examine constraint string and operand type and determine a weight value.
3366  /// The operand object must already have been set up with the operand type.
3367  virtual ConstraintWeight getSingleConstraintMatchWeight(
3368  AsmOperandInfo &info, const char *constraint) const;
3369 
3370  /// Determines the constraint code and constraint type to use for the specific
3371  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3372  /// If the actual operand being passed in is available, it can be passed in as
3373  /// Op, otherwise an empty SDValue can be passed.
3374  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3375  SDValue Op,
3376  SelectionDAG *DAG = nullptr) const;
3377 
3378  /// Given a constraint, return the type of constraint it is for this target.
3379  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3380 
3381  /// Given a physical register constraint (e.g. {edx}), return the register
3382  /// number and the register class for the register.
3383  ///
3384  /// Given a register class constraint, like 'r', if this corresponds directly
3385  /// to an LLVM register class, return a register of 0 and the register class
3386  /// pointer.
3387  ///
3388  /// This should only be used for C_Register constraints. On error, this
3389  /// returns a register number of 0 and a null register class pointer.
3390  virtual std::pair<unsigned, const TargetRegisterClass *>
3391  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3392  StringRef Constraint, MVT VT) const;
3393 
3394  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3395  if (ConstraintCode == "i")
3396  return InlineAsm::Constraint_i;
3397  else if (ConstraintCode == "m")
3398  return InlineAsm::Constraint_m;
3400  }
3401 
3402  /// Try to replace an X constraint, which matches anything, with another that
3403  /// has more specific requirements based on the type of the corresponding
3404  /// operand. This returns null if there is no replacement to make.
3405  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3406 
3407  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3408  /// add anything to Ops.
3409  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3410  std::vector<SDValue> &Ops,
3411  SelectionDAG &DAG) const;
3412 
3413  //===--------------------------------------------------------------------===//
3414  // Div utility functions
3415  //
3416  SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3417  bool IsAfterLegalization,
3418  std::vector<SDNode *> *Created) const;
3419  SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3420  bool IsAfterLegalization,
3421  std::vector<SDNode *> *Created) const;
3422 
3423  /// Targets may override this function to provide custom SDIV lowering for
3424  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3425  /// assumes SDIV is expensive and replaces it with a series of other integer
3426  /// operations.
3427  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3428  SelectionDAG &DAG,
3429  std::vector<SDNode *> *Created) const;
3430 
3431  /// Indicate whether this target prefers to combine FDIVs with the same
3432  /// divisor. If the transform should never be done, return zero. If the
3433  /// transform should be done, return the minimum number of divisor uses
3434  /// that must exist.
3435  virtual unsigned combineRepeatedFPDivisors() const {
3436  return 0;
3437  }
3438 
3439  /// Hooks for building estimates in place of slower divisions and square
3440  /// roots.
3441 
3442  /// Return either a square root or its reciprocal estimate value for the input
3443  /// operand.
3444  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3445  /// 'Enabled' as set by a potential default override attribute.
3446  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3447  /// refinement iterations required to generate a sufficient (though not
3448  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3449  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3450  /// algorithm implementation that uses either one or two constants.
3451  /// The boolean Reciprocal is used to select whether the estimate is for the
3452  /// square root of the input operand or the reciprocal of its square root.
3453  /// A target may choose to implement its own refinement within this function.
3454  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3455  /// any further refinement of the estimate.
3456  /// An empty SDValue return means no estimate sequence can be created.
3458  int Enabled, int &RefinementSteps,
3459  bool &UseOneConstNR, bool Reciprocal) const {
3460  return SDValue();
3461  }
3462 
3463  /// Return a reciprocal estimate value for the input operand.
3464  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3465  /// 'Enabled' as set by a potential default override attribute.
3466  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3467  /// refinement iterations required to generate a sufficient (though not
3468  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3469  /// A target may choose to implement its own refinement within this function.
3470  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3471  /// any further refinement of the estimate.
3472  /// An empty SDValue return means no estimate sequence can be created.
3474  int Enabled, int &RefinementSteps) const {
3475  return SDValue();
3476  }
3477 
3478  //===--------------------------------------------------------------------===//
3479  // Legalization utility functions
3480  //
3481 
3482  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3483  /// respectively, each computing an n/2-bit part of the result.
3484  /// \param Result A vector that will be filled with the parts of the result
3485  /// in little-endian order.
3486  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3487  /// if you want to control how low bits are extracted from the LHS.
3488  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3489  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3490  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3491  /// \returns true if the node has been expanded, false if it has not
3492  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3493  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3495  SDValue LL = SDValue(), SDValue LH = SDValue(),
3496  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3497 
3498  /// Expand a MUL into two nodes. One that computes the high bits of
3499  /// the result and one that computes the low bits.
3500  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3501  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3502  /// if you want to control how low bits are extracted from the LHS.
3503  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3504  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3505  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3506  /// \returns true if the node has been expanded. false if it has not
3507  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3508  SelectionDAG &DAG, MulExpansionKind Kind,
3509  SDValue LL = SDValue(), SDValue LH = SDValue(),
3510  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3511 
3512  /// Expand float(f32) to SINT(i64) conversion
3513  /// \param N Node to expand
3514  /// \param Result output after conversion
3515  /// \returns True, if the expansion was successful, false otherwise
3516  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3517 
3518  /// Turn load of vector type into a load of the individual elements.
3519  /// \param LD load to expand
3520  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3521  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3522 
3523  // Turn a store of a vector type into stores of the individual elements.
3524  /// \param ST Store with a vector value type
3525  /// \returns MERGE_VALUs of the individual store chains.
3526  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3527 
3528  /// Expands an unaligned load to 2 half-size loads for an integer, and
3529  /// possibly more for vectors.
3530  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3531  SelectionDAG &DAG) const;
3532 
3533  /// Expands an unaligned store to 2 half-size stores for integer values, and
3534  /// possibly more for vectors.
3535  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3536 
3537  /// Increments memory address \p Addr according to the type of the value
3538  /// \p DataVT that should be stored. If the data is stored in compressed
3539  /// form, the memory address should be incremented according to the number of
3540  /// the stored elements. This number is equal to the number of '1's bits
3541  /// in the \p Mask.
3542  /// \p DataVT is a vector type. \p Mask is a vector value.
3543  /// \p DataVT and \p Mask have the same number of vector elements.
3544  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3545  EVT DataVT, SelectionDAG &DAG,
3546  bool IsCompressedMemory) const;
3547 
3548  /// Get a pointer to vector element \p Idx located in memory for a vector of
3549  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3550  /// bounds the returned pointer is unspecified, but will be within the vector
3551  /// bounds.
3552  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3553  SDValue Idx) const;
3554 
3555  //===--------------------------------------------------------------------===//
3556  // Instruction Emitting Hooks
3557  //
3558 
3559  /// This method should be implemented by targets that mark instructions with
3560  /// the 'usesCustomInserter' flag. These instructions are special in various
3561  /// ways, which require special support to insert. The specified MachineInstr
3562  /// is created but not inserted into any basic blocks, and this method is
3563  /// called to expand it into a sequence of instructions, potentially also
3564  /// creating new basic blocks and control flow.
3565  /// As long as the returned basic block is different (i.e., we created a new
3566  /// one), the custom inserter is free to modify the rest of \p MBB.
3567  virtual MachineBasicBlock *
3568  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3569 
3570  /// This method should be implemented by targets that mark instructions with
3571  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3572  /// instruction selection by target hooks. e.g. To fill in optional defs for
3573  /// ARM 's' setting instructions.
3574  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3575  SDNode *Node) const;
3576 
3577  /// If this function returns true, SelectionDAGBuilder emits a
3578  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3579  virtual bool useLoadStackGuardNode() const {
3580  return false;
3581  }
3582 
3584  const SDLoc &DL) const {
3585  llvm_unreachable("not implemented for this target");
3586  }
3587 
3588  /// Lower TLS global address SDNode for target independent emulated TLS model.
3589  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3590  SelectionDAG &DAG) const;
3591 
3592  /// Expands target specific indirect branch for the case of JumpTable
3593  /// expanasion.
3595  SelectionDAG &DAG) const {
3596  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3597  }
3598 
3599  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3600  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3601  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3602  // combiner can fold the new nodes.
3603  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3604 
3605 private:
3606  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3607  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3608  const SDLoc &DL) const;
3609 };
3610 
3611 /// Given an LLVM IR type and return type attributes, compute the return value
3612 /// EVTs and flags, and optionally also the offsets, if the return value is
3613 /// being lowered to memory.
3616  const TargetLowering &TLI, const DataLayout &DL);
3617 
3618 } // end namespace llvm
3619 
3620 #endif // LLVM_CODEGEN_TARGETLOWERING_H
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
virtual MVT getRegisterTypeForCallingConv(MVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
static MVT getIntegerVT(unsigned BitWidth)
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, DivergenceAnalysis *DA) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:837
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:245
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:571
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, EVT VT) const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:365
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:236
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:312
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static ISD::NodeType getExtendForContent(BooleanContent Content)
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
An instruction for reading from memory.
Definition: Instructions.h:164
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:360
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
void * PointerTy
Definition: GenericValue.h:22
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:497
Definition: BitVector.h:921
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:677
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:63
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:306
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:919
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:170
Class to represent pointers.
Definition: DerivedTypes.h:467
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:42
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:894
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:16
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:579
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:471
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:90
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:391
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:901
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:212
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:725
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:724
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
static bool Enabled
Definition: Statistic.cpp:51
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Class to represent vector types.
Definition: DerivedTypes.h:393
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:69
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform&#39;s va_list object.
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
LegalizeTypeAction getTypeAction(MVT VT) const
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:446
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:172
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:449
ValueTypeActionImpl ValueTypeActions
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
virtual bool needsFixedCatchObjects() const
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:574
Flags
Flags values. These may be or&#39;d together.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool useSoftFloat() const
CallLoweringInfo & setTailCall(bool Value=true)
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:607
virtual bool isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const
Similar to isShuffleMaskLegal.
Representation of each machine instruction.
Definition: MachineInstr.h:60
Basic Alias true
CallLoweringInfo & setConvergent(bool Value=true)
SmallVector< SDValue, 32 > OutVals
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, EVT VT) const
Certain targets require unusual breakdowns of certain types.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1299
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
const ValueTypeActionImpl & getValueTypeActions() const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
void setTypeAction(MVT VT, LegalizeTypeAction Action)
bool isPositionIndependent() const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const
Insert explicit copies in entry and exit blocks.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:583
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
Establish a view to a call site for examination.
Definition: CallSite.h:713
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that&#39;s to be used to test the result of the comparison libcall against zero...
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:882
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:309
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
const unsigned Kind
Multiway switch.
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger s...
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void GetReturnInfo(Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
unsigned getMinFunctionAlignment() const
Return the minimum function alignment.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual unsigned getMemcmpEqZeroLoadsPerBlock() const
For memcmp expansion when the memcmp result is only compared equal or not-equal to 0...
CallLoweringInfo & setInRegister(bool Value=true)
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:372
LLVM Value Representation.
Definition: Value.h:73
void setUseUnderscoreSetJmp(bool Val)
Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _...
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
bool isOperationLegalOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal using promotion...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal on this target.
bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal or custom on this target.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
virtual bool mergeStoresAfterLegalization() const
Allow store merging after legalization in addition to before legalization.
Type * getElementType() const
Definition: DerivedTypes.h:360
virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
IRTranslator LLVM IR MI
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:418
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
virtual bool isShuffleMaskLegal(ArrayRef< int >, EVT) const
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
Conversion operators.
Definition: ISDOpcodes.h:443
BooleanContent
Enum that describes how the target represents true/false values.
unsigned getGatherAllAliasesMaxDepth() const
bool isBigEndian() const
Definition: DataLayout.h:222
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
bool hasTargetDAGCombine(ISD::NodeType NT) const
If true, the target has custom DAG combine transformations that it can perform for the specified node...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
virtual bool hasBitPreservingFPLogic(EVT VT) const
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array...
virtual bool shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool isLegalAddImmediate(int64_t) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
virtual bool isDesirableToCommuteWithShift(const SDNode *N) const
Return true if it is profitable to move a following shift through this.
The operation is expected to be selectable directly by the target, and no transformation is necessary...
Definition: LegalizerInfo.h:45
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
bool use_empty() const
Definition: Value.h:328
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
Definition: ValueTypes.h:131
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const