LLVM  11.0.0git
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instruction.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Alignment.h"
50 #include "llvm/Support/Casting.h"
53 #include <algorithm>
54 #include <cassert>
55 #include <climits>
56 #include <cstdint>
57 #include <iterator>
58 #include <map>
59 #include <string>
60 #include <utility>
61 #include <vector>
62 
63 namespace llvm {
64 
65 class BranchProbability;
66 class CCState;
67 class CCValAssign;
68 class Constant;
69 class FastISel;
70 class FunctionLoweringInfo;
71 class GlobalValue;
72 class GISelKnownBits;
73 class IntrinsicInst;
74 struct KnownBits;
75 class LegacyDivergenceAnalysis;
76 class LLVMContext;
77 class MachineBasicBlock;
78 class MachineFunction;
79 class MachineInstr;
80 class MachineJumpTableInfo;
81 class MachineLoop;
82 class MachineRegisterInfo;
83 class MCContext;
84 class MCExpr;
85 class Module;
86 class ProfileSummaryInfo;
87 class TargetLibraryInfo;
88 class TargetMachine;
89 class TargetRegisterClass;
90 class TargetRegisterInfo;
91 class TargetTransformInfo;
92 class Value;
93 
94 namespace Sched {
95 
96  enum Preference {
97  None, // No preference
98  Source, // Follow source order.
99  RegPressure, // Scheduling for lowest register pressure.
100  Hybrid, // Scheduling for both latency and register pressure.
101  ILP, // Scheduling for ILP in low register pressure mode.
102  VLIW // Scheduling for VLIW targets.
103  };
104 
105 } // end namespace Sched
106 
107 // MemOp models a memory operation, either memset or memcpy/memmove.
108 struct MemOp {
109 private:
110  // Shared
111  uint64_t Size;
112  bool DstAlignCanChange; // true if destination alignment can satisfy any
113  // constraint.
114  Align DstAlign; // Specified alignment of the memory operation.
115 
116  bool AllowOverlap;
117  // memset only
118  bool IsMemset; // If setthis memory operation is a memset.
119  bool ZeroMemset; // If set clears out memory with zeros.
120  // memcpy only
121  bool MemcpyStrSrc; // Indicates whether the memcpy source is an in-register
122  // constant so it does not need to be loaded.
123  Align SrcAlign; // Inferred alignment of the source or default value if the
124  // memory operation does not need to load the value.
125 public:
126  static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign,
127  Align SrcAlign, bool IsVolatile,
128  bool MemcpyStrSrc = false) {
129  MemOp Op;
130  Op.Size = Size;
131  Op.DstAlignCanChange = DstAlignCanChange;
132  Op.DstAlign = DstAlign;
133  Op.AllowOverlap = !IsVolatile;
134  Op.IsMemset = false;
135  Op.ZeroMemset = false;
136  Op.MemcpyStrSrc = MemcpyStrSrc;
137  Op.SrcAlign = SrcAlign;
138  return Op;
139  }
140 
141  static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign,
142  bool IsZeroMemset, bool IsVolatile) {
143  MemOp Op;
144  Op.Size = Size;
145  Op.DstAlignCanChange = DstAlignCanChange;
146  Op.DstAlign = DstAlign;
147  Op.AllowOverlap = !IsVolatile;
148  Op.IsMemset = true;
149  Op.ZeroMemset = IsZeroMemset;
150  Op.MemcpyStrSrc = false;
151  return Op;
152  }
153 
154  uint64_t size() const { return Size; }
155  Align getDstAlign() const {
156  assert(!DstAlignCanChange);
157  return DstAlign;
158  }
159  bool isFixedDstAlign() const { return !DstAlignCanChange; }
160  bool allowOverlap() const { return AllowOverlap; }
161  bool isMemset() const { return IsMemset; }
162  bool isMemcpy() const { return !IsMemset; }
164  return isMemcpy() && !DstAlignCanChange;
165  }
166  bool isZeroMemset() const { return isMemset() && ZeroMemset; }
167  bool isMemcpyStrSrc() const {
168  assert(isMemcpy() && "Must be a memcpy");
169  return MemcpyStrSrc;
170  }
171  Align getSrcAlign() const {
172  assert(isMemcpy() && "Must be a memcpy");
173  return SrcAlign;
174  }
175  bool isSrcAligned(Align AlignCheck) const {
176  return isMemset() || llvm::isAligned(AlignCheck, SrcAlign.value());
177  }
178  bool isDstAligned(Align AlignCheck) const {
179  return DstAlignCanChange || llvm::isAligned(AlignCheck, DstAlign.value());
180  }
181  bool isAligned(Align AlignCheck) const {
182  return isSrcAligned(AlignCheck) && isDstAligned(AlignCheck);
183  }
184 };
185 
186 /// This base class for TargetLowering contains the SelectionDAG-independent
187 /// parts that can be used from the rest of CodeGen.
189 public:
190  /// This enum indicates whether operations are valid for a target, and if not,
191  /// what action should be used to make them valid.
192  enum LegalizeAction : uint8_t {
193  Legal, // The target natively supports this operation.
194  Promote, // This operation should be executed in a larger type.
195  Expand, // Try to expand this to other ops, otherwise use a libcall.
196  LibCall, // Don't try to expand this to other ops, always use a libcall.
197  Custom // Use the LowerOperation hook to implement custom lowering.
198  };
199 
200  /// This enum indicates whether a types are legal for a target, and if not,
201  /// what action should be used to make them valid.
202  enum LegalizeTypeAction : uint8_t {
203  TypeLegal, // The target natively supports this type.
204  TypePromoteInteger, // Replace this integer with a larger one.
205  TypeExpandInteger, // Split this integer into two of half the size.
206  TypeSoftenFloat, // Convert this float to a same size integer type.
207  TypeExpandFloat, // Split this float into two of half the size.
208  TypeScalarizeVector, // Replace this one-element vector with its element.
209  TypeSplitVector, // Split this vector into two of half the size.
210  TypeWidenVector, // This vector should be widened into a larger vector.
211  TypePromoteFloat, // Replace this float with a larger one.
212  TypeSoftPromoteHalf, // Soften half to i16 and use float to do arithmetic.
213  };
214 
215  /// LegalizeKind holds the legalization kind that needs to happen to EVT
216  /// in order to type-legalize it.
217  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
218 
219  /// Enum that describes how the target represents true/false values.
221  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
222  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
223  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
224  };
225 
226  /// Enum that describes what type of support for selects the target has.
228  ScalarValSelect, // The target supports scalar selects (ex: cmov).
229  ScalarCondVectorVal, // The target supports selects with a scalar condition
230  // and vector values (ex: cmov).
231  VectorMaskSelect // The target supports vector selects with a vector
232  // mask (ex: x86 blends).
233  };
234 
235  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
236  /// to, if at all. Exists because different targets have different levels of
237  /// support for these atomic instructions, and also have different options
238  /// w.r.t. what they should expand to.
239  enum class AtomicExpansionKind {
240  None, // Don't expand the instruction.
241  LLSC, // Expand the instruction into loadlinked/storeconditional; used
242  // by ARM/AArch64.
243  LLOnly, // Expand the (load) instruction into just a load-linked, which has
244  // greater atomic guarantees than a normal load.
245  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
246  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
247  };
248 
249  /// Enum that specifies when a multiplication should be expanded.
250  enum class MulExpansionKind {
251  Always, // Always expand the instruction.
252  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
253  // or custom.
254  };
255 
256  /// Enum that specifies when a float negation is beneficial.
257  enum class NegatibleCost {
258  Cheaper = 0, // Negated expression is cheaper.
259  Neutral = 1, // Negated expression has the same cost.
260  Expensive = 2 // Negated expression is more expensive.
261  };
262 
263  class ArgListEntry {
264  public:
265  Value *Val = nullptr;
267  Type *Ty = nullptr;
268  bool IsSExt : 1;
269  bool IsZExt : 1;
270  bool IsInReg : 1;
271  bool IsSRet : 1;
272  bool IsNest : 1;
273  bool IsByVal : 1;
274  bool IsInAlloca : 1;
275  bool IsPreallocated : 1;
276  bool IsReturned : 1;
277  bool IsSwiftSelf : 1;
278  bool IsSwiftError : 1;
279  bool IsCFGuardTarget : 1;
280  MaybeAlign Alignment = None;
281  Type *ByValType = nullptr;
282  Type *PreallocatedType = nullptr;
283 
285  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
286  IsNest(false), IsByVal(false), IsInAlloca(false),
287  IsPreallocated(false), IsReturned(false), IsSwiftSelf(false),
288  IsSwiftError(false), IsCFGuardTarget(false) {}
289 
290  void setAttributes(const CallBase *Call, unsigned ArgIdx);
291  };
292  using ArgListTy = std::vector<ArgListEntry>;
293 
294  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
295  ArgListTy &Args) const {};
296 
298  switch (Content) {
299  case UndefinedBooleanContent:
300  // Extend by adding rubbish bits.
301  return ISD::ANY_EXTEND;
302  case ZeroOrOneBooleanContent:
303  // Extend by adding zero bits.
304  return ISD::ZERO_EXTEND;
305  case ZeroOrNegativeOneBooleanContent:
306  // Extend by copying the sign bit.
307  return ISD::SIGN_EXTEND;
308  }
309  llvm_unreachable("Invalid content kind");
310  }
311 
312  explicit TargetLoweringBase(const TargetMachine &TM);
313  TargetLoweringBase(const TargetLoweringBase &) = delete;
314  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
315  virtual ~TargetLoweringBase() = default;
316 
317  /// Return true if the target support strict float operation
318  bool isStrictFPEnabled() const {
319  return IsStrictFPEnabled;
320  }
321 
322 protected:
323  /// Initialize all of the actions to default values.
324  void initActions();
325 
326 public:
327  const TargetMachine &getTargetMachine() const { return TM; }
328 
329  virtual bool useSoftFloat() const { return false; }
330 
331  /// Return the pointer type for the given address space, defaults to
332  /// the pointer type from the data layout.
333  /// FIXME: The default needs to be removed once all the code is updated.
334  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
336  }
337 
338  /// Return the in-memory pointer type for the given address space, defaults to
339  /// the pointer type from the data layout. FIXME: The default needs to be
340  /// removed once all the code is updated.
341  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
343  }
344 
345  /// Return the type for frame index, which is determined by
346  /// the alloca address space specified through the data layout.
347  MVT getFrameIndexTy(const DataLayout &DL) const {
348  return getPointerTy(DL, DL.getAllocaAddrSpace());
349  }
350 
351  /// Return the type for code pointers, which is determined by the program
352  /// address space specified through the data layout.
353  MVT getProgramPointerTy(const DataLayout &DL) const {
354  return getPointerTy(DL, DL.getProgramAddressSpace());
355  }
356 
357  /// Return the type for operands of fence.
358  /// TODO: Let fence operands be of i32 type and remove this.
359  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
360  return getPointerTy(DL);
361  }
362 
363  /// EVT is not used in-tree, but is used by out-of-tree target.
364  /// A documentation for this function would be nice...
365  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
366 
367  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
368  bool LegalTypes = true) const;
369 
370  /// Returns the type to be used for the index operand of:
371  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
372  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
373  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
374  return getPointerTy(DL);
375  }
376 
377  /// This callback is used to inspect load/store instructions and add
378  /// target-specific MachineMemOperand flags to them. The default
379  /// implementation does nothing.
382  }
383 
384  MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI,
385  const DataLayout &DL) const;
386  MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI,
387  const DataLayout &DL) const;
388  MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI,
389  const DataLayout &DL) const;
390 
391  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
392  return true;
393  }
394 
395  /// Return true if it is profitable to convert a select of FP constants into
396  /// a constant pool load whose address depends on the select condition. The
397  /// parameter may be used to differentiate a select with FP compare from
398  /// integer compare.
399  virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
400  return true;
401  }
402 
403  /// Return true if multiple condition registers are available.
405  return HasMultipleConditionRegisters;
406  }
407 
408  /// Return true if the target has BitExtract instructions.
409  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
410 
411  /// Return the preferred vector type legalization action.
414  // The default action for one element vectors is to scalarize
415  if (VT.getVectorNumElements() == 1)
416  return TypeScalarizeVector;
417  // The default action for an odd-width vector is to widen.
418  if (!VT.isPow2VectorType())
419  return TypeWidenVector;
420  // The default action for other vectors is to promote
421  return TypePromoteInteger;
422  }
423 
424  // Return true if the half type should be passed around as i16, but promoted
425  // to float around arithmetic. The default behavior is to pass around as
426  // float and convert around loads/stores/bitcasts and other places where
427  // the size matters.
428  virtual bool softPromoteHalfType() const { return false; }
429 
430  // There are two general methods for expanding a BUILD_VECTOR node:
431  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
432  // them together.
433  // 2. Build the vector on the stack and then load it.
434  // If this function returns true, then method (1) will be used, subject to
435  // the constraint that all of the necessary shuffles are legal (as determined
436  // by isShuffleMaskLegal). If this function returns false, then method (2) is
437  // always used. The vector type, and the number of defined values, are
438  // provided.
439  virtual bool
441  unsigned DefinedValues) const {
442  return DefinedValues < 3;
443  }
444 
445  /// Return true if integer divide is usually cheaper than a sequence of
446  /// several shifts, adds, and multiplies for this target.
447  /// The definition of "cheaper" may depend on whether we're optimizing
448  /// for speed or for size.
449  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
450 
451  /// Return true if the target can handle a standalone remainder operation.
452  virtual bool hasStandaloneRem(EVT VT) const {
453  return true;
454  }
455 
456  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
457  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
458  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
459  return false;
460  }
461 
462  /// Reciprocal estimate status values used by the functions below.
463  enum ReciprocalEstimate : int {
464  Unspecified = -1,
465  Disabled = 0,
467  };
468 
469  /// Return a ReciprocalEstimate enum value for a square root of the given type
470  /// based on the function's attributes. If the operation is not overridden by
471  /// the function's attributes, "Unspecified" is returned and target defaults
472  /// are expected to be used for instruction selection.
473  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
474 
475  /// Return a ReciprocalEstimate enum value for a division of the given type
476  /// based on the function's attributes. If the operation is not overridden by
477  /// the function's attributes, "Unspecified" is returned and target defaults
478  /// are expected to be used for instruction selection.
479  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
480 
481  /// Return the refinement step count for a square root of the given type based
482  /// on the function's attributes. If the operation is not overridden by
483  /// the function's attributes, "Unspecified" is returned and target defaults
484  /// are expected to be used for instruction selection.
485  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
486 
487  /// Return the refinement step count for a division of the given type based
488  /// on the function's attributes. If the operation is not overridden by
489  /// the function's attributes, "Unspecified" is returned and target defaults
490  /// are expected to be used for instruction selection.
491  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
492 
493  /// Returns true if target has indicated at least one type should be bypassed.
494  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
495 
496  /// Returns map of slow types for division or remainder with corresponding
497  /// fast types
499  return BypassSlowDivWidths;
500  }
501 
502  /// Return true if Flow Control is an expensive operation that should be
503  /// avoided.
504  bool isJumpExpensive() const { return JumpIsExpensive; }
505 
506  /// Return true if selects are only cheaper than branches if the branch is
507  /// unlikely to be predicted right.
509  return PredictableSelectIsExpensive;
510  }
511 
512  /// If a branch or a select condition is skewed in one direction by more than
513  /// this factor, it is very likely to be predicted correctly.
514  virtual BranchProbability getPredictableBranchThreshold() const;
515 
516  /// Return true if the following transform is beneficial:
517  /// fold (conv (load x)) -> (load (conv*)x)
518  /// On architectures that don't natively support some vector loads
519  /// efficiently, casting the load to a smaller vector of larger types and
520  /// loading is more efficient, however, this can be undone by optimizations in
521  /// dag combiner.
522  virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
523  const SelectionDAG &DAG,
524  const MachineMemOperand &MMO) const {
525  // Don't do if we could do an indexed load on the original type, but not on
526  // the new one.
527  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
528  return true;
529 
530  MVT LoadMVT = LoadVT.getSimpleVT();
531 
532  // Don't bother doing this if it's just going to be promoted again later, as
533  // doing so might interfere with other combines.
534  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
535  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
536  return false;
537 
538  bool Fast = false;
539  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
540  MMO, &Fast) && Fast;
541  }
542 
543  /// Return true if the following transform is beneficial:
544  /// (store (y (conv x)), y*)) -> (store x, (x*))
545  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
546  const SelectionDAG &DAG,
547  const MachineMemOperand &MMO) const {
548  // Default to the same logic as loads.
549  return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
550  }
551 
552  /// Return true if it is expected to be cheaper to do a store of a non-zero
553  /// vector constant with the given size and type for the address space than to
554  /// store the individual scalar element constants.
555  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
556  unsigned NumElem,
557  unsigned AddrSpace) const {
558  return false;
559  }
560 
561  /// Allow store merging for the specified type after legalization in addition
562  /// to before legalization. This may transform stores that do not exist
563  /// earlier (for example, stores created from intrinsics).
564  virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
565  return true;
566  }
567 
568  /// Returns if it's reasonable to merge stores to MemVT size.
569  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
570  const SelectionDAG &DAG) const {
571  return true;
572  }
573 
574  /// Return true if it is cheap to speculate a call to intrinsic cttz.
575  virtual bool isCheapToSpeculateCttz() const {
576  return false;
577  }
578 
579  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
580  virtual bool isCheapToSpeculateCtlz() const {
581  return false;
582  }
583 
584  /// Return true if ctlz instruction is fast.
585  virtual bool isCtlzFast() const {
586  return false;
587  }
588 
589  /// Return true if instruction generated for equality comparison is folded
590  /// with instruction generated for signed comparison.
591  virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
592 
593  /// Return true if it is safe to transform an integer-domain bitwise operation
594  /// into the equivalent floating-point operation. This should be set to true
595  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
596  /// type.
597  virtual bool hasBitPreservingFPLogic(EVT VT) const {
598  return false;
599  }
600 
601  /// Return true if it is cheaper to split the store of a merged int val
602  /// from a pair of smaller values into multiple stores.
603  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
604  return false;
605  }
606 
607  /// Return if the target supports combining a
608  /// chain like:
609  /// \code
610  /// %andResult = and %val1, #mask
611  /// %icmpResult = icmp %andResult, 0
612  /// \endcode
613  /// into a single machine instruction of a form like:
614  /// \code
615  /// cc = test %register, #mask
616  /// \endcode
617  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
618  return false;
619  }
620 
621  /// Use bitwise logic to make pairs of compares more efficient. For example:
622  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
623  /// This should be true when it takes more than one instruction to lower
624  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
625  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
626  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
627  return false;
628  }
629 
630  /// Return the preferred operand type if the target has a quick way to compare
631  /// integer values of the given size. Assume that any legal integer type can
632  /// be compared efficiently. Targets may override this to allow illegal wide
633  /// types to return a vector type if there is support to compare that type.
634  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
635  MVT VT = MVT::getIntegerVT(NumBits);
636  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
637  }
638 
639  /// Return true if the target should transform:
640  /// (X & Y) == Y ---> (~X & Y) == 0
641  /// (X & Y) != Y ---> (~X & Y) != 0
642  ///
643  /// This may be profitable if the target has a bitwise and-not operation that
644  /// sets comparison flags. A target may want to limit the transformation based
645  /// on the type of Y or if Y is a constant.
646  ///
647  /// Note that the transform will not occur if Y is known to be a power-of-2
648  /// because a mask and compare of a single bit can be handled by inverting the
649  /// predicate, for example:
650  /// (X & 8) == 8 ---> (X & 8) != 0
651  virtual bool hasAndNotCompare(SDValue Y) const {
652  return false;
653  }
654 
655  /// Return true if the target has a bitwise and-not operation:
656  /// X = ~A & B
657  /// This can be used to simplify select or other instructions.
658  virtual bool hasAndNot(SDValue X) const {
659  // If the target has the more complex version of this operation, assume that
660  // it has this operation too.
661  return hasAndNotCompare(X);
662  }
663 
664  /// Return true if the target has a bit-test instruction:
665  /// (X & (1 << Y)) ==/!= 0
666  /// This knowledge can be used to prevent breaking the pattern,
667  /// or creating it if it could be recognized.
668  virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
669 
670  /// There are two ways to clear extreme bits (either low or high):
671  /// Mask: x & (-1 << y) (the instcombine canonical form)
672  /// Shifts: x >> y << y
673  /// Return true if the variant with 2 variable shifts is preferred.
674  /// Return false if there is no preference.
676  // By default, let's assume that no one prefers shifts.
677  return false;
678  }
679 
680  /// Return true if it is profitable to fold a pair of shifts into a mask.
681  /// This is usually true on most targets. But some targets, like Thumb1,
682  /// have immediate shift instructions, but no immediate "and" instruction;
683  /// this makes the fold unprofitable.
685  CombineLevel Level) const {
686  return true;
687  }
688 
689  /// Should we tranform the IR-optimal check for whether given truncation
690  /// down into KeptBits would be truncating or not:
691  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
692  /// Into it's more traditional form:
693  /// ((%x << C) a>> C) dstcond %x
694  /// Return true if we should transform.
695  /// Return false if there is no preference.
697  unsigned KeptBits) const {
698  // By default, let's assume that no one prefers shifts.
699  return false;
700  }
701 
702  /// Given the pattern
703  /// (X & (C l>>/<< Y)) ==/!= 0
704  /// return true if it should be transformed into:
705  /// ((X <</l>> Y) & C) ==/!= 0
706  /// WARNING: if 'X' is a constant, the fold may deadlock!
707  /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
708  /// here because it can end up being not linked in.
711  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
712  SelectionDAG &DAG) const {
713  if (hasBitTest(X, Y)) {
714  // One interesting pattern that we'd want to form is 'bit test':
715  // ((1 << Y) & C) ==/!= 0
716  // But we also need to be careful not to try to reverse that fold.
717 
718  // Is this '1 << Y' ?
719  if (OldShiftOpcode == ISD::SHL && CC->isOne())
720  return false; // Keep the 'bit test' pattern.
721 
722  // Will it be '1 << Y' after the transform ?
723  if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
724  return true; // Do form the 'bit test' pattern.
725  }
726 
727  // If 'X' is a constant, and we transform, then we will immediately
728  // try to undo the fold, thus causing endless combine loop.
729  // So by default, let's assume everyone prefers the fold
730  // iff 'X' is not a constant.
731  return !XC;
732  }
733 
734  /// These two forms are equivalent:
735  /// sub %y, (xor %x, -1)
736  /// add (add %x, 1), %y
737  /// The variant with two add's is IR-canonical.
738  /// Some targets may prefer one to the other.
739  virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
740  // By default, let's assume that everyone prefers the form with two add's.
741  return true;
742  }
743 
744  /// Return true if the target wants to use the optimization that
745  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
746  /// promotedInst1(...(promotedInstN(ext(load)))).
747  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
748 
749  /// Return true if the target can combine store(extractelement VectorTy,
750  /// Idx).
751  /// \p Cost[out] gives the cost of that transformation when this is true.
752  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
753  unsigned &Cost) const {
754  return false;
755  }
756 
757  /// Return true if inserting a scalar into a variable element of an undef
758  /// vector is more efficiently handled by splatting the scalar instead.
759  virtual bool shouldSplatInsEltVarIndex(EVT) const {
760  return false;
761  }
762 
763  /// Return true if target always beneficiates from combining into FMA for a
764  /// given value type. This must typically return false on targets where FMA
765  /// takes more cycles to execute than FADD.
766  virtual bool enableAggressiveFMAFusion(EVT VT) const {
767  return false;
768  }
769 
770  /// Return the ValueType of the result of SETCC operations.
771  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
772  EVT VT) const;
773 
774  /// Return the ValueType for comparison libcalls. Comparions libcalls include
775  /// floating point comparion calls, and Ordered/Unordered check calls on
776  /// floating point numbers.
777  virtual
778  MVT::SimpleValueType getCmpLibcallReturnType() const;
779 
780  /// For targets without i1 registers, this gives the nature of the high-bits
781  /// of boolean values held in types wider than i1.
782  ///
783  /// "Boolean values" are special true/false values produced by nodes like
784  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
785  /// Not to be confused with general values promoted from i1. Some cpus
786  /// distinguish between vectors of boolean and scalars; the isVec parameter
787  /// selects between the two kinds. For example on X86 a scalar boolean should
788  /// be zero extended from i1, while the elements of a vector of booleans
789  /// should be sign extended from i1.
790  ///
791  /// Some cpus also treat floating point types the same way as they treat
792  /// vectors instead of the way they treat scalars.
793  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
794  if (isVec)
795  return BooleanVectorContents;
796  return isFloat ? BooleanFloatContents : BooleanContents;
797  }
798 
800  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
801  }
802 
803  /// Return target scheduling preference.
805  return SchedPreferenceInfo;
806  }
807 
808  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
809  /// for different nodes. This function returns the preference (or none) for
810  /// the given node.
812  return Sched::None;
813  }
814 
815  /// Return the register class that should be used for the specified value
816  /// type.
817  virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
818  (void)isDivergent;
819  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
820  assert(RC && "This value type is not natively supported!");
821  return RC;
822  }
823 
824  /// Allows target to decide about the register class of the
825  /// specific value that is live outside the defining block.
826  /// Returns true if the value needs uniform register class.
828  const Value *) const {
829  return false;
830  }
831 
832  /// Return the 'representative' register class for the specified value
833  /// type.
834  ///
835  /// The 'representative' register class is the largest legal super-reg
836  /// register class for the register class of the value type. For example, on
837  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
838  /// register class is GR64 on x86_64.
839  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
840  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
841  return RC;
842  }
843 
844  /// Return the cost of the 'representative' register class for the specified
845  /// value type.
846  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
847  return RepRegClassCostForVT[VT.SimpleTy];
848  }
849 
850  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
851  /// instructions, and false if a library call is preferred (e.g for code-size
852  /// reasons).
853  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
854  return true;
855  }
856 
857  /// Return true if the target has native support for the specified value type.
858  /// This means that it has a register that directly holds it without
859  /// promotions or expansions.
860  bool isTypeLegal(EVT VT) const {
861  assert(!VT.isSimple() ||
862  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
863  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
864  }
865 
867  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
868  /// that indicates how instruction selection should deal with the type.
869  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
870 
871  public:
873  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
874  TypeLegal);
875  }
876 
878  return ValueTypeActions[VT.SimpleTy];
879  }
880 
882  ValueTypeActions[VT.SimpleTy] = Action;
883  }
884  };
885 
887  return ValueTypeActions;
888  }
889 
890  /// Return how we should legalize values of this type, either it is already
891  /// legal (return 'Legal') or we need to promote it to a larger type (return
892  /// 'Promote'), or we need to expand it into multiple registers of smaller
893  /// integer type (return 'Expand'). 'Custom' is not an option.
895  return getTypeConversion(Context, VT).first;
896  }
898  return ValueTypeActions.getTypeAction(VT);
899  }
900 
901  /// For types supported by the target, this is an identity function. For
902  /// types that must be promoted to larger types, this returns the larger type
903  /// to promote to. For integer types that are larger than the largest integer
904  /// register, this contains one step in the expansion to get to the smaller
905  /// register. For illegal floating point types, this returns the integer type
906  /// to transform to.
907  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
908  return getTypeConversion(Context, VT).second;
909  }
910 
911  /// For types supported by the target, this is an identity function. For
912  /// types that must be expanded (i.e. integer types that are larger than the
913  /// largest integer register or illegal floating point types), this returns
914  /// the largest legal type it will be expanded to.
915  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
916  assert(!VT.isVector());
917  while (true) {
918  switch (getTypeAction(Context, VT)) {
919  case TypeLegal:
920  return VT;
921  case TypeExpandInteger:
922  VT = getTypeToTransformTo(Context, VT);
923  break;
924  default:
925  llvm_unreachable("Type is not legal nor is it to be expanded!");
926  }
927  }
928  }
929 
930  /// Vector types are broken down into some number of legal first class types.
931  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
932  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
933  /// turns into 4 EVT::i32 values with both PPC and X86.
934  ///
935  /// This method returns the number of registers needed, and the VT for each
936  /// register. It also returns the VT and quantity of the intermediate values
937  /// before they are promoted/expanded.
938  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
939  EVT &IntermediateVT,
940  unsigned &NumIntermediates,
941  MVT &RegisterVT) const;
942 
943  /// Certain targets such as MIPS require that some types such as vectors are
944  /// always broken down into scalars in some contexts. This occurs even if the
945  /// vector type is legal.
947  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
948  unsigned &NumIntermediates, MVT &RegisterVT) const {
949  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
950  RegisterVT);
951  }
952 
953  struct IntrinsicInfo {
954  unsigned opc = 0; // target opcode
955  EVT memVT; // memory VT
956 
957  // value representing memory location
959 
960  int offset = 0; // offset off of ptrVal
961  uint64_t size = 0; // the size of the memory location
962  // (taken from memVT if zero)
963  MaybeAlign align = Align(1); // alignment
964 
966  IntrinsicInfo() = default;
967  };
968 
969  /// Given an intrinsic, checks if on the target the intrinsic will need to map
970  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
971  /// true and store the intrinsic information into the IntrinsicInfo that was
972  /// passed to the function.
973  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
974  MachineFunction &,
975  unsigned /*Intrinsic*/) const {
976  return false;
977  }
978 
979  /// Returns true if the target can instruction select the specified FP
980  /// immediate natively. If false, the legalizer will materialize the FP
981  /// immediate as a load from a constant pool.
982  virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
983  bool ForCodeSize = false) const {
984  return false;
985  }
986 
987  /// Targets can use this to indicate that they only support *some*
988  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
989  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
990  /// legal.
991  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
992  return true;
993  }
994 
995  /// Returns true if the operation can trap for the value type.
996  ///
997  /// VT must be a legal type. By default, we optimistically assume most
998  /// operations don't trap except for integer divide and remainder.
999  virtual bool canOpTrap(unsigned Op, EVT VT) const;
1000 
1001  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1002  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1003  /// constant pool entry.
1004  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
1005  EVT /*VT*/) const {
1006  return false;
1007  }
1008 
1009  /// Return how this operation should be treated: either it is legal, needs to
1010  /// be promoted to a larger size, needs to be expanded to some other code
1011  /// sequence, or the target has a custom expander for it.
1012  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
1013  if (VT.isExtended()) return Expand;
1014  // If a target-specific SDNode requires legalization, require the target
1015  // to provide custom legalization for it.
1016  if (Op >= array_lengthof(OpActions[0])) return Custom;
1017  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
1018  }
1019 
1020  /// Custom method defined by each target to indicate if an operation which
1021  /// may require a scale is supported natively by the target.
1022  /// If not, the operation is illegal.
1023  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
1024  unsigned Scale) const {
1025  return false;
1026  }
1027 
1028  /// Some fixed point operations may be natively supported by the target but
1029  /// only for specific scales. This method allows for checking
1030  /// if the width is supported by the target for a given operation that may
1031  /// depend on scale.
1033  unsigned Scale) const {
1034  auto Action = getOperationAction(Op, VT);
1035  if (Action != Legal)
1036  return Action;
1037 
1038  // This operation is supported in this type but may only work on specific
1039  // scales.
1040  bool Supported;
1041  switch (Op) {
1042  default:
1043  llvm_unreachable("Unexpected fixed point operation.");
1044  case ISD::SMULFIX:
1045  case ISD::SMULFIXSAT:
1046  case ISD::UMULFIX:
1047  case ISD::UMULFIXSAT:
1048  case ISD::SDIVFIX:
1049  case ISD::SDIVFIXSAT:
1050  case ISD::UDIVFIX:
1051  case ISD::UDIVFIXSAT:
1052  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
1053  break;
1054  }
1055 
1056  return Supported ? Action : Expand;
1057  }
1058 
1059  // If Op is a strict floating-point operation, return the result
1060  // of getOperationAction for the equivalent non-strict operation.
1062  unsigned EqOpc;
1063  switch (Op) {
1064  default: llvm_unreachable("Unexpected FP pseudo-opcode");
1065 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1066  case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
1067 #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1068  case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
1069 #include "llvm/IR/ConstrainedOps.def"
1070  }
1071 
1072  return getOperationAction(EqOpc, VT);
1073  }
1074 
1075  /// Return true if the specified operation is legal on this target or can be
1076  /// made legal with custom lowering. This is used to help guide high-level
1077  /// lowering decisions.
1078  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
1079  return (VT == MVT::Other || isTypeLegal(VT)) &&
1080  (getOperationAction(Op, VT) == Legal ||
1081  getOperationAction(Op, VT) == Custom);
1082  }
1083 
1084  /// Return true if the specified operation is legal on this target or can be
1085  /// made legal using promotion. This is used to help guide high-level lowering
1086  /// decisions.
1087  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
1088  return (VT == MVT::Other || isTypeLegal(VT)) &&
1089  (getOperationAction(Op, VT) == Legal ||
1090  getOperationAction(Op, VT) == Promote);
1091  }
1092 
1093  /// Return true if the specified operation is legal on this target or can be
1094  /// made legal with custom lowering or using promotion. This is used to help
1095  /// guide high-level lowering decisions.
1096  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
1097  return (VT == MVT::Other || isTypeLegal(VT)) &&
1098  (getOperationAction(Op, VT) == Legal ||
1099  getOperationAction(Op, VT) == Custom ||
1100  getOperationAction(Op, VT) == Promote);
1101  }
1102 
1103  /// Return true if the operation uses custom lowering, regardless of whether
1104  /// the type is legal or not.
1105  bool isOperationCustom(unsigned Op, EVT VT) const {
1106  return getOperationAction(Op, VT) == Custom;
1107  }
1108 
1109  /// Return true if lowering to a jump table is allowed.
1110  virtual bool areJTsAllowed(const Function *Fn) const {
1111  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1112  return false;
1113 
1114  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1115  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
1116  }
1117 
1118  /// Check whether the range [Low,High] fits in a machine word.
1119  bool rangeFitsInWord(const APInt &Low, const APInt &High,
1120  const DataLayout &DL) const {
1121  // FIXME: Using the pointer type doesn't seem ideal.
1122  uint64_t BW = DL.getIndexSizeInBits(0u);
1123  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
1124  return Range <= BW;
1125  }
1126 
1127  /// Return true if lowering to a jump table is suitable for a set of case
1128  /// clusters which may contain \p NumCases cases, \p Range range of values.
1129  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1130  uint64_t Range, ProfileSummaryInfo *PSI,
1131  BlockFrequencyInfo *BFI) const;
1132 
1133  /// Return true if lowering to a bit test is suitable for a set of case
1134  /// clusters which contains \p NumDests unique destinations, \p Low and
1135  /// \p High as its lowest and highest case values, and expects \p NumCmps
1136  /// case value comparisons. Check if the number of destinations, comparison
1137  /// metric, and range are all suitable.
1138  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1139  const APInt &Low, const APInt &High,
1140  const DataLayout &DL) const {
1141  // FIXME: I don't think NumCmps is the correct metric: a single case and a
1142  // range of cases both require only one branch to lower. Just looking at the
1143  // number of clusters and destinations should be enough to decide whether to
1144  // build bit tests.
1145 
1146  // To lower a range with bit tests, the range must fit the bitwidth of a
1147  // machine word.
1148  if (!rangeFitsInWord(Low, High, DL))
1149  return false;
1150 
1151  // Decide whether it's profitable to lower this range with bit tests. Each
1152  // destination requires a bit test and branch, and there is an overall range
1153  // check branch. For a small number of clusters, separate comparisons might
1154  // be cheaper, and for many destinations, splitting the range might be
1155  // better.
1156  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1157  (NumDests == 3 && NumCmps >= 6);
1158  }
1159 
1160  /// Return true if the specified operation is illegal on this target or
1161  /// unlikely to be made legal with custom lowering. This is used to help guide
1162  /// high-level lowering decisions.
1163  bool isOperationExpand(unsigned Op, EVT VT) const {
1164  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1165  }
1166 
1167  /// Return true if the specified operation is legal on this target.
1168  bool isOperationLegal(unsigned Op, EVT VT) const {
1169  return (VT == MVT::Other || isTypeLegal(VT)) &&
1170  getOperationAction(Op, VT) == Legal;
1171  }
1172 
1173  /// Return how this load with extension should be treated: either it is legal,
1174  /// needs to be promoted to a larger size, needs to be expanded to some other
1175  /// code sequence, or the target has a custom expander for it.
1177  EVT MemVT) const {
1178  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1179  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1180  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1181  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1182  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1183  unsigned Shift = 4 * ExtType;
1184  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1185  }
1186 
1187  /// Return true if the specified load with extension is legal on this target.
1188  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1189  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1190  }
1191 
1192  /// Return true if the specified load with extension is legal or custom
1193  /// on this target.
1194  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1195  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1196  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1197  }
1198 
1199  /// Return how this store with truncation should be treated: either it is
1200  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1201  /// other code sequence, or the target has a custom expander for it.
1203  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1204  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1205  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1206  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1207  "Table isn't big enough!");
1208  return TruncStoreActions[ValI][MemI];
1209  }
1210 
1211  /// Return true if the specified store with truncation is legal on this
1212  /// target.
1213  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1214  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1215  }
1216 
1217  /// Return true if the specified store with truncation has solution on this
1218  /// target.
1219  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1220  return isTypeLegal(ValVT) &&
1221  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1222  getTruncStoreAction(ValVT, MemVT) == Custom);
1223  }
1224 
1225  /// Return how the indexed load should be treated: either it is legal, needs
1226  /// to be promoted to a larger size, needs to be expanded to some other code
1227  /// sequence, or the target has a custom expander for it.
1228  LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1229  return getIndexedModeAction(IdxMode, VT, IMAB_Load);
1230  }
1231 
1232  /// Return true if the specified indexed load is legal on this target.
1233  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1234  return VT.isSimple() &&
1235  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1236  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1237  }
1238 
1239  /// Return how the indexed store should be treated: either it is legal, needs
1240  /// to be promoted to a larger size, needs to be expanded to some other code
1241  /// sequence, or the target has a custom expander for it.
1242  LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1243  return getIndexedModeAction(IdxMode, VT, IMAB_Store);
1244  }
1245 
1246  /// Return true if the specified indexed load is legal on this target.
1247  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1248  return VT.isSimple() &&
1249  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1250  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1251  }
1252 
1253  /// Return how the indexed load should be treated: either it is legal, needs
1254  /// to be promoted to a larger size, needs to be expanded to some other code
1255  /// sequence, or the target has a custom expander for it.
1256  LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const {
1257  return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
1258  }
1259 
1260  /// Return true if the specified indexed load is legal on this target.
1261  bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const {
1262  return VT.isSimple() &&
1263  (getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1264  getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1265  }
1266 
1267  /// Return how the indexed store should be treated: either it is legal, needs
1268  /// to be promoted to a larger size, needs to be expanded to some other code
1269  /// sequence, or the target has a custom expander for it.
1270  LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const {
1271  return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
1272  }
1273 
1274  /// Return true if the specified indexed load is legal on this target.
1275  bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const {
1276  return VT.isSimple() &&
1277  (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1278  getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1279  }
1280 
1281  /// Return how the condition code should be treated: either it is legal, needs
1282  /// to be expanded to some other code sequence, or the target has a custom
1283  /// expander for it.
1286  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1287  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1288  "Table isn't big enough!");
1289  // See setCondCodeAction for how this is encoded.
1290  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1291  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1292  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1293  assert(Action != Promote && "Can't promote condition code!");
1294  return Action;
1295  }
1296 
1297  /// Return true if the specified condition code is legal on this target.
1298  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1299  return getCondCodeAction(CC, VT) == Legal;
1300  }
1301 
1302  /// Return true if the specified condition code is legal or custom on this
1303  /// target.
1305  return getCondCodeAction(CC, VT) == Legal ||
1306  getCondCodeAction(CC, VT) == Custom;
1307  }
1308 
1309  /// If the action for this operation is to promote, this method returns the
1310  /// ValueType to promote to.
1311  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1312  assert(getOperationAction(Op, VT) == Promote &&
1313  "This operation isn't promoted!");
1314 
1315  // See if this has an explicit type specified.
1316  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1318  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1319  if (PTTI != PromoteToType.end()) return PTTI->second;
1320 
1321  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1322  "Cannot autopromote this type, add it with AddPromotedToType.");
1323 
1324  MVT NVT = VT;
1325  do {
1326  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1327  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1328  "Didn't find type to promote to!");
1329  } while (!isTypeLegal(NVT) ||
1330  getOperationAction(Op, NVT) == Promote);
1331  return NVT;
1332  }
1333 
1334  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1335  /// operations except for the pointer size. If AllowUnknown is true, this
1336  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1337  /// otherwise it will assert.
1339  bool AllowUnknown = false) const {
1340  // Lower scalar pointers to native pointer types.
1341  if (auto *PTy = dyn_cast<PointerType>(Ty))
1342  return getPointerTy(DL, PTy->getAddressSpace());
1343 
1344  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1345  Type *EltTy = VTy->getElementType();
1346  // Lower vectors of pointers to native pointer types.
1347  if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1348  EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1349  EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1350  }
1351  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1352  VTy->getElementCount());
1353  }
1354 
1355  return EVT::getEVT(Ty, AllowUnknown);
1356  }
1357 
1359  bool AllowUnknown = false) const {
1360  // Lower scalar pointers to native pointer types.
1361  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1362  return getPointerMemTy(DL, PTy->getAddressSpace());
1363  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1364  Type *Elm = VTy->getElementType();
1365  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1366  EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1367  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1368  }
1369  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1370  VTy->getElementCount());
1371  }
1372 
1373  return getValueType(DL, Ty, AllowUnknown);
1374  }
1375 
1376 
1377  /// Return the MVT corresponding to this LLVM type. See getValueType.
1379  bool AllowUnknown = false) const {
1380  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1381  }
1382 
1383  /// Return the desired alignment for ByVal or InAlloca aggregate function
1384  /// arguments in the caller parameter area. This is the actual alignment, not
1385  /// its logarithm.
1386  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1387 
1388  /// Return the type of registers that this ValueType will eventually require.
1390  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1391  return RegisterTypeForVT[VT.SimpleTy];
1392  }
1393 
1394  /// Return the type of registers that this ValueType will eventually require.
1395  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1396  if (VT.isSimple()) {
1397  assert((unsigned)VT.getSimpleVT().SimpleTy <
1398  array_lengthof(RegisterTypeForVT));
1399  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1400  }
1401  if (VT.isVector()) {
1402  EVT VT1;
1403  MVT RegisterVT;
1404  unsigned NumIntermediates;
1405  (void)getVectorTypeBreakdown(Context, VT, VT1,
1406  NumIntermediates, RegisterVT);
1407  return RegisterVT;
1408  }
1409  if (VT.isInteger()) {
1410  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1411  }
1412  llvm_unreachable("Unsupported extended type!");
1413  }
1414 
1415  /// Return the number of registers that this ValueType will eventually
1416  /// require.
1417  ///
1418  /// This is one for any types promoted to live in larger registers, but may be
1419  /// more than one for types (like i64) that are split into pieces. For types
1420  /// like i140, which are first promoted then expanded, it is the number of
1421  /// registers needed to hold all the bits of the original type. For an i140
1422  /// on a 32 bit machine this means 5 registers.
1423  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1424  if (VT.isSimple()) {
1425  assert((unsigned)VT.getSimpleVT().SimpleTy <
1426  array_lengthof(NumRegistersForVT));
1427  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1428  }
1429  if (VT.isVector()) {
1430  EVT VT1;
1431  MVT VT2;
1432  unsigned NumIntermediates;
1433  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1434  }
1435  if (VT.isInteger()) {
1436  unsigned BitWidth = VT.getSizeInBits();
1437  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1438  return (BitWidth + RegWidth - 1) / RegWidth;
1439  }
1440  llvm_unreachable("Unsupported extended type!");
1441  }
1442 
1443  /// Certain combinations of ABIs, Targets and features require that types
1444  /// are legal for some operations and not for other operations.
1445  /// For MIPS all vector types must be passed through the integer register set.
1447  CallingConv::ID CC, EVT VT) const {
1448  return getRegisterType(Context, VT);
1449  }
1450 
1451  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1452  /// this occurs when a vector type is used, as vector are passed through the
1453  /// integer register set.
1454  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1455  CallingConv::ID CC,
1456  EVT VT) const {
1457  return getNumRegisters(Context, VT);
1458  }
1459 
1460  /// Certain targets have context senstive alignment requirements, where one
1461  /// type has the alignment requirement of another type.
1463  DataLayout DL) const {
1464  return Align(DL.getABITypeAlignment(ArgTy));
1465  }
1466 
1467  /// If true, then instruction selection should seek to shrink the FP constant
1468  /// of the specified type to a smaller type in order to save space and / or
1469  /// reduce runtime.
1470  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1471 
1472  /// Return true if it is profitable to reduce a load to a smaller type.
1473  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1475  EVT NewVT) const {
1476  // By default, assume that it is cheaper to extract a subvector from a wide
1477  // vector load rather than creating multiple narrow vector loads.
1478  if (NewVT.isVector() && !Load->hasOneUse())
1479  return false;
1480 
1481  return true;
1482  }
1483 
1484  /// When splitting a value of the specified type into parts, does the Lo
1485  /// or Hi part come first? This usually follows the endianness, except
1486  /// for ppcf128, where the Hi part always comes first.
1487  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1488  return DL.isBigEndian() || VT == MVT::ppcf128;
1489  }
1490 
1491  /// If true, the target has custom DAG combine transformations that it can
1492  /// perform for the specified node.
1494  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1495  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1496  }
1497 
1498  unsigned getGatherAllAliasesMaxDepth() const {
1499  return GatherAllAliasesMaxDepth;
1500  }
1501 
1502  /// Returns the size of the platform's va_list object.
1503  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1504  return getPointerTy(DL).getSizeInBits();
1505  }
1506 
1507  /// Get maximum # of store operations permitted for llvm.memset
1508  ///
1509  /// This function returns the maximum number of store operations permitted
1510  /// to replace a call to llvm.memset. The value is set by the target at the
1511  /// performance threshold for such a replacement. If OptSize is true,
1512  /// return the limit for functions that have OptSize attribute.
1513  unsigned getMaxStoresPerMemset(bool OptSize) const {
1514  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1515  }
1516 
1517  /// Get maximum # of store operations permitted for llvm.memcpy
1518  ///
1519  /// This function returns the maximum number of store operations permitted
1520  /// to replace a call to llvm.memcpy. The value is set by the target at the
1521  /// performance threshold for such a replacement. If OptSize is true,
1522  /// return the limit for functions that have OptSize attribute.
1523  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1524  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1525  }
1526 
1527  /// \brief Get maximum # of store operations to be glued together
1528  ///
1529  /// This function returns the maximum number of store operations permitted
1530  /// to glue together during lowering of llvm.memcpy. The value is set by
1531  // the target at the performance threshold for such a replacement.
1532  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1533  return MaxGluedStoresPerMemcpy;
1534  }
1535 
1536  /// Get maximum # of load operations permitted for memcmp
1537  ///
1538  /// This function returns the maximum number of load operations permitted
1539  /// to replace a call to memcmp. The value is set by the target at the
1540  /// performance threshold for such a replacement. If OptSize is true,
1541  /// return the limit for functions that have OptSize attribute.
1542  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1543  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1544  }
1545 
1546  /// Get maximum # of store operations permitted for llvm.memmove
1547  ///
1548  /// This function returns the maximum number of store operations permitted
1549  /// to replace a call to llvm.memmove. The value is set by the target at the
1550  /// performance threshold for such a replacement. If OptSize is true,
1551  /// return the limit for functions that have OptSize attribute.
1552  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1553  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1554  }
1555 
1556  /// Determine if the target supports unaligned memory accesses.
1557  ///
1558  /// This function returns true if the target allows unaligned memory accesses
1559  /// of the specified type in the given address space. If true, it also returns
1560  /// whether the unaligned memory access is "fast" in the last argument by
1561  /// reference. This is used, for example, in situations where an array
1562  /// copy/move/set is converted to a sequence of store operations. Its use
1563  /// helps to ensure that such replacements don't generate code that causes an
1564  /// alignment error (trap) on the target machine.
1566  EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1568  bool * /*Fast*/ = nullptr) const {
1569  return false;
1570  }
1571 
1572  /// LLT handling variant.
1574  LLT, unsigned AddrSpace = 0, unsigned Align = 1,
1576  bool * /*Fast*/ = nullptr) const {
1577  return false;
1578  }
1579 
1580  /// This function returns true if the memory access is aligned or if the
1581  /// target allows this specific unaligned memory access. If the access is
1582  /// allowed, the optional final parameter returns if the access is also fast
1583  /// (as defined by the target).
1584  bool allowsMemoryAccessForAlignment(
1585  LLVMContext &Context, const DataLayout &DL, EVT VT,
1586  unsigned AddrSpace = 0, unsigned Alignment = 1,
1588  bool *Fast = nullptr) const;
1589 
1590  /// Return true if the memory access of this type is aligned or if the target
1591  /// allows this specific unaligned access for the given MachineMemOperand.
1592  /// If the access is allowed, the optional final parameter returns if the
1593  /// access is also fast (as defined by the target).
1594  bool allowsMemoryAccessForAlignment(LLVMContext &Context,
1595  const DataLayout &DL, EVT VT,
1596  const MachineMemOperand &MMO,
1597  bool *Fast = nullptr) const;
1598 
1599  /// Return true if the target supports a memory access of this type for the
1600  /// given address space and alignment. If the access is allowed, the optional
1601  /// final parameter returns if the access is also fast (as defined by the
1602  /// target).
1603  virtual bool
1604  allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1605  unsigned AddrSpace = 0, unsigned Alignment = 1,
1607  bool *Fast = nullptr) const;
1608 
1609  /// Return true if the target supports a memory access of this type for the
1610  /// given MachineMemOperand. If the access is allowed, the optional
1611  /// final parameter returns if the access is also fast (as defined by the
1612  /// target).
1613  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1614  const MachineMemOperand &MMO,
1615  bool *Fast = nullptr) const;
1616 
1617  /// Returns the target specific optimal type for load and store operations as
1618  /// a result of memset, memcpy, and memmove lowering.
1619  /// It returns EVT::Other if the type should be determined using generic
1620  /// target-independent logic.
1621  virtual EVT
1623  const AttributeList & /*FuncAttributes*/) const {
1624  return MVT::Other;
1625  }
1626 
1627  /// LLT returning variant.
1628  virtual LLT
1630  const AttributeList & /*FuncAttributes*/) const {
1631  return LLT();
1632  }
1633 
1634  /// Returns true if it's safe to use load / store of the specified type to
1635  /// expand memcpy / memset inline.
1636  ///
1637  /// This is mostly true for all types except for some special cases. For
1638  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1639  /// fstpl which also does type conversion. Note the specified type doesn't
1640  /// have to be legal as the hook is used before type legalization.
1641  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1642 
1643  /// Return lower limit for number of blocks in a jump table.
1644  virtual unsigned getMinimumJumpTableEntries() const;
1645 
1646  /// Return lower limit of the density in a jump table.
1647  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1648 
1649  /// Return upper limit for number of entries in a jump table.
1650  /// Zero if no limit.
1651  unsigned getMaximumJumpTableSize() const;
1652 
1653  virtual bool isJumpTableRelative() const;
1654 
1655  /// Return true if a mulh[s|u] node for a specific type is cheaper than
1656  /// a multiply followed by a shift. This is false by default.
1657  virtual bool isMulhCheaperThanMulShift(EVT Type) const { return false; }
1658 
1659  /// If a physical register, this specifies the register that
1660  /// llvm.savestack/llvm.restorestack should save and restore.
1662  return StackPointerRegisterToSaveRestore;
1663  }
1664 
1665  /// If a physical register, this returns the register that receives the
1666  /// exception address on entry to an EH pad.
1667  virtual Register
1668  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1669  return Register();
1670  }
1671 
1672  /// If a physical register, this returns the register that receives the
1673  /// exception typeid on entry to a landing pad.
1674  virtual Register
1675  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1676  return Register();
1677  }
1678 
1679  virtual bool needsFixedCatchObjects() const {
1680  report_fatal_error("Funclet EH is not implemented for this target");
1681  }
1682 
1683  /// Return the minimum stack alignment of an argument.
1685  return MinStackArgumentAlignment;
1686  }
1687 
1688  /// Return the minimum function alignment.
1689  Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
1690 
1691  /// Return the preferred function alignment.
1692  Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
1693 
1694  /// Return the preferred loop alignment.
1695  virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1696  return PrefLoopAlignment;
1697  }
1698 
1699  /// Should loops be aligned even when the function is marked OptSize (but not
1700  /// MinSize).
1701  virtual bool alignLoopsWithOptSize() const {
1702  return false;
1703  }
1704 
1705  /// If the target has a standard location for the stack protector guard,
1706  /// returns the address of that location. Otherwise, returns nullptr.
1707  /// DEPRECATED: please override useLoadStackGuardNode and customize
1708  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1709  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1710 
1711  /// Inserts necessary declarations for SSP (stack protection) purpose.
1712  /// Should be used only when getIRStackGuard returns nullptr.
1713  virtual void insertSSPDeclarations(Module &M) const;
1714 
1715  /// Return the variable that's previously inserted by insertSSPDeclarations,
1716  /// if any, otherwise return nullptr. Should be used only when
1717  /// getIRStackGuard returns nullptr.
1718  virtual Value *getSDagStackGuard(const Module &M) const;
1719 
1720  /// If this function returns true, stack protection checks should XOR the
1721  /// frame pointer (or whichever pointer is used to address locals) into the
1722  /// stack guard value before checking it. getIRStackGuard must return nullptr
1723  /// if this returns true.
1724  virtual bool useStackGuardXorFP() const { return false; }
1725 
1726  /// If the target has a standard stack protection check function that
1727  /// performs validation and error handling, returns the function. Otherwise,
1728  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1729  /// Should be used only when getIRStackGuard returns nullptr.
1730  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1731 
1732 protected:
1733  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1734  bool UseTLS) const;
1735 
1736 public:
1737  /// Returns the target-specific address of the unsafe stack pointer.
1738  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1739 
1740  /// Returns the name of the symbol used to emit stack probes or the empty
1741  /// string if not applicable.
1742  virtual bool hasStackProbeSymbol(MachineFunction &MF) const { return false; }
1743 
1744  virtual bool hasInlineStackProbe(MachineFunction &MF) const { return false; }
1745 
1747  return "";
1748  }
1749 
1750  /// Returns true if a cast between SrcAS and DestAS is a noop.
1751  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1752  return false;
1753  }
1754 
1755  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1756  /// are happy to sink it into basic blocks. A cast may be free, but not
1757  /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1758  virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1759  return isNoopAddrSpaceCast(SrcAS, DestAS);
1760  }
1761 
1762  /// Return true if the pointer arguments to CI should be aligned by aligning
1763  /// the object whose address is being passed. If so then MinSize is set to the
1764  /// minimum size the object must be to be aligned and PrefAlign is set to the
1765  /// preferred alignment.
1766  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1767  unsigned & /*PrefAlign*/) const {
1768  return false;
1769  }
1770 
1771  //===--------------------------------------------------------------------===//
1772  /// \name Helpers for TargetTransformInfo implementations
1773  /// @{
1774 
1775  /// Get the ISD node that corresponds to the Instruction class opcode.
1776  int InstructionOpcodeToISD(unsigned Opcode) const;
1777 
1778  /// Estimate the cost of type-legalization and the legalized type.
1779  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1780  Type *Ty) const;
1781 
1782  /// @}
1783 
1784  //===--------------------------------------------------------------------===//
1785  /// \name Helpers for atomic expansion.
1786  /// @{
1787 
1788  /// Returns the maximum atomic operation size (in bits) supported by
1789  /// the backend. Atomic operations greater than this size (as well
1790  /// as ones that are not naturally aligned), will be expanded by
1791  /// AtomicExpandPass into an __atomic_* library call.
1793  return MaxAtomicSizeInBitsSupported;
1794  }
1795 
1796  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1797  /// the backend supports. Any smaller operations are widened in
1798  /// AtomicExpandPass.
1799  ///
1800  /// Note that *unlike* operations above the maximum size, atomic ops
1801  /// are still natively supported below the minimum; they just
1802  /// require a more complex expansion.
1803  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1804 
1805  /// Whether the target supports unaligned atomic operations.
1806  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1807 
1808  /// Whether AtomicExpandPass should automatically insert fences and reduce
1809  /// ordering for this atomic. This should be true for most architectures with
1810  /// weak memory ordering. Defaults to false.
1811  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1812  return false;
1813  }
1814 
1815  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1816  /// corresponding pointee type. This may entail some non-trivial operations to
1817  /// truncate or reconstruct types that will be illegal in the backend. See
1818  /// ARMISelLowering for an example implementation.
1819  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1820  AtomicOrdering Ord) const {
1821  llvm_unreachable("Load linked unimplemented on this target");
1822  }
1823 
1824  /// Perform a store-conditional operation to Addr. Return the status of the
1825  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1826  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1827  Value *Addr, AtomicOrdering Ord) const {
1828  llvm_unreachable("Store conditional unimplemented on this target");
1829  }
1830 
1831  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1832  /// represents the core LL/SC loop which will be lowered at a late stage by
1833  /// the backend.
1835  AtomicRMWInst *AI,
1836  Value *AlignedAddr, Value *Incr,
1837  Value *Mask, Value *ShiftAmt,
1838  AtomicOrdering Ord) const {
1839  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1840  }
1841 
1842  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1843  /// represents the core LL/SC loop which will be lowered at a late stage by
1844  /// the backend.
1846  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1847  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1848  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1849  }
1850 
1851  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1852  /// It is called by AtomicExpandPass before expanding an
1853  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1854  /// if shouldInsertFencesForAtomic returns true.
1855  ///
1856  /// Inst is the original atomic instruction, prior to other expansions that
1857  /// may be performed.
1858  ///
1859  /// This function should either return a nullptr, or a pointer to an IR-level
1860  /// Instruction*. Even complex fence sequences can be represented by a
1861  /// single Instruction* through an intrinsic to be lowered later.
1862  /// Backends should override this method to produce target-specific intrinsic
1863  /// for their fences.
1864  /// FIXME: Please note that the default implementation here in terms of
1865  /// IR-level fences exists for historical/compatibility reasons and is
1866  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1867  /// consistency. For example, consider the following example:
1868  /// atomic<int> x = y = 0;
1869  /// int r1, r2, r3, r4;
1870  /// Thread 0:
1871  /// x.store(1);
1872  /// Thread 1:
1873  /// y.store(1);
1874  /// Thread 2:
1875  /// r1 = x.load();
1876  /// r2 = y.load();
1877  /// Thread 3:
1878  /// r3 = y.load();
1879  /// r4 = x.load();
1880  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1881  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1882  /// IR-level fences can prevent it.
1883  /// @{
1885  AtomicOrdering Ord) const {
1886  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1887  return Builder.CreateFence(Ord);
1888  else
1889  return nullptr;
1890  }
1891 
1893  Instruction *Inst,
1894  AtomicOrdering Ord) const {
1895  if (isAcquireOrStronger(Ord))
1896  return Builder.CreateFence(Ord);
1897  else
1898  return nullptr;
1899  }
1900  /// @}
1901 
1902  // Emits code that executes when the comparison result in the ll/sc
1903  // expansion of a cmpxchg instruction is such that the store-conditional will
1904  // not execute. This makes it possible to balance out the load-linked with
1905  // a dedicated instruction, if desired.
1906  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1907  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1908  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1909 
1910  /// Returns true if the given (atomic) store should be expanded by the
1911  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1912  virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1913  return false;
1914  }
1915 
1916  /// Returns true if arguments should be sign-extended in lib calls.
1917  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1918  return IsSigned;
1919  }
1920 
1921  /// Returns true if arguments should be extended in lib calls.
1922  virtual bool shouldExtendTypeInLibCall(EVT Type) const {
1923  return true;
1924  }
1925 
1926  /// Returns how the given (atomic) load should be expanded by the
1927  /// IR-level AtomicExpand pass.
1930  }
1931 
1932  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1933  /// AtomicExpand pass.
1934  virtual AtomicExpansionKind
1937  }
1938 
1939  /// Returns how the IR-level AtomicExpand pass should expand the given
1940  /// AtomicRMW, if at all. Default is to never expand.
1942  return RMW->isFloatingPointOperation() ?
1943  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1944  }
1945 
1946  /// On some platforms, an AtomicRMW that never actually modifies the value
1947  /// (such as fetch_add of 0) can be turned into a fence followed by an
1948  /// atomic load. This may sound useless, but it makes it possible for the
1949  /// processor to keep the cacheline shared, dramatically improving
1950  /// performance. And such idempotent RMWs are useful for implementing some
1951  /// kinds of locks, see for example (justification + benchmarks):
1952  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1953  /// This method tries doing that transformation, returning the atomic load if
1954  /// it succeeds, and nullptr otherwise.
1955  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1956  /// another round of expansion.
1957  virtual LoadInst *
1959  return nullptr;
1960  }
1961 
1962  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1963  /// SIGN_EXTEND, or ANY_EXTEND).
1965  return ISD::ZERO_EXTEND;
1966  }
1967 
1968  /// Returns how the platform's atomic compare and swap expects its comparison
1969  /// value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). This is
1970  /// separate from getExtendForAtomicOps, which is concerned with the
1971  /// sign-extension of the instruction's output, whereas here we are concerned
1972  /// with the sign-extension of the input. For targets with compare-and-swap
1973  /// instructions (or sub-word comparisons in their LL/SC loop expansions),
1974  /// the input can be ANY_EXTEND, but the output will still have a specific
1975  /// extension.
1977  return ISD::ANY_EXTEND;
1978  }
1979 
1980  /// @}
1981 
1982  /// Returns true if we should normalize
1983  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1984  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1985  /// that it saves us from materializing N0 and N1 in an integer register.
1986  /// Targets that are able to perform and/or on flags should return false here.
1988  EVT VT) const {
1989  // If a target has multiple condition registers, then it likely has logical
1990  // operations on those registers.
1991  if (hasMultipleConditionRegisters())
1992  return false;
1993  // Only do the transform if the value won't be split into multiple
1994  // registers.
1995  LegalizeTypeAction Action = getTypeAction(Context, VT);
1996  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1997  Action != TypeSplitVector;
1998  }
1999 
2000  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
2001 
2002  /// Return true if a select of constants (select Cond, C1, C2) should be
2003  /// transformed into simple math ops with the condition value. For example:
2004  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
2005  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
2006  return false;
2007  }
2008 
2009  /// Return true if it is profitable to transform an integer
2010  /// multiplication-by-constant into simpler operations like shifts and adds.
2011  /// This may be true if the target does not directly support the
2012  /// multiplication operation for the specified type or the sequence of simpler
2013  /// ops is faster than the multiply.
2014  virtual bool decomposeMulByConstant(LLVMContext &Context,
2015  EVT VT, SDValue C) const {
2016  return false;
2017  }
2018 
2019  /// Return true if it is more correct/profitable to use strict FP_TO_INT
2020  /// conversion operations - canonicalizing the FP source value instead of
2021  /// converting all cases and then selecting based on value.
2022  /// This may be true if the target throws exceptions for out of bounds
2023  /// conversions or has fast FP CMOV.
2024  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
2025  bool IsSigned) const {
2026  return false;
2027  }
2028 
2029  //===--------------------------------------------------------------------===//
2030  // TargetLowering Configuration Methods - These methods should be invoked by
2031  // the derived class constructor to configure this object for the target.
2032  //
2033 protected:
2034  /// Specify how the target extends the result of integer and floating point
2035  /// boolean values from i1 to a wider type. See getBooleanContents.
2037  BooleanContents = Ty;
2038  BooleanFloatContents = Ty;
2039  }
2040 
2041  /// Specify how the target extends the result of integer and floating point
2042  /// boolean values from i1 to a wider type. See getBooleanContents.
2044  BooleanContents = IntTy;
2045  BooleanFloatContents = FloatTy;
2046  }
2047 
2048  /// Specify how the target extends the result of a vector boolean value from a
2049  /// vector of i1 to a wider type. See getBooleanContents.
2051  BooleanVectorContents = Ty;
2052  }
2053 
2054  /// Specify the target scheduling preference.
2056  SchedPreferenceInfo = Pref;
2057  }
2058 
2059  /// Indicate the minimum number of blocks to generate jump tables.
2060  void setMinimumJumpTableEntries(unsigned Val);
2061 
2062  /// Indicate the maximum number of entries in jump tables.
2063  /// Set to zero to generate unlimited jump tables.
2064  void setMaximumJumpTableSize(unsigned);
2065 
2066  /// If set to a physical register, this specifies the register that
2067  /// llvm.savestack/llvm.restorestack should save and restore.
2069  StackPointerRegisterToSaveRestore = R;
2070  }
2071 
2072  /// Tells the code generator that the target has multiple (allocatable)
2073  /// condition registers that can be used to store the results of comparisons
2074  /// for use by selects and conditional branches. With multiple condition
2075  /// registers, the code generator will not aggressively sink comparisons into
2076  /// the blocks of their users.
2077  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
2078  HasMultipleConditionRegisters = hasManyRegs;
2079  }
2080 
2081  /// Tells the code generator that the target has BitExtract instructions.
2082  /// The code generator will aggressively sink "shift"s into the blocks of
2083  /// their users if the users will generate "and" instructions which can be
2084  /// combined with "shift" to BitExtract instructions.
2085  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
2086  HasExtractBitsInsn = hasExtractInsn;
2087  }
2088 
2089  /// Tells the code generator not to expand logic operations on comparison
2090  /// predicates into separate sequences that increase the amount of flow
2091  /// control.
2092  void setJumpIsExpensive(bool isExpensive = true);
2093 
2094  /// Tells the code generator which bitwidths to bypass.
2095  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
2096  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2097  }
2098 
2099  /// Add the specified register class as an available regclass for the
2100  /// specified value type. This indicates the selector can handle values of
2101  /// that class natively.
2103  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
2104  RegClassForVT[VT.SimpleTy] = RC;
2105  }
2106 
2107  /// Return the largest legal super-reg register class of the register class
2108  /// for the specified type and its associated "cost".
2109  virtual std::pair<const TargetRegisterClass *, uint8_t>
2110  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
2111 
2112  /// Once all of the register classes are added, this allows us to compute
2113  /// derived properties we expose.
2114  void computeRegisterProperties(const TargetRegisterInfo *TRI);
2115 
2116  /// Indicate that the specified operation does not work with the specified
2117  /// type and indicate what to do about it. Note that VT may refer to either
2118  /// the type of a result or that of an operand of Op.
2119  void setOperationAction(unsigned Op, MVT VT,
2120  LegalizeAction Action) {
2121  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
2122  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
2123  }
2124 
2125  /// Indicate that the specified load with extension does not work with the
2126  /// specified type and indicate what to do about it.
2127  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
2128  LegalizeAction Action) {
2129  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
2130  MemVT.isValid() && "Table isn't big enough!");
2131  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2132  unsigned Shift = 4 * ExtType;
2133  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
2134  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
2135  }
2136 
2137  /// Indicate that the specified truncating store does not work with the
2138  /// specified type and indicate what to do about it.
2139  void setTruncStoreAction(MVT ValVT, MVT MemVT,
2140  LegalizeAction Action) {
2141  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
2142  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
2143  }
2144 
2145  /// Indicate that the specified indexed load does or does not work with the
2146  /// specified type and indicate what to do abort it.
2147  ///
2148  /// NOTE: All indexed mode loads are initialized to Expand in
2149  /// TargetLowering.cpp
2150  void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) {
2151  setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
2152  }
2153 
2154  /// Indicate that the specified indexed store does or does not work with the
2155  /// specified type and indicate what to do about it.
2156  ///
2157  /// NOTE: All indexed mode stores are initialized to Expand in
2158  /// TargetLowering.cpp
2159  void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) {
2160  setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
2161  }
2162 
2163  /// Indicate that the specified indexed masked load does or does not work with
2164  /// the specified type and indicate what to do about it.
2165  ///
2166  /// NOTE: All indexed mode masked loads are initialized to Expand in
2167  /// TargetLowering.cpp
2168  void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT,
2169  LegalizeAction Action) {
2170  setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
2171  }
2172 
2173  /// Indicate that the specified indexed masked store does or does not work
2174  /// with the specified type and indicate what to do about it.
2175  ///
2176  /// NOTE: All indexed mode masked stores are initialized to Expand in
2177  /// TargetLowering.cpp
2178  void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT,
2179  LegalizeAction Action) {
2180  setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
2181  }
2182 
2183  /// Indicate that the specified condition code is or isn't supported on the
2184  /// target and indicate what to do about it.
2186  LegalizeAction Action) {
2187  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
2188  "Table isn't big enough!");
2189  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2190  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2191  /// value and the upper 29 bits index into the second dimension of the array
2192  /// to select what 32-bit value to use.
2193  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2194  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2195  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2196  }
2197 
2198  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2199  /// to trying a larger integer/fp until it can find one that works. If that
2200  /// default is insufficient, this method can be used by the target to override
2201  /// the default.
2202  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2203  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2204  }
2205 
2206  /// Convenience method to set an operation to Promote and specify the type
2207  /// in a single call.
2208  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2209  setOperationAction(Opc, OrigVT, Promote);
2210  AddPromotedToType(Opc, OrigVT, DestVT);
2211  }
2212 
2213  /// Targets should invoke this method for each target independent node that
2214  /// they want to provide a custom DAG combiner for by implementing the
2215  /// PerformDAGCombine virtual method.
2217  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2218  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2219  }
2220 
2221  /// Set the target's minimum function alignment.
2222  void setMinFunctionAlignment(Align Alignment) {
2223  MinFunctionAlignment = Alignment;
2224  }
2225 
2226  /// Set the target's preferred function alignment. This should be set if
2227  /// there is a performance benefit to higher-than-minimum alignment
2229  PrefFunctionAlignment = Alignment;
2230  }
2231 
2232  /// Set the target's preferred loop alignment. Default alignment is one, it
2233  /// means the target does not care about loop alignment. The target may also
2234  /// override getPrefLoopAlignment to provide per-loop values.
2235  void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }
2236 
2237  /// Set the minimum stack alignment of an argument.
2239  MinStackArgumentAlignment = Alignment;
2240  }
2241 
2242  /// Set the maximum atomic operation size supported by the
2243  /// backend. Atomic operations greater than this size (as well as
2244  /// ones that are not naturally aligned), will be expanded by
2245  /// AtomicExpandPass into an __atomic_* library call.
2246  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2247  MaxAtomicSizeInBitsSupported = SizeInBits;
2248  }
2249 
2250  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2251  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2252  MinCmpXchgSizeInBits = SizeInBits;
2253  }
2254 
2255  /// Sets whether unaligned atomic operations are supported.
2256  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2257  SupportsUnalignedAtomics = UnalignedSupported;
2258  }
2259 
2260 public:
2261  //===--------------------------------------------------------------------===//
2262  // Addressing mode description hooks (used by LSR etc).
2263  //
2264 
2265  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2266  /// instructions reading the address. This allows as much computation as
2267  /// possible to be done in the address mode for that operand. This hook lets
2268  /// targets also pass back when this should be done on intrinsics which
2269  /// load/store.
2270  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2271  SmallVectorImpl<Value*> &/*Ops*/,
2272  Type *&/*AccessTy*/) const {
2273  return false;
2274  }
2275 
2276  /// This represents an addressing mode of:
2277  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2278  /// If BaseGV is null, there is no BaseGV.
2279  /// If BaseOffs is zero, there is no base offset.
2280  /// If HasBaseReg is false, there is no base register.
2281  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2282  /// no scale.
2283  struct AddrMode {
2284  GlobalValue *BaseGV = nullptr;
2285  int64_t BaseOffs = 0;
2286  bool HasBaseReg = false;
2287  int64_t Scale = 0;
2288  AddrMode() = default;
2289  };
2290 
2291  /// Return true if the addressing mode represented by AM is legal for this
2292  /// target, for a load/store of the specified type.
2293  ///
2294  /// The type may be VoidTy, in which case only return true if the addressing
2295  /// mode is legal for a load/store of any legal type. TODO: Handle
2296  /// pre/postinc as well.
2297  ///
2298  /// If the address space cannot be determined, it will be -1.
2299  ///
2300  /// TODO: Remove default argument
2301  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2302  Type *Ty, unsigned AddrSpace,
2303  Instruction *I = nullptr) const;
2304 
2305  /// Return the cost of the scaling factor used in the addressing mode
2306  /// represented by AM for this target, for a load/store of the specified type.
2307  ///
2308  /// If the AM is supported, the return value must be >= 0.
2309  /// If the AM is not supported, it returns a negative value.
2310  /// TODO: Handle pre/postinc as well.
2311  /// TODO: Remove default argument
2312  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2313  Type *Ty, unsigned AS = 0) const {
2314  // Default: assume that any scaling factor used in a legal AM is free.
2315  if (isLegalAddressingMode(DL, AM, Ty, AS))
2316  return 0;
2317  return -1;
2318  }
2319 
2320  /// Return true if the specified immediate is legal icmp immediate, that is
2321  /// the target has icmp instructions which can compare a register against the
2322  /// immediate without having to materialize the immediate into a register.
2323  virtual bool isLegalICmpImmediate(int64_t) const {
2324  return true;
2325  }
2326 
2327  /// Return true if the specified immediate is legal add immediate, that is the
2328  /// target has add instructions which can add a register with the immediate
2329  /// without having to materialize the immediate into a register.
2330  virtual bool isLegalAddImmediate(int64_t) const {
2331  return true;
2332  }
2333 
2334  /// Return true if the specified immediate is legal for the value input of a
2335  /// store instruction.
2336  virtual bool isLegalStoreImmediate(int64_t Value) const {
2337  // Default implementation assumes that at least 0 works since it is likely
2338  // that a zero register exists or a zero immediate is allowed.
2339  return Value == 0;
2340  }
2341 
2342  /// Return true if it's significantly cheaper to shift a vector by a uniform
2343  /// scalar than by an amount which will vary across each lane. On x86 before
2344  /// AVX2 for example, there is a "psllw" instruction for the former case, but
2345  /// no simple instruction for a general "a << b" operation on vectors.
2346  /// This should also apply to lowering for vector funnel shifts (rotates).
2347  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2348  return false;
2349  }
2350 
2351  /// Given a shuffle vector SVI representing a vector splat, return a new
2352  /// scalar type of size equal to SVI's scalar type if the new type is more
2353  /// profitable. Returns nullptr otherwise. For example under MVE float splats
2354  /// are converted to integer to prevent the need to move from SPR to GPR
2355  /// registers.
2357  return nullptr;
2358  }
2359 
2360  /// Returns true if the opcode is a commutative binary operation.
2361  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2362  // FIXME: This should get its info from the td file.
2363  switch (Opcode) {
2364  case ISD::ADD:
2365  case ISD::SMIN:
2366  case ISD::SMAX:
2367  case ISD::UMIN:
2368  case ISD::UMAX:
2369  case ISD::MUL:
2370  case ISD::MULHU:
2371  case ISD::MULHS:
2372  case ISD::SMUL_LOHI:
2373  case ISD::UMUL_LOHI:
2374  case ISD::FADD:
2375  case ISD::FMUL:
2376  case ISD::AND:
2377  case ISD::OR:
2378  case ISD::XOR:
2379  case ISD::SADDO:
2380  case ISD::UADDO:
2381  case ISD::ADDC:
2382  case ISD::ADDE:
2383  case ISD::SADDSAT:
2384  case ISD::UADDSAT:
2385  case ISD::FMINNUM:
2386  case ISD::FMAXNUM:
2387  case ISD::FMINNUM_IEEE:
2388  case ISD::FMAXNUM_IEEE:
2389  case ISD::FMINIMUM:
2390  case ISD::FMAXIMUM:
2391  return true;
2392  default: return false;
2393  }
2394  }
2395 
2396  /// Return true if the node is a math/logic binary operator.
2397  virtual bool isBinOp(unsigned Opcode) const {
2398  // A commutative binop must be a binop.
2399  if (isCommutativeBinOp(Opcode))
2400  return true;
2401  // These are non-commutative binops.
2402  switch (Opcode) {
2403  case ISD::SUB:
2404  case ISD::SHL:
2405  case ISD::SRL:
2406  case ISD::SRA:
2407  case ISD::SDIV:
2408  case ISD::UDIV:
2409  case ISD::SREM:
2410  case ISD::UREM:
2411  case ISD::FSUB:
2412  case ISD::FDIV:
2413  case ISD::FREM:
2414  return true;
2415  default:
2416  return false;
2417  }
2418  }
2419 
2420  /// Return true if it's free to truncate a value of type FromTy to type
2421  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2422  /// by referencing its sub-register AX.
2423  /// Targets must return false when FromTy <= ToTy.
2424  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2425  return false;
2426  }
2427 
2428  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2429  /// whether a call is in tail position. Typically this means that both results
2430  /// would be assigned to the same register or stack slot, but it could mean
2431  /// the target performs adequate checks of its own before proceeding with the
2432  /// tail call. Targets must return false when FromTy <= ToTy.
2433  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2434  return false;
2435  }
2436 
2437  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2438  return false;
2439  }
2440 
2441  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2442 
2443  /// Return true if the extension represented by \p I is free.
2444  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2445  /// this method can use the context provided by \p I to decide
2446  /// whether or not \p I is free.
2447  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2448  /// In other words, if is[Z|FP]Free returns true, then this method
2449  /// returns true as well. The converse is not true.
2450  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2451  /// \pre \p I must be a sign, zero, or fp extension.
2452  bool isExtFree(const Instruction *I) const {
2453  switch (I->getOpcode()) {
2454  case Instruction::FPExt:
2455  if (isFPExtFree(EVT::getEVT(I->getType()),
2456  EVT::getEVT(I->getOperand(0)->getType())))
2457  return true;
2458  break;
2459  case Instruction::ZExt:
2460  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2461  return true;
2462  break;
2463  case Instruction::SExt:
2464  break;
2465  default:
2466  llvm_unreachable("Instruction is not an extension");
2467  }
2468  return isExtFreeImpl(I);
2469  }
2470 
2471  /// Return true if \p Load and \p Ext can form an ExtLoad.
2472  /// For example, in AArch64
2473  /// %L = load i8, i8* %ptr
2474  /// %E = zext i8 %L to i32
2475  /// can be lowered into one load instruction
2476  /// ldrb w0, [x0]
2477  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2478  const DataLayout &DL) const {
2479  EVT VT = getValueType(DL, Ext->getType());
2480  EVT LoadVT = getValueType(DL, Load->getType());
2481 
2482  // If the load has other users and the truncate is not free, the ext
2483  // probably isn't free.
2484  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2485  !isTruncateFree(Ext->getType(), Load->getType()))
2486  return false;
2487 
2488  // Check whether the target supports casts folded into loads.
2489  unsigned LType;
2490  if (isa<ZExtInst>(Ext))
2491  LType = ISD::ZEXTLOAD;
2492  else {
2493  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2494  LType = ISD::SEXTLOAD;
2495  }
2496 
2497  return isLoadExtLegal(LType, VT, LoadVT);
2498  }
2499 
2500  /// Return true if any actual instruction that defines a value of type FromTy
2501  /// implicitly zero-extends the value to ToTy in the result register.
2502  ///
2503  /// The function should return true when it is likely that the truncate can
2504  /// be freely folded with an instruction defining a value of FromTy. If
2505  /// the defining instruction is unknown (because you're looking at a
2506  /// function argument, PHI, etc.) then the target may require an
2507  /// explicit truncate, which is not necessarily free, but this function
2508  /// does not deal with those cases.
2509  /// Targets must return false when FromTy >= ToTy.
2510  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2511  return false;
2512  }
2513 
2514  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2515  return false;
2516  }
2517 
2518  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2519  /// zero-extension.
2520  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2521  return false;
2522  }
2523 
2524  /// Return true if sinking I's operands to the same basic block as I is
2525  /// profitable, e.g. because the operands can be folded into a target
2526  /// instruction during instruction selection. After calling the function
2527  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2528  /// come first).
2530  SmallVectorImpl<Use *> &Ops) const {
2531  return false;
2532  }
2533 
2534  /// Return true if the target supplies and combines to a paired load
2535  /// two loaded values of type LoadedType next to each other in memory.
2536  /// RequiredAlignment gives the minimal alignment constraints that must be met
2537  /// to be able to select this paired load.
2538  ///
2539  /// This information is *not* used to generate actual paired loads, but it is
2540  /// used to generate a sequence of loads that is easier to combine into a
2541  /// paired load.
2542  /// For instance, something like this:
2543  /// a = load i64* addr
2544  /// b = trunc i64 a to i32
2545  /// c = lshr i64 a, 32
2546  /// d = trunc i64 c to i32
2547  /// will be optimized into:
2548  /// b = load i32* addr1
2549  /// d = load i32* addr2
2550  /// Where addr1 = addr2 +/- sizeof(i32).
2551  ///
2552  /// In other words, unless the target performs a post-isel load combining,
2553  /// this information should not be provided because it will generate more
2554  /// loads.
2555  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2556  unsigned & /*RequiredAlignment*/) const {
2557  return false;
2558  }
2559 
2560  /// Return true if the target has a vector blend instruction.
2561  virtual bool hasVectorBlend() const { return false; }
2562 
2563  /// Get the maximum supported factor for interleaved memory accesses.
2564  /// Default to be the minimum interleave factor: 2.
2565  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2566 
2567  /// Lower an interleaved load to target specific intrinsics. Return
2568  /// true on success.
2569  ///
2570  /// \p LI is the vector load instruction.
2571  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2572  /// \p Indices is the corresponding indices for each shufflevector.
2573  /// \p Factor is the interleave factor.
2574  virtual bool lowerInterleavedLoad(LoadInst *LI,
2576  ArrayRef<unsigned> Indices,
2577  unsigned Factor) const {
2578  return false;
2579  }
2580 
2581  /// Lower an interleaved store to target specific intrinsics. Return
2582  /// true on success.
2583  ///
2584  /// \p SI is the vector store instruction.
2585  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2586  /// \p Factor is the interleave factor.
2588  unsigned Factor) const {
2589  return false;
2590  }
2591 
2592  /// Return true if zero-extending the specific node Val to type VT2 is free
2593  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2594  /// because it's folded such as X86 zero-extending loads).
2595  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2596  return isZExtFree(Val.getValueType(), VT2);
2597  }
2598 
2599  /// Return true if an fpext operation is free (for instance, because
2600  /// single-precision floating-point numbers are implicitly extended to
2601  /// double-precision).
2602  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2603  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2604  "invalid fpext types");
2605  return false;
2606  }
2607 
2608  /// Return true if an fpext operation input to an \p Opcode operation is free
2609  /// (for instance, because half-precision floating-point numbers are
2610  /// implicitly extended to float-precision) for an FMA instruction.
2611  virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
2612  EVT DestVT, EVT SrcVT) const {
2613  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2614  "invalid fpext types");
2615  return isFPExtFree(DestVT, SrcVT);
2616  }
2617 
2618  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2619  /// extend node) is profitable.
2620  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2621 
2622  /// Return true if an fneg operation is free to the point where it is never
2623  /// worthwhile to replace it with a bitwise operation.
2624  virtual bool isFNegFree(EVT VT) const {
2625  assert(VT.isFloatingPoint());
2626  return false;
2627  }
2628 
2629  /// Return true if an fabs operation is free to the point where it is never
2630  /// worthwhile to replace it with a bitwise operation.
2631  virtual bool isFAbsFree(EVT VT) const {
2632  assert(VT.isFloatingPoint());
2633  return false;
2634  }
2635 
2636  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2637  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2638  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2639  ///
2640  /// NOTE: This may be called before legalization on types for which FMAs are
2641  /// not legal, but should return true if those types will eventually legalize
2642  /// to types that support FMAs. After legalization, it will only be called on
2643  /// types that support FMAs (via Legal or Custom actions)
2645  EVT) const {
2646  return false;
2647  }
2648 
2649  /// IR version
2650  virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const {
2651  return false;
2652  }
2653 
2654  /// Returns true if be combined with to form an ISD::FMAD. \p N may be an
2655  /// ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an
2656  /// fadd/fsub.
2657  virtual bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const {
2658  assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB ||
2659  N->getOpcode() == ISD::FMUL) &&
2660  "unexpected node in FMAD forming combine");
2661  return isOperationLegal(ISD::FMAD, N->getValueType(0));
2662  }
2663 
2664  /// Return true if it's profitable to narrow operations of type VT1 to
2665  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2666  /// i32 to i16.
2667  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2668  return false;
2669  }
2670 
2671  /// Return true if it is beneficial to convert a load of a constant to
2672  /// just the constant itself.
2673  /// On some targets it might be more efficient to use a combination of
2674  /// arithmetic instructions to materialize the constant instead of loading it
2675  /// from a constant pool.
2676  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2677  Type *Ty) const {
2678  return false;
2679  }
2680 
2681  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2682  /// from this source type with this index. This is needed because
2683  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2684  /// the first element, and only the target knows which lowering is cheap.
2685  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2686  unsigned Index) const {
2687  return false;
2688  }
2689 
2690  /// Try to convert an extract element of a vector binary operation into an
2691  /// extract element followed by a scalar operation.
2692  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2693  return false;
2694  }
2695 
2696  /// Return true if extraction of a scalar element from the given vector type
2697  /// at the given index is cheap. For example, if scalar operations occur on
2698  /// the same register file as vector operations, then an extract element may
2699  /// be a sub-register rename rather than an actual instruction.
2700  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2701  return false;
2702  }
2703 
2704  /// Try to convert math with an overflow comparison into the corresponding DAG
2705  /// node operation. Targets may want to override this independently of whether
2706  /// the operation is legal/custom for the given type because it may obscure
2707  /// matching of other patterns.
2708  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
2709  bool MathUsed) const {
2710  // TODO: The default logic is inherited from code in CodeGenPrepare.
2711  // The opcode should not make a difference by default?
2712  if (Opcode != ISD::UADDO)
2713  return false;
2714 
2715  // Allow the transform as long as we have an integer type that is not
2716  // obviously illegal and unsupported and if the math result is used
2717  // besides the overflow check. On some targets (e.g. SPARC), it is
2718  // not profitable to form on overflow op if the math result has no
2719  // concrete users.
2720  if (VT.isVector())
2721  return false;
2722  return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT));
2723  }
2724 
2725  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2726  // even if the vector itself has multiple uses.
2727  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2728  return false;
2729  }
2730 
2731  // Return true if CodeGenPrepare should consider splitting large offset of a
2732  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2733  // same blocks of its users.
2734  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2735 
2736  /// Return true if creating a shift of the type by the given
2737  /// amount is not profitable.
2738  virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const {
2739  return false;
2740  }
2741 
2742  //===--------------------------------------------------------------------===//
2743  // Runtime Library hooks
2744  //
2745 
2746  /// Rename the default libcall routine name for the specified libcall.
2747  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2748  LibcallRoutineNames[Call] = Name;
2749  }
2750 
2751  /// Get the libcall routine name for the specified libcall.
2752  const char *getLibcallName(RTLIB::Libcall Call) const {
2753  return LibcallRoutineNames[Call];
2754  }
2755 
2756  /// Override the default CondCode to be used to test the result of the
2757  /// comparison libcall against zero.
2759  CmpLibcallCCs[Call] = CC;
2760  }
2761 
2762  /// Get the CondCode that's to be used to test the result of the comparison
2763  /// libcall against zero.
2765  return CmpLibcallCCs[Call];
2766  }
2767 
2768  /// Set the CallingConv that should be used for the specified libcall.
2770  LibcallCallingConvs[Call] = CC;
2771  }
2772 
2773  /// Get the CallingConv that should be used for the specified libcall.
2775  return LibcallCallingConvs[Call];
2776  }
2777 
2778  /// Execute target specific actions to finalize target lowering.
2779  /// This is used to set extra flags in MachineFrameInformation and freezing
2780  /// the set of reserved registers.
2781  /// The default implementation just freezes the set of reserved registers.
2782  virtual void finalizeLowering(MachineFunction &MF) const;
2783 
2784  //===----------------------------------------------------------------------===//
2785  // GlobalISel Hooks
2786  //===----------------------------------------------------------------------===//
2787  /// Check whether or not \p MI needs to be moved close to its uses.
2788  virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const;
2789 
2790 
2791 private:
2792  const TargetMachine &TM;
2793 
2794  /// Tells the code generator that the target has multiple (allocatable)
2795  /// condition registers that can be used to store the results of comparisons
2796  /// for use by selects and conditional branches. With multiple condition
2797  /// registers, the code generator will not aggressively sink comparisons into
2798  /// the blocks of their users.
2799  bool HasMultipleConditionRegisters;
2800 
2801  /// Tells the code generator that the target has BitExtract instructions.
2802  /// The code generator will aggressively sink "shift"s into the blocks of
2803  /// their users if the users will generate "and" instructions which can be
2804  /// combined with "shift" to BitExtract instructions.
2805  bool HasExtractBitsInsn;
2806 
2807  /// Tells the code generator to bypass slow divide or remainder
2808  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2809  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2810  /// div/rem when the operands are positive and less than 256.
2811  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2812 
2813  /// Tells the code generator that it shouldn't generate extra flow control
2814  /// instructions and should attempt to combine flow control instructions via
2815  /// predication.
2816  bool JumpIsExpensive;
2817 
2818  /// Information about the contents of the high-bits in boolean values held in
2819  /// a type wider than i1. See getBooleanContents.
2820  BooleanContent BooleanContents;
2821 
2822  /// Information about the contents of the high-bits in boolean values held in
2823  /// a type wider than i1. See getBooleanContents.
2824  BooleanContent BooleanFloatContents;
2825 
2826  /// Information about the contents of the high-bits in boolean vector values
2827  /// when the element type is wider than i1. See getBooleanContents.
2828  BooleanContent BooleanVectorContents;
2829 
2830  /// The target scheduling preference: shortest possible total cycles or lowest
2831  /// register usage.
2832  Sched::Preference SchedPreferenceInfo;
2833 
2834  /// The minimum alignment that any argument on the stack needs to have.
2835  Align MinStackArgumentAlignment;
2836 
2837  /// The minimum function alignment (used when optimizing for size, and to
2838  /// prevent explicitly provided alignment from leading to incorrect code).
2839  Align MinFunctionAlignment;
2840 
2841  /// The preferred function alignment (used when alignment unspecified and
2842  /// optimizing for speed).
2843  Align PrefFunctionAlignment;
2844 
2845  /// The preferred loop alignment (in log2 bot in bytes).
2846  Align PrefLoopAlignment;
2847 
2848  /// Size in bits of the maximum atomics size the backend supports.
2849  /// Accesses larger than this will be expanded by AtomicExpandPass.
2850  unsigned MaxAtomicSizeInBitsSupported;
2851 
2852  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2853  /// backend supports.
2854  unsigned MinCmpXchgSizeInBits;
2855 
2856  /// This indicates if the target supports unaligned atomic operations.
2857  bool SupportsUnalignedAtomics;
2858 
2859  /// If set to a physical register, this specifies the register that
2860  /// llvm.savestack/llvm.restorestack should save and restore.
2861  Register StackPointerRegisterToSaveRestore;
2862 
2863  /// This indicates the default register class to use for each ValueType the
2864  /// target supports natively.
2865  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2866  uint16_t NumRegistersForVT[MVT::LAST_VALUETYPE];
2867  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2868 
2869  /// This indicates the "representative" register class to use for each
2870  /// ValueType the target supports natively. This information is used by the
2871  /// scheduler to track register pressure. By default, the representative
2872  /// register class is the largest legal super-reg register class of the
2873  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2874  /// representative class would be GR32.
2875  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2876 
2877  /// This indicates the "cost" of the "representative" register class for each
2878  /// ValueType. The cost is used by the scheduler to approximate register
2879  /// pressure.
2880  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2881 
2882  /// For any value types we are promoting or expanding, this contains the value
2883  /// type that we are changing to. For Expanded types, this contains one step
2884  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2885  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2886  /// the same type (e.g. i32 -> i32).
2887  MVT TransformToType[MVT::LAST_VALUETYPE];
2888 
2889  /// For each operation and each value type, keep a LegalizeAction that
2890  /// indicates how instruction selection should deal with the operation. Most
2891  /// operations are Legal (aka, supported natively by the target), but
2892  /// operations that are not should be described. Note that operations on
2893  /// non-legal value types are not described here.
2895 
2896  /// For each load extension type and each value type, keep a LegalizeAction
2897  /// that indicates how instruction selection should deal with a load of a
2898  /// specific value type and extension type. Uses 4-bits to store the action
2899  /// for each of the 4 load ext types.
2901 
2902  /// For each value type pair keep a LegalizeAction that indicates whether a
2903  /// truncating store of a specific value type and truncating type is legal.
2905 
2906  /// For each indexed mode and each value type, keep a quad of LegalizeAction
2907  /// that indicates how instruction selection should deal with the load /
2908  /// store / maskedload / maskedstore.
2909  ///
2910  /// The first dimension is the value_type for the reference. The second
2911  /// dimension represents the various modes for load store.
2913 
2914  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2915  /// indicates how instruction selection should deal with the condition code.
2916  ///
2917  /// Because each CC action takes up 4 bits, we need to have the array size be
2918  /// large enough to fit all of the value types. This can be done by rounding
2919  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2920  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2921 
2922  ValueTypeActionImpl ValueTypeActions;
2923 
2924 private:
2925  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2926 
2927  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2928  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2929  /// array.
2930  unsigned char
2931  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2932 
2933  /// For operations that must be promoted to a specific type, this holds the
2934  /// destination type. This map should be sparse, so don't hold it as an
2935  /// array.
2936  ///
2937  /// Targets add entries to this map with AddPromotedToType(..), clients access
2938  /// this with getTypeToPromoteTo(..).
2939  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2940  PromoteToType;
2941 
2942  /// Stores the name each libcall.
2943  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2944 
2945  /// The ISD::CondCode that should be used to test the result of each of the
2946  /// comparison libcall against zero.
2947  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2948 
2949  /// Stores the CallingConv that should be used for each libcall.
2950  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2951 
2952  /// Set default libcall names and calling conventions.
2953  void InitLibcalls(const Triple &TT);
2954 
2955  /// The bits of IndexedModeActions used to store the legalisation actions
2956  /// We store the data as | ML | MS | L | S | each taking 4 bits.
2957  enum IndexedModeActionsBits {
2958  IMAB_Store = 0,
2959  IMAB_Load = 4,
2960  IMAB_MaskedStore = 8,
2961  IMAB_MaskedLoad = 12
2962  };
2963 
2964  void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift,
2965  LegalizeAction Action) {
2966  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2967  (unsigned)Action < 0xf && "Table isn't big enough!");
2968  unsigned Ty = (unsigned)VT.SimpleTy;
2969  IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift);
2970  IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift;
2971  }
2972 
2973  LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT,
2974  unsigned Shift) const {
2975  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
2976  "Table isn't big enough!");
2977  unsigned Ty = (unsigned)VT.SimpleTy;
2978  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf);
2979  }
2980 
2981 protected:
2982  /// Return true if the extension represented by \p I is free.
2983  /// \pre \p I is a sign, zero, or fp extension and
2984  /// is[Z|FP]ExtFree of the related types is not true.
2985  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2986 
2987  /// Depth that GatherAllAliases should should continue looking for chain
2988  /// dependencies when trying to find a more preferable chain. As an
2989  /// approximation, this should be more than the number of consecutive stores
2990  /// expected to be merged.
2992 
2993  /// \brief Specify maximum number of store instructions per memset call.
2994  ///
2995  /// When lowering \@llvm.memset this field specifies the maximum number of
2996  /// store operations that may be substituted for the call to memset. Targets
2997  /// must set this value based on the cost threshold for that target. Targets
2998  /// should assume that the memset will be done using as many of the largest
2999  /// store operations first, followed by smaller ones, if necessary, per
3000  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
3001  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
3002  /// store. This only applies to setting a constant array of a constant size.
3004  /// Likewise for functions with the OptSize attribute.
3006 
3007  /// \brief Specify maximum number of store instructions per memcpy call.
3008  ///
3009  /// When lowering \@llvm.memcpy this field specifies the maximum number of
3010  /// store operations that may be substituted for a call to memcpy. Targets
3011  /// must set this value based on the cost threshold for that target. Targets
3012  /// should assume that the memcpy will be done using as many of the largest
3013  /// store operations first, followed by smaller ones, if necessary, per
3014  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
3015  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
3016  /// and one 1-byte store. This only applies to copying a constant array of
3017  /// constant size.
3019  /// Likewise for functions with the OptSize attribute.
3021  /// \brief Specify max number of store instructions to glue in inlined memcpy.
3022  ///
3023  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
3024  /// of store instructions to keep together. This helps in pairing and
3025  // vectorization later on.
3026  unsigned MaxGluedStoresPerMemcpy = 0;
3027 
3028  /// \brief Specify maximum number of load instructions per memcmp call.
3029  ///
3030  /// When lowering \@llvm.memcmp this field specifies the maximum number of
3031  /// pairs of load operations that may be substituted for a call to memcmp.
3032  /// Targets must set this value based on the cost threshold for that target.
3033  /// Targets should assume that the memcmp will be done using as many of the
3034  /// largest load operations first, followed by smaller ones, if necessary, per
3035  /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
3036  /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
3037  /// and one 1-byte load. This only applies to copying a constant array of
3038  /// constant size.
3040  /// Likewise for functions with the OptSize attribute.
3042 
3043  /// \brief Specify maximum number of store instructions per memmove call.
3044  ///
3045  /// When lowering \@llvm.memmove this field specifies the maximum number of
3046  /// store instructions that may be substituted for a call to memmove. Targets
3047  /// must set this value based on the cost threshold for that target. Targets
3048  /// should assume that the memmove will be done using as many of the largest
3049  /// store operations first, followed by smaller ones, if necessary, per
3050  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
3051  /// with 8-bit alignment would result in nine 1-byte stores. This only
3052  /// applies to copying a constant array of constant size.
3054  /// Likewise for functions with the OptSize attribute.
3056 
3057  /// Tells the code generator that select is more expensive than a branch if
3058  /// the branch is usually predicted right.
3060 
3061  /// \see enableExtLdPromotion.
3063 
3064  /// Return true if the value types that can be represented by the specified
3065  /// register class are all legal.
3066  bool isLegalRC(const TargetRegisterInfo &TRI,
3067  const TargetRegisterClass &RC) const;
3068 
3069  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
3070  /// sequence of memory operands that is recognized by PrologEpilogInserter.
3071  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
3072  MachineBasicBlock *MBB) const;
3073 
3074  /// Replace/modify the XRay custom event operands with target-dependent
3075  /// details.
3076  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
3077  MachineBasicBlock *MBB) const;
3078 
3079  /// Replace/modify the XRay typed event operands with target-dependent
3080  /// details.
3081  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
3082  MachineBasicBlock *MBB) const;
3083 
3085 };
3086 
3087 /// This class defines information used to lower LLVM code to legal SelectionDAG
3088 /// operators that the target instruction selector can accept natively.
3089 ///
3090 /// This class also defines callbacks that targets must implement to lower
3091 /// target-specific constructs to SelectionDAG operators.
3093 public:
3094  struct DAGCombinerInfo;
3095  struct MakeLibCallOptions;
3096 
3097  TargetLowering(const TargetLowering &) = delete;
3098  TargetLowering &operator=(const TargetLowering &) = delete;
3099 
3100  explicit TargetLowering(const TargetMachine &TM);
3101 
3102  bool isPositionIndependent() const;
3103 
3104  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
3105  FunctionLoweringInfo *FLI,
3106  LegacyDivergenceAnalysis *DA) const {
3107  return false;
3108  }
3109 
3110  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
3111  return false;
3112  }
3113 
3114  /// Returns true by value, base pointer and offset pointer and addressing mode
3115  /// by reference if the node's address can be legally represented as
3116  /// pre-indexed load / store address.
3117  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
3118  SDValue &/*Offset*/,
3119  ISD::MemIndexedMode &/*AM*/,
3120  SelectionDAG &/*DAG*/) const {
3121  return false;
3122  }
3123 
3124  /// Returns true by value, base pointer and offset pointer and addressing mode
3125  /// by reference if this node can be combined with a load / store to form a
3126  /// post-indexed load / store.
3127  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
3128  SDValue &/*Base*/,
3129  SDValue &/*Offset*/,
3130  ISD::MemIndexedMode &/*AM*/,
3131  SelectionDAG &/*DAG*/) const {
3132  return false;
3133  }
3134 
3135  /// Returns true if the specified base+offset is a legal indexed addressing
3136  /// mode for this target. \p MI is the load or store instruction that is being
3137  /// considered for transformation.
3139  bool IsPre, MachineRegisterInfo &MRI) const {
3140  return false;
3141  }
3142 
3143  /// Return the entry encoding for a jump table in the current function. The
3144  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
3145  virtual unsigned getJumpTableEncoding() const;
3146 
3147  virtual const MCExpr *
3149  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
3150  MCContext &/*Ctx*/) const {
3151  llvm_unreachable("Need to implement this hook if target has custom JTIs");
3152  }
3153 
3154  /// Returns relocation base for the given PIC jumptable.
3155  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
3156  SelectionDAG &DAG) const;
3157 
3158  /// This returns the relocation base for the given PIC jumptable, the same as
3159  /// getPICJumpTableRelocBase, but as an MCExpr.
3160  virtual const MCExpr *
3161  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3162  unsigned JTI, MCContext &Ctx) const;
3163 
3164  /// Return true if folding a constant offset with the given GlobalAddress is
3165  /// legal. It is frequently not legal in PIC relocation models.
3166  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
3167 
3169  SDValue &Chain) const;
3170 
3171  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3172  SDValue &NewRHS, ISD::CondCode &CCCode,
3173  const SDLoc &DL, const SDValue OldLHS,
3174  const SDValue OldRHS) const;
3175 
3176  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3177  SDValue &NewRHS, ISD::CondCode &CCCode,
3178  const SDLoc &DL, const SDValue OldLHS,
3179  const SDValue OldRHS, SDValue &Chain,
3180  bool IsSignaling = false) const;
3181 
3182  /// Returns a pair of (return value, chain).
3183  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
3184  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
3185  EVT RetVT, ArrayRef<SDValue> Ops,
3186  MakeLibCallOptions CallOptions,
3187  const SDLoc &dl,
3188  SDValue Chain = SDValue()) const;
3189 
3190  /// Check whether parameters to a call that are passed in callee saved
3191  /// registers are the same as from the calling function. This needs to be
3192  /// checked for tail call eligibility.
3193  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
3194  const uint32_t *CallerPreservedMask,
3195  const SmallVectorImpl<CCValAssign> &ArgLocs,
3196  const SmallVectorImpl<SDValue> &OutVals) const;
3197 
3198  //===--------------------------------------------------------------------===//
3199  // TargetLowering Optimization Methods
3200  //
3201 
3202  /// A convenience struct that encapsulates a DAG, and two SDValues for
3203  /// returning information from TargetLowering to its clients that want to
3204  /// combine.
3207  bool LegalTys;
3208  bool LegalOps;
3211 
3213  bool LT, bool LO) :
3214  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
3215 
3216  bool LegalTypes() const { return LegalTys; }
3217  bool LegalOperations() const { return LegalOps; }
3218 
3220  Old = O;
3221  New = N;
3222  return true;
3223  }
3224  };
3225 
3226  /// Determines the optimal series of memory ops to replace the memset / memcpy.
3227  /// Return true if the number of memory ops is below the threshold (Limit).
3228  /// It returns the types of the sequence of memory ops to perform
3229  /// memset / memcpy by reference.
3230  bool findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
3231  const MemOp &Op, unsigned DstAS, unsigned SrcAS,
3232  const AttributeList &FuncAttributes) const;
3233 
3234  /// Check to see if the specified operand of the specified instruction is a
3235  /// constant integer. If so, check to see if there are any bits set in the
3236  /// constant that are not demanded. If so, shrink the constant and return
3237  /// true.
3238  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3239  TargetLoweringOpt &TLO) const;
3240 
3241  // Target hook to do target-specific const optimization, which is called by
3242  // ShrinkDemandedConstant. This function should return true if the target
3243  // doesn't want ShrinkDemandedConstant to further optimize the constant.
3244  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3245  TargetLoweringOpt &TLO) const {
3246  return false;
3247  }
3248 
3249  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3250  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3251  /// generalized for targets with other types of implicit widening casts.
3252  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3253  TargetLoweringOpt &TLO) const;
3254 
3255  /// Look at Op. At this point, we know that only the DemandedBits bits of the
3256  /// result of Op are ever used downstream. If we can use this information to
3257  /// simplify Op, create a new simplified DAG node and return true, returning
3258  /// the original and new nodes in Old and New. Otherwise, analyze the
3259  /// expression and return a mask of KnownOne and KnownZero bits for the
3260  /// expression (used to simplify the caller). The KnownZero/One bits may only
3261  /// be accurate for those bits in the Demanded masks.
3262  /// \p AssumeSingleUse When this parameter is true, this function will
3263  /// attempt to simplify \p Op even if there are multiple uses.
3264  /// Callers are responsible for correctly updating the DAG based on the
3265  /// results of this function, because simply replacing replacing TLO.Old
3266  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3267  /// has multiple uses.
3268  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3269  const APInt &DemandedElts, KnownBits &Known,
3270  TargetLoweringOpt &TLO, unsigned Depth = 0,
3271  bool AssumeSingleUse = false) const;
3272 
3273  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3274  /// Adds Op back to the worklist upon success.
3275  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3276  KnownBits &Known, TargetLoweringOpt &TLO,
3277  unsigned Depth = 0,
3278  bool AssumeSingleUse = false) const;
3279 
3280  /// Helper wrapper around SimplifyDemandedBits.
3281  /// Adds Op back to the worklist upon success.
3282  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3283  DAGCombinerInfo &DCI) const;
3284 
3285  /// More limited version of SimplifyDemandedBits that can be used to "look
3286  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3287  /// bitwise ops etc.
3288  SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3289  const APInt &DemandedElts,
3290  SelectionDAG &DAG,
3291  unsigned Depth) const;
3292 
3293  /// Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all
3294  /// elements.
3295  SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3296  SelectionDAG &DAG,
3297  unsigned Depth = 0) const;
3298 
3299  /// Look at Vector Op. At this point, we know that only the DemandedElts
3300  /// elements of the result of Op are ever used downstream. If we can use
3301  /// this information to simplify Op, create a new simplified DAG node and
3302  /// return true, storing the original and new nodes in TLO.
3303  /// Otherwise, analyze the expression and return a mask of KnownUndef and
3304  /// KnownZero elements for the expression (used to simplify the caller).
3305  /// The KnownUndef/Zero elements may only be accurate for those bits
3306  /// in the DemandedMask.
3307  /// \p AssumeSingleUse When this parameter is true, this function will
3308  /// attempt to simplify \p Op even if there are multiple uses.
3309  /// Callers are responsible for correctly updating the DAG based on the
3310  /// results of this function, because simply replacing replacing TLO.Old
3311  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3312  /// has multiple uses.
3313  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3314  APInt &KnownUndef, APInt &KnownZero,
3315  TargetLoweringOpt &TLO, unsigned Depth = 0,
3316  bool AssumeSingleUse = false) const;
3317 
3318  /// Helper wrapper around SimplifyDemandedVectorElts.
3319  /// Adds Op back to the worklist upon success.
3320  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3321  APInt &KnownUndef, APInt &KnownZero,
3322  DAGCombinerInfo &DCI) const;
3323 
3324  /// Determine which of the bits specified in Mask are known to be either zero
3325  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3326  /// argument allows us to only collect the known bits that are shared by the
3327  /// requested vector elements.
3328  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3329  KnownBits &Known,
3330  const APInt &DemandedElts,
3331  const SelectionDAG &DAG,
3332  unsigned Depth = 0) const;
3333 
3334  /// Determine which of the bits specified in Mask are known to be either zero
3335  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3336  /// argument allows us to only collect the known bits that are shared by the
3337  /// requested vector elements. This is for GISel.
3338  virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis,
3339  Register R, KnownBits &Known,
3340  const APInt &DemandedElts,
3341  const MachineRegisterInfo &MRI,
3342  unsigned Depth = 0) const;
3343 
3344  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3345  /// Default implementation computes low bits based on alignment
3346  /// information. This should preserve known bits passed into it.
3347  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3348  KnownBits &Known,
3349  const APInt &DemandedElts,
3350  const SelectionDAG &DAG,
3351  unsigned Depth = 0) const;
3352 
3353  /// This method can be implemented by targets that want to expose additional
3354  /// information about sign bits to the DAG Combiner. The DemandedElts
3355  /// argument allows us to only collect the minimum sign bits that are shared
3356  /// by the requested vector elements.
3357  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3358  const APInt &DemandedElts,
3359  const SelectionDAG &DAG,
3360  unsigned Depth = 0) const;
3361 
3362  /// This method can be implemented by targets that want to expose additional
3363  /// information about sign bits to GlobalISel combiners. The DemandedElts
3364  /// argument allows us to only collect the minimum sign bits that are shared
3365  /// by the requested vector elements.
3366  virtual unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis,
3367  Register R,
3368  const APInt &DemandedElts,
3369  const MachineRegisterInfo &MRI,
3370  unsigned Depth = 0) const;
3371 
3372  /// Attempt to simplify any target nodes based on the demanded vector
3373  /// elements, returning true on success. Otherwise, analyze the expression and
3374  /// return a mask of KnownUndef and KnownZero elements for the expression
3375  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3376  /// accurate for those bits in the DemandedMask.
3377  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3378  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3379  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3380 
3381  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3382  /// returning true on success. Otherwise, analyze the
3383  /// expression and return a mask of KnownOne and KnownZero bits for the
3384  /// expression (used to simplify the caller). The KnownZero/One bits may only
3385  /// be accurate for those bits in the Demanded masks.
3386  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3387  const APInt &DemandedBits,
3388  const APInt &DemandedElts,
3389  KnownBits &Known,
3390  TargetLoweringOpt &TLO,
3391  unsigned Depth = 0) const;
3392 
3393  /// More limited version of SimplifyDemandedBits that can be used to "look
3394  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3395  /// bitwise ops etc.
3396  virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
3397  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3398  SelectionDAG &DAG, unsigned Depth) const;
3399 
3400  /// Tries to build a legal vector shuffle using the provided parameters
3401  /// or equivalent variations. The Mask argument maybe be modified as the
3402  /// function tries different variations.
3403  /// Returns an empty SDValue if the operation fails.
3404  SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
3406  SelectionDAG &DAG) const;
3407 
3408  /// This method returns the constant pool value that will be loaded by LD.
3409  /// NOTE: You must check for implicit extensions of the constant by LD.
3410  virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
3411 
3412  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3413  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3414  /// NaN.
3415  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3416  const SelectionDAG &DAG,
3417  bool SNaN = false,
3418  unsigned Depth = 0) const;
3420  void *DC; // The DAG Combiner object.
3423 
3424  public:
3426 
3427  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3428  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3429 
3430  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3431  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3432  bool isAfterLegalizeDAG() const { return Level >= AfterLegalizeDAG; }
3434  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3435 
3436  void AddToWorklist(SDNode *N);
3437  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3438  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3439  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3440 
3441  bool recursivelyDeleteUnusedNodes(SDNode *N);
3442 
3443  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3444  };
3445 
3446  /// Return if the N is a constant or constant vector equal to the true value
3447  /// from getBooleanContents().
3448  bool isConstTrueVal(const SDNode *N) const;
3449 
3450  /// Return if the N is a constant or constant vector equal to the false value
3451  /// from getBooleanContents().
3452  bool isConstFalseVal(const SDNode *N) const;
3453 
3454  /// Return if \p N is a True value when extended to \p VT.
3455  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3456 
3457  /// Try to simplify a setcc built with the specified operands and cc. If it is
3458  /// unable to simplify it, return a null SDValue.
3459  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3460  bool foldBooleans, DAGCombinerInfo &DCI,
3461  const SDLoc &dl) const;
3462 
3463  // For targets which wrap address, unwrap for analysis.
3464  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3465 
3466  /// Returns true (and the GlobalValue and the offset) if the node is a
3467  /// GlobalAddress + offset.
3468  virtual bool
3469  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3470 
3471  /// This method will be invoked for all target nodes and for any
3472  /// target-independent nodes that the target has registered with invoke it
3473  /// for.
3474  ///
3475  /// The semantics are as follows:
3476  /// Return Value:
3477  /// SDValue.Val == 0 - No change was made
3478  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3479  /// otherwise - N should be replaced by the returned Operand.
3480  ///
3481  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3482  /// more complex transformations.
3483  ///
3484  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3485 
3486  /// Return true if it is profitable to move this shift by a constant amount
3487  /// though its operand, adjusting any immediate operands as necessary to
3488  /// preserve semantics. This transformation may not be desirable if it
3489  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3490  /// extraction in AArch64). By default, it returns true.
3491  ///
3492  /// @param N the shift node
3493  /// @param Level the current DAGCombine legalization level.
3494  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3495  CombineLevel Level) const {
3496  return true;
3497  }
3498 
3499  /// Return true if the target has native support for the specified value type
3500  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3501  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3502  /// and some i16 instructions are slow.
3503  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3504  // By default, assume all legal types are desirable.
3505  return isTypeLegal(VT);
3506  }
3507 
3508  /// Return true if it is profitable for dag combiner to transform a floating
3509  /// point op of specified opcode to a equivalent op of an integer
3510  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3511  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3512  EVT /*VT*/) const {
3513  return false;
3514  }
3515 
3516  /// This method query the target whether it is beneficial for dag combiner to
3517  /// promote the specified node. If true, it should return the desired
3518  /// promotion type by reference.
3519  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3520  return false;
3521  }
3522 
3523  /// Return true if the target supports swifterror attribute. It optimizes
3524  /// loads and stores to reading and writing a specific register.
3525  virtual bool supportSwiftError() const {
3526  return false;
3527  }
3528 
3529  /// Return true if the target supports that a subset of CSRs for the given
3530  /// machine function is handled explicitly via copies.
3531  virtual bool supportSplitCSR(MachineFunction *MF) const {
3532  return false;
3533  }
3534 
3535  /// Perform necessary initialization to handle a subset of CSRs explicitly
3536  /// via copies. This function is called at the beginning of instruction
3537  /// selection.
3538  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3539  llvm_unreachable("Not Implemented");
3540  }
3541 
3542  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3543  /// CSRs to virtual registers in the entry block, and copy them back to
3544  /// physical registers in the exit blocks. This function is called at the end
3545  /// of instruction selection.
3546  virtual void insertCopiesSplitCSR(
3547  MachineBasicBlock *Entry,
3548  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3549  llvm_unreachable("Not Implemented");
3550  }
3551 
3552  /// Return the newly negated expression if the cost is not expensive and
3553  /// set the cost in \p Cost to indicate that if it is cheaper or neutral to
3554  /// do the negation.
3555  virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
3556  bool LegalOps, bool OptForSize,
3557  NegatibleCost &Cost,
3558  unsigned Depth = 0) const;
3559 
3560  /// This is the helper function to return the newly negated expression only
3561  /// when the cost is cheaper.
3563  bool LegalOps, bool OptForSize,
3564  unsigned Depth = 0) const {
3565  NegatibleCost Cost = NegatibleCost::Expensive;
3566  SDValue Neg =
3567  getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
3568  if (Neg && Cost == NegatibleCost::Cheaper)
3569  return Neg;
3570  // Remove the new created node to avoid the side effect to the DAG.
3571  if (Neg && Neg.getNode()->use_empty())
3572  DAG.RemoveDeadNode(Neg.getNode());
3573  return SDValue();
3574  }
3575 
3576  /// This is the helper function to return the newly negated expression if
3577  /// the cost is not expensive.
3579  bool OptForSize, unsigned Depth = 0) const {
3580  NegatibleCost Cost = NegatibleCost::Expensive;
3581  return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
3582  }
3583 
3584  //===--------------------------------------------------------------------===//
3585  // Lowering methods - These methods must be implemented by targets so that
3586  // the SelectionDAGBuilder code knows how to lower these.
3587  //
3588 
3589  /// This hook must be implemented to lower the incoming (formal) arguments,
3590  /// described by the Ins array, into the specified DAG. The implementation
3591  /// should fill in the InVals array with legal-type argument values, and
3592  /// return the resulting token chain value.
3594  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3595  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3596  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3597  llvm_unreachable("Not Implemented");
3598  }
3599 
3600  /// This structure contains all information that is necessary for lowering
3601  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3602  /// needs to lower a call, and targets will see this struct in their LowerCall
3603  /// implementation.
3606  Type *RetTy = nullptr;
3607  bool RetSExt : 1;
3608  bool RetZExt : 1;
3609  bool IsVarArg : 1;
3610  bool IsInReg : 1;
3611  bool DoesNotReturn : 1;
3613  bool IsConvergent : 1;
3614  bool IsPatchPoint : 1;
3615  bool IsPreallocated : 1;
3616  bool NoMerge : 1;
3617 
3618  // IsTailCall should be modified by implementations of
3619  // TargetLowering::LowerCall that perform tail call conversions.
3620  bool IsTailCall = false;
3621 
3622  // Is Call lowering done post SelectionDAG type legalization.
3623  bool IsPostTypeLegalization = false;
3624 
3625  unsigned NumFixedArgs = -1;
3628  ArgListTy Args;
3631  const CallBase *CB = nullptr;
3636 
3638  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3639  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3640  IsPatchPoint(false), IsPreallocated(false), NoMerge(false),
3641  DAG(DAG) {}
3642 
3644  DL = dl;
3645  return *this;
3646  }
3647 
3649  Chain = InChain;
3650  return *this;
3651  }
3652 
3653  // setCallee with target/module-specific attributes
3655  SDValue Target, ArgListTy &&ArgsList) {
3656  RetTy = ResultType;
3657  Callee = Target;
3658  CallConv = CC;
3659  NumFixedArgs = ArgsList.size();
3660  Args = std::move(ArgsList);
3661 
3663  &(DAG.getMachineFunction()), CC, Args);
3664  return *this;
3665  }
3666 
3668  SDValue Target, ArgListTy &&ArgsList) {
3669  RetTy = ResultType;
3670  Callee = Target;
3671  CallConv = CC;
3672  NumFixedArgs = ArgsList.size();
3673  Args = std::move(ArgsList);
3674  return *this;
3675  }
3676 
3678  SDValue Target, ArgListTy &&ArgsList,
3679  const CallBase &Call) {
3680  RetTy = ResultType;
3681 
3682  IsInReg = Call.hasRetAttr(Attribute::InReg);
3683  DoesNotReturn =
3684  Call.doesNotReturn() ||
3685  (!isa<InvokeInst>(Call) && isa<UnreachableInst>(Call.getNextNode()));
3686  IsVarArg = FTy->isVarArg();
3687  IsReturnValueUsed = !Call.use_empty();
3688  RetSExt = Call.hasRetAttr(Attribute::SExt);
3689  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3690  NoMerge = Call.hasFnAttr(Attribute::NoMerge);
3691 
3692  Callee = Target;
3693 
3694  CallConv = Call.getCallingConv();
3695  NumFixedArgs = FTy->getNumParams();
3696  Args = std::move(ArgsList);
3697 
3698  CB = &Call;
3699 
3700  return *this;
3701  }
3702 
3704  IsInReg = Value;
3705  return *this;
3706  }
3707 
3709  DoesNotReturn = Value;
3710  return *this;
3711  }
3712 
3714  IsVarArg = Value;
3715  return *this;
3716  }
3717 
3719  IsTailCall = Value;
3720  return *this;
3721  }
3722 
3724  IsReturnValueUsed = !Value;
3725  return *this;
3726  }
3727 
3729  IsConvergent = Value;
3730  return *this;
3731  }
3732 
3734  RetSExt = Value;
3735  return *this;
3736  }
3737 
3739  RetZExt = Value;
3740  return *this;
3741  }
3742 
3744  IsPatchPoint = Value;
3745  return *this;
3746  }
3747 
3749  IsPreallocated = Value;
3750  return *this;
3751  }
3752 
3754  IsPostTypeLegalization = Value;
3755  return *this;
3756  }
3757 
3758  ArgListTy &getArgs() {
3759  return Args;
3760  }
3761  };
3762 
3763  /// This structure is used to pass arguments to makeLibCall function.
3765  // By passing type list before soften to makeLibCall, the target hook
3766  // shouldExtendTypeInLibCall can get the original type before soften.
3769  bool IsSExt : 1;
3770  bool DoesNotReturn : 1;
3773  bool IsSoften : 1;
3774 
3776  : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
3777  IsPostTypeLegalization(false), IsSoften(false) {}
3778 
3780  IsSExt = Value;
3781  return *this;
3782  }
3783 
3785  DoesNotReturn = Value;
3786  return *this;
3787  }
3788 
3790  IsReturnValueUsed = !Value;
3791  return *this;
3792  }
3793 
3795  IsPostTypeLegalization = Value;
3796  return *this;
3797  }
3798 
3800  bool Value = true) {
3801  OpsVTBeforeSoften = OpsVT;
3802  RetVTBeforeSoften = RetVT;
3803  IsSoften = Value;
3804  return *this;
3805  }
3806  };
3807 
3808  /// This function lowers an abstract call to a function into an actual call.
3809  /// This returns a pair of operands. The first element is the return value
3810  /// for the function (if RetTy is not VoidTy). The second element is the
3811  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3812  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3813 
3814  /// This hook must be implemented to lower calls into the specified
3815  /// DAG. The outgoing arguments to the call are described by the Outs array,
3816  /// and the values to be returned by the call are described by the Ins
3817  /// array. The implementation should fill in the InVals array with legal-type
3818  /// return values from the call, and return the resulting token chain value.
3819  virtual SDValue
3821  SmallVectorImpl<SDValue> &/*InVals*/) const {
3822  llvm_unreachable("Not Implemented");
3823  }
3824 
3825  /// Target-specific cleanup for formal ByVal parameters.
3826  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3827 
3828  /// This hook should be implemented to check whether the return values
3829  /// described by the Outs array can fit into the return registers. If false
3830  /// is returned, an sret-demotion is performed.
3831  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3832  MachineFunction &/*MF*/, bool /*isVarArg*/,
3833  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3834  LLVMContext &/*Context*/) const
3835  {
3836  // Return true by default to get preexisting behavior.
3837  return true;
3838  }
3839 
3840  /// This hook must be implemented to lower outgoing return values, described
3841  /// by the Outs array, into the specified DAG. The implementation should
3842  /// return the resulting token chain value.
3843  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3844  bool /*isVarArg*/,
3845  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3846  const SmallVectorImpl<SDValue> & /*OutVals*/,
3847  const SDLoc & /*dl*/,
3848  SelectionDAG & /*DAG*/) const {
3849  llvm_unreachable("Not Implemented");
3850  }
3851 
3852  /// Return true if result of the specified node is used by a return node
3853  /// only. It also compute and return the input chain for the tail call.
3854  ///
3855  /// This is used to determine whether it is possible to codegen a libcall as
3856  /// tail call at legalization time.
3857  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3858  return false;
3859  }
3860 
3861  /// Return true if the target may be able emit the call instruction as a tail
3862  /// call. This is used by optimization passes to determine if it's profitable
3863  /// to duplicate return instructions to enable tailcall optimization.
3864  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3865  return false;
3866  }
3867 
3868  /// Return the builtin name for the __builtin___clear_cache intrinsic
3869  /// Default is to invoke the clear cache library call
3870  virtual const char * getClearCacheBuiltinName() const {
3871  return "__clear_cache";
3872  }
3873 
3874  /// Return the register ID of the name passed in. Used by named register
3875  /// global variables extension. There is no target-independent behaviour
3876  /// so the default action is to bail.
3877  virtual Register getRegisterByName(const char* RegName, LLT Ty,
3878  const MachineFunction &MF) const {
3879  report_fatal_error("Named registers not implemented for this target");
3880  }
3881 
3882  /// Return the type that should be used to zero or sign extend a
3883  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3884  /// require the return type to be promoted, but this is not true all the time,
3885  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3886  /// conventions. The frontend should handle this and include all of the
3887  /// necessary information.
3889  ISD::NodeType /*ExtendKind*/) const {
3890  EVT MinVT = getRegisterType(Context, MVT::i32);
3891  return VT.bitsLT(MinVT) ? MinVT : VT;
3892  }
3893 
3894  /// For some targets, an LLVM struct type must be broken down into multiple
3895  /// simple types, but the calling convention specifies that the entire struct
3896  /// must be passed in a block of consecutive registers.
3897  virtual bool
3899  bool isVarArg) const {
3900  return false;
3901  }
3902 
3903  /// For most targets, an LLVM type must be broken down into multiple
3904  /// smaller types. Usually the halves are ordered according to the endianness
3905  /// but for some platform that would break. So this method will default to
3906  /// matching the endianness but can be overridden.
3907  virtual bool
3909  return DL.isLittleEndian();
3910  }
3911 
3912  /// Returns a 0 terminated array of registers that can be safely used as
3913  /// scratch registers.
3914  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3915  return nullptr;
3916  }
3917 
3918  /// This callback is used to prepare for a volatile or atomic load.
3919  /// It takes a chain node as input and returns the chain for the load itself.
3920  ///
3921  /// Having a callback like this is necessary for targets like SystemZ,
3922  /// which allows a CPU to reuse the result of a previous load indefinitely,
3923  /// even if a cache-coherent store is performed by another CPU. The default
3924  /// implementation does nothing.
3926  SelectionDAG &DAG) const {
3927  return Chain;
3928  }
3929 
3930  /// Should SelectionDAG lower an atomic store of the given kind as a normal
3931  /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3932  /// eventually migrate all targets to the using StoreSDNodes, but porting is
3933  /// being done target at a time.
3934  virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const {
3935  assert(SI.isAtomic() && "violated precondition");
3936  return false;
3937  }
3938 
3939  /// Should SelectionDAG lower an atomic load of the given kind as a normal
3940  /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3941  /// eventually migrate all targets to the using LoadSDNodes, but porting is
3942  /// being done target at a time.
3943  virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const {
3944  assert(LI.isAtomic() && "violated precondition");
3945  return false;
3946  }
3947 
3948 
3949  /// This callback is invoked by the type legalizer to legalize nodes with an
3950  /// illegal operand type but legal result types. It replaces the
3951  /// LowerOperation callback in the type Legalizer. The reason we can not do
3952  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3953  /// use this callback.
3954  ///
3955  /// TODO: Consider merging with ReplaceNodeResults.
3956  ///
3957  /// The target places new result values for the node in Results (their number
3958  /// and types must exactly match those of the original return values of
3959  /// the node), or leaves Results empty, which indicates that the node is not
3960  /// to be custom lowered after all.
3961  /// The default implementation calls LowerOperation.
3962  virtual void LowerOperationWrapper(SDNode *N,
3964  SelectionDAG &DAG) const;
3965 
3966  /// This callback is invoked for operations that are unsupported by the
3967  /// target, which are registered to use 'custom' lowering, and whose defined
3968  /// values are all legal. If the target has no operations that require custom
3969  /// lowering, it need not implement this. The default implementation of this
3970  /// aborts.
3971  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3972 
3973  /// This callback is invoked when a node result type is illegal for the
3974  /// target, and the operation was registered to use 'custom' lowering for that
3975  /// result type. The target places new result values for the node in Results
3976  /// (their number and types must exactly match those of the original return
3977  /// values of the node), or leaves Results empty, which indicates that the
3978  /// node is not to be custom lowered after all.
3979  ///
3980  /// If the target has no operations that require custom lowering, it need not
3981  /// implement this. The default implementation aborts.
3982  virtual void ReplaceNodeResults(SDNode * /*N*/,
3983  SmallVectorImpl<SDValue> &/*Results*/,
3984  SelectionDAG &/*DAG*/) const {
3985  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3986  }
3987 
3988  /// This method returns the name of a target specific DAG node.
3989  virtual const char *getTargetNodeName(unsigned Opcode) const;
3990 
3991  /// This method returns a target specific FastISel object, or null if the
3992  /// target does not support "fast" ISel.
3994  const TargetLibraryInfo *) const {
3995  return nullptr;
3996  }
3997 
3998  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3999  SelectionDAG &DAG) const;
4000 
4001  //===--------------------------------------------------------------------===//
4002  // Inline Asm Support hooks
4003  //
4004 
4005  /// This hook allows the target to expand an inline asm call to be explicit
4006  /// llvm code if it wants to. This is useful for turning simple inline asms
4007  /// into LLVM intrinsics, which gives the compiler more information about the
4008  /// behavior of the code.
4009  virtual bool ExpandInlineAsm(CallInst *) const {
4010  return false;
4011  }
4012 
4014  C_Register, // Constraint represents specific register(s).
4015  C_RegisterClass, // Constraint represents any of register(s) in class.
4016  C_Memory, // Memory constraint.
4017  C_Immediate, // Requires an immediate.
4018  C_Other, // Something else.
4019  C_Unknown // Unsupported constraint.
4020  };
4021 
4023  // Generic weights.
4024  CW_Invalid = -1, // No match.
4025  CW_Okay = 0, // Acceptable.
4026  CW_Good = 1, // Good weight.
4027  CW_Better = 2, // Better weight.
4028  CW_Best = 3, // Best weight.
4029 
4030  // Well-known weights.
4031  CW_SpecificReg = CW_Okay, // Specific register operands.
4032  CW_Register = CW_Good, // Register operands.
4033  CW_Memory = CW_Better, // Memory operands.
4034  CW_Constant = CW_Best, // Constant operand.
4035  CW_Default = CW_Okay // Default or don't know type.
4036  };
4037 
4038  /// This contains information for each constraint that we are lowering.
4040  /// This contains the actual string for the code, like "m". TargetLowering
4041  /// picks the 'best' code from ConstraintInfo::Codes that most closely
4042  /// matches the operand.
4043  std::string ConstraintCode;
4044 
4045  /// Information about the constraint code, e.g. Register, RegisterClass,
4046  /// Memory, Other, Unknown.
4048 
4049  /// If this is the result output operand or a clobber, this is null,
4050  /// otherwise it is the incoming operand to the CallInst. This gets
4051  /// modified as the asm is processed.
4052  Value *CallOperandVal = nullptr;
4053 
4054  /// The ValueType for the operand value.
4055  MVT ConstraintVT = MVT::Other;
4056 
4057  /// Copy constructor for copying from a ConstraintInfo.
4059  : InlineAsm::ConstraintInfo(std::move(Info)) {}
4060 
4061  /// Return true of this is an input operand that is a matching constraint
4062  /// like "4".
4063  bool isMatchingInputConstraint() const;
4064 
4065  /// If this is an input matching constraint, this method returns the output
4066  /// operand it matches.
4067  unsigned getMatchedOperand() const;
4068  };
4069 
4070  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
4071 
4072  /// Split up the constraint string from the inline assembly value into the
4073  /// specific constraints and their prefixes, and also tie in the associated
4074  /// operand values. If this returns an empty vector, and if the constraint
4075  /// string itself isn't empty, there was an error parsing.
4076  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
4077  const TargetRegisterInfo *TRI,
4078  const CallBase &Call) const;
4079 
4080  /// Examine constraint type and operand type and determine a weight value.
4081  /// The operand object must already have been set up with the operand type.
4082  virtual ConstraintWeight getMultipleConstraintMatchWeight(
4083  AsmOperandInfo &info, int maIndex) const;
4084 
4085  /// Examine constraint string and operand type and determine a weight value.
4086  /// The operand object must already have been set up with the operand type.
4087  virtual ConstraintWeight getSingleConstraintMatchWeight(
4088  AsmOperandInfo &info, const char *constraint) const;
4089 
4090  /// Determines the constraint code and constraint type to use for the specific
4091  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
4092  /// If the actual operand being passed in is available, it can be passed in as
4093  /// Op, otherwise an empty SDValue can be passed.
4094  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
4095  SDValue Op,
4096  SelectionDAG *DAG = nullptr) const;
4097 
4098  /// Given a constraint, return the type of constraint it is for this target.
4099  virtual ConstraintType getConstraintType(StringRef Constraint) const;
4100 
4101  /// Given a physical register constraint (e.g. {edx}), return the register
4102  /// number and the register class for the register.
4103  ///
4104  /// Given a register class constraint, like 'r', if this corresponds directly
4105  /// to an LLVM register class, return a register of 0 and the register class
4106  /// pointer.
4107  ///
4108  /// This should only be used for C_Register constraints. On error, this
4109  /// returns a register number of 0 and a null register class pointer.
4110  virtual std::pair<unsigned, const TargetRegisterClass *>
4111  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
4112  StringRef Constraint, MVT VT) const;
4113 
4114  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
4115  if (ConstraintCode == "m")
4116  return InlineAsm::Constraint_m;
4118  }
4119 
4120  /// Try to replace an X constraint, which matches anything, with another that
4121  /// has more specific requirements based on the type of the corresponding
4122  /// operand. This returns null if there is no replacement to make.
4123  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
4124 
4125  /// Lower the specified operand into the Ops vector. If it is invalid, don't
4126  /// add anything to Ops.
4127  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
4128  std::vector<SDValue> &Ops,
4129  SelectionDAG &DAG) const;
4130 
4131  // Lower custom output constraints. If invalid, return SDValue().
4132  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
4133  SDLoc DL,
4134  const AsmOperandInfo &OpInfo,
4135  SelectionDAG &DAG) const;
4136 
4137  //===--------------------------------------------------------------------===//
4138  // Div utility functions
4139  //
4140  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
4141  SmallVectorImpl<SDNode *> &Created) const;
4142  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
4143  SmallVectorImpl<SDNode *> &Created) const;
4144 
4145  /// Targets may override this function to provide custom SDIV lowering for
4146  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
4147  /// assumes SDIV is expensive and replaces it with a series of other integer
4148  /// operations.
4149  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
4150  SelectionDAG &DAG,
4151  SmallVectorImpl<SDNode *> &Created) const;
4152 
4153  /// Indicate whether this target prefers to combine FDIVs with the same
4154  /// divisor. If the transform should never be done, return zero. If the
4155  /// transform should be done, return the minimum number of divisor uses
4156  /// that must exist.
4157  virtual unsigned combineRepeatedFPDivisors() const {
4158  return 0;
4159  }
4160 
4161  /// Hooks for building estimates in place of slower divisions and square
4162  /// roots.
4163 
4164  /// Return either a square root or its reciprocal estimate value for the input
4165  /// operand.
4166  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
4167  /// 'Enabled' as set by a potential default override attribute.
4168  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
4169  /// refinement iterations required to generate a sufficient (though not
4170  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
4171  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
4172  /// algorithm implementation that uses either one or two constants.
4173  /// The boolean Reciprocal is used to select whether the estimate is for the
4174  /// square root of the input operand or the reciprocal of its square root.
4175  /// A target may choose to implement its own refinement within this function.
4176  /// If that's true, then return '0' as the number of RefinementSteps to avoid
4177  /// any further refinement of the estimate.
4178  /// An empty SDValue return means no estimate sequence can be created.
4180  int Enabled, int &RefinementSteps,
4181  bool &UseOneConstNR, bool Reciprocal) const {
4182  return SDValue();
4183  }
4184 
4185  /// Return a reciprocal estimate value for the input operand.
4186  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
4187  /// 'Enabled' as set by a potential default override attribute.
4188  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
4189  /// refinement iterations required to generate a sufficient (though not
4190  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
4191  /// A target may choose to implement its own refinement within this function.
4192  /// If that's true, then return '0' as the number of RefinementSteps to avoid
4193  /// any further refinement of the estimate.
4194  /// An empty SDValue return means no estimate sequence can be created.
4196  int Enabled, int &RefinementSteps) const {
4197  return SDValue();
4198  }
4199 
4200  //===--------------------------------------------------------------------===//
4201  // Legalization utility functions
4202  //
4203 
4204  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
4205  /// respectively, each computing an n/2-bit part of the result.
4206  /// \param Result A vector that will be filled with the parts of the result
4207  /// in little-endian order.
4208  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4209  /// if you want to control how low bits are extracted from the LHS.
4210  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4211  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4212  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4213  /// \returns true if the node has been expanded, false if it has not
4214  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
4215  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
4217  SDValue LL = SDValue(), SDValue LH = SDValue(),
4218  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4219 
4220  /// Expand a MUL into two nodes. One that computes the high bits of
4221  /// the result and one that computes the low bits.
4222  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
4223  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4224  /// if you want to control how low bits are extracted from the LHS.
4225  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4226  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4227  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4228  /// \returns true if the node has been expanded. false if it has not
4229  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
4230  SelectionDAG &DAG, MulExpansionKind Kind,
4231  SDValue LL = SDValue(), SDValue LH = SDValue(),
4232  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4233 
4234  /// Expand funnel shift.
4235  /// \param N Node to expand
4236  /// \param Result output after conversion
4237  /// \returns True, if the expansion was successful, false otherwise
4238  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4239 
4240  /// Expand rotations.
4241  /// \param N Node to expand
4242  /// \param Result output after conversion
4243  /// \returns True, if the expansion was successful, false otherwise
4244  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4245 
4246  /// Expand float(f32) to SINT(i64) conversion
4247  /// \param N Node to expand
4248  /// \param Result output after conversion
4249  /// \returns True, if the expansion was successful, false otherwise
4250  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4251 
4252  /// Expand float to UINT conversion
4253  /// \param N Node to expand
4254  /// \param Result output after conversion
4255  /// \param Chain output chain after conversion
4256  /// \returns True, if the expansion was successful, false otherwise
4257  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain,
4258  SelectionDAG &DAG) const;
4259 
4260  /// Expand UINT(i64) to double(f64) conversion
4261  /// \param N Node to expand
4262  /// \param Result output after conversion
4263  /// \param Chain output chain after conversion
4264  /// \returns True, if the expansion was successful, false otherwise
4265  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain,
4266  SelectionDAG &DAG) const;
4267 
4268  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
4269  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
4270 
4271  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4272  /// vector nodes can only succeed if all operations are legal/custom.
4273  /// \param N Node to expand
4274  /// \param Result output after conversion
4275  /// \returns True, if the expansion was successful, false otherwise
4276  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4277 
4278  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4279  /// vector nodes can only succeed if all operations are legal/custom.
4280  /// \param N Node to expand
4281  /// \param Result output after conversion
4282  /// \returns True, if the expansion was successful, false otherwise
4283  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4284 
4285  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4286  /// vector nodes can only succeed if all operations are legal/custom.
4287  /// \param N Node to expand
4288  /// \param Result output after conversion
4289  /// \returns True, if the expansion was successful, false otherwise
4290  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4291 
4292  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4293  /// vector nodes can only succeed if all operations are legal/custom.
4294  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4295  /// \param N Node to expand
4296  /// \param Result output after conversion
4297  /// \returns True, if the expansion was successful, false otherwise
4298  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4299 
4300  /// Turn load of vector type into a load of the individual elements.
4301  /// \param LD load to expand
4302  /// \returns BUILD_VECTOR and TokenFactor nodes.
4303  std::pair<SDValue, SDValue> scalarizeVectorLoad(LoadSDNode *LD,
4304  SelectionDAG &DAG) const;
4305 
4306  // Turn a store of a vector type into stores of the individual elements.
4307  /// \param ST Store with a vector value type
4308  /// \returns TokenFactor of the individual store chains.
4310 
4311  /// Expands an unaligned load to 2 half-size loads for an integer, and
4312  /// possibly more for vectors.
4313  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
4314  SelectionDAG &DAG) const;
4315 
4316  /// Expands an unaligned store to 2 half-size stores for integer values, and
4317  /// possibly more for vectors.
4318  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
4319 
4320  /// Increments memory address \p Addr according to the type of the value
4321  /// \p DataVT that should be stored. If the data is stored in compressed
4322  /// form, the memory address should be incremented according to the number of
4323  /// the stored elements. This number is equal to the number of '1's bits
4324  /// in the \p Mask.
4325  /// \p DataVT is a vector type. \p Mask is a vector value.
4326  /// \p DataVT and \p Mask have the same number of vector elements.
4327  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
4328  EVT DataVT, SelectionDAG &DAG,
4329  bool IsCompressedMemory) const;
4330 
4331  /// Get a pointer to vector element \p Idx located in memory for a vector of
4332  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4333  /// bounds the returned pointer is unspecified, but will be within the vector
4334  /// bounds.
4335  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4336  SDValue Index) const;
4337 
4338  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4339  /// method accepts integers as its arguments.
4340  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
4341 
4342  /// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This
4343  /// method accepts integers as its arguments.
4344  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
4345 
4346  /// Method for building the DAG expansion of ISD::[US]DIVFIX[SAT]. This
4347  /// method accepts integers as its arguments.
4348  /// Note: This method may fail if the division could not be performed
4349  /// within the type. Clients must retry with a wider type if this happens.
4350  SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
4351  SDValue LHS, SDValue RHS,
4352  unsigned Scale, SelectionDAG &DAG) const;
4353 
4354  /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4355  /// always suceeds and populates the Result and Overflow arguments.
4356  void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4357  SelectionDAG &DAG) const;
4358 
4359  /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4360  /// always suceeds and populates the Result and Overflow arguments.
4361  void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4362  SelectionDAG &DAG) const;
4363 
4364  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4365  /// expansion was successful and populates the Result and Overflow arguments.
4366  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4367  SelectionDAG &DAG) const;
4368 
4369  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4370  /// only the first Count elements of the vector are used.
4371  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
4372 
4373  //===--------------------------------------------------------------------===//
4374  // Instruction Emitting Hooks
4375  //
4376 
4377  /// This method should be implemented by targets that mark instructions with
4378  /// the 'usesCustomInserter' flag. These instructions are special in various
4379  /// ways, which require special support to insert. The specified MachineInstr
4380  /// is created but not inserted into any basic blocks, and this method is
4381  /// called to expand it into a sequence of instructions, potentially also
4382  /// creating new basic blocks and control flow.
4383  /// As long as the returned basic block is different (i.e., we created a new
4384  /// one), the custom inserter is free to modify the rest of \p MBB.
4385  virtual MachineBasicBlock *
4386  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4387 
4388  /// This method should be implemented by targets that mark instructions with
4389  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4390  /// instruction selection by target hooks. e.g. To fill in optional defs for
4391  /// ARM 's' setting instructions.
4392  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4393  SDNode *Node) const;
4394 
4395  /// If this function returns true, SelectionDAGBuilder emits a
4396  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4397  virtual bool useLoadStackGuardNode() const {
4398  return false;
4399  }
4400 
4402  const SDLoc &DL) const {
4403  llvm_unreachable("not implemented for this target");
4404  }
4405 
4406  /// Lower TLS global address SDNode for target independent emulated TLS model.
4407  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4408  SelectionDAG &DAG) const;
4409 
4410  /// Expands target specific indirect branch for the case of JumpTable
4411  /// expanasion.
4413  SelectionDAG &DAG) const {
4414  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4415  }
4416 
4417  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4418  // If we're comparing for equality to zero and isCtlzFast is true, expose the
4419  // fact that this can be implemented as a ctlz/srl pair, so that the dag
4420  // combiner can fold the new nodes.
4421  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4422 
4423 private:
4424  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4425  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4426  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4427  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4428 
4429  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4430  SDValue N1, ISD::CondCode Cond,
4431  DAGCombinerInfo &DCI,
4432  const SDLoc &DL) const;
4433 
4434  // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4435  SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
4436  EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
4437  DAGCombinerInfo &DCI, const SDLoc &DL) const;
4438 
4439  SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4440  SDValue CompTargetNode, ISD::CondCode Cond,
4441  DAGCombinerInfo &DCI, const SDLoc &DL,
4442  SmallVectorImpl<SDNode *> &Created) const;
4443  SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4444  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4445  const SDLoc &DL) const;
4446 
4447  SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
4448  SDValue CompTargetNode, ISD::CondCode Cond,
4449  DAGCombinerInfo &DCI, const SDLoc &DL,
4450  SmallVectorImpl<SDNode *> &Created) const;
4451  SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4452  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4453  const SDLoc &DL) const;
4454 };
4455 
4456 /// Given an LLVM IR type and return type attributes, compute the return value
4457 /// EVTs and flags, and optionally also the offsets, if the return value is
4458 /// being lowered to memory.
4461  const TargetLowering &TLI, const DataLayout &DL);
4462 
4463 } // end namespace llvm
4464 
4465 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
uint64_t CallInst * C
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1110
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:793
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:402
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT, bool Value=true)
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
bool isAtomic() const
Return true if this instruction has an AtomicOrdering of unordered or higher.
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:806
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:67
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
Machine Debugify Module
constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
This structure is used to pass arguments to makeLibCall function.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:502
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:324
virtual bool shouldExtendTypeInLibCall(EVT Type) const
Returns true if arguments should be extended in lib calls.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
MakeLibCallOptions & setIsPostTypeLegalization(bool Value=true)
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:252
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Analysis providing profile information.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:249
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:283
static ISD::NodeType getExtendForContent(BooleanContent Content)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isFixedDstAlign() const
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression only when the cost is cheaper...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:392
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset...
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:135
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1098
F(f)
virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const
Should SelectionDAG lower an atomic load of the given kind as a normal LoadSDNode (as opposed to an A...
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const
Return true if creating a shift of the type by the given amount is not profitable.
virtual Register getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const
Return the register ID of the name passed in.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:544
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:665
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
uint64_t High
Align getMinFunctionAlignment() const
Return the minimum function alignment.
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const
Should SelectionDAG lower an atomic store of the given kind as a normal StoreSDNode (as opposed to an...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:127
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
bool hasRetAttr(Attribute::AttrKind Kind) const
Determine whether the return value has the given attribute.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:130
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:273
void * PointerTy
Definition: GenericValue.h:21
bool hasOneUse() const
Return true if there is exactly one use of this node.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
A description of a memory reference used in the backend.
Definition: BitVector.h:959
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Shift and rotation operations.
Definition: ISDOpcodes.h:575
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:165
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:318
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.