LLVM  9.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
52 #include "llvm/Support/Casting.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <climits>
59 #include <cstdint>
60 #include <iterator>
61 #include <map>
62 #include <string>
63 #include <utility>
64 #include <vector>
65 
66 namespace llvm {
67 
68 class BranchProbability;
69 class CCState;
70 class CCValAssign;
71 class Constant;
72 class FastISel;
73 class FunctionLoweringInfo;
74 class GlobalValue;
75 class IntrinsicInst;
76 struct KnownBits;
77 class LLVMContext;
78 class MachineBasicBlock;
79 class MachineFunction;
80 class MachineInstr;
81 class MachineJumpTableInfo;
82 class MachineLoop;
83 class MachineRegisterInfo;
84 class MCContext;
85 class MCExpr;
86 class Module;
87 class TargetRegisterClass;
88 class TargetLibraryInfo;
89 class TargetRegisterInfo;
90 class Value;
91 
92 namespace Sched {
93 
94  enum Preference {
95  None, // No preference
96  Source, // Follow source order.
97  RegPressure, // Scheduling for lowest register pressure.
98  Hybrid, // Scheduling for both latency and register pressure.
99  ILP, // Scheduling for ILP in low register pressure mode.
100  VLIW // Scheduling for VLIW targets.
101  };
102 
103 } // end namespace Sched
104 
105 /// This base class for TargetLowering contains the SelectionDAG-independent
106 /// parts that can be used from the rest of CodeGen.
108 public:
109  /// This enum indicates whether operations are valid for a target, and if not,
110  /// what action should be used to make them valid.
111  enum LegalizeAction : uint8_t {
112  Legal, // The target natively supports this operation.
113  Promote, // This operation should be executed in a larger type.
114  Expand, // Try to expand this to other ops, otherwise use a libcall.
115  LibCall, // Don't try to expand this to other ops, always use a libcall.
116  Custom // Use the LowerOperation hook to implement custom lowering.
117  };
118 
119  /// This enum indicates whether a types are legal for a target, and if not,
120  /// what action should be used to make them valid.
121  enum LegalizeTypeAction : uint8_t {
122  TypeLegal, // The target natively supports this type.
123  TypePromoteInteger, // Replace this integer with a larger one.
124  TypeExpandInteger, // Split this integer into two of half the size.
125  TypeSoftenFloat, // Convert this float to a same size integer type,
126  // if an operation is not supported in target HW.
127  TypeExpandFloat, // Split this float into two of half the size.
128  TypeScalarizeVector, // Replace this one-element vector with its element.
129  TypeSplitVector, // Split this vector into two of half the size.
130  TypeWidenVector, // This vector should be widened into a larger vector.
131  TypePromoteFloat // Replace this float with a larger one.
132  };
133 
134  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135  /// in order to type-legalize it.
136  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 
138  /// Enum that describes how the target represents true/false values.
140  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143  };
144 
145  /// Enum that describes what type of support for selects the target has.
147  ScalarValSelect, // The target supports scalar selects (ex: cmov).
148  ScalarCondVectorVal, // The target supports selects with a scalar condition
149  // and vector values (ex: cmov).
150  VectorMaskSelect // The target supports vector selects with a vector
151  // mask (ex: x86 blends).
152  };
153 
154  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155  /// to, if at all. Exists because different targets have different levels of
156  /// support for these atomic instructions, and also have different options
157  /// w.r.t. what they should expand to.
158  enum class AtomicExpansionKind {
159  None, // Don't expand the instruction.
160  LLSC, // Expand the instruction into loadlinked/storeconditional; used
161  // by ARM/AArch64.
162  LLOnly, // Expand the (load) instruction into just a load-linked, which has
163  // greater atomic guarantees than a normal load.
164  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
198  };
199  using ArgListTy = std::vector<ArgListEntry>;
200 
201  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202  ArgListTy &Args) const {};
203 
205  switch (Content) {
206  case UndefinedBooleanContent:
207  // Extend by adding rubbish bits.
208  return ISD::ANY_EXTEND;
209  case ZeroOrOneBooleanContent:
210  // Extend by adding zero bits.
211  return ISD::ZERO_EXTEND;
212  case ZeroOrNegativeOneBooleanContent:
213  // Extend by copying the sign bit.
214  return ISD::SIGN_EXTEND;
215  }
216  llvm_unreachable("Invalid content kind");
217  }
218 
219  /// NOTE: The TargetMachine owns TLOF.
220  explicit TargetLoweringBase(const TargetMachine &TM);
221  TargetLoweringBase(const TargetLoweringBase &) = delete;
222  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223  virtual ~TargetLoweringBase() = default;
224 
225 protected:
226  /// Initialize all of the actions to default values.
227  void initActions();
228 
229 public:
230  const TargetMachine &getTargetMachine() const { return TM; }
231 
232  virtual bool useSoftFloat() const { return false; }
233 
234  /// Return the pointer type for the given address space, defaults to
235  /// the pointer type from the data layout.
236  /// FIXME: The default needs to be removed once all the code is updated.
237  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239  }
240 
241  /// Return the type for frame index, which is determined by
242  /// the alloca address space specified through the data layout.
243  MVT getFrameIndexTy(const DataLayout &DL) const {
244  return getPointerTy(DL, DL.getAllocaAddrSpace());
245  }
246 
247  /// Return the type for operands of fence.
248  /// TODO: Let fence operands be of i32 type and remove this.
249  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250  return getPointerTy(DL);
251  }
252 
253  /// EVT is not used in-tree, but is used by out-of-tree target.
254  /// A documentation for this function would be nice...
255  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
256 
257  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258  bool LegalTypes = true) const;
259 
260  /// Returns the type to be used for the index operand of:
261  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264  return getPointerTy(DL);
265  }
266 
267  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
268  return true;
269  }
270 
271  /// Return true if it is profitable to convert a select of FP constants into
272  /// a constant pool load whose address depends on the select condition. The
273  /// parameter may be used to differentiate a select with FP compare from
274  /// integer compare.
275  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
276  return true;
277  }
278 
279  /// Return true if multiple condition registers are available.
281  return HasMultipleConditionRegisters;
282  }
283 
284  /// Return true if the target has BitExtract instructions.
285  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
286 
287  /// Return the preferred vector type legalization action.
290  // The default action for one element vectors is to scalarize
291  if (VT.getVectorNumElements() == 1)
292  return TypeScalarizeVector;
293  // The default action for other vectors is to promote
294  return TypePromoteInteger;
295  }
296 
297  // There are two general methods for expanding a BUILD_VECTOR node:
298  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
299  // them together.
300  // 2. Build the vector on the stack and then load it.
301  // If this function returns true, then method (1) will be used, subject to
302  // the constraint that all of the necessary shuffles are legal (as determined
303  // by isShuffleMaskLegal). If this function returns false, then method (2) is
304  // always used. The vector type, and the number of defined values, are
305  // provided.
306  virtual bool
308  unsigned DefinedValues) const {
309  return DefinedValues < 3;
310  }
311 
312  /// Return true if integer divide is usually cheaper than a sequence of
313  /// several shifts, adds, and multiplies for this target.
314  /// The definition of "cheaper" may depend on whether we're optimizing
315  /// for speed or for size.
316  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
317 
318  /// Return true if the target can handle a standalone remainder operation.
319  virtual bool hasStandaloneRem(EVT VT) const {
320  return true;
321  }
322 
323  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
324  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
325  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
326  return false;
327  }
328 
329  /// Reciprocal estimate status values used by the functions below.
330  enum ReciprocalEstimate : int {
331  Unspecified = -1,
332  Disabled = 0,
334  };
335 
336  /// Return a ReciprocalEstimate enum value for a square root of the given type
337  /// based on the function's attributes. If the operation is not overridden by
338  /// the function's attributes, "Unspecified" is returned and target defaults
339  /// are expected to be used for instruction selection.
340  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
341 
342  /// Return a ReciprocalEstimate enum value for a division of the given type
343  /// based on the function's attributes. If the operation is not overridden by
344  /// the function's attributes, "Unspecified" is returned and target defaults
345  /// are expected to be used for instruction selection.
346  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
347 
348  /// Return the refinement step count for a square root of the given type based
349  /// on the function's attributes. If the operation is not overridden by
350  /// the function's attributes, "Unspecified" is returned and target defaults
351  /// are expected to be used for instruction selection.
352  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
353 
354  /// Return the refinement step count for a division of the given type based
355  /// on the function's attributes. If the operation is not overridden by
356  /// the function's attributes, "Unspecified" is returned and target defaults
357  /// are expected to be used for instruction selection.
358  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
359 
360  /// Returns true if target has indicated at least one type should be bypassed.
361  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
362 
363  /// Returns map of slow types for division or remainder with corresponding
364  /// fast types
366  return BypassSlowDivWidths;
367  }
368 
369  /// Return true if Flow Control is an expensive operation that should be
370  /// avoided.
371  bool isJumpExpensive() const { return JumpIsExpensive; }
372 
373  /// Return true if selects are only cheaper than branches if the branch is
374  /// unlikely to be predicted right.
376  return PredictableSelectIsExpensive;
377  }
378 
379  /// If a branch or a select condition is skewed in one direction by more than
380  /// this factor, it is very likely to be predicted correctly.
381  virtual BranchProbability getPredictableBranchThreshold() const;
382 
383  /// Return true if the following transform is beneficial:
384  /// fold (conv (load x)) -> (load (conv*)x)
385  /// On architectures that don't natively support some vector loads
386  /// efficiently, casting the load to a smaller vector of larger types and
387  /// loading is more efficient, however, this can be undone by optimizations in
388  /// dag combiner.
389  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
390  EVT BitcastVT) const {
391  // Don't do if we could do an indexed load on the original type, but not on
392  // the new one.
393  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
394  return true;
395 
396  MVT LoadMVT = LoadVT.getSimpleVT();
397 
398  // Don't bother doing this if it's just going to be promoted again later, as
399  // doing so might interfere with other combines.
400  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
401  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
402  return false;
403 
404  return true;
405  }
406 
407  /// Return true if the following transform is beneficial:
408  /// (store (y (conv x)), y*)) -> (store x, (x*))
409  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
410  // Default to the same logic as loads.
411  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
412  }
413 
414  /// Return true if it is expected to be cheaper to do a store of a non-zero
415  /// vector constant with the given size and type for the address space than to
416  /// store the individual scalar element constants.
417  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
418  unsigned NumElem,
419  unsigned AddrSpace) const {
420  return false;
421  }
422 
423  /// Allow store merging after legalization in addition to before legalization.
424  /// This may catch stores that do not exist earlier (eg, stores created from
425  /// intrinsics).
426  virtual bool mergeStoresAfterLegalization() const { return true; }
427 
428  /// Returns if it's reasonable to merge stores to MemVT size.
429  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
430  const SelectionDAG &DAG) const {
431  return true;
432  }
433 
434  /// Return true if it is cheap to speculate a call to intrinsic cttz.
435  virtual bool isCheapToSpeculateCttz() const {
436  return false;
437  }
438 
439  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
440  virtual bool isCheapToSpeculateCtlz() const {
441  return false;
442  }
443 
444  /// Return true if ctlz instruction is fast.
445  virtual bool isCtlzFast() const {
446  return false;
447  }
448 
449  /// Return true if it is safe to transform an integer-domain bitwise operation
450  /// into the equivalent floating-point operation. This should be set to true
451  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
452  /// type.
453  virtual bool hasBitPreservingFPLogic(EVT VT) const {
454  return false;
455  }
456 
457  /// Return true if it is cheaper to split the store of a merged int val
458  /// from a pair of smaller values into multiple stores.
459  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
460  return false;
461  }
462 
463  /// Return if the target supports combining a
464  /// chain like:
465  /// \code
466  /// %andResult = and %val1, #mask
467  /// %icmpResult = icmp %andResult, 0
468  /// \endcode
469  /// into a single machine instruction of a form like:
470  /// \code
471  /// cc = test %register, #mask
472  /// \endcode
473  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
474  return false;
475  }
476 
477  /// Use bitwise logic to make pairs of compares more efficient. For example:
478  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
479  /// This should be true when it takes more than one instruction to lower
480  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
481  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
482  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
483  return false;
484  }
485 
486  /// Return the preferred operand type if the target has a quick way to compare
487  /// integer values of the given size. Assume that any legal integer type can
488  /// be compared efficiently. Targets may override this to allow illegal wide
489  /// types to return a vector type if there is support to compare that type.
490  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
491  MVT VT = MVT::getIntegerVT(NumBits);
492  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
493  }
494 
495  /// Return true if the target should transform:
496  /// (X & Y) == Y ---> (~X & Y) == 0
497  /// (X & Y) != Y ---> (~X & Y) != 0
498  ///
499  /// This may be profitable if the target has a bitwise and-not operation that
500  /// sets comparison flags. A target may want to limit the transformation based
501  /// on the type of Y or if Y is a constant.
502  ///
503  /// Note that the transform will not occur if Y is known to be a power-of-2
504  /// because a mask and compare of a single bit can be handled by inverting the
505  /// predicate, for example:
506  /// (X & 8) == 8 ---> (X & 8) != 0
507  virtual bool hasAndNotCompare(SDValue Y) const {
508  return false;
509  }
510 
511  /// Return true if the target has a bitwise and-not operation:
512  /// X = ~A & B
513  /// This can be used to simplify select or other instructions.
514  virtual bool hasAndNot(SDValue X) const {
515  // If the target has the more complex version of this operation, assume that
516  // it has this operation too.
517  return hasAndNotCompare(X);
518  }
519 
520  /// There are two ways to clear extreme bits (either low or high):
521  /// Mask: x & (-1 << y) (the instcombine canonical form)
522  /// Shifts: x >> y << y
523  /// Return true if the variant with 2 shifts is preferred.
524  /// Return false if there is no preference.
526  // By default, let's assume that no one prefers shifts.
527  return false;
528  }
529 
530  /// Should we tranform the IR-optimal check for whether given truncation
531  /// down into KeptBits would be truncating or not:
532  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
533  /// Into it's more traditional form:
534  /// ((%x << C) a>> C) dstcond %x
535  /// Return true if we should transform.
536  /// Return false if there is no preference.
538  unsigned KeptBits) const {
539  // By default, let's assume that no one prefers shifts.
540  return false;
541  }
542 
543  /// Return true if the target wants to use the optimization that
544  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
545  /// promotedInst1(...(promotedInstN(ext(load)))).
546  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
547 
548  /// Return true if the target can combine store(extractelement VectorTy,
549  /// Idx).
550  /// \p Cost[out] gives the cost of that transformation when this is true.
551  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
552  unsigned &Cost) const {
553  return false;
554  }
555 
556  /// Return true if inserting a scalar into a variable element of an undef
557  /// vector is more efficiently handled by splatting the scalar instead.
558  virtual bool shouldSplatInsEltVarIndex(EVT) const {
559  return false;
560  }
561 
562  /// Return true if target supports floating point exceptions.
564  return HasFloatingPointExceptions;
565  }
566 
567  /// Return true if target always beneficiates from combining into FMA for a
568  /// given value type. This must typically return false on targets where FMA
569  /// takes more cycles to execute than FADD.
570  virtual bool enableAggressiveFMAFusion(EVT VT) const {
571  return false;
572  }
573 
574  /// Return the ValueType of the result of SETCC operations.
575  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
576  EVT VT) const;
577 
578  /// Return the ValueType for comparison libcalls. Comparions libcalls include
579  /// floating point comparion calls, and Ordered/Unordered check calls on
580  /// floating point numbers.
581  virtual
582  MVT::SimpleValueType getCmpLibcallReturnType() const;
583 
584  /// For targets without i1 registers, this gives the nature of the high-bits
585  /// of boolean values held in types wider than i1.
586  ///
587  /// "Boolean values" are special true/false values produced by nodes like
588  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
589  /// Not to be confused with general values promoted from i1. Some cpus
590  /// distinguish between vectors of boolean and scalars; the isVec parameter
591  /// selects between the two kinds. For example on X86 a scalar boolean should
592  /// be zero extended from i1, while the elements of a vector of booleans
593  /// should be sign extended from i1.
594  ///
595  /// Some cpus also treat floating point types the same way as they treat
596  /// vectors instead of the way they treat scalars.
597  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
598  if (isVec)
599  return BooleanVectorContents;
600  return isFloat ? BooleanFloatContents : BooleanContents;
601  }
602 
604  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
605  }
606 
607  /// Return target scheduling preference.
609  return SchedPreferenceInfo;
610  }
611 
612  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
613  /// for different nodes. This function returns the preference (or none) for
614  /// the given node.
616  return Sched::None;
617  }
618 
619  /// Return the register class that should be used for the specified value
620  /// type.
621  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
622  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
623  assert(RC && "This value type is not natively supported!");
624  return RC;
625  }
626 
627  /// Return the 'representative' register class for the specified value
628  /// type.
629  ///
630  /// The 'representative' register class is the largest legal super-reg
631  /// register class for the register class of the value type. For example, on
632  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
633  /// register class is GR64 on x86_64.
634  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
635  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
636  return RC;
637  }
638 
639  /// Return the cost of the 'representative' register class for the specified
640  /// value type.
641  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
642  return RepRegClassCostForVT[VT.SimpleTy];
643  }
644 
645  /// Return true if the target has native support for the specified value type.
646  /// This means that it has a register that directly holds it without
647  /// promotions or expansions.
648  bool isTypeLegal(EVT VT) const {
649  assert(!VT.isSimple() ||
650  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
651  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
652  }
653 
655  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
656  /// that indicates how instruction selection should deal with the type.
657  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
658 
659  public:
661  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
662  TypeLegal);
663  }
664 
666  return ValueTypeActions[VT.SimpleTy];
667  }
668 
670  ValueTypeActions[VT.SimpleTy] = Action;
671  }
672  };
673 
675  return ValueTypeActions;
676  }
677 
678  /// Return how we should legalize values of this type, either it is already
679  /// legal (return 'Legal') or we need to promote it to a larger type (return
680  /// 'Promote'), or we need to expand it into multiple registers of smaller
681  /// integer type (return 'Expand'). 'Custom' is not an option.
683  return getTypeConversion(Context, VT).first;
684  }
686  return ValueTypeActions.getTypeAction(VT);
687  }
688 
689  /// For types supported by the target, this is an identity function. For
690  /// types that must be promoted to larger types, this returns the larger type
691  /// to promote to. For integer types that are larger than the largest integer
692  /// register, this contains one step in the expansion to get to the smaller
693  /// register. For illegal floating point types, this returns the integer type
694  /// to transform to.
695  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
696  return getTypeConversion(Context, VT).second;
697  }
698 
699  /// For types supported by the target, this is an identity function. For
700  /// types that must be expanded (i.e. integer types that are larger than the
701  /// largest integer register or illegal floating point types), this returns
702  /// the largest legal type it will be expanded to.
703  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
704  assert(!VT.isVector());
705  while (true) {
706  switch (getTypeAction(Context, VT)) {
707  case TypeLegal:
708  return VT;
709  case TypeExpandInteger:
710  VT = getTypeToTransformTo(Context, VT);
711  break;
712  default:
713  llvm_unreachable("Type is not legal nor is it to be expanded!");
714  }
715  }
716  }
717 
718  /// Vector types are broken down into some number of legal first class types.
719  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
720  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
721  /// turns into 4 EVT::i32 values with both PPC and X86.
722  ///
723  /// This method returns the number of registers needed, and the VT for each
724  /// register. It also returns the VT and quantity of the intermediate values
725  /// before they are promoted/expanded.
726  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
727  EVT &IntermediateVT,
728  unsigned &NumIntermediates,
729  MVT &RegisterVT) const;
730 
731  /// Certain targets such as MIPS require that some types such as vectors are
732  /// always broken down into scalars in some contexts. This occurs even if the
733  /// vector type is legal.
735  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
736  unsigned &NumIntermediates, MVT &RegisterVT) const {
737  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
738  RegisterVT);
739  }
740 
741  struct IntrinsicInfo {
742  unsigned opc = 0; // target opcode
743  EVT memVT; // memory VT
744 
745  // value representing memory location
747 
748  int offset = 0; // offset off of ptrVal
749  unsigned size = 0; // the size of the memory location
750  // (taken from memVT if zero)
751  unsigned align = 1; // alignment
752 
754  IntrinsicInfo() = default;
755  };
756 
757  /// Given an intrinsic, checks if on the target the intrinsic will need to map
758  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
759  /// true and store the intrinsic information into the IntrinsicInfo that was
760  /// passed to the function.
761  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
762  MachineFunction &,
763  unsigned /*Intrinsic*/) const {
764  return false;
765  }
766 
767  /// Returns true if the target can instruction select the specified FP
768  /// immediate natively. If false, the legalizer will materialize the FP
769  /// immediate as a load from a constant pool.
770  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
771  return false;
772  }
773 
774  /// Targets can use this to indicate that they only support *some*
775  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
776  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
777  /// legal.
778  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
779  return true;
780  }
781 
782  /// Returns true if the operation can trap for the value type.
783  ///
784  /// VT must be a legal type. By default, we optimistically assume most
785  /// operations don't trap except for integer divide and remainder.
786  virtual bool canOpTrap(unsigned Op, EVT VT) const;
787 
788  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
789  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
790  /// constant pool entry.
791  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
792  EVT /*VT*/) const {
793  return false;
794  }
795 
796  /// Return how this operation should be treated: either it is legal, needs to
797  /// be promoted to a larger size, needs to be expanded to some other code
798  /// sequence, or the target has a custom expander for it.
799  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
800  if (VT.isExtended()) return Expand;
801  // If a target-specific SDNode requires legalization, require the target
802  // to provide custom legalization for it.
803  if (Op >= array_lengthof(OpActions[0])) return Custom;
804  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
805  }
806 
807  /// Custom method defined by each target to indicate if an operation which
808  /// may require a scale is supported natively by the target.
809  /// If not, the operation is illegal.
810  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
811  unsigned Scale) const {
812  return false;
813  }
814 
815  /// Some fixed point operations may be natively supported by the target but
816  /// only for specific scales. This method allows for checking
817  /// if the width is supported by the target for a given operation that may
818  /// depend on scale.
820  unsigned Scale) const {
821  auto Action = getOperationAction(Op, VT);
822  if (Action != Legal)
823  return Action;
824 
825  // This operation is supported in this type but may only work on specific
826  // scales.
827  bool Supported;
828  switch (Op) {
829  default:
830  llvm_unreachable("Unexpected fixed point operation.");
831  case ISD::SMULFIX:
832  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
833  break;
834  }
835 
836  return Supported ? Action : Expand;
837  }
838 
840  unsigned EqOpc;
841  switch (Op) {
842  default: llvm_unreachable("Unexpected FP pseudo-opcode");
843  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
844  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
845  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
846  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
847  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
848  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
849  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
850  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
851  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
852  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
853  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
854  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
855  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
856  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
857  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
858  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
859  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
860  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
861  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
862  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
863  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
864  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
865  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
866  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
867  }
868 
869  auto Action = getOperationAction(EqOpc, VT);
870 
871  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
872  // For now, we just expand for those cases.
873  if (Action != Legal)
874  Action = Expand;
875 
876  return Action;
877  }
878 
879  /// Return true if the specified operation is legal on this target or can be
880  /// made legal with custom lowering. This is used to help guide high-level
881  /// lowering decisions.
882  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
883  return (VT == MVT::Other || isTypeLegal(VT)) &&
884  (getOperationAction(Op, VT) == Legal ||
885  getOperationAction(Op, VT) == Custom);
886  }
887 
888  /// Return true if the specified operation is legal on this target or can be
889  /// made legal using promotion. This is used to help guide high-level lowering
890  /// decisions.
891  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
892  return (VT == MVT::Other || isTypeLegal(VT)) &&
893  (getOperationAction(Op, VT) == Legal ||
894  getOperationAction(Op, VT) == Promote);
895  }
896 
897  /// Return true if the specified operation is legal on this target or can be
898  /// made legal with custom lowering or using promotion. This is used to help
899  /// guide high-level lowering decisions.
900  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
901  return (VT == MVT::Other || isTypeLegal(VT)) &&
902  (getOperationAction(Op, VT) == Legal ||
903  getOperationAction(Op, VT) == Custom ||
904  getOperationAction(Op, VT) == Promote);
905  }
906 
907  /// Return true if the operation uses custom lowering, regardless of whether
908  /// the type is legal or not.
909  bool isOperationCustom(unsigned Op, EVT VT) const {
910  return getOperationAction(Op, VT) == Custom;
911  }
912 
913  /// Return true if lowering to a jump table is allowed.
914  virtual bool areJTsAllowed(const Function *Fn) const {
915  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
916  return false;
917 
918  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
919  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
920  }
921 
922  /// Check whether the range [Low,High] fits in a machine word.
923  bool rangeFitsInWord(const APInt &Low, const APInt &High,
924  const DataLayout &DL) const {
925  // FIXME: Using the pointer type doesn't seem ideal.
926  uint64_t BW = DL.getIndexSizeInBits(0u);
927  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
928  return Range <= BW;
929  }
930 
931  /// Return true if lowering to a jump table is suitable for a set of case
932  /// clusters which may contain \p NumCases cases, \p Range range of values.
933  /// FIXME: This function check the maximum table size and density, but the
934  /// minimum size is not checked. It would be nice if the minimum size is
935  /// also combined within this function. Currently, the minimum size check is
936  /// performed in findJumpTable() in SelectionDAGBuiler and
937  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
938  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
939  uint64_t Range) const {
940  const bool OptForSize = SI->getParent()->getParent()->optForSize();
941  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
942  const unsigned MaxJumpTableSize =
943  OptForSize || getMaximumJumpTableSize() == 0
944  ? UINT_MAX
945  : getMaximumJumpTableSize();
946  // Check whether a range of clusters is dense enough for a jump table.
947  if (Range <= MaxJumpTableSize &&
948  (NumCases * 100 >= Range * MinDensity)) {
949  return true;
950  }
951  return false;
952  }
953 
954  /// Return true if lowering to a bit test is suitable for a set of case
955  /// clusters which contains \p NumDests unique destinations, \p Low and
956  /// \p High as its lowest and highest case values, and expects \p NumCmps
957  /// case value comparisons. Check if the number of destinations, comparison
958  /// metric, and range are all suitable.
959  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
960  const APInt &Low, const APInt &High,
961  const DataLayout &DL) const {
962  // FIXME: I don't think NumCmps is the correct metric: a single case and a
963  // range of cases both require only one branch to lower. Just looking at the
964  // number of clusters and destinations should be enough to decide whether to
965  // build bit tests.
966 
967  // To lower a range with bit tests, the range must fit the bitwidth of a
968  // machine word.
969  if (!rangeFitsInWord(Low, High, DL))
970  return false;
971 
972  // Decide whether it's profitable to lower this range with bit tests. Each
973  // destination requires a bit test and branch, and there is an overall range
974  // check branch. For a small number of clusters, separate comparisons might
975  // be cheaper, and for many destinations, splitting the range might be
976  // better.
977  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
978  (NumDests == 3 && NumCmps >= 6);
979  }
980 
981  /// Return true if the specified operation is illegal on this target or
982  /// unlikely to be made legal with custom lowering. This is used to help guide
983  /// high-level lowering decisions.
984  bool isOperationExpand(unsigned Op, EVT VT) const {
985  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
986  }
987 
988  /// Return true if the specified operation is legal on this target.
989  bool isOperationLegal(unsigned Op, EVT VT) const {
990  return (VT == MVT::Other || isTypeLegal(VT)) &&
991  getOperationAction(Op, VT) == Legal;
992  }
993 
994  /// Return how this load with extension should be treated: either it is legal,
995  /// needs to be promoted to a larger size, needs to be expanded to some other
996  /// code sequence, or the target has a custom expander for it.
998  EVT MemVT) const {
999  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1000  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1001  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1002  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1003  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1004  unsigned Shift = 4 * ExtType;
1005  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1006  }
1007 
1008  /// Return true if the specified load with extension is legal on this target.
1009  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1010  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1011  }
1012 
1013  /// Return true if the specified load with extension is legal or custom
1014  /// on this target.
1015  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1016  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1017  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1018  }
1019 
1020  /// Return how this store with truncation should be treated: either it is
1021  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1022  /// other code sequence, or the target has a custom expander for it.
1024  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1025  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1026  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1027  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1028  "Table isn't big enough!");
1029  return TruncStoreActions[ValI][MemI];
1030  }
1031 
1032  /// Return true if the specified store with truncation is legal on this
1033  /// target.
1034  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1035  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1036  }
1037 
1038  /// Return true if the specified store with truncation has solution on this
1039  /// target.
1040  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1041  return isTypeLegal(ValVT) &&
1042  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1043  getTruncStoreAction(ValVT, MemVT) == Custom);
1044  }
1045 
1046  /// Return how the indexed load should be treated: either it is legal, needs
1047  /// to be promoted to a larger size, needs to be expanded to some other code
1048  /// sequence, or the target has a custom expander for it.
1050  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1051  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1052  "Table isn't big enough!");
1053  unsigned Ty = (unsigned)VT.SimpleTy;
1054  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1055  }
1056 
1057  /// Return true if the specified indexed load is legal on this target.
1058  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1059  return VT.isSimple() &&
1060  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1061  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1062  }
1063 
1064  /// Return how the indexed store should be treated: either it is legal, needs
1065  /// to be promoted to a larger size, needs to be expanded to some other code
1066  /// sequence, or the target has a custom expander for it.
1068  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1069  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1070  "Table isn't big enough!");
1071  unsigned Ty = (unsigned)VT.SimpleTy;
1072  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1073  }
1074 
1075  /// Return true if the specified indexed load is legal on this target.
1076  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1077  return VT.isSimple() &&
1078  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1079  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1080  }
1081 
1082  /// Return how the condition code should be treated: either it is legal, needs
1083  /// to be expanded to some other code sequence, or the target has a custom
1084  /// expander for it.
1087  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1088  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1089  "Table isn't big enough!");
1090  // See setCondCodeAction for how this is encoded.
1091  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1092  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1093  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1094  assert(Action != Promote && "Can't promote condition code!");
1095  return Action;
1096  }
1097 
1098  /// Return true if the specified condition code is legal on this target.
1099  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1100  return getCondCodeAction(CC, VT) == Legal;
1101  }
1102 
1103  /// Return true if the specified condition code is legal or custom on this
1104  /// target.
1106  return getCondCodeAction(CC, VT) == Legal ||
1107  getCondCodeAction(CC, VT) == Custom;
1108  }
1109 
1110  /// If the action for this operation is to promote, this method returns the
1111  /// ValueType to promote to.
1112  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1113  assert(getOperationAction(Op, VT) == Promote &&
1114  "This operation isn't promoted!");
1115 
1116  // See if this has an explicit type specified.
1117  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1118  MVT::SimpleValueType>::const_iterator PTTI =
1119  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1120  if (PTTI != PromoteToType.end()) return PTTI->second;
1121 
1122  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1123  "Cannot autopromote this type, add it with AddPromotedToType.");
1124 
1125  MVT NVT = VT;
1126  do {
1127  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1128  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1129  "Didn't find type to promote to!");
1130  } while (!isTypeLegal(NVT) ||
1131  getOperationAction(Op, NVT) == Promote);
1132  return NVT;
1133  }
1134 
1135  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1136  /// operations except for the pointer size. If AllowUnknown is true, this
1137  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1138  /// otherwise it will assert.
1140  bool AllowUnknown = false) const {
1141  // Lower scalar pointers to native pointer types.
1142  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1143  return getPointerTy(DL, PTy->getAddressSpace());
1144 
1145  if (Ty->isVectorTy()) {
1146  VectorType *VTy = cast<VectorType>(Ty);
1147  Type *Elm = VTy->getElementType();
1148  // Lower vectors of pointers to native pointer types.
1149  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1150  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1151  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1152  }
1153 
1154  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1155  VTy->getNumElements());
1156  }
1157  return EVT::getEVT(Ty, AllowUnknown);
1158  }
1159 
1160  /// Return the MVT corresponding to this LLVM type. See getValueType.
1162  bool AllowUnknown = false) const {
1163  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1164  }
1165 
1166  /// Return the desired alignment for ByVal or InAlloca aggregate function
1167  /// arguments in the caller parameter area. This is the actual alignment, not
1168  /// its logarithm.
1169  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1170 
1171  /// Return the type of registers that this ValueType will eventually require.
1173  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1174  return RegisterTypeForVT[VT.SimpleTy];
1175  }
1176 
1177  /// Return the type of registers that this ValueType will eventually require.
1178  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1179  if (VT.isSimple()) {
1180  assert((unsigned)VT.getSimpleVT().SimpleTy <
1181  array_lengthof(RegisterTypeForVT));
1182  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1183  }
1184  if (VT.isVector()) {
1185  EVT VT1;
1186  MVT RegisterVT;
1187  unsigned NumIntermediates;
1188  (void)getVectorTypeBreakdown(Context, VT, VT1,
1189  NumIntermediates, RegisterVT);
1190  return RegisterVT;
1191  }
1192  if (VT.isInteger()) {
1193  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1194  }
1195  llvm_unreachable("Unsupported extended type!");
1196  }
1197 
1198  /// Return the number of registers that this ValueType will eventually
1199  /// require.
1200  ///
1201  /// This is one for any types promoted to live in larger registers, but may be
1202  /// more than one for types (like i64) that are split into pieces. For types
1203  /// like i140, which are first promoted then expanded, it is the number of
1204  /// registers needed to hold all the bits of the original type. For an i140
1205  /// on a 32 bit machine this means 5 registers.
1206  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1207  if (VT.isSimple()) {
1208  assert((unsigned)VT.getSimpleVT().SimpleTy <
1209  array_lengthof(NumRegistersForVT));
1210  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1211  }
1212  if (VT.isVector()) {
1213  EVT VT1;
1214  MVT VT2;
1215  unsigned NumIntermediates;
1216  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1217  }
1218  if (VT.isInteger()) {
1219  unsigned BitWidth = VT.getSizeInBits();
1220  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1221  return (BitWidth + RegWidth - 1) / RegWidth;
1222  }
1223  llvm_unreachable("Unsupported extended type!");
1224  }
1225 
1226  /// Certain combinations of ABIs, Targets and features require that types
1227  /// are legal for some operations and not for other operations.
1228  /// For MIPS all vector types must be passed through the integer register set.
1230  CallingConv::ID CC, EVT VT) const {
1231  return getRegisterType(Context, VT);
1232  }
1233 
1234  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1235  /// this occurs when a vector type is used, as vector are passed through the
1236  /// integer register set.
1237  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1238  CallingConv::ID CC,
1239  EVT VT) const {
1240  return getNumRegisters(Context, VT);
1241  }
1242 
1243  /// Certain targets have context senstive alignment requirements, where one
1244  /// type has the alignment requirement of another type.
1245  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1246  DataLayout DL) const {
1247  return DL.getABITypeAlignment(ArgTy);
1248  }
1249 
1250  /// If true, then instruction selection should seek to shrink the FP constant
1251  /// of the specified type to a smaller type in order to save space and / or
1252  /// reduce runtime.
1253  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1254 
1255  /// Return true if it is profitable to reduce a load to a smaller type.
1256  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1258  EVT NewVT) const {
1259  // By default, assume that it is cheaper to extract a subvector from a wide
1260  // vector load rather than creating multiple narrow vector loads.
1261  if (NewVT.isVector() && !Load->hasOneUse())
1262  return false;
1263 
1264  return true;
1265  }
1266 
1267  /// When splitting a value of the specified type into parts, does the Lo
1268  /// or Hi part come first? This usually follows the endianness, except
1269  /// for ppcf128, where the Hi part always comes first.
1270  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1271  return DL.isBigEndian() || VT == MVT::ppcf128;
1272  }
1273 
1274  /// If true, the target has custom DAG combine transformations that it can
1275  /// perform for the specified node.
1277  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1278  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1279  }
1280 
1281  unsigned getGatherAllAliasesMaxDepth() const {
1282  return GatherAllAliasesMaxDepth;
1283  }
1284 
1285  /// Returns the size of the platform's va_list object.
1286  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1287  return getPointerTy(DL).getSizeInBits();
1288  }
1289 
1290  /// Get maximum # of store operations permitted for llvm.memset
1291  ///
1292  /// This function returns the maximum number of store operations permitted
1293  /// to replace a call to llvm.memset. The value is set by the target at the
1294  /// performance threshold for such a replacement. If OptSize is true,
1295  /// return the limit for functions that have OptSize attribute.
1296  unsigned getMaxStoresPerMemset(bool OptSize) const {
1297  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1298  }
1299 
1300  /// Get maximum # of store operations permitted for llvm.memcpy
1301  ///
1302  /// This function returns the maximum number of store operations permitted
1303  /// to replace a call to llvm.memcpy. The value is set by the target at the
1304  /// performance threshold for such a replacement. If OptSize is true,
1305  /// return the limit for functions that have OptSize attribute.
1306  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1307  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1308  }
1309 
1310  /// \brief Get maximum # of store operations to be glued together
1311  ///
1312  /// This function returns the maximum number of store operations permitted
1313  /// to glue together during lowering of llvm.memcpy. The value is set by
1314  // the target at the performance threshold for such a replacement.
1315  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1316  return MaxGluedStoresPerMemcpy;
1317  }
1318 
1319  /// Get maximum # of load operations permitted for memcmp
1320  ///
1321  /// This function returns the maximum number of load operations permitted
1322  /// to replace a call to memcmp. The value is set by the target at the
1323  /// performance threshold for such a replacement. If OptSize is true,
1324  /// return the limit for functions that have OptSize attribute.
1325  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1326  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1327  }
1328 
1329  /// For memcmp expansion when the memcmp result is only compared equal or
1330  /// not-equal to 0, allow up to this number of load pairs per block. As an
1331  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1332  /// a0 = load2bytes &a[0]
1333  /// b0 = load2bytes &b[0]
1334  /// a2 = load1byte &a[2]
1335  /// b2 = load1byte &b[2]
1336  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1337  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1338  return 1;
1339  }
1340 
1341  /// Get maximum # of store operations permitted for llvm.memmove
1342  ///
1343  /// This function returns the maximum number of store operations permitted
1344  /// to replace a call to llvm.memmove. The value is set by the target at the
1345  /// performance threshold for such a replacement. If OptSize is true,
1346  /// return the limit for functions that have OptSize attribute.
1347  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1348  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1349  }
1350 
1351  /// Determine if the target supports unaligned memory accesses.
1352  ///
1353  /// This function returns true if the target allows unaligned memory accesses
1354  /// of the specified type in the given address space. If true, it also returns
1355  /// whether the unaligned memory access is "fast" in the last argument by
1356  /// reference. This is used, for example, in situations where an array
1357  /// copy/move/set is converted to a sequence of store operations. Its use
1358  /// helps to ensure that such replacements don't generate code that causes an
1359  /// alignment error (trap) on the target machine.
1361  unsigned AddrSpace = 0,
1362  unsigned Align = 1,
1363  bool * /*Fast*/ = nullptr) const {
1364  return false;
1365  }
1366 
1367  /// Return true if the target supports a memory access of this type for the
1368  /// given address space and alignment. If the access is allowed, the optional
1369  /// final parameter returns if the access is also fast (as defined by the
1370  /// target).
1371  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1372  unsigned AddrSpace = 0, unsigned Alignment = 1,
1373  bool *Fast = nullptr) const;
1374 
1375  /// Returns the target specific optimal type for load and store operations as
1376  /// a result of memset, memcpy, and memmove lowering.
1377  ///
1378  /// If DstAlign is zero that means it's safe to destination alignment can
1379  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1380  /// a need to check it against alignment requirement, probably because the
1381  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1382  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1383  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1384  /// does not need to be loaded. It returns EVT::Other if the type should be
1385  /// determined using generic target-independent logic.
1386  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1387  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1388  bool /*IsMemset*/,
1389  bool /*ZeroMemset*/,
1390  bool /*MemcpyStrSrc*/,
1391  MachineFunction &/*MF*/) const {
1392  return MVT::Other;
1393  }
1394 
1395  /// Returns true if it's safe to use load / store of the specified type to
1396  /// expand memcpy / memset inline.
1397  ///
1398  /// This is mostly true for all types except for some special cases. For
1399  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1400  /// fstpl which also does type conversion. Note the specified type doesn't
1401  /// have to be legal as the hook is used before type legalization.
1402  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1403 
1404  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1405  bool usesUnderscoreSetJmp() const {
1406  return UseUnderscoreSetJmp;
1407  }
1408 
1409  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1410  bool usesUnderscoreLongJmp() const {
1411  return UseUnderscoreLongJmp;
1412  }
1413 
1414  /// Return lower limit for number of blocks in a jump table.
1415  virtual unsigned getMinimumJumpTableEntries() const;
1416 
1417  /// Return lower limit of the density in a jump table.
1418  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1419 
1420  /// Return upper limit for number of entries in a jump table.
1421  /// Zero if no limit.
1422  unsigned getMaximumJumpTableSize() const;
1423 
1424  virtual bool isJumpTableRelative() const {
1425  return TM.isPositionIndependent();
1426  }
1427 
1428  /// If a physical register, this specifies the register that
1429  /// llvm.savestack/llvm.restorestack should save and restore.
1431  return StackPointerRegisterToSaveRestore;
1432  }
1433 
1434  /// If a physical register, this returns the register that receives the
1435  /// exception address on entry to an EH pad.
1436  virtual unsigned
1437  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1438  // 0 is guaranteed to be the NoRegister value on all targets
1439  return 0;
1440  }
1441 
1442  /// If a physical register, this returns the register that receives the
1443  /// exception typeid on entry to a landing pad.
1444  virtual unsigned
1445  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1446  // 0 is guaranteed to be the NoRegister value on all targets
1447  return 0;
1448  }
1449 
1450  virtual bool needsFixedCatchObjects() const {
1451  report_fatal_error("Funclet EH is not implemented for this target");
1452  }
1453 
1454  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1455  /// 200)
1456  unsigned getJumpBufSize() const {
1457  return JumpBufSize;
1458  }
1459 
1460  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1461  /// is 0)
1462  unsigned getJumpBufAlignment() const {
1463  return JumpBufAlignment;
1464  }
1465 
1466  /// Return the minimum stack alignment of an argument.
1467  unsigned getMinStackArgumentAlignment() const {
1468  return MinStackArgumentAlignment;
1469  }
1470 
1471  /// Return the minimum function alignment.
1472  unsigned getMinFunctionAlignment() const {
1473  return MinFunctionAlignment;
1474  }
1475 
1476  /// Return the preferred function alignment.
1477  unsigned getPrefFunctionAlignment() const {
1478  return PrefFunctionAlignment;
1479  }
1480 
1481  /// Return the preferred loop alignment.
1482  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1483  return PrefLoopAlignment;
1484  }
1485 
1486  /// Should loops be aligned even when the function is marked OptSize (but not
1487  /// MinSize).
1488  virtual bool alignLoopsWithOptSize() const {
1489  return false;
1490  }
1491 
1492  /// If the target has a standard location for the stack protector guard,
1493  /// returns the address of that location. Otherwise, returns nullptr.
1494  /// DEPRECATED: please override useLoadStackGuardNode and customize
1495  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1496  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1497 
1498  /// Inserts necessary declarations for SSP (stack protection) purpose.
1499  /// Should be used only when getIRStackGuard returns nullptr.
1500  virtual void insertSSPDeclarations(Module &M) const;
1501 
1502  /// Return the variable that's previously inserted by insertSSPDeclarations,
1503  /// if any, otherwise return nullptr. Should be used only when
1504  /// getIRStackGuard returns nullptr.
1505  virtual Value *getSDagStackGuard(const Module &M) const;
1506 
1507  /// If this function returns true, stack protection checks should XOR the
1508  /// frame pointer (or whichever pointer is used to address locals) into the
1509  /// stack guard value before checking it. getIRStackGuard must return nullptr
1510  /// if this returns true.
1511  virtual bool useStackGuardXorFP() const { return false; }
1512 
1513  /// If the target has a standard stack protection check function that
1514  /// performs validation and error handling, returns the function. Otherwise,
1515  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1516  /// Should be used only when getIRStackGuard returns nullptr.
1517  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1518 
1519 protected:
1520  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1521  bool UseTLS) const;
1522 
1523 public:
1524  /// Returns the target-specific address of the unsafe stack pointer.
1525  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1526 
1527  /// Returns the name of the symbol used to emit stack probes or the empty
1528  /// string if not applicable.
1530  return "";
1531  }
1532 
1533  /// Returns true if a cast between SrcAS and DestAS is a noop.
1534  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1535  return false;
1536  }
1537 
1538  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1539  /// are happy to sink it into basic blocks.
1540  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1541  return isNoopAddrSpaceCast(SrcAS, DestAS);
1542  }
1543 
1544  /// Return true if the pointer arguments to CI should be aligned by aligning
1545  /// the object whose address is being passed. If so then MinSize is set to the
1546  /// minimum size the object must be to be aligned and PrefAlign is set to the
1547  /// preferred alignment.
1548  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1549  unsigned & /*PrefAlign*/) const {
1550  return false;
1551  }
1552 
1553  //===--------------------------------------------------------------------===//
1554  /// \name Helpers for TargetTransformInfo implementations
1555  /// @{
1556 
1557  /// Get the ISD node that corresponds to the Instruction class opcode.
1558  int InstructionOpcodeToISD(unsigned Opcode) const;
1559 
1560  /// Estimate the cost of type-legalization and the legalized type.
1561  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1562  Type *Ty) const;
1563 
1564  /// @}
1565 
1566  //===--------------------------------------------------------------------===//
1567  /// \name Helpers for atomic expansion.
1568  /// @{
1569 
1570  /// Returns the maximum atomic operation size (in bits) supported by
1571  /// the backend. Atomic operations greater than this size (as well
1572  /// as ones that are not naturally aligned), will be expanded by
1573  /// AtomicExpandPass into an __atomic_* library call.
1575  return MaxAtomicSizeInBitsSupported;
1576  }
1577 
1578  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1579  /// the backend supports. Any smaller operations are widened in
1580  /// AtomicExpandPass.
1581  ///
1582  /// Note that *unlike* operations above the maximum size, atomic ops
1583  /// are still natively supported below the minimum; they just
1584  /// require a more complex expansion.
1585  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1586 
1587  /// Whether the target supports unaligned atomic operations.
1588  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1589 
1590  /// Whether AtomicExpandPass should automatically insert fences and reduce
1591  /// ordering for this atomic. This should be true for most architectures with
1592  /// weak memory ordering. Defaults to false.
1593  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1594  return false;
1595  }
1596 
1597  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1598  /// corresponding pointee type. This may entail some non-trivial operations to
1599  /// truncate or reconstruct types that will be illegal in the backend. See
1600  /// ARMISelLowering for an example implementation.
1601  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1602  AtomicOrdering Ord) const {
1603  llvm_unreachable("Load linked unimplemented on this target");
1604  }
1605 
1606  /// Perform a store-conditional operation to Addr. Return the status of the
1607  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1608  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1609  Value *Addr, AtomicOrdering Ord) const {
1610  llvm_unreachable("Store conditional unimplemented on this target");
1611  }
1612 
1613  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1614  /// represents the core LL/SC loop which will be lowered at a late stage by
1615  /// the backend.
1617  AtomicRMWInst *AI,
1618  Value *AlignedAddr, Value *Incr,
1619  Value *Mask, Value *ShiftAmt,
1620  AtomicOrdering Ord) const {
1621  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1622  }
1623 
1624  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1625  /// represents the core LL/SC loop which will be lowered at a late stage by
1626  /// the backend.
1628  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1629  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1630  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1631  }
1632 
1633  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1634  /// It is called by AtomicExpandPass before expanding an
1635  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1636  /// if shouldInsertFencesForAtomic returns true.
1637  ///
1638  /// Inst is the original atomic instruction, prior to other expansions that
1639  /// may be performed.
1640  ///
1641  /// This function should either return a nullptr, or a pointer to an IR-level
1642  /// Instruction*. Even complex fence sequences can be represented by a
1643  /// single Instruction* through an intrinsic to be lowered later.
1644  /// Backends should override this method to produce target-specific intrinsic
1645  /// for their fences.
1646  /// FIXME: Please note that the default implementation here in terms of
1647  /// IR-level fences exists for historical/compatibility reasons and is
1648  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1649  /// consistency. For example, consider the following example:
1650  /// atomic<int> x = y = 0;
1651  /// int r1, r2, r3, r4;
1652  /// Thread 0:
1653  /// x.store(1);
1654  /// Thread 1:
1655  /// y.store(1);
1656  /// Thread 2:
1657  /// r1 = x.load();
1658  /// r2 = y.load();
1659  /// Thread 3:
1660  /// r3 = y.load();
1661  /// r4 = x.load();
1662  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1663  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1664  /// IR-level fences can prevent it.
1665  /// @{
1667  AtomicOrdering Ord) const {
1668  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1669  return Builder.CreateFence(Ord);
1670  else
1671  return nullptr;
1672  }
1673 
1675  Instruction *Inst,
1676  AtomicOrdering Ord) const {
1677  if (isAcquireOrStronger(Ord))
1678  return Builder.CreateFence(Ord);
1679  else
1680  return nullptr;
1681  }
1682  /// @}
1683 
1684  // Emits code that executes when the comparison result in the ll/sc
1685  // expansion of a cmpxchg instruction is such that the store-conditional will
1686  // not execute. This makes it possible to balance out the load-linked with
1687  // a dedicated instruction, if desired.
1688  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1689  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1690  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1691 
1692  /// Returns true if the given (atomic) store should be expanded by the
1693  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1695  return false;
1696  }
1697 
1698  /// Returns true if arguments should be sign-extended in lib calls.
1699  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1700  return IsSigned;
1701  }
1702 
1703  /// Returns how the given (atomic) load should be expanded by the
1704  /// IR-level AtomicExpand pass.
1707  }
1708 
1709  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1710  /// AtomicExpand pass.
1711  virtual AtomicExpansionKind
1714  }
1715 
1716  /// Returns how the IR-level AtomicExpand pass should expand the given
1717  /// AtomicRMW, if at all. Default is to never expand.
1719  return RMW->isFloatingPointOperation() ?
1720  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1721  }
1722 
1723  /// On some platforms, an AtomicRMW that never actually modifies the value
1724  /// (such as fetch_add of 0) can be turned into a fence followed by an
1725  /// atomic load. This may sound useless, but it makes it possible for the
1726  /// processor to keep the cacheline shared, dramatically improving
1727  /// performance. And such idempotent RMWs are useful for implementing some
1728  /// kinds of locks, see for example (justification + benchmarks):
1729  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1730  /// This method tries doing that transformation, returning the atomic load if
1731  /// it succeeds, and nullptr otherwise.
1732  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1733  /// another round of expansion.
1734  virtual LoadInst *
1736  return nullptr;
1737  }
1738 
1739  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1740  /// SIGN_EXTEND, or ANY_EXTEND).
1742  return ISD::ZERO_EXTEND;
1743  }
1744 
1745  /// @}
1746 
1747  /// Returns true if we should normalize
1748  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1749  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1750  /// that it saves us from materializing N0 and N1 in an integer register.
1751  /// Targets that are able to perform and/or on flags should return false here.
1753  EVT VT) const {
1754  // If a target has multiple condition registers, then it likely has logical
1755  // operations on those registers.
1756  if (hasMultipleConditionRegisters())
1757  return false;
1758  // Only do the transform if the value won't be split into multiple
1759  // registers.
1760  LegalizeTypeAction Action = getTypeAction(Context, VT);
1761  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1762  Action != TypeSplitVector;
1763  }
1764 
1765  /// Return true if a select of constants (select Cond, C1, C2) should be
1766  /// transformed into simple math ops with the condition value. For example:
1767  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1768  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1769  return false;
1770  }
1771 
1772  /// Return true if it is profitable to transform an integer
1773  /// multiplication-by-constant into simpler operations like shifts and adds.
1774  /// This may be true if the target does not directly support the
1775  /// multiplication operation for the specified type or the sequence of simpler
1776  /// ops is faster than the multiply.
1777  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1778  return false;
1779  }
1780 
1781  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1782  /// conversion operations - canonicalizing the FP source value instead of
1783  /// converting all cases and then selecting based on value.
1784  /// This may be true if the target throws exceptions for out of bounds
1785  /// conversions or has fast FP CMOV.
1786  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1787  bool IsSigned) const {
1788  return false;
1789  }
1790 
1791  //===--------------------------------------------------------------------===//
1792  // TargetLowering Configuration Methods - These methods should be invoked by
1793  // the derived class constructor to configure this object for the target.
1794  //
1795 protected:
1796  /// Specify how the target extends the result of integer and floating point
1797  /// boolean values from i1 to a wider type. See getBooleanContents.
1799  BooleanContents = Ty;
1800  BooleanFloatContents = Ty;
1801  }
1802 
1803  /// Specify how the target extends the result of integer and floating point
1804  /// boolean values from i1 to a wider type. See getBooleanContents.
1806  BooleanContents = IntTy;
1807  BooleanFloatContents = FloatTy;
1808  }
1809 
1810  /// Specify how the target extends the result of a vector boolean value from a
1811  /// vector of i1 to a wider type. See getBooleanContents.
1813  BooleanVectorContents = Ty;
1814  }
1815 
1816  /// Specify the target scheduling preference.
1818  SchedPreferenceInfo = Pref;
1819  }
1820 
1821  /// Indicate whether this target prefers to use _setjmp to implement
1822  /// llvm.setjmp or the version without _. Defaults to false.
1823  void setUseUnderscoreSetJmp(bool Val) {
1824  UseUnderscoreSetJmp = Val;
1825  }
1826 
1827  /// Indicate whether this target prefers to use _longjmp to implement
1828  /// llvm.longjmp or the version without _. Defaults to false.
1829  void setUseUnderscoreLongJmp(bool Val) {
1830  UseUnderscoreLongJmp = Val;
1831  }
1832 
1833  /// Indicate the minimum number of blocks to generate jump tables.
1834  void setMinimumJumpTableEntries(unsigned Val);
1835 
1836  /// Indicate the maximum number of entries in jump tables.
1837  /// Set to zero to generate unlimited jump tables.
1838  void setMaximumJumpTableSize(unsigned);
1839 
1840  /// If set to a physical register, this specifies the register that
1841  /// llvm.savestack/llvm.restorestack should save and restore.
1843  StackPointerRegisterToSaveRestore = R;
1844  }
1845 
1846  /// Tells the code generator that the target has multiple (allocatable)
1847  /// condition registers that can be used to store the results of comparisons
1848  /// for use by selects and conditional branches. With multiple condition
1849  /// registers, the code generator will not aggressively sink comparisons into
1850  /// the blocks of their users.
1851  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1852  HasMultipleConditionRegisters = hasManyRegs;
1853  }
1854 
1855  /// Tells the code generator that the target has BitExtract instructions.
1856  /// The code generator will aggressively sink "shift"s into the blocks of
1857  /// their users if the users will generate "and" instructions which can be
1858  /// combined with "shift" to BitExtract instructions.
1859  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1860  HasExtractBitsInsn = hasExtractInsn;
1861  }
1862 
1863  /// Tells the code generator not to expand logic operations on comparison
1864  /// predicates into separate sequences that increase the amount of flow
1865  /// control.
1866  void setJumpIsExpensive(bool isExpensive = true);
1867 
1868  /// Tells the code generator that this target supports floating point
1869  /// exceptions and cares about preserving floating point exception behavior.
1870  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1871  HasFloatingPointExceptions = FPExceptions;
1872  }
1873 
1874  /// Tells the code generator which bitwidths to bypass.
1875  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1876  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1877  }
1878 
1879  /// Add the specified register class as an available regclass for the
1880  /// specified value type. This indicates the selector can handle values of
1881  /// that class natively.
1883  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1884  RegClassForVT[VT.SimpleTy] = RC;
1885  }
1886 
1887  /// Return the largest legal super-reg register class of the register class
1888  /// for the specified type and its associated "cost".
1889  virtual std::pair<const TargetRegisterClass *, uint8_t>
1890  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1891 
1892  /// Once all of the register classes are added, this allows us to compute
1893  /// derived properties we expose.
1894  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1895 
1896  /// Indicate that the specified operation does not work with the specified
1897  /// type and indicate what to do about it. Note that VT may refer to either
1898  /// the type of a result or that of an operand of Op.
1899  void setOperationAction(unsigned Op, MVT VT,
1900  LegalizeAction Action) {
1901  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1902  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1903  }
1904 
1905  /// Indicate that the specified load with extension does not work with the
1906  /// specified type and indicate what to do about it.
1907  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1908  LegalizeAction Action) {
1909  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1910  MemVT.isValid() && "Table isn't big enough!");
1911  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1912  unsigned Shift = 4 * ExtType;
1913  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1914  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1915  }
1916 
1917  /// Indicate that the specified truncating store does not work with the
1918  /// specified type and indicate what to do about it.
1919  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1920  LegalizeAction Action) {
1921  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1922  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1923  }
1924 
1925  /// Indicate that the specified indexed load does or does not work with the
1926  /// specified type and indicate what to do abort it.
1927  ///
1928  /// NOTE: All indexed mode loads are initialized to Expand in
1929  /// TargetLowering.cpp
1930  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1931  LegalizeAction Action) {
1932  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1933  (unsigned)Action < 0xf && "Table isn't big enough!");
1934  // Load action are kept in the upper half.
1935  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1936  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1937  }
1938 
1939  /// Indicate that the specified indexed store does or does not work with the
1940  /// specified type and indicate what to do about it.
1941  ///
1942  /// NOTE: All indexed mode stores are initialized to Expand in
1943  /// TargetLowering.cpp
1944  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1945  LegalizeAction Action) {
1946  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1947  (unsigned)Action < 0xf && "Table isn't big enough!");
1948  // Store action are kept in the lower half.
1949  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1950  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1951  }
1952 
1953  /// Indicate that the specified condition code is or isn't supported on the
1954  /// target and indicate what to do about it.
1956  LegalizeAction Action) {
1957  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1958  "Table isn't big enough!");
1959  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1960  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1961  /// value and the upper 29 bits index into the second dimension of the array
1962  /// to select what 32-bit value to use.
1963  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1964  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1965  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1966  }
1967 
1968  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1969  /// to trying a larger integer/fp until it can find one that works. If that
1970  /// default is insufficient, this method can be used by the target to override
1971  /// the default.
1972  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1973  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1974  }
1975 
1976  /// Convenience method to set an operation to Promote and specify the type
1977  /// in a single call.
1978  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1979  setOperationAction(Opc, OrigVT, Promote);
1980  AddPromotedToType(Opc, OrigVT, DestVT);
1981  }
1982 
1983  /// Targets should invoke this method for each target independent node that
1984  /// they want to provide a custom DAG combiner for by implementing the
1985  /// PerformDAGCombine virtual method.
1987  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1988  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1989  }
1990 
1991  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1992  void setJumpBufSize(unsigned Size) {
1993  JumpBufSize = Size;
1994  }
1995 
1996  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1997  /// 0
1998  void setJumpBufAlignment(unsigned Align) {
1999  JumpBufAlignment = Align;
2000  }
2001 
2002  /// Set the target's minimum function alignment (in log2(bytes))
2004  MinFunctionAlignment = Align;
2005  }
2006 
2007  /// Set the target's preferred function alignment. This should be set if
2008  /// there is a performance benefit to higher-than-minimum alignment (in
2009  /// log2(bytes))
2011  PrefFunctionAlignment = Align;
2012  }
2013 
2014  /// Set the target's preferred loop alignment. Default alignment is zero, it
2015  /// means the target does not care about loop alignment. The alignment is
2016  /// specified in log2(bytes). The target may also override
2017  /// getPrefLoopAlignment to provide per-loop values.
2018  void setPrefLoopAlignment(unsigned Align) {
2019  PrefLoopAlignment = Align;
2020  }
2021 
2022  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2024  MinStackArgumentAlignment = Align;
2025  }
2026 
2027  /// Set the maximum atomic operation size supported by the
2028  /// backend. Atomic operations greater than this size (as well as
2029  /// ones that are not naturally aligned), will be expanded by
2030  /// AtomicExpandPass into an __atomic_* library call.
2031  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2032  MaxAtomicSizeInBitsSupported = SizeInBits;
2033  }
2034 
2035  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2036  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2037  MinCmpXchgSizeInBits = SizeInBits;
2038  }
2039 
2040  /// Sets whether unaligned atomic operations are supported.
2041  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2042  SupportsUnalignedAtomics = UnalignedSupported;
2043  }
2044 
2045 public:
2046  //===--------------------------------------------------------------------===//
2047  // Addressing mode description hooks (used by LSR etc).
2048  //
2049 
2050  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2051  /// instructions reading the address. This allows as much computation as
2052  /// possible to be done in the address mode for that operand. This hook lets
2053  /// targets also pass back when this should be done on intrinsics which
2054  /// load/store.
2055  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2056  SmallVectorImpl<Value*> &/*Ops*/,
2057  Type *&/*AccessTy*/) const {
2058  return false;
2059  }
2060 
2061  /// This represents an addressing mode of:
2062  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2063  /// If BaseGV is null, there is no BaseGV.
2064  /// If BaseOffs is zero, there is no base offset.
2065  /// If HasBaseReg is false, there is no base register.
2066  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2067  /// no scale.
2068  struct AddrMode {
2069  GlobalValue *BaseGV = nullptr;
2070  int64_t BaseOffs = 0;
2071  bool HasBaseReg = false;
2072  int64_t Scale = 0;
2073  AddrMode() = default;
2074  };
2075 
2076  /// Return true if the addressing mode represented by AM is legal for this
2077  /// target, for a load/store of the specified type.
2078  ///
2079  /// The type may be VoidTy, in which case only return true if the addressing
2080  /// mode is legal for a load/store of any legal type. TODO: Handle
2081  /// pre/postinc as well.
2082  ///
2083  /// If the address space cannot be determined, it will be -1.
2084  ///
2085  /// TODO: Remove default argument
2086  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2087  Type *Ty, unsigned AddrSpace,
2088  Instruction *I = nullptr) const;
2089 
2090  /// Return the cost of the scaling factor used in the addressing mode
2091  /// represented by AM for this target, for a load/store of the specified type.
2092  ///
2093  /// If the AM is supported, the return value must be >= 0.
2094  /// If the AM is not supported, it returns a negative value.
2095  /// TODO: Handle pre/postinc as well.
2096  /// TODO: Remove default argument
2097  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2098  Type *Ty, unsigned AS = 0) const {
2099  // Default: assume that any scaling factor used in a legal AM is free.
2100  if (isLegalAddressingMode(DL, AM, Ty, AS))
2101  return 0;
2102  return -1;
2103  }
2104 
2105  /// Return true if the specified immediate is legal icmp immediate, that is
2106  /// the target has icmp instructions which can compare a register against the
2107  /// immediate without having to materialize the immediate into a register.
2108  virtual bool isLegalICmpImmediate(int64_t) const {
2109  return true;
2110  }
2111 
2112  /// Return true if the specified immediate is legal add immediate, that is the
2113  /// target has add instructions which can add a register with the immediate
2114  /// without having to materialize the immediate into a register.
2115  virtual bool isLegalAddImmediate(int64_t) const {
2116  return true;
2117  }
2118 
2119  /// Return true if the specified immediate is legal for the value input of a
2120  /// store instruction.
2121  virtual bool isLegalStoreImmediate(int64_t Value) const {
2122  // Default implementation assumes that at least 0 works since it is likely
2123  // that a zero register exists or a zero immediate is allowed.
2124  return Value == 0;
2125  }
2126 
2127  /// Return true if it's significantly cheaper to shift a vector by a uniform
2128  /// scalar than by an amount which will vary across each lane. On x86, for
2129  /// example, there is a "psllw" instruction for the former case, but no simple
2130  /// instruction for a general "a << b" operation on vectors.
2131  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2132  return false;
2133  }
2134 
2135  /// Returns true if the opcode is a commutative binary operation.
2136  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2137  // FIXME: This should get its info from the td file.
2138  switch (Opcode) {
2139  case ISD::ADD:
2140  case ISD::SMIN:
2141  case ISD::SMAX:
2142  case ISD::UMIN:
2143  case ISD::UMAX:
2144  case ISD::MUL:
2145  case ISD::MULHU:
2146  case ISD::MULHS:
2147  case ISD::SMUL_LOHI:
2148  case ISD::UMUL_LOHI:
2149  case ISD::FADD:
2150  case ISD::FMUL:
2151  case ISD::AND:
2152  case ISD::OR:
2153  case ISD::XOR:
2154  case ISD::SADDO:
2155  case ISD::UADDO:
2156  case ISD::ADDC:
2157  case ISD::ADDE:
2158  case ISD::SADDSAT:
2159  case ISD::UADDSAT:
2160  case ISD::FMINNUM:
2161  case ISD::FMAXNUM:
2162  case ISD::FMINIMUM:
2163  case ISD::FMAXIMUM:
2164  return true;
2165  default: return false;
2166  }
2167  }
2168 
2169  /// Return true if it's free to truncate a value of type FromTy to type
2170  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2171  /// by referencing its sub-register AX.
2172  /// Targets must return false when FromTy <= ToTy.
2173  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2174  return false;
2175  }
2176 
2177  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2178  /// whether a call is in tail position. Typically this means that both results
2179  /// would be assigned to the same register or stack slot, but it could mean
2180  /// the target performs adequate checks of its own before proceeding with the
2181  /// tail call. Targets must return false when FromTy <= ToTy.
2182  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2183  return false;
2184  }
2185 
2186  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2187  return false;
2188  }
2189 
2190  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2191 
2192  /// Return true if the extension represented by \p I is free.
2193  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2194  /// this method can use the context provided by \p I to decide
2195  /// whether or not \p I is free.
2196  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2197  /// In other words, if is[Z|FP]Free returns true, then this method
2198  /// returns true as well. The converse is not true.
2199  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2200  /// \pre \p I must be a sign, zero, or fp extension.
2201  bool isExtFree(const Instruction *I) const {
2202  switch (I->getOpcode()) {
2203  case Instruction::FPExt:
2204  if (isFPExtFree(EVT::getEVT(I->getType()),
2205  EVT::getEVT(I->getOperand(0)->getType())))
2206  return true;
2207  break;
2208  case Instruction::ZExt:
2209  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2210  return true;
2211  break;
2212  case Instruction::SExt:
2213  break;
2214  default:
2215  llvm_unreachable("Instruction is not an extension");
2216  }
2217  return isExtFreeImpl(I);
2218  }
2219 
2220  /// Return true if \p Load and \p Ext can form an ExtLoad.
2221  /// For example, in AArch64
2222  /// %L = load i8, i8* %ptr
2223  /// %E = zext i8 %L to i32
2224  /// can be lowered into one load instruction
2225  /// ldrb w0, [x0]
2226  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2227  const DataLayout &DL) const {
2228  EVT VT = getValueType(DL, Ext->getType());
2229  EVT LoadVT = getValueType(DL, Load->getType());
2230 
2231  // If the load has other users and the truncate is not free, the ext
2232  // probably isn't free.
2233  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2234  !isTruncateFree(Ext->getType(), Load->getType()))
2235  return false;
2236 
2237  // Check whether the target supports casts folded into loads.
2238  unsigned LType;
2239  if (isa<ZExtInst>(Ext))
2240  LType = ISD::ZEXTLOAD;
2241  else {
2242  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2243  LType = ISD::SEXTLOAD;
2244  }
2245 
2246  return isLoadExtLegal(LType, VT, LoadVT);
2247  }
2248 
2249  /// Return true if any actual instruction that defines a value of type FromTy
2250  /// implicitly zero-extends the value to ToTy in the result register.
2251  ///
2252  /// The function should return true when it is likely that the truncate can
2253  /// be freely folded with an instruction defining a value of FromTy. If
2254  /// the defining instruction is unknown (because you're looking at a
2255  /// function argument, PHI, etc.) then the target may require an
2256  /// explicit truncate, which is not necessarily free, but this function
2257  /// does not deal with those cases.
2258  /// Targets must return false when FromTy >= ToTy.
2259  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2260  return false;
2261  }
2262 
2263  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2264  return false;
2265  }
2266 
2267  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2268  /// zero-extension.
2269  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2270  return false;
2271  }
2272 
2273  /// Return true if the target supplies and combines to a paired load
2274  /// two loaded values of type LoadedType next to each other in memory.
2275  /// RequiredAlignment gives the minimal alignment constraints that must be met
2276  /// to be able to select this paired load.
2277  ///
2278  /// This information is *not* used to generate actual paired loads, but it is
2279  /// used to generate a sequence of loads that is easier to combine into a
2280  /// paired load.
2281  /// For instance, something like this:
2282  /// a = load i64* addr
2283  /// b = trunc i64 a to i32
2284  /// c = lshr i64 a, 32
2285  /// d = trunc i64 c to i32
2286  /// will be optimized into:
2287  /// b = load i32* addr1
2288  /// d = load i32* addr2
2289  /// Where addr1 = addr2 +/- sizeof(i32).
2290  ///
2291  /// In other words, unless the target performs a post-isel load combining,
2292  /// this information should not be provided because it will generate more
2293  /// loads.
2294  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2295  unsigned & /*RequiredAlignment*/) const {
2296  return false;
2297  }
2298 
2299  /// Return true if the target has a vector blend instruction.
2300  virtual bool hasVectorBlend() const { return false; }
2301 
2302  /// Get the maximum supported factor for interleaved memory accesses.
2303  /// Default to be the minimum interleave factor: 2.
2304  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2305 
2306  /// Lower an interleaved load to target specific intrinsics. Return
2307  /// true on success.
2308  ///
2309  /// \p LI is the vector load instruction.
2310  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2311  /// \p Indices is the corresponding indices for each shufflevector.
2312  /// \p Factor is the interleave factor.
2313  virtual bool lowerInterleavedLoad(LoadInst *LI,
2315  ArrayRef<unsigned> Indices,
2316  unsigned Factor) const {
2317  return false;
2318  }
2319 
2320  /// Lower an interleaved store to target specific intrinsics. Return
2321  /// true on success.
2322  ///
2323  /// \p SI is the vector store instruction.
2324  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2325  /// \p Factor is the interleave factor.
2327  unsigned Factor) const {
2328  return false;
2329  }
2330 
2331  /// Return true if zero-extending the specific node Val to type VT2 is free
2332  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2333  /// because it's folded such as X86 zero-extending loads).
2334  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2335  return isZExtFree(Val.getValueType(), VT2);
2336  }
2337 
2338  /// Return true if an fpext operation is free (for instance, because
2339  /// single-precision floating-point numbers are implicitly extended to
2340  /// double-precision).
2341  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2342  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2343  "invalid fpext types");
2344  return false;
2345  }
2346 
2347  /// Return true if an fpext operation input to an \p Opcode operation is free
2348  /// (for instance, because half-precision floating-point numbers are
2349  /// implicitly extended to float-precision) for an FMA instruction.
2350  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2351  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2352  "invalid fpext types");
2353  return isFPExtFree(DestVT, SrcVT);
2354  }
2355 
2356  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2357  /// extend node) is profitable.
2358  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2359 
2360  /// Return true if an fneg operation is free to the point where it is never
2361  /// worthwhile to replace it with a bitwise operation.
2362  virtual bool isFNegFree(EVT VT) const {
2363  assert(VT.isFloatingPoint());
2364  return false;
2365  }
2366 
2367  /// Return true if an fabs operation is free to the point where it is never
2368  /// worthwhile to replace it with a bitwise operation.
2369  virtual bool isFAbsFree(EVT VT) const {
2370  assert(VT.isFloatingPoint());
2371  return false;
2372  }
2373 
2374  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2375  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2376  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2377  ///
2378  /// NOTE: This may be called before legalization on types for which FMAs are
2379  /// not legal, but should return true if those types will eventually legalize
2380  /// to types that support FMAs. After legalization, it will only be called on
2381  /// types that support FMAs (via Legal or Custom actions)
2382  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2383  return false;
2384  }
2385 
2386  /// Return true if it's profitable to narrow operations of type VT1 to
2387  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2388  /// i32 to i16.
2389  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2390  return false;
2391  }
2392 
2393  /// Return true if it is beneficial to convert a load of a constant to
2394  /// just the constant itself.
2395  /// On some targets it might be more efficient to use a combination of
2396  /// arithmetic instructions to materialize the constant instead of loading it
2397  /// from a constant pool.
2398  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2399  Type *Ty) const {
2400  return false;
2401  }
2402 
2403  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2404  /// from this source type with this index. This is needed because
2405  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2406  /// the first element, and only the target knows which lowering is cheap.
2407  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2408  unsigned Index) const {
2409  return false;
2410  }
2411 
2412  /// Try to convert an extract element of a vector binary operation into an
2413  /// extract element followed by a scalar operation.
2414  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2415  return false;
2416  }
2417 
2418  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2419  // even if the vector itself has multiple uses.
2420  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2421  return false;
2422  }
2423 
2424  // Return true if CodeGenPrepare should consider splitting large offset of a
2425  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2426  // same blocks of its users.
2427  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2428 
2429  //===--------------------------------------------------------------------===//
2430  // Runtime Library hooks
2431  //
2432 
2433  /// Rename the default libcall routine name for the specified libcall.
2434  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2435  LibcallRoutineNames[Call] = Name;
2436  }
2437 
2438  /// Get the libcall routine name for the specified libcall.
2439  const char *getLibcallName(RTLIB::Libcall Call) const {
2440  return LibcallRoutineNames[Call];
2441  }
2442 
2443  /// Override the default CondCode to be used to test the result of the
2444  /// comparison libcall against zero.
2446  CmpLibcallCCs[Call] = CC;
2447  }
2448 
2449  /// Get the CondCode that's to be used to test the result of the comparison
2450  /// libcall against zero.
2452  return CmpLibcallCCs[Call];
2453  }
2454 
2455  /// Set the CallingConv that should be used for the specified libcall.
2457  LibcallCallingConvs[Call] = CC;
2458  }
2459 
2460  /// Get the CallingConv that should be used for the specified libcall.
2462  return LibcallCallingConvs[Call];
2463  }
2464 
2465  /// Execute target specific actions to finalize target lowering.
2466  /// This is used to set extra flags in MachineFrameInformation and freezing
2467  /// the set of reserved registers.
2468  /// The default implementation just freezes the set of reserved registers.
2469  virtual void finalizeLowering(MachineFunction &MF) const;
2470 
2471 private:
2472  const TargetMachine &TM;
2473 
2474  /// Tells the code generator that the target has multiple (allocatable)
2475  /// condition registers that can be used to store the results of comparisons
2476  /// for use by selects and conditional branches. With multiple condition
2477  /// registers, the code generator will not aggressively sink comparisons into
2478  /// the blocks of their users.
2479  bool HasMultipleConditionRegisters;
2480 
2481  /// Tells the code generator that the target has BitExtract instructions.
2482  /// The code generator will aggressively sink "shift"s into the blocks of
2483  /// their users if the users will generate "and" instructions which can be
2484  /// combined with "shift" to BitExtract instructions.
2485  bool HasExtractBitsInsn;
2486 
2487  /// Tells the code generator to bypass slow divide or remainder
2488  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2489  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2490  /// div/rem when the operands are positive and less than 256.
2491  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2492 
2493  /// Tells the code generator that it shouldn't generate extra flow control
2494  /// instructions and should attempt to combine flow control instructions via
2495  /// predication.
2496  bool JumpIsExpensive;
2497 
2498  /// Whether the target supports or cares about preserving floating point
2499  /// exception behavior.
2500  bool HasFloatingPointExceptions;
2501 
2502  /// This target prefers to use _setjmp to implement llvm.setjmp.
2503  ///
2504  /// Defaults to false.
2505  bool UseUnderscoreSetJmp;
2506 
2507  /// This target prefers to use _longjmp to implement llvm.longjmp.
2508  ///
2509  /// Defaults to false.
2510  bool UseUnderscoreLongJmp;
2511 
2512  /// Information about the contents of the high-bits in boolean values held in
2513  /// a type wider than i1. See getBooleanContents.
2514  BooleanContent BooleanContents;
2515 
2516  /// Information about the contents of the high-bits in boolean values held in
2517  /// a type wider than i1. See getBooleanContents.
2518  BooleanContent BooleanFloatContents;
2519 
2520  /// Information about the contents of the high-bits in boolean vector values
2521  /// when the element type is wider than i1. See getBooleanContents.
2522  BooleanContent BooleanVectorContents;
2523 
2524  /// The target scheduling preference: shortest possible total cycles or lowest
2525  /// register usage.
2526  Sched::Preference SchedPreferenceInfo;
2527 
2528  /// The size, in bytes, of the target's jmp_buf buffers
2529  unsigned JumpBufSize;
2530 
2531  /// The alignment, in bytes, of the target's jmp_buf buffers
2532  unsigned JumpBufAlignment;
2533 
2534  /// The minimum alignment that any argument on the stack needs to have.
2535  unsigned MinStackArgumentAlignment;
2536 
2537  /// The minimum function alignment (used when optimizing for size, and to
2538  /// prevent explicitly provided alignment from leading to incorrect code).
2539  unsigned MinFunctionAlignment;
2540 
2541  /// The preferred function alignment (used when alignment unspecified and
2542  /// optimizing for speed).
2543  unsigned PrefFunctionAlignment;
2544 
2545  /// The preferred loop alignment.
2546  unsigned PrefLoopAlignment;
2547 
2548  /// Size in bits of the maximum atomics size the backend supports.
2549  /// Accesses larger than this will be expanded by AtomicExpandPass.
2550  unsigned MaxAtomicSizeInBitsSupported;
2551 
2552  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2553  /// backend supports.
2554  unsigned MinCmpXchgSizeInBits;
2555 
2556  /// This indicates if the target supports unaligned atomic operations.
2557  bool SupportsUnalignedAtomics;
2558 
2559  /// If set to a physical register, this specifies the register that
2560  /// llvm.savestack/llvm.restorestack should save and restore.
2561  unsigned StackPointerRegisterToSaveRestore;
2562 
2563  /// This indicates the default register class to use for each ValueType the
2564  /// target supports natively.
2565  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2566  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2567  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2568 
2569  /// This indicates the "representative" register class to use for each
2570  /// ValueType the target supports natively. This information is used by the
2571  /// scheduler to track register pressure. By default, the representative
2572  /// register class is the largest legal super-reg register class of the
2573  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2574  /// representative class would be GR32.
2575  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2576 
2577  /// This indicates the "cost" of the "representative" register class for each
2578  /// ValueType. The cost is used by the scheduler to approximate register
2579  /// pressure.
2580  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2581 
2582  /// For any value types we are promoting or expanding, this contains the value
2583  /// type that we are changing to. For Expanded types, this contains one step
2584  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2585  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2586  /// the same type (e.g. i32 -> i32).
2587  MVT TransformToType[MVT::LAST_VALUETYPE];
2588 
2589  /// For each operation and each value type, keep a LegalizeAction that
2590  /// indicates how instruction selection should deal with the operation. Most
2591  /// operations are Legal (aka, supported natively by the target), but
2592  /// operations that are not should be described. Note that operations on
2593  /// non-legal value types are not described here.
2595 
2596  /// For each load extension type and each value type, keep a LegalizeAction
2597  /// that indicates how instruction selection should deal with a load of a
2598  /// specific value type and extension type. Uses 4-bits to store the action
2599  /// for each of the 4 load ext types.
2600  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2601 
2602  /// For each value type pair keep a LegalizeAction that indicates whether a
2603  /// truncating store of a specific value type and truncating type is legal.
2605 
2606  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2607  /// that indicates how instruction selection should deal with the load /
2608  /// store.
2609  ///
2610  /// The first dimension is the value_type for the reference. The second
2611  /// dimension represents the various modes for load store.
2612  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2613 
2614  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2615  /// indicates how instruction selection should deal with the condition code.
2616  ///
2617  /// Because each CC action takes up 4 bits, we need to have the array size be
2618  /// large enough to fit all of the value types. This can be done by rounding
2619  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2620  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2621 
2622 protected:
2624 
2625 private:
2626  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2627 
2628  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2629  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2630  /// array.
2631  unsigned char
2632  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2633 
2634  /// For operations that must be promoted to a specific type, this holds the
2635  /// destination type. This map should be sparse, so don't hold it as an
2636  /// array.
2637  ///
2638  /// Targets add entries to this map with AddPromotedToType(..), clients access
2639  /// this with getTypeToPromoteTo(..).
2640  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2641  PromoteToType;
2642 
2643  /// Stores the name each libcall.
2644  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2645 
2646  /// The ISD::CondCode that should be used to test the result of each of the
2647  /// comparison libcall against zero.
2648  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2649 
2650  /// Stores the CallingConv that should be used for each libcall.
2651  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2652 
2653  /// Set default libcall names and calling conventions.
2654  void InitLibcalls(const Triple &TT);
2655 
2656 protected:
2657  /// Return true if the extension represented by \p I is free.
2658  /// \pre \p I is a sign, zero, or fp extension and
2659  /// is[Z|FP]ExtFree of the related types is not true.
2660  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2661 
2662  /// Depth that GatherAllAliases should should continue looking for chain
2663  /// dependencies when trying to find a more preferable chain. As an
2664  /// approximation, this should be more than the number of consecutive stores
2665  /// expected to be merged.
2667 
2668  /// Specify maximum number of store instructions per memset call.
2669  ///
2670  /// When lowering \@llvm.memset this field specifies the maximum number of
2671  /// store operations that may be substituted for the call to memset. Targets
2672  /// must set this value based on the cost threshold for that target. Targets
2673  /// should assume that the memset will be done using as many of the largest
2674  /// store operations first, followed by smaller ones, if necessary, per
2675  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2676  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2677  /// store. This only applies to setting a constant array of a constant size.
2679 
2680  /// Maximum number of stores operations that may be substituted for the call
2681  /// to memset, used for functions with OptSize attribute.
2683 
2684  /// Specify maximum bytes of store instructions per memcpy call.
2685  ///
2686  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2687  /// store operations that may be substituted for a call to memcpy. Targets
2688  /// must set this value based on the cost threshold for that target. Targets
2689  /// should assume that the memcpy will be done using as many of the largest
2690  /// store operations first, followed by smaller ones, if necessary, per
2691  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2692  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2693  /// and one 1-byte store. This only applies to copying a constant array of
2694  /// constant size.
2696 
2697 
2698  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2699  ///
2700  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2701  /// of store instructions to keep together. This helps in pairing and
2702  // vectorization later on.
2703  unsigned MaxGluedStoresPerMemcpy = 0;
2704 
2705  /// Maximum number of store operations that may be substituted for a call to
2706  /// memcpy, used for functions with OptSize attribute.
2710 
2711  /// Specify maximum bytes of store instructions per memmove call.
2712  ///
2713  /// When lowering \@llvm.memmove this field specifies the maximum number of
2714  /// store instructions that may be substituted for a call to memmove. Targets
2715  /// must set this value based on the cost threshold for that target. Targets
2716  /// should assume that the memmove will be done using as many of the largest
2717  /// store operations first, followed by smaller ones, if necessary, per
2718  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2719  /// with 8-bit alignment would result in nine 1-byte stores. This only
2720  /// applies to copying a constant array of constant size.
2722 
2723  /// Maximum number of store instructions that may be substituted for a call to
2724  /// memmove, used for functions with OptSize attribute.
2726 
2727  /// Tells the code generator that select is more expensive than a branch if
2728  /// the branch is usually predicted right.
2730 
2731  /// \see enableExtLdPromotion.
2733 
2734  /// Return true if the value types that can be represented by the specified
2735  /// register class are all legal.
2736  bool isLegalRC(const TargetRegisterInfo &TRI,
2737  const TargetRegisterClass &RC) const;
2738 
2739  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2740  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2741  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2742  MachineBasicBlock *MBB) const;
2743 
2744  /// Replace/modify the XRay custom event operands with target-dependent
2745  /// details.
2746  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2747  MachineBasicBlock *MBB) const;
2748 
2749  /// Replace/modify the XRay typed event operands with target-dependent
2750  /// details.
2751  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2752  MachineBasicBlock *MBB) const;
2753 };
2754 
2755 /// This class defines information used to lower LLVM code to legal SelectionDAG
2756 /// operators that the target instruction selector can accept natively.
2757 ///
2758 /// This class also defines callbacks that targets must implement to lower
2759 /// target-specific constructs to SelectionDAG operators.
2761 public:
2762  struct DAGCombinerInfo;
2763 
2764  TargetLowering(const TargetLowering &) = delete;
2765  TargetLowering &operator=(const TargetLowering &) = delete;
2766 
2767  /// NOTE: The TargetMachine owns TLOF.
2768  explicit TargetLowering(const TargetMachine &TM);
2769 
2770  bool isPositionIndependent() const;
2771 
2772  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2773  FunctionLoweringInfo *FLI,
2774  LegacyDivergenceAnalysis *DA) const {
2775  return false;
2776  }
2777 
2778  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2779  return false;
2780  }
2781 
2782  /// Returns true by value, base pointer and offset pointer and addressing mode
2783  /// by reference if the node's address can be legally represented as
2784  /// pre-indexed load / store address.
2785  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2786  SDValue &/*Offset*/,
2787  ISD::MemIndexedMode &/*AM*/,
2788  SelectionDAG &/*DAG*/) const {
2789  return false;
2790  }
2791 
2792  /// Returns true by value, base pointer and offset pointer and addressing mode
2793  /// by reference if this node can be combined with a load / store to form a
2794  /// post-indexed load / store.
2795  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2796  SDValue &/*Base*/,
2797  SDValue &/*Offset*/,
2798  ISD::MemIndexedMode &/*AM*/,
2799  SelectionDAG &/*DAG*/) const {
2800  return false;
2801  }
2802 
2803  /// Return the entry encoding for a jump table in the current function. The
2804  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2805  virtual unsigned getJumpTableEncoding() const;
2806 
2807  virtual const MCExpr *
2809  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2810  MCContext &/*Ctx*/) const {
2811  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2812  }
2813 
2814  /// Returns relocation base for the given PIC jumptable.
2815  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2816  SelectionDAG &DAG) const;
2817 
2818  /// This returns the relocation base for the given PIC jumptable, the same as
2819  /// getPICJumpTableRelocBase, but as an MCExpr.
2820  virtual const MCExpr *
2821  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2822  unsigned JTI, MCContext &Ctx) const;
2823 
2824  /// Return true if folding a constant offset with the given GlobalAddress is
2825  /// legal. It is frequently not legal in PIC relocation models.
2826  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2827 
2829  SDValue &Chain) const;
2830 
2831  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2832  SDValue &NewRHS, ISD::CondCode &CCCode,
2833  const SDLoc &DL) const;
2834 
2835  /// Returns a pair of (return value, chain).
2836  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2837  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2838  EVT RetVT, ArrayRef<SDValue> Ops,
2839  bool isSigned, const SDLoc &dl,
2840  bool doesNotReturn = false,
2841  bool isReturnValueUsed = true) const;
2842 
2843  /// Check whether parameters to a call that are passed in callee saved
2844  /// registers are the same as from the calling function. This needs to be
2845  /// checked for tail call eligibility.
2846  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2847  const uint32_t *CallerPreservedMask,
2848  const SmallVectorImpl<CCValAssign> &ArgLocs,
2849  const SmallVectorImpl<SDValue> &OutVals) const;
2850 
2851  //===--------------------------------------------------------------------===//
2852  // TargetLowering Optimization Methods
2853  //
2854 
2855  /// A convenience struct that encapsulates a DAG, and two SDValues for
2856  /// returning information from TargetLowering to its clients that want to
2857  /// combine.
2860  bool LegalTys;
2861  bool LegalOps;
2864 
2866  bool LT, bool LO) :
2867  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2868 
2869  bool LegalTypes() const { return LegalTys; }
2870  bool LegalOperations() const { return LegalOps; }
2871 
2873  Old = O;
2874  New = N;
2875  return true;
2876  }
2877  };
2878 
2879  /// Check to see if the specified operand of the specified instruction is a
2880  /// constant integer. If so, check to see if there are any bits set in the
2881  /// constant that are not demanded. If so, shrink the constant and return
2882  /// true.
2883  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2884  TargetLoweringOpt &TLO) const;
2885 
2886  // Target hook to do target-specific const optimization, which is called by
2887  // ShrinkDemandedConstant. This function should return true if the target
2888  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2889  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2890  TargetLoweringOpt &TLO) const {
2891  return false;
2892  }
2893 
2894  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2895  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2896  /// generalized for targets with other types of implicit widening casts.
2897  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2898  TargetLoweringOpt &TLO) const;
2899 
2900  /// Look at Op. At this point, we know that only the DemandedBits bits of the
2901  /// result of Op are ever used downstream. If we can use this information to
2902  /// simplify Op, create a new simplified DAG node and return true, returning
2903  /// the original and new nodes in Old and New. Otherwise, analyze the
2904  /// expression and return a mask of KnownOne and KnownZero bits for the
2905  /// expression (used to simplify the caller). The KnownZero/One bits may only
2906  /// be accurate for those bits in the Demanded masks.
2907  /// \p AssumeSingleUse When this parameter is true, this function will
2908  /// attempt to simplify \p Op even if there are multiple uses.
2909  /// Callers are responsible for correctly updating the DAG based on the
2910  /// results of this function, because simply replacing replacing TLO.Old
2911  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2912  /// has multiple uses.
2913  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2914  const APInt &DemandedElts, KnownBits &Known,
2915  TargetLoweringOpt &TLO, unsigned Depth = 0,
2916  bool AssumeSingleUse = false) const;
2917 
2918  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
2919  /// Adds Op back to the worklist upon success.
2920  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2921  KnownBits &Known, TargetLoweringOpt &TLO,
2922  unsigned Depth = 0,
2923  bool AssumeSingleUse = false) const;
2924 
2925  /// Helper wrapper around SimplifyDemandedBits.
2926  /// Adds Op back to the worklist upon success.
2927  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2928  DAGCombinerInfo &DCI) const;
2929 
2930  /// Look at Vector Op. At this point, we know that only the DemandedElts
2931  /// elements of the result of Op are ever used downstream. If we can use
2932  /// this information to simplify Op, create a new simplified DAG node and
2933  /// return true, storing the original and new nodes in TLO.
2934  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2935  /// KnownZero elements for the expression (used to simplify the caller).
2936  /// The KnownUndef/Zero elements may only be accurate for those bits
2937  /// in the DemandedMask.
2938  /// \p AssumeSingleUse When this parameter is true, this function will
2939  /// attempt to simplify \p Op even if there are multiple uses.
2940  /// Callers are responsible for correctly updating the DAG based on the
2941  /// results of this function, because simply replacing replacing TLO.Old
2942  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2943  /// has multiple uses.
2944  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2945  APInt &KnownUndef, APInt &KnownZero,
2946  TargetLoweringOpt &TLO, unsigned Depth = 0,
2947  bool AssumeSingleUse = false) const;
2948 
2949  /// Helper wrapper around SimplifyDemandedVectorElts.
2950  /// Adds Op back to the worklist upon success.
2951  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2952  APInt &KnownUndef, APInt &KnownZero,
2953  DAGCombinerInfo &DCI) const;
2954 
2955  /// Determine which of the bits specified in Mask are known to be either zero
2956  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2957  /// argument allows us to only collect the known bits that are shared by the
2958  /// requested vector elements.
2959  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2960  KnownBits &Known,
2961  const APInt &DemandedElts,
2962  const SelectionDAG &DAG,
2963  unsigned Depth = 0) const;
2964 
2965  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2966  /// Default implementation computes low bits based on alignment
2967  /// information. This should preserve known bits passed into it.
2968  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2969  KnownBits &Known,
2970  const APInt &DemandedElts,
2971  const SelectionDAG &DAG,
2972  unsigned Depth = 0) const;
2973 
2974  /// This method can be implemented by targets that want to expose additional
2975  /// information about sign bits to the DAG Combiner. The DemandedElts
2976  /// argument allows us to only collect the minimum sign bits that are shared
2977  /// by the requested vector elements.
2978  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2979  const APInt &DemandedElts,
2980  const SelectionDAG &DAG,
2981  unsigned Depth = 0) const;
2982 
2983  /// Attempt to simplify any target nodes based on the demanded vector
2984  /// elements, returning true on success. Otherwise, analyze the expression and
2985  /// return a mask of KnownUndef and KnownZero elements for the expression
2986  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2987  /// accurate for those bits in the DemandedMask.
2988  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2989  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2990  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2991 
2992  /// Attempt to simplify any target nodes based on the demanded bits/elts,
2993  /// returning true on success. Otherwise, analyze the
2994  /// expression and return a mask of KnownOne and KnownZero bits for the
2995  /// expression (used to simplify the caller). The KnownZero/One bits may only
2996  /// be accurate for those bits in the Demanded masks.
2997  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
2998  const APInt &DemandedBits,
2999  const APInt &DemandedElts,
3000  KnownBits &Known,
3001  TargetLoweringOpt &TLO,
3002  unsigned Depth = 0) const;
3003 
3004  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3005  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3006  /// NaN.
3007  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3008  const SelectionDAG &DAG,
3009  bool SNaN = false,
3010  unsigned Depth = 0) const;
3012  void *DC; // The DAG Combiner object.
3015 
3016  public:
3018 
3019  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3020  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3021 
3022  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3023  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3024  bool isAfterLegalizeDAG() const {
3025  return Level == AfterLegalizeDAG;
3026  }
3028  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3029 
3030  void AddToWorklist(SDNode *N);
3031  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3032  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3033  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3034 
3035  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3036  };
3037 
3038  /// Return if the N is a constant or constant vector equal to the true value
3039  /// from getBooleanContents().
3040  bool isConstTrueVal(const SDNode *N) const;
3041 
3042  /// Return if the N is a constant or constant vector equal to the false value
3043  /// from getBooleanContents().
3044  bool isConstFalseVal(const SDNode *N) const;
3045 
3046  /// Return if \p N is a True value when extended to \p VT.
3047  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3048 
3049  /// Try to simplify a setcc built with the specified operands and cc. If it is
3050  /// unable to simplify it, return a null SDValue.
3051  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3052  bool foldBooleans, DAGCombinerInfo &DCI,
3053  const SDLoc &dl) const;
3054 
3055  // For targets which wrap address, unwrap for analysis.
3056  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3057 
3058  /// Returns true (and the GlobalValue and the offset) if the node is a
3059  /// GlobalAddress + offset.
3060  virtual bool
3061  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3062 
3063  /// This method will be invoked for all target nodes and for any
3064  /// target-independent nodes that the target has registered with invoke it
3065  /// for.
3066  ///
3067  /// The semantics are as follows:
3068  /// Return Value:
3069  /// SDValue.Val == 0 - No change was made
3070  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3071  /// otherwise - N should be replaced by the returned Operand.
3072  ///
3073  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3074  /// more complex transformations.
3075  ///
3076  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3077 
3078  /// Return true if it is profitable to move this shift by a constant amount
3079  /// though its operand, adjusting any immediate operands as necessary to
3080  /// preserve semantics. This transformation may not be desirable if it
3081  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3082  /// extraction in AArch64). By default, it returns true.
3083  ///
3084  /// @param N the shift node
3085  /// @param Level the current DAGCombine legalization level.
3086  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3087  CombineLevel Level) const {
3088  return true;
3089  }
3090 
3091  /// Return true if it is profitable to fold a pair of shifts into a mask.
3092  /// This is usually true on most targets. But some targets, like Thumb1,
3093  /// have immediate shift instructions, but no immediate "and" instruction;
3094  /// this makes the fold unprofitable.
3095  virtual bool shouldFoldShiftPairToMask(const SDNode *N,
3096  CombineLevel Level) const {
3097  return true;
3098  }
3099 
3100  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3101  // to a shuffle and a truncate.
3102  // Example of such a combine:
3103  // v4i32 build_vector((extract_elt V, 1),
3104  // (extract_elt V, 3),
3105  // (extract_elt V, 5),
3106  // (extract_elt V, 7))
3107  // -->
3108  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3110  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3111  return false;
3112  }
3113 
3114  /// Return true if the target has native support for the specified value type
3115  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3116  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3117  /// and some i16 instructions are slow.
3118  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3119  // By default, assume all legal types are desirable.
3120  return isTypeLegal(VT);
3121  }
3122 
3123  /// Return true if it is profitable for dag combiner to transform a floating
3124  /// point op of specified opcode to a equivalent op of an integer
3125  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3126  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3127  EVT /*VT*/) const {
3128  return false;
3129  }
3130 
3131  /// This method query the target whether it is beneficial for dag combiner to
3132  /// promote the specified node. If true, it should return the desired
3133  /// promotion type by reference.
3134  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3135  return false;
3136  }
3137 
3138  /// Return true if the target supports swifterror attribute. It optimizes
3139  /// loads and stores to reading and writing a specific register.
3140  virtual bool supportSwiftError() const {
3141  return false;
3142  }
3143 
3144  /// Return true if the target supports that a subset of CSRs for the given
3145  /// machine function is handled explicitly via copies.
3146  virtual bool supportSplitCSR(MachineFunction *MF) const {
3147  return false;
3148  }
3149 
3150  /// Perform necessary initialization to handle a subset of CSRs explicitly
3151  /// via copies. This function is called at the beginning of instruction
3152  /// selection.
3153  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3154  llvm_unreachable("Not Implemented");
3155  }
3156 
3157  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3158  /// CSRs to virtual registers in the entry block, and copy them back to
3159  /// physical registers in the exit blocks. This function is called at the end
3160  /// of instruction selection.
3161  virtual void insertCopiesSplitCSR(
3162  MachineBasicBlock *Entry,
3163  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3164  llvm_unreachable("Not Implemented");
3165  }
3166 
3167  //===--------------------------------------------------------------------===//
3168  // Lowering methods - These methods must be implemented by targets so that
3169  // the SelectionDAGBuilder code knows how to lower these.
3170  //
3171 
3172  /// This hook must be implemented to lower the incoming (formal) arguments,
3173  /// described by the Ins array, into the specified DAG. The implementation
3174  /// should fill in the InVals array with legal-type argument values, and
3175  /// return the resulting token chain value.
3177  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3178  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3179  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3180  llvm_unreachable("Not Implemented");
3181  }
3182 
3183  /// This structure contains all information that is necessary for lowering
3184  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3185  /// needs to lower a call, and targets will see this struct in their LowerCall
3186  /// implementation.
3189  Type *RetTy = nullptr;
3190  bool RetSExt : 1;
3191  bool RetZExt : 1;
3192  bool IsVarArg : 1;
3193  bool IsInReg : 1;
3194  bool DoesNotReturn : 1;
3196  bool IsConvergent : 1;
3197  bool IsPatchPoint : 1;
3198 
3199  // IsTailCall should be modified by implementations of
3200  // TargetLowering::LowerCall that perform tail call conversions.
3201  bool IsTailCall = false;
3202 
3203  // Is Call lowering done post SelectionDAG type legalization.
3204  bool IsPostTypeLegalization = false;
3205 
3206  unsigned NumFixedArgs = -1;
3209  ArgListTy Args;
3217 
3219  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3220  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3221  IsPatchPoint(false), DAG(DAG) {}
3222 
3224  DL = dl;
3225  return *this;
3226  }
3227 
3229  Chain = InChain;
3230  return *this;
3231  }
3232 
3233  // setCallee with target/module-specific attributes
3235  SDValue Target, ArgListTy &&ArgsList) {
3236  RetTy = ResultType;
3237  Callee = Target;
3238  CallConv = CC;
3239  NumFixedArgs = ArgsList.size();
3240  Args = std::move(ArgsList);
3241 
3243  &(DAG.getMachineFunction()), CC, Args);
3244  return *this;
3245  }
3246 
3248  SDValue Target, ArgListTy &&ArgsList) {
3249  RetTy = ResultType;
3250  Callee = Target;
3251  CallConv = CC;
3252  NumFixedArgs = ArgsList.size();
3253  Args = std::move(ArgsList);
3254  return *this;
3255  }
3256 
3258  SDValue Target, ArgListTy &&ArgsList,
3259  ImmutableCallSite Call) {
3260  RetTy = ResultType;
3261 
3262  IsInReg = Call.hasRetAttr(Attribute::InReg);
3263  DoesNotReturn =
3264  Call.doesNotReturn() ||
3265  (!Call.isInvoke() &&
3266  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3267  IsVarArg = FTy->isVarArg();
3268  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3269  RetSExt = Call.hasRetAttr(Attribute::SExt);
3270  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3271 
3272  Callee = Target;
3273 
3274  CallConv = Call.getCallingConv();
3275  NumFixedArgs = FTy->getNumParams();
3276  Args = std::move(ArgsList);
3277 
3278  CS = Call;
3279 
3280  return *this;
3281  }
3282 
3284  IsInReg = Value;
3285  return *this;
3286  }
3287 
3289  DoesNotReturn = Value;
3290  return *this;
3291  }
3292 
3294  IsVarArg = Value;
3295  return *this;
3296  }
3297 
3299  IsTailCall = Value;
3300  return *this;
3301  }
3302 
3304  IsReturnValueUsed = !Value;
3305  return *this;
3306  }
3307 
3309  IsConvergent = Value;
3310  return *this;
3311  }
3312 
3314  RetSExt = Value;
3315  return *this;
3316  }
3317 
3319  RetZExt = Value;
3320  return *this;
3321  }
3322 
3324  IsPatchPoint = Value;
3325  return *this;
3326  }
3327 
3329  IsPostTypeLegalization = Value;
3330  return *this;
3331  }
3332 
3333  ArgListTy &getArgs() {
3334  return Args;
3335  }
3336  };
3337 
3338  /// This function lowers an abstract call to a function into an actual call.
3339  /// This returns a pair of operands. The first element is the return value
3340  /// for the function (if RetTy is not VoidTy). The second element is the
3341  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3342  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3343 
3344  /// This hook must be implemented to lower calls into the specified
3345  /// DAG. The outgoing arguments to the call are described by the Outs array,
3346  /// and the values to be returned by the call are described by the Ins
3347  /// array. The implementation should fill in the InVals array with legal-type
3348  /// return values from the call, and return the resulting token chain value.
3349  virtual SDValue
3351  SmallVectorImpl<SDValue> &/*InVals*/) const {
3352  llvm_unreachable("Not Implemented");
3353  }
3354 
3355  /// Target-specific cleanup for formal ByVal parameters.
3356  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3357 
3358  /// This hook should be implemented to check whether the return values
3359  /// described by the Outs array can fit into the return registers. If false
3360  /// is returned, an sret-demotion is performed.
3361  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3362  MachineFunction &/*MF*/, bool /*isVarArg*/,
3363  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3364  LLVMContext &/*Context*/) const
3365  {
3366  // Return true by default to get preexisting behavior.
3367  return true;
3368  }
3369 
3370  /// This hook must be implemented to lower outgoing return values, described
3371  /// by the Outs array, into the specified DAG. The implementation should
3372  /// return the resulting token chain value.
3373  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3374  bool /*isVarArg*/,
3375  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3376  const SmallVectorImpl<SDValue> & /*OutVals*/,
3377  const SDLoc & /*dl*/,
3378  SelectionDAG & /*DAG*/) const {
3379  llvm_unreachable("Not Implemented");
3380  }
3381 
3382  /// Return true if result of the specified node is used by a return node
3383  /// only. It also compute and return the input chain for the tail call.
3384  ///
3385  /// This is used to determine whether it is possible to codegen a libcall as
3386  /// tail call at legalization time.
3387  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3388  return false;
3389  }
3390 
3391  /// Return true if the target may be able emit the call instruction as a tail
3392  /// call. This is used by optimization passes to determine if it's profitable
3393  /// to duplicate return instructions to enable tailcall optimization.
3394  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3395  return false;
3396  }
3397 
3398  /// Return the builtin name for the __builtin___clear_cache intrinsic
3399  /// Default is to invoke the clear cache library call
3400  virtual const char * getClearCacheBuiltinName() const {
3401  return "__clear_cache";
3402  }
3403 
3404  /// Return the register ID of the name passed in. Used by named register
3405  /// global variables extension. There is no target-independent behaviour
3406  /// so the default action is to bail.
3407  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3408  SelectionDAG &DAG) const {
3409  report_fatal_error("Named registers not implemented for this target");
3410  }
3411 
3412  /// Return the type that should be used to zero or sign extend a
3413  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3414  /// require the return type to be promoted, but this is not true all the time,
3415  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3416  /// conventions. The frontend should handle this and include all of the
3417  /// necessary information.
3419  ISD::NodeType /*ExtendKind*/) const {
3420  EVT MinVT = getRegisterType(Context, MVT::i32);
3421  return VT.bitsLT(MinVT) ? MinVT : VT;
3422  }
3423 
3424  /// For some targets, an LLVM struct type must be broken down into multiple
3425  /// simple types, but the calling convention specifies that the entire struct
3426  /// must be passed in a block of consecutive registers.
3427  virtual bool
3429  bool isVarArg) const {
3430  return false;
3431  }
3432 
3433  /// Returns a 0 terminated array of registers that can be safely used as
3434  /// scratch registers.
3435  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3436  return nullptr;
3437  }
3438 
3439  /// This callback is used to prepare for a volatile or atomic load.
3440  /// It takes a chain node as input and returns the chain for the load itself.
3441  ///
3442  /// Having a callback like this is necessary for targets like SystemZ,
3443  /// which allows a CPU to reuse the result of a previous load indefinitely,
3444  /// even if a cache-coherent store is performed by another CPU. The default
3445  /// implementation does nothing.
3447  SelectionDAG &DAG) const {
3448  return Chain;
3449  }
3450 
3451  /// This callback is used to inspect load/store instructions and add
3452  /// target-specific MachineMemOperand flags to them. The default
3453  /// implementation does nothing.
3456  }
3457 
3458  /// This callback is invoked by the type legalizer to legalize nodes with an
3459  /// illegal operand type but legal result types. It replaces the
3460  /// LowerOperation callback in the type Legalizer. The reason we can not do
3461  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3462  /// use this callback.
3463  ///
3464  /// TODO: Consider merging with ReplaceNodeResults.
3465  ///
3466  /// The target places new result values for the node in Results (their number
3467  /// and types must exactly match those of the original return values of
3468  /// the node), or leaves Results empty, which indicates that the node is not
3469  /// to be custom lowered after all.
3470  /// The default implementation calls LowerOperation.
3471  virtual void LowerOperationWrapper(SDNode *N,
3473  SelectionDAG &DAG) const;
3474 
3475  /// This callback is invoked for operations that are unsupported by the
3476  /// target, which are registered to use 'custom' lowering, and whose defined
3477  /// values are all legal. If the target has no operations that require custom
3478  /// lowering, it need not implement this. The default implementation of this
3479  /// aborts.
3480  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3481 
3482  /// This callback is invoked when a node result type is illegal for the
3483  /// target, and the operation was registered to use 'custom' lowering for that
3484  /// result type. The target places new result values for the node in Results
3485  /// (their number and types must exactly match those of the original return
3486  /// values of the node), or leaves Results empty, which indicates that the
3487  /// node is not to be custom lowered after all.
3488  ///
3489  /// If the target has no operations that require custom lowering, it need not
3490  /// implement this. The default implementation aborts.
3491  virtual void ReplaceNodeResults(SDNode * /*N*/,
3492  SmallVectorImpl<SDValue> &/*Results*/,
3493  SelectionDAG &/*DAG*/) const {
3494  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3495  }
3496 
3497  /// This method returns the name of a target specific DAG node.
3498  virtual const char *getTargetNodeName(unsigned Opcode) const;
3499 
3500  /// This method returns a target specific FastISel object, or null if the
3501  /// target does not support "fast" ISel.
3503  const TargetLibraryInfo *) const {
3504  return nullptr;
3505  }
3506 
3507  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3508  SelectionDAG &DAG) const;
3509 
3510  //===--------------------------------------------------------------------===//
3511  // Inline Asm Support hooks
3512  //
3513 
3514  /// This hook allows the target to expand an inline asm call to be explicit
3515  /// llvm code if it wants to. This is useful for turning simple inline asms
3516  /// into LLVM intrinsics, which gives the compiler more information about the
3517  /// behavior of the code.
3518  virtual bool ExpandInlineAsm(CallInst *) const {
3519  return false;
3520  }
3521 
3523  C_Register, // Constraint represents specific register(s).
3524  C_RegisterClass, // Constraint represents any of register(s) in class.
3525  C_Memory, // Memory constraint.
3526  C_Other, // Something else.
3527  C_Unknown // Unsupported constraint.
3528  };
3529 
3531  // Generic weights.
3532  CW_Invalid = -1, // No match.
3533  CW_Okay = 0, // Acceptable.
3534  CW_Good = 1, // Good weight.
3535  CW_Better = 2, // Better weight.
3536  CW_Best = 3, // Best weight.
3537 
3538  // Well-known weights.
3539  CW_SpecificReg = CW_Okay, // Specific register operands.
3540  CW_Register = CW_Good, // Register operands.
3541  CW_Memory = CW_Better, // Memory operands.
3542  CW_Constant = CW_Best, // Constant operand.
3543  CW_Default = CW_Okay // Default or don't know type.
3544  };
3545 
3546  /// This contains information for each constraint that we are lowering.
3548  /// This contains the actual string for the code, like "m". TargetLowering
3549  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3550  /// matches the operand.
3551  std::string ConstraintCode;
3552 
3553  /// Information about the constraint code, e.g. Register, RegisterClass,
3554  /// Memory, Other, Unknown.
3556 
3557  /// If this is the result output operand or a clobber, this is null,
3558  /// otherwise it is the incoming operand to the CallInst. This gets
3559  /// modified as the asm is processed.
3560  Value *CallOperandVal = nullptr;
3561 
3562  /// The ValueType for the operand value.
3563  MVT ConstraintVT = MVT::Other;
3564 
3565  /// Copy constructor for copying from a ConstraintInfo.
3567  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3568 
3569  /// Return true of this is an input operand that is a matching constraint
3570  /// like "4".
3571  bool isMatchingInputConstraint() const;
3572 
3573  /// If this is an input matching constraint, this method returns the output
3574  /// operand it matches.
3575  unsigned getMatchedOperand() const;
3576  };
3577 
3578  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3579 
3580  /// Split up the constraint string from the inline assembly value into the
3581  /// specific constraints and their prefixes, and also tie in the associated
3582  /// operand values. If this returns an empty vector, and if the constraint
3583  /// string itself isn't empty, there was an error parsing.
3584  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3585  const TargetRegisterInfo *TRI,
3586  ImmutableCallSite CS) const;
3587 
3588  /// Examine constraint type and operand type and determine a weight value.
3589  /// The operand object must already have been set up with the operand type.
3590  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3591  AsmOperandInfo &info, int maIndex) const;
3592 
3593  /// Examine constraint string and operand type and determine a weight value.
3594  /// The operand object must already have been set up with the operand type.
3595  virtual ConstraintWeight getSingleConstraintMatchWeight(
3596  AsmOperandInfo &info, const char *constraint) const;
3597 
3598  /// Determines the constraint code and constraint type to use for the specific
3599  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3600  /// If the actual operand being passed in is available, it can be passed in as
3601  /// Op, otherwise an empty SDValue can be passed.
3602  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3603  SDValue Op,
3604  SelectionDAG *DAG = nullptr) const;
3605 
3606  /// Given a constraint, return the type of constraint it is for this target.
3607  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3608 
3609  /// Given a physical register constraint (e.g. {edx}), return the register
3610  /// number and the register class for the register.
3611  ///
3612  /// Given a register class constraint, like 'r', if this corresponds directly
3613  /// to an LLVM register class, return a register of 0 and the register class
3614  /// pointer.
3615  ///
3616  /// This should only be used for C_Register constraints. On error, this
3617  /// returns a register number of 0 and a null register class pointer.
3618  virtual std::pair<unsigned, const TargetRegisterClass *>
3619  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3620  StringRef Constraint, MVT VT) const;
3621 
3622  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3623  if (ConstraintCode == "i")
3624  return InlineAsm::Constraint_i;
3625  else if (ConstraintCode == "m")
3626  return InlineAsm::Constraint_m;
3628  }
3629 
3630  /// Try to replace an X constraint, which matches anything, with another that
3631  /// has more specific requirements based on the type of the corresponding
3632  /// operand. This returns null if there is no replacement to make.
3633  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3634 
3635  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3636  /// add anything to Ops.
3637  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3638  std::vector<SDValue> &Ops,
3639  SelectionDAG &DAG) const;
3640 
3641  //===--------------------------------------------------------------------===//
3642  // Div utility functions
3643  //
3644  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3645  SmallVectorImpl<SDNode *> &Created) const;
3646  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3647  SmallVectorImpl<SDNode *> &Created) const;
3648 
3649  /// Targets may override this function to provide custom SDIV lowering for
3650  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3651  /// assumes SDIV is expensive and replaces it with a series of other integer
3652  /// operations.
3653  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3654  SelectionDAG &DAG,
3655  SmallVectorImpl<SDNode *> &Created) const;
3656 
3657  /// Indicate whether this target prefers to combine FDIVs with the same
3658  /// divisor. If the transform should never be done, return zero. If the
3659  /// transform should be done, return the minimum number of divisor uses
3660  /// that must exist.
3661  virtual unsigned combineRepeatedFPDivisors() const {
3662  return 0;
3663  }
3664 
3665  /// Hooks for building estimates in place of slower divisions and square
3666  /// roots.
3667 
3668  /// Return either a square root or its reciprocal estimate value for the input
3669  /// operand.
3670  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3671  /// 'Enabled' as set by a potential default override attribute.
3672  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3673  /// refinement iterations required to generate a sufficient (though not
3674  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3675  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3676  /// algorithm implementation that uses either one or two constants.
3677  /// The boolean Reciprocal is used to select whether the estimate is for the
3678  /// square root of the input operand or the reciprocal of its square root.
3679  /// A target may choose to implement its own refinement within this function.
3680  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3681  /// any further refinement of the estimate.
3682  /// An empty SDValue return means no estimate sequence can be created.
3684  int Enabled, int &RefinementSteps,
3685  bool &UseOneConstNR, bool Reciprocal) const {
3686  return SDValue();
3687  }
3688 
3689  /// Return a reciprocal estimate value for the input operand.
3690  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3691  /// 'Enabled' as set by a potential default override attribute.
3692  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3693  /// refinement iterations required to generate a sufficient (though not
3694  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3695  /// A target may choose to implement its own refinement within this function.
3696  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3697  /// any further refinement of the estimate.
3698  /// An empty SDValue return means no estimate sequence can be created.
3700  int Enabled, int &RefinementSteps) const {
3701  return SDValue();
3702  }
3703 
3704  //===--------------------------------------------------------------------===//
3705  // Legalization utility functions
3706  //
3707 
3708  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3709  /// respectively, each computing an n/2-bit part of the result.
3710  /// \param Result A vector that will be filled with the parts of the result
3711  /// in little-endian order.
3712  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3713  /// if you want to control how low bits are extracted from the LHS.
3714  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3715  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3716  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3717  /// \returns true if the node has been expanded, false if it has not
3718  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3719  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3721  SDValue LL = SDValue(), SDValue LH = SDValue(),
3722  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3723 
3724  /// Expand a MUL into two nodes. One that computes the high bits of
3725  /// the result and one that computes the low bits.
3726  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3727  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3728  /// if you want to control how low bits are extracted from the LHS.
3729  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3730  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3731  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3732  /// \returns true if the node has been expanded. false if it has not
3733  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3734  SelectionDAG &DAG, MulExpansionKind Kind,
3735  SDValue LL = SDValue(), SDValue LH = SDValue(),
3736  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3737 
3738  /// Expand funnel shift.
3739  /// \param N Node to expand
3740  /// \param Result output after conversion
3741  /// \returns True, if the expansion was successful, false otherwise
3742  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3743 
3744  /// Expand rotations.
3745  /// \param N Node to expand
3746  /// \param Result output after conversion
3747  /// \returns True, if the expansion was successful, false otherwise
3748  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3749 
3750  /// Expand float(f32) to SINT(i64) conversion
3751  /// \param N Node to expand
3752  /// \param Result output after conversion
3753  /// \returns True, if the expansion was successful, false otherwise
3754  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3755 
3756  /// Expand float to UINT conversion
3757  /// \param N Node to expand
3758  /// \param Result output after conversion
3759  /// \returns True, if the expansion was successful, false otherwise
3760  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3761 
3762  /// Expand UINT(i64) to double(f64) conversion
3763  /// \param N Node to expand
3764  /// \param Result output after conversion
3765  /// \returns True, if the expansion was successful, false otherwise
3766  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3767 
3768  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3769  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3770 
3771  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3772  /// vector nodes can only succeed if all operations are legal/custom.
3773  /// \param N Node to expand
3774  /// \param Result output after conversion
3775  /// \returns True, if the expansion was successful, false otherwise
3776  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3777 
3778  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3779  /// vector nodes can only succeed if all operations are legal/custom.
3780  /// \param N Node to expand
3781  /// \param Result output after conversion
3782  /// \returns True, if the expansion was successful, false otherwise
3783  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3784 
3785  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3786  /// vector nodes can only succeed if all operations are legal/custom.
3787  /// \param N Node to expand
3788  /// \param Result output after conversion
3789  /// \returns True, if the expansion was successful, false otherwise
3790  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3791 
3792  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
3793  /// vector nodes can only succeed if all operations are legal/custom.
3794  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
3795  /// \param N Node to expand
3796  /// \param Result output after conversion
3797  /// \returns True, if the expansion was successful, false otherwise
3798  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3799 
3800  /// Turn load of vector type into a load of the individual elements.
3801  /// \param LD load to expand
3802  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3803  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3804 
3805  // Turn a store of a vector type into stores of the individual elements.
3806  /// \param ST Store with a vector value type
3807  /// \returns MERGE_VALUs of the individual store chains.
3808  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3809 
3810  /// Expands an unaligned load to 2 half-size loads for an integer, and
3811  /// possibly more for vectors.
3812  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3813  SelectionDAG &DAG) const;
3814 
3815  /// Expands an unaligned store to 2 half-size stores for integer values, and
3816  /// possibly more for vectors.
3817  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3818 
3819  /// Increments memory address \p Addr according to the type of the value
3820  /// \p DataVT that should be stored. If the data is stored in compressed
3821  /// form, the memory address should be incremented according to the number of
3822  /// the stored elements. This number is equal to the number of '1's bits
3823  /// in the \p Mask.
3824  /// \p DataVT is a vector type. \p Mask is a vector value.
3825  /// \p DataVT and \p Mask have the same number of vector elements.
3826  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3827  EVT DataVT, SelectionDAG &DAG,
3828  bool IsCompressedMemory) const;
3829 
3830  /// Get a pointer to vector element \p Idx located in memory for a vector of
3831  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3832  /// bounds the returned pointer is unspecified, but will be within the vector
3833  /// bounds.
3834  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3835  SDValue Index) const;
3836 
3837  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3838  /// method accepts integers as its arguments.
3839  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
3840 
3841  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
3842  /// integers as its arguments.
3843  SDValue getExpandedFixedPointMultiplication(SDNode *Node,
3844  SelectionDAG &DAG) const;
3845 
3846  //===--------------------------------------------------------------------===//
3847  // Instruction Emitting Hooks
3848  //
3849 
3850  /// This method should be implemented by targets that mark instructions with
3851  /// the 'usesCustomInserter' flag. These instructions are special in various
3852  /// ways, which require special support to insert. The specified MachineInstr
3853  /// is created but not inserted into any basic blocks, and this method is
3854  /// called to expand it into a sequence of instructions, potentially also
3855  /// creating new basic blocks and control flow.
3856  /// As long as the returned basic block is different (i.e., we created a new
3857  /// one), the custom inserter is free to modify the rest of \p MBB.
3858  virtual MachineBasicBlock *
3859  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3860 
3861  /// This method should be implemented by targets that mark instructions with
3862  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3863  /// instruction selection by target hooks. e.g. To fill in optional defs for
3864  /// ARM 's' setting instructions.
3865  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3866  SDNode *Node) const;
3867 
3868  /// If this function returns true, SelectionDAGBuilder emits a
3869  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3870  virtual bool useLoadStackGuardNode() const {
3871  return false;
3872  }
3873 
3875  const SDLoc &DL) const {
3876  llvm_unreachable("not implemented for this target");
3877  }
3878 
3879  /// Lower TLS global address SDNode for target independent emulated TLS model.
3880  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3881  SelectionDAG &DAG) const;
3882 
3883  /// Expands target specific indirect branch for the case of JumpTable
3884  /// expanasion.
3886  SelectionDAG &DAG) const {
3887  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3888  }
3889 
3890  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3891  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3892  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3893  // combiner can fold the new nodes.
3894  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3895 
3896 private:
3897  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3898  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3899  const SDLoc &DL) const;
3900 
3901  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3902  SDValue N1, ISD::CondCode Cond,
3903  DAGCombinerInfo &DCI,
3904  const SDLoc &DL) const;
3905 };
3906 
3907 /// Given an LLVM IR type and return type attributes, compute the return value
3908 /// EVTs and flags, and optionally also the offsets, if the return value is
3909 /// being lowered to memory.
3912  const TargetLowering &TLI, const DataLayout &DL);
3913 
3914 } // end namespace llvm
3915 
3916 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:878
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:593
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:372
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:311
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:604
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:362
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:257
void * PointerTy
Definition: GenericValue.h:21
bool hasOneUse() const
Return true if there is exactly one use of this node.
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:496
amdgpu Simplify well known AMD library false Value Value const Twine & Name
Definition: BitVector.h:937
virtual bool decomposeMulByConstant(EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:201
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same wi...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:91
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:358
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:62
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:102
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:397
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:122
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:320
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:960
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:466
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:41
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isFloatingPointOperation() const
Definition: Instructions.h:823
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:935
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:15
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:597
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:470
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:89
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool shouldScalarizeBinop(SDValue VecOp) const
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:403
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:942
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
virtual bool shouldConsiderGEPOffsetSplit() const
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:729
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.