LLVM  8.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file describes how to lower LLVM code to machine code. This has two
12 /// main components:
13 ///
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
17 ///
18 /// In addition it has a few other components, like information about FP
19 /// immediates.
20 ///
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
25 
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/CallSite.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/IRBuilder.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/Instruction.h"
49 #include "llvm/IR/Instructions.h"
50 #include "llvm/IR/Type.h"
51 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class IntrinsicInst;
77 struct KnownBits;
78 class LLVMContext;
79 class MachineBasicBlock;
80 class MachineFunction;
81 class MachineInstr;
82 class MachineJumpTableInfo;
83 class MachineLoop;
84 class MachineRegisterInfo;
85 class MCContext;
86 class MCExpr;
87 class Module;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
91 class Value;
92 
93 namespace Sched {
94 
95  enum Preference {
96  None, // No preference
97  Source, // Follow source order.
98  RegPressure, // Scheduling for lowest register pressure.
99  Hybrid, // Scheduling for both latency and register pressure.
100  ILP, // Scheduling for ILP in low register pressure mode.
101  VLIW // Scheduling for VLIW targets.
102  };
103 
104 } // end namespace Sched
105 
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
109 public:
110  /// This enum indicates whether operations are valid for a target, and if not,
111  /// what action should be used to make them valid.
112  enum LegalizeAction : uint8_t {
113  Legal, // The target natively supports this operation.
114  Promote, // This operation should be executed in a larger type.
115  Expand, // Try to expand this to other ops, otherwise use a libcall.
116  LibCall, // Don't try to expand this to other ops, always use a libcall.
117  Custom // Use the LowerOperation hook to implement custom lowering.
118  };
119 
120  /// This enum indicates whether a types are legal for a target, and if not,
121  /// what action should be used to make them valid.
122  enum LegalizeTypeAction : uint8_t {
123  TypeLegal, // The target natively supports this type.
124  TypePromoteInteger, // Replace this integer with a larger one.
125  TypeExpandInteger, // Split this integer into two of half the size.
126  TypeSoftenFloat, // Convert this float to a same size integer type,
127  // if an operation is not supported in target HW.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
178  SDValue Node = SDValue();
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
198  };
199  using ArgListTy = std::vector<ArgListEntry>;
200 
201  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202  ArgListTy &Args) const {};
203 
205  switch (Content) {
206  case UndefinedBooleanContent:
207  // Extend by adding rubbish bits.
208  return ISD::ANY_EXTEND;
209  case ZeroOrOneBooleanContent:
210  // Extend by adding zero bits.
211  return ISD::ZERO_EXTEND;
212  case ZeroOrNegativeOneBooleanContent:
213  // Extend by copying the sign bit.
214  return ISD::SIGN_EXTEND;
215  }
216  llvm_unreachable("Invalid content kind");
217  }
218 
219  /// NOTE: The TargetMachine owns TLOF.
220  explicit TargetLoweringBase(const TargetMachine &TM);
221  TargetLoweringBase(const TargetLoweringBase &) = delete;
222  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223  virtual ~TargetLoweringBase() = default;
224 
225 protected:
226  /// Initialize all of the actions to default values.
227  void initActions();
228 
229 public:
230  const TargetMachine &getTargetMachine() const { return TM; }
231 
232  virtual bool useSoftFloat() const { return false; }
233 
234  /// Return the pointer type for the given address space, defaults to
235  /// the pointer type from the data layout.
236  /// FIXME: The default needs to be removed once all the code is updated.
237  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239  }
240 
241  /// Return the type for frame index, which is determined by
242  /// the alloca address space specified through the data layout.
243  MVT getFrameIndexTy(const DataLayout &DL) const {
244  return getPointerTy(DL, DL.getAllocaAddrSpace());
245  }
246 
247  /// Return the type for operands of fence.
248  /// TODO: Let fence operands be of i32 type and remove this.
249  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250  return getPointerTy(DL);
251  }
252 
253  /// EVT is not used in-tree, but is used by out-of-tree target.
254  /// A documentation for this function would be nice...
255  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
256 
257  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258  bool LegalTypes = true) const;
259 
260  /// Returns the type to be used for the index operand of:
261  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264  return getPointerTy(DL);
265  }
266 
267  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
268  return true;
269  }
270 
271  /// Return true if multiple condition registers are available.
273  return HasMultipleConditionRegisters;
274  }
275 
276  /// Return true if the target has BitExtract instructions.
277  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
278 
279  /// Return the preferred vector type legalization action.
282  // The default action for one element vectors is to scalarize
283  if (VT.getVectorNumElements() == 1)
284  return TypeScalarizeVector;
285  // The default action for other vectors is to promote
286  return TypePromoteInteger;
287  }
288 
289  // There are two general methods for expanding a BUILD_VECTOR node:
290  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
291  // them together.
292  // 2. Build the vector on the stack and then load it.
293  // If this function returns true, then method (1) will be used, subject to
294  // the constraint that all of the necessary shuffles are legal (as determined
295  // by isShuffleMaskLegal). If this function returns false, then method (2) is
296  // always used. The vector type, and the number of defined values, are
297  // provided.
298  virtual bool
300  unsigned DefinedValues) const {
301  return DefinedValues < 3;
302  }
303 
304  /// Return true if integer divide is usually cheaper than a sequence of
305  /// several shifts, adds, and multiplies for this target.
306  /// The definition of "cheaper" may depend on whether we're optimizing
307  /// for speed or for size.
308  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
309 
310  /// Return true if the target can handle a standalone remainder operation.
311  virtual bool hasStandaloneRem(EVT VT) const {
312  return true;
313  }
314 
315  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
316  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
317  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
318  return false;
319  }
320 
321  /// Reciprocal estimate status values used by the functions below.
322  enum ReciprocalEstimate : int {
323  Unspecified = -1,
324  Disabled = 0,
326  };
327 
328  /// Return a ReciprocalEstimate enum value for a square root of the given type
329  /// based on the function's attributes. If the operation is not overridden by
330  /// the function's attributes, "Unspecified" is returned and target defaults
331  /// are expected to be used for instruction selection.
332  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
333 
334  /// Return a ReciprocalEstimate enum value for a division of the given type
335  /// based on the function's attributes. If the operation is not overridden by
336  /// the function's attributes, "Unspecified" is returned and target defaults
337  /// are expected to be used for instruction selection.
338  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
339 
340  /// Return the refinement step count for a square root of the given type based
341  /// on the function's attributes. If the operation is not overridden by
342  /// the function's attributes, "Unspecified" is returned and target defaults
343  /// are expected to be used for instruction selection.
344  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
345 
346  /// Return the refinement step count for a division of the given type based
347  /// on the function's attributes. If the operation is not overridden by
348  /// the function's attributes, "Unspecified" is returned and target defaults
349  /// are expected to be used for instruction selection.
350  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
351 
352  /// Returns true if target has indicated at least one type should be bypassed.
353  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
354 
355  /// Returns map of slow types for division or remainder with corresponding
356  /// fast types
358  return BypassSlowDivWidths;
359  }
360 
361  /// Return true if Flow Control is an expensive operation that should be
362  /// avoided.
363  bool isJumpExpensive() const { return JumpIsExpensive; }
364 
365  /// Return true if selects are only cheaper than branches if the branch is
366  /// unlikely to be predicted right.
368  return PredictableSelectIsExpensive;
369  }
370 
371  /// If a branch or a select condition is skewed in one direction by more than
372  /// this factor, it is very likely to be predicted correctly.
373  virtual BranchProbability getPredictableBranchThreshold() const;
374 
375  /// Return true if the following transform is beneficial:
376  /// fold (conv (load x)) -> (load (conv*)x)
377  /// On architectures that don't natively support some vector loads
378  /// efficiently, casting the load to a smaller vector of larger types and
379  /// loading is more efficient, however, this can be undone by optimizations in
380  /// dag combiner.
381  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
382  EVT BitcastVT) const {
383  // Don't do if we could do an indexed load on the original type, but not on
384  // the new one.
385  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
386  return true;
387 
388  MVT LoadMVT = LoadVT.getSimpleVT();
389 
390  // Don't bother doing this if it's just going to be promoted again later, as
391  // doing so might interfere with other combines.
392  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
393  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
394  return false;
395 
396  return true;
397  }
398 
399  /// Return true if the following transform is beneficial:
400  /// (store (y (conv x)), y*)) -> (store x, (x*))
401  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
402  // Default to the same logic as loads.
403  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
404  }
405 
406  /// Return true if it is expected to be cheaper to do a store of a non-zero
407  /// vector constant with the given size and type for the address space than to
408  /// store the individual scalar element constants.
409  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
410  unsigned NumElem,
411  unsigned AddrSpace) const {
412  return false;
413  }
414 
415  /// Allow store merging after legalization in addition to before legalization.
416  /// This may catch stores that do not exist earlier (eg, stores created from
417  /// intrinsics).
418  virtual bool mergeStoresAfterLegalization() const { return true; }
419 
420  /// Returns if it's reasonable to merge stores to MemVT size.
421  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
422  const SelectionDAG &DAG) const {
423  return true;
424  }
425 
426  /// Return true if it is cheap to speculate a call to intrinsic cttz.
427  virtual bool isCheapToSpeculateCttz() const {
428  return false;
429  }
430 
431  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
432  virtual bool isCheapToSpeculateCtlz() const {
433  return false;
434  }
435 
436  /// Return true if ctlz instruction is fast.
437  virtual bool isCtlzFast() const {
438  return false;
439  }
440 
441  /// Return true if it is safe to transform an integer-domain bitwise operation
442  /// into the equivalent floating-point operation. This should be set to true
443  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
444  /// type.
445  virtual bool hasBitPreservingFPLogic(EVT VT) const {
446  return false;
447  }
448 
449  /// Return true if it is cheaper to split the store of a merged int val
450  /// from a pair of smaller values into multiple stores.
451  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
452  return false;
453  }
454 
455  /// Return if the target supports combining a
456  /// chain like:
457  /// \code
458  /// %andResult = and %val1, #mask
459  /// %icmpResult = icmp %andResult, 0
460  /// \endcode
461  /// into a single machine instruction of a form like:
462  /// \code
463  /// cc = test %register, #mask
464  /// \endcode
465  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
466  return false;
467  }
468 
469  /// Use bitwise logic to make pairs of compares more efficient. For example:
470  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
471  /// This should be true when it takes more than one instruction to lower
472  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
473  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
474  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
475  return false;
476  }
477 
478  /// Return the preferred operand type if the target has a quick way to compare
479  /// integer values of the given size. Assume that any legal integer type can
480  /// be compared efficiently. Targets may override this to allow illegal wide
481  /// types to return a vector type if there is support to compare that type.
482  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
483  MVT VT = MVT::getIntegerVT(NumBits);
484  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
485  }
486 
487  /// Return true if the target should transform:
488  /// (X & Y) == Y ---> (~X & Y) == 0
489  /// (X & Y) != Y ---> (~X & Y) != 0
490  ///
491  /// This may be profitable if the target has a bitwise and-not operation that
492  /// sets comparison flags. A target may want to limit the transformation based
493  /// on the type of Y or if Y is a constant.
494  ///
495  /// Note that the transform will not occur if Y is known to be a power-of-2
496  /// because a mask and compare of a single bit can be handled by inverting the
497  /// predicate, for example:
498  /// (X & 8) == 8 ---> (X & 8) != 0
499  virtual bool hasAndNotCompare(SDValue Y) const {
500  return false;
501  }
502 
503  /// Return true if the target has a bitwise and-not operation:
504  /// X = ~A & B
505  /// This can be used to simplify select or other instructions.
506  virtual bool hasAndNot(SDValue X) const {
507  // If the target has the more complex version of this operation, assume that
508  // it has this operation too.
509  return hasAndNotCompare(X);
510  }
511 
512  /// There are two ways to clear extreme bits (either low or high):
513  /// Mask: x & (-1 << y) (the instcombine canonical form)
514  /// Shifts: x >> y << y
515  /// Return true if the variant with 2 shifts is preferred.
516  /// Return false if there is no preference.
518  // By default, let's assume that no one prefers shifts.
519  return false;
520  }
521 
522  /// Should we tranform the IR-optimal check for whether given truncation
523  /// down into KeptBits would be truncating or not:
524  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
525  /// Into it's more traditional form:
526  /// ((%x << C) a>> C) dstcond %x
527  /// Return true if we should transform.
528  /// Return false if there is no preference.
530  unsigned KeptBits) const {
531  // By default, let's assume that no one prefers shifts.
532  return false;
533  }
534 
535  /// Return true if the target wants to use the optimization that
536  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
537  /// promotedInst1(...(promotedInstN(ext(load)))).
538  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
539 
540  /// Return true if the target can combine store(extractelement VectorTy,
541  /// Idx).
542  /// \p Cost[out] gives the cost of that transformation when this is true.
543  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
544  unsigned &Cost) const {
545  return false;
546  }
547 
548  /// Return true if inserting a scalar into a variable element of an undef
549  /// vector is more efficiently handled by splatting the scalar instead.
550  virtual bool shouldSplatInsEltVarIndex(EVT) const {
551  return false;
552  }
553 
554  /// Return true if target supports floating point exceptions.
556  return HasFloatingPointExceptions;
557  }
558 
559  /// Return true if target always beneficiates from combining into FMA for a
560  /// given value type. This must typically return false on targets where FMA
561  /// takes more cycles to execute than FADD.
562  virtual bool enableAggressiveFMAFusion(EVT VT) const {
563  return false;
564  }
565 
566  /// Return the ValueType of the result of SETCC operations.
567  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
568  EVT VT) const;
569 
570  /// Return the ValueType for comparison libcalls. Comparions libcalls include
571  /// floating point comparion calls, and Ordered/Unordered check calls on
572  /// floating point numbers.
573  virtual
574  MVT::SimpleValueType getCmpLibcallReturnType() const;
575 
576  /// For targets without i1 registers, this gives the nature of the high-bits
577  /// of boolean values held in types wider than i1.
578  ///
579  /// "Boolean values" are special true/false values produced by nodes like
580  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
581  /// Not to be confused with general values promoted from i1. Some cpus
582  /// distinguish between vectors of boolean and scalars; the isVec parameter
583  /// selects between the two kinds. For example on X86 a scalar boolean should
584  /// be zero extended from i1, while the elements of a vector of booleans
585  /// should be sign extended from i1.
586  ///
587  /// Some cpus also treat floating point types the same way as they treat
588  /// vectors instead of the way they treat scalars.
589  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
590  if (isVec)
591  return BooleanVectorContents;
592  return isFloat ? BooleanFloatContents : BooleanContents;
593  }
594 
596  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
597  }
598 
599  /// Return target scheduling preference.
601  return SchedPreferenceInfo;
602  }
603 
604  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
605  /// for different nodes. This function returns the preference (or none) for
606  /// the given node.
608  return Sched::None;
609  }
610 
611  /// Return the register class that should be used for the specified value
612  /// type.
613  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
614  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
615  assert(RC && "This value type is not natively supported!");
616  return RC;
617  }
618 
619  /// Return the 'representative' register class for the specified value
620  /// type.
621  ///
622  /// The 'representative' register class is the largest legal super-reg
623  /// register class for the register class of the value type. For example, on
624  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
625  /// register class is GR64 on x86_64.
626  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
627  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
628  return RC;
629  }
630 
631  /// Return the cost of the 'representative' register class for the specified
632  /// value type.
633  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
634  return RepRegClassCostForVT[VT.SimpleTy];
635  }
636 
637  /// Return true if the target has native support for the specified value type.
638  /// This means that it has a register that directly holds it without
639  /// promotions or expansions.
640  bool isTypeLegal(EVT VT) const {
641  assert(!VT.isSimple() ||
642  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
643  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
644  }
645 
647  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
648  /// that indicates how instruction selection should deal with the type.
649  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
650 
651  public:
653  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
654  TypeLegal);
655  }
656 
658  return ValueTypeActions[VT.SimpleTy];
659  }
660 
662  ValueTypeActions[VT.SimpleTy] = Action;
663  }
664  };
665 
667  return ValueTypeActions;
668  }
669 
670  /// Return how we should legalize values of this type, either it is already
671  /// legal (return 'Legal') or we need to promote it to a larger type (return
672  /// 'Promote'), or we need to expand it into multiple registers of smaller
673  /// integer type (return 'Expand'). 'Custom' is not an option.
675  return getTypeConversion(Context, VT).first;
676  }
678  return ValueTypeActions.getTypeAction(VT);
679  }
680 
681  /// For types supported by the target, this is an identity function. For
682  /// types that must be promoted to larger types, this returns the larger type
683  /// to promote to. For integer types that are larger than the largest integer
684  /// register, this contains one step in the expansion to get to the smaller
685  /// register. For illegal floating point types, this returns the integer type
686  /// to transform to.
687  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
688  return getTypeConversion(Context, VT).second;
689  }
690 
691  /// For types supported by the target, this is an identity function. For
692  /// types that must be expanded (i.e. integer types that are larger than the
693  /// largest integer register or illegal floating point types), this returns
694  /// the largest legal type it will be expanded to.
695  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
696  assert(!VT.isVector());
697  while (true) {
698  switch (getTypeAction(Context, VT)) {
699  case TypeLegal:
700  return VT;
701  case TypeExpandInteger:
702  VT = getTypeToTransformTo(Context, VT);
703  break;
704  default:
705  llvm_unreachable("Type is not legal nor is it to be expanded!");
706  }
707  }
708  }
709 
710  /// Vector types are broken down into some number of legal first class types.
711  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
712  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
713  /// turns into 4 EVT::i32 values with both PPC and X86.
714  ///
715  /// This method returns the number of registers needed, and the VT for each
716  /// register. It also returns the VT and quantity of the intermediate values
717  /// before they are promoted/expanded.
718  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
719  EVT &IntermediateVT,
720  unsigned &NumIntermediates,
721  MVT &RegisterVT) const;
722 
723  /// Certain targets such as MIPS require that some types such as vectors are
724  /// always broken down into scalars in some contexts. This occurs even if the
725  /// vector type is legal.
727  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
728  unsigned &NumIntermediates, MVT &RegisterVT) const {
729  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
730  RegisterVT);
731  }
732 
733  struct IntrinsicInfo {
734  unsigned opc = 0; // target opcode
735  EVT memVT; // memory VT
736 
737  // value representing memory location
739 
740  int offset = 0; // offset off of ptrVal
741  unsigned size = 0; // the size of the memory location
742  // (taken from memVT if zero)
743  unsigned align = 1; // alignment
744 
746  IntrinsicInfo() = default;
747  };
748 
749  /// Given an intrinsic, checks if on the target the intrinsic will need to map
750  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
751  /// true and store the intrinsic information into the IntrinsicInfo that was
752  /// passed to the function.
753  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
754  MachineFunction &,
755  unsigned /*Intrinsic*/) const {
756  return false;
757  }
758 
759  /// Returns true if the target can instruction select the specified FP
760  /// immediate natively. If false, the legalizer will materialize the FP
761  /// immediate as a load from a constant pool.
762  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
763  return false;
764  }
765 
766  /// Targets can use this to indicate that they only support *some*
767  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
768  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
769  /// legal.
770  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
771  return true;
772  }
773 
774  /// Returns true if the operation can trap for the value type.
775  ///
776  /// VT must be a legal type. By default, we optimistically assume most
777  /// operations don't trap except for integer divide and remainder.
778  virtual bool canOpTrap(unsigned Op, EVT VT) const;
779 
780  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
781  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
782  /// constant pool entry.
783  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
784  EVT /*VT*/) const {
785  return false;
786  }
787 
788  /// Return how this operation should be treated: either it is legal, needs to
789  /// be promoted to a larger size, needs to be expanded to some other code
790  /// sequence, or the target has a custom expander for it.
791  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
792  if (VT.isExtended()) return Expand;
793  // If a target-specific SDNode requires legalization, require the target
794  // to provide custom legalization for it.
795  if (Op >= array_lengthof(OpActions[0])) return Custom;
796  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
797  }
798 
800  unsigned EqOpc;
801  switch (Op) {
802  default: llvm_unreachable("Unexpected FP pseudo-opcode");
803  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
804  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
805  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
806  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
807  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
808  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
809  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
810  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
811  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
812  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
813  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
814  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
815  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
816  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
817  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
818  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
819  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
820  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
821  }
822 
823  auto Action = getOperationAction(EqOpc, VT);
824 
825  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
826  // For now, we just expand for those cases.
827  if (Action != Legal)
828  Action = Expand;
829 
830  return Action;
831  }
832 
833  /// Return true if the specified operation is legal on this target or can be
834  /// made legal with custom lowering. This is used to help guide high-level
835  /// lowering decisions.
836  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
837  return (VT == MVT::Other || isTypeLegal(VT)) &&
838  (getOperationAction(Op, VT) == Legal ||
839  getOperationAction(Op, VT) == Custom);
840  }
841 
842  /// Return true if the specified operation is legal on this target or can be
843  /// made legal using promotion. This is used to help guide high-level lowering
844  /// decisions.
845  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
846  return (VT == MVT::Other || isTypeLegal(VT)) &&
847  (getOperationAction(Op, VT) == Legal ||
848  getOperationAction(Op, VT) == Promote);
849  }
850 
851  /// Return true if the specified operation is legal on this target or can be
852  /// made legal with custom lowering or using promotion. This is used to help
853  /// guide high-level lowering decisions.
854  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
855  return (VT == MVT::Other || isTypeLegal(VT)) &&
856  (getOperationAction(Op, VT) == Legal ||
857  getOperationAction(Op, VT) == Custom ||
858  getOperationAction(Op, VT) == Promote);
859  }
860 
861  /// Return true if the operation uses custom lowering, regardless of whether
862  /// the type is legal or not.
863  bool isOperationCustom(unsigned Op, EVT VT) const {
864  return getOperationAction(Op, VT) == Custom;
865  }
866 
867  /// Return true if lowering to a jump table is allowed.
868  virtual bool areJTsAllowed(const Function *Fn) const {
869  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
870  return false;
871 
872  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
873  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
874  }
875 
876  /// Check whether the range [Low,High] fits in a machine word.
877  bool rangeFitsInWord(const APInt &Low, const APInt &High,
878  const DataLayout &DL) const {
879  // FIXME: Using the pointer type doesn't seem ideal.
880  uint64_t BW = DL.getIndexSizeInBits(0u);
881  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
882  return Range <= BW;
883  }
884 
885  /// Return true if lowering to a jump table is suitable for a set of case
886  /// clusters which may contain \p NumCases cases, \p Range range of values.
887  /// FIXME: This function check the maximum table size and density, but the
888  /// minimum size is not checked. It would be nice if the minimum size is
889  /// also combined within this function. Currently, the minimum size check is
890  /// performed in findJumpTable() in SelectionDAGBuiler and
891  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
892  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
893  uint64_t Range) const {
894  const bool OptForSize = SI->getParent()->getParent()->optForSize();
895  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
896  const unsigned MaxJumpTableSize =
897  OptForSize || getMaximumJumpTableSize() == 0
898  ? UINT_MAX
899  : getMaximumJumpTableSize();
900  // Check whether a range of clusters is dense enough for a jump table.
901  if (Range <= MaxJumpTableSize &&
902  (NumCases * 100 >= Range * MinDensity)) {
903  return true;
904  }
905  return false;
906  }
907 
908  /// Return true if lowering to a bit test is suitable for a set of case
909  /// clusters which contains \p NumDests unique destinations, \p Low and
910  /// \p High as its lowest and highest case values, and expects \p NumCmps
911  /// case value comparisons. Check if the number of destinations, comparison
912  /// metric, and range are all suitable.
913  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
914  const APInt &Low, const APInt &High,
915  const DataLayout &DL) const {
916  // FIXME: I don't think NumCmps is the correct metric: a single case and a
917  // range of cases both require only one branch to lower. Just looking at the
918  // number of clusters and destinations should be enough to decide whether to
919  // build bit tests.
920 
921  // To lower a range with bit tests, the range must fit the bitwidth of a
922  // machine word.
923  if (!rangeFitsInWord(Low, High, DL))
924  return false;
925 
926  // Decide whether it's profitable to lower this range with bit tests. Each
927  // destination requires a bit test and branch, and there is an overall range
928  // check branch. For a small number of clusters, separate comparisons might
929  // be cheaper, and for many destinations, splitting the range might be
930  // better.
931  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
932  (NumDests == 3 && NumCmps >= 6);
933  }
934 
935  /// Return true if the specified operation is illegal on this target or
936  /// unlikely to be made legal with custom lowering. This is used to help guide
937  /// high-level lowering decisions.
938  bool isOperationExpand(unsigned Op, EVT VT) const {
939  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
940  }
941 
942  /// Return true if the specified operation is legal on this target.
943  bool isOperationLegal(unsigned Op, EVT VT) const {
944  return (VT == MVT::Other || isTypeLegal(VT)) &&
945  getOperationAction(Op, VT) == Legal;
946  }
947 
948  /// Return how this load with extension should be treated: either it is legal,
949  /// needs to be promoted to a larger size, needs to be expanded to some other
950  /// code sequence, or the target has a custom expander for it.
952  EVT MemVT) const {
953  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
954  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
955  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
956  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
957  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
958  unsigned Shift = 4 * ExtType;
959  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
960  }
961 
962  /// Return true if the specified load with extension is legal on this target.
963  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
964  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
965  }
966 
967  /// Return true if the specified load with extension is legal or custom
968  /// on this target.
969  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
970  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
971  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
972  }
973 
974  /// Return how this store with truncation should be treated: either it is
975  /// legal, needs to be promoted to a larger size, needs to be expanded to some
976  /// other code sequence, or the target has a custom expander for it.
978  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
979  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
980  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
982  "Table isn't big enough!");
983  return TruncStoreActions[ValI][MemI];
984  }
985 
986  /// Return true if the specified store with truncation is legal on this
987  /// target.
988  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
989  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
990  }
991 
992  /// Return true if the specified store with truncation has solution on this
993  /// target.
994  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
995  return isTypeLegal(ValVT) &&
996  (getTruncStoreAction(ValVT, MemVT) == Legal ||
997  getTruncStoreAction(ValVT, MemVT) == Custom);
998  }
999 
1000  /// Return how the indexed load should be treated: either it is legal, needs
1001  /// to be promoted to a larger size, needs to be expanded to some other code
1002  /// sequence, or the target has a custom expander for it.
1004  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1005  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1006  "Table isn't big enough!");
1007  unsigned Ty = (unsigned)VT.SimpleTy;
1008  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1009  }
1010 
1011  /// Return true if the specified indexed load is legal on this target.
1012  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1013  return VT.isSimple() &&
1014  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1015  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1016  }
1017 
1018  /// Return how the indexed store should be treated: either it is legal, needs
1019  /// to be promoted to a larger size, needs to be expanded to some other code
1020  /// sequence, or the target has a custom expander for it.
1022  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1023  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1024  "Table isn't big enough!");
1025  unsigned Ty = (unsigned)VT.SimpleTy;
1026  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1027  }
1028 
1029  /// Return true if the specified indexed load is legal on this target.
1030  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1031  return VT.isSimple() &&
1032  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1033  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1034  }
1035 
1036  /// Return how the condition code should be treated: either it is legal, needs
1037  /// to be expanded to some other code sequence, or the target has a custom
1038  /// expander for it.
1041  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1042  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1043  "Table isn't big enough!");
1044  // See setCondCodeAction for how this is encoded.
1045  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1046  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1047  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1048  assert(Action != Promote && "Can't promote condition code!");
1049  return Action;
1050  }
1051 
1052  /// Return true if the specified condition code is legal on this target.
1053  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1054  return getCondCodeAction(CC, VT) == Legal;
1055  }
1056 
1057  /// Return true if the specified condition code is legal or custom on this
1058  /// target.
1060  return getCondCodeAction(CC, VT) == Legal ||
1061  getCondCodeAction(CC, VT) == Custom;
1062  }
1063 
1064  /// If the action for this operation is to promote, this method returns the
1065  /// ValueType to promote to.
1066  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1067  assert(getOperationAction(Op, VT) == Promote &&
1068  "This operation isn't promoted!");
1069 
1070  // See if this has an explicit type specified.
1071  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1072  MVT::SimpleValueType>::const_iterator PTTI =
1073  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1074  if (PTTI != PromoteToType.end()) return PTTI->second;
1075 
1076  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1077  "Cannot autopromote this type, add it with AddPromotedToType.");
1078 
1079  MVT NVT = VT;
1080  do {
1081  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1082  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1083  "Didn't find type to promote to!");
1084  } while (!isTypeLegal(NVT) ||
1085  getOperationAction(Op, NVT) == Promote);
1086  return NVT;
1087  }
1088 
1089  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1090  /// operations except for the pointer size. If AllowUnknown is true, this
1091  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1092  /// otherwise it will assert.
1094  bool AllowUnknown = false) const {
1095  // Lower scalar pointers to native pointer types.
1096  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1097  return getPointerTy(DL, PTy->getAddressSpace());
1098 
1099  if (Ty->isVectorTy()) {
1100  VectorType *VTy = cast<VectorType>(Ty);
1101  Type *Elm = VTy->getElementType();
1102  // Lower vectors of pointers to native pointer types.
1103  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1104  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1105  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1106  }
1107 
1108  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1109  VTy->getNumElements());
1110  }
1111  return EVT::getEVT(Ty, AllowUnknown);
1112  }
1113 
1114  /// Return the MVT corresponding to this LLVM type. See getValueType.
1116  bool AllowUnknown = false) const {
1117  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1118  }
1119 
1120  /// Return the desired alignment for ByVal or InAlloca aggregate function
1121  /// arguments in the caller parameter area. This is the actual alignment, not
1122  /// its logarithm.
1123  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1124 
1125  /// Return the type of registers that this ValueType will eventually require.
1127  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1128  return RegisterTypeForVT[VT.SimpleTy];
1129  }
1130 
1131  /// Return the type of registers that this ValueType will eventually require.
1132  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1133  if (VT.isSimple()) {
1134  assert((unsigned)VT.getSimpleVT().SimpleTy <
1135  array_lengthof(RegisterTypeForVT));
1136  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1137  }
1138  if (VT.isVector()) {
1139  EVT VT1;
1140  MVT RegisterVT;
1141  unsigned NumIntermediates;
1142  (void)getVectorTypeBreakdown(Context, VT, VT1,
1143  NumIntermediates, RegisterVT);
1144  return RegisterVT;
1145  }
1146  if (VT.isInteger()) {
1147  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1148  }
1149  llvm_unreachable("Unsupported extended type!");
1150  }
1151 
1152  /// Return the number of registers that this ValueType will eventually
1153  /// require.
1154  ///
1155  /// This is one for any types promoted to live in larger registers, but may be
1156  /// more than one for types (like i64) that are split into pieces. For types
1157  /// like i140, which are first promoted then expanded, it is the number of
1158  /// registers needed to hold all the bits of the original type. For an i140
1159  /// on a 32 bit machine this means 5 registers.
1160  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1161  if (VT.isSimple()) {
1162  assert((unsigned)VT.getSimpleVT().SimpleTy <
1163  array_lengthof(NumRegistersForVT));
1164  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1165  }
1166  if (VT.isVector()) {
1167  EVT VT1;
1168  MVT VT2;
1169  unsigned NumIntermediates;
1170  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1171  }
1172  if (VT.isInteger()) {
1173  unsigned BitWidth = VT.getSizeInBits();
1174  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1175  return (BitWidth + RegWidth - 1) / RegWidth;
1176  }
1177  llvm_unreachable("Unsupported extended type!");
1178  }
1179 
1180  /// Certain combinations of ABIs, Targets and features require that types
1181  /// are legal for some operations and not for other operations.
1182  /// For MIPS all vector types must be passed through the integer register set.
1184  CallingConv::ID CC, EVT VT) const {
1185  return getRegisterType(Context, VT);
1186  }
1187 
1188  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1189  /// this occurs when a vector type is used, as vector are passed through the
1190  /// integer register set.
1191  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1192  CallingConv::ID CC,
1193  EVT VT) const {
1194  return getNumRegisters(Context, VT);
1195  }
1196 
1197  /// Certain targets have context senstive alignment requirements, where one
1198  /// type has the alignment requirement of another type.
1199  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1200  DataLayout DL) const {
1201  return DL.getABITypeAlignment(ArgTy);
1202  }
1203 
1204  /// If true, then instruction selection should seek to shrink the FP constant
1205  /// of the specified type to a smaller type in order to save space and / or
1206  /// reduce runtime.
1207  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1208 
1209  // Return true if it is profitable to reduce the given load node to a smaller
1210  // type.
1211  //
1212  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1214  ISD::LoadExtType ExtTy,
1215  EVT NewVT) const {
1216  return true;
1217  }
1218 
1219  /// When splitting a value of the specified type into parts, does the Lo
1220  /// or Hi part come first? This usually follows the endianness, except
1221  /// for ppcf128, where the Hi part always comes first.
1222  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1223  return DL.isBigEndian() || VT == MVT::ppcf128;
1224  }
1225 
1226  /// If true, the target has custom DAG combine transformations that it can
1227  /// perform for the specified node.
1229  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1230  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1231  }
1232 
1233  unsigned getGatherAllAliasesMaxDepth() const {
1234  return GatherAllAliasesMaxDepth;
1235  }
1236 
1237  /// Returns the size of the platform's va_list object.
1238  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1239  return getPointerTy(DL).getSizeInBits();
1240  }
1241 
1242  /// Get maximum # of store operations permitted for llvm.memset
1243  ///
1244  /// This function returns the maximum number of store operations permitted
1245  /// to replace a call to llvm.memset. The value is set by the target at the
1246  /// performance threshold for such a replacement. If OptSize is true,
1247  /// return the limit for functions that have OptSize attribute.
1248  unsigned getMaxStoresPerMemset(bool OptSize) const {
1249  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1250  }
1251 
1252  /// Get maximum # of store operations permitted for llvm.memcpy
1253  ///
1254  /// This function returns the maximum number of store operations permitted
1255  /// to replace a call to llvm.memcpy. The value is set by the target at the
1256  /// performance threshold for such a replacement. If OptSize is true,
1257  /// return the limit for functions that have OptSize attribute.
1258  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1259  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1260  }
1261 
1262  /// \brief Get maximum # of store operations to be glued together
1263  ///
1264  /// This function returns the maximum number of store operations permitted
1265  /// to glue together during lowering of llvm.memcpy. The value is set by
1266  // the target at the performance threshold for such a replacement.
1267  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1268  return MaxGluedStoresPerMemcpy;
1269  }
1270 
1271  /// Get maximum # of load operations permitted for memcmp
1272  ///
1273  /// This function returns the maximum number of load operations permitted
1274  /// to replace a call to memcmp. The value is set by the target at the
1275  /// performance threshold for such a replacement. If OptSize is true,
1276  /// return the limit for functions that have OptSize attribute.
1277  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1278  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1279  }
1280 
1281  /// For memcmp expansion when the memcmp result is only compared equal or
1282  /// not-equal to 0, allow up to this number of load pairs per block. As an
1283  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1284  /// a0 = load2bytes &a[0]
1285  /// b0 = load2bytes &b[0]
1286  /// a2 = load1byte &a[2]
1287  /// b2 = load1byte &b[2]
1288  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1289  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1290  return 1;
1291  }
1292 
1293  /// Get maximum # of store operations permitted for llvm.memmove
1294  ///
1295  /// This function returns the maximum number of store operations permitted
1296  /// to replace a call to llvm.memmove. The value is set by the target at the
1297  /// performance threshold for such a replacement. If OptSize is true,
1298  /// return the limit for functions that have OptSize attribute.
1299  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1300  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1301  }
1302 
1303  /// Determine if the target supports unaligned memory accesses.
1304  ///
1305  /// This function returns true if the target allows unaligned memory accesses
1306  /// of the specified type in the given address space. If true, it also returns
1307  /// whether the unaligned memory access is "fast" in the last argument by
1308  /// reference. This is used, for example, in situations where an array
1309  /// copy/move/set is converted to a sequence of store operations. Its use
1310  /// helps to ensure that such replacements don't generate code that causes an
1311  /// alignment error (trap) on the target machine.
1313  unsigned AddrSpace = 0,
1314  unsigned Align = 1,
1315  bool * /*Fast*/ = nullptr) const {
1316  return false;
1317  }
1318 
1319  /// Return true if the target supports a memory access of this type for the
1320  /// given address space and alignment. If the access is allowed, the optional
1321  /// final parameter returns if the access is also fast (as defined by the
1322  /// target).
1323  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1324  unsigned AddrSpace = 0, unsigned Alignment = 1,
1325  bool *Fast = nullptr) const;
1326 
1327  /// Returns the target specific optimal type for load and store operations as
1328  /// a result of memset, memcpy, and memmove lowering.
1329  ///
1330  /// If DstAlign is zero that means it's safe to destination alignment can
1331  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1332  /// a need to check it against alignment requirement, probably because the
1333  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1334  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1335  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1336  /// does not need to be loaded. It returns EVT::Other if the type should be
1337  /// determined using generic target-independent logic.
1338  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1339  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1340  bool /*IsMemset*/,
1341  bool /*ZeroMemset*/,
1342  bool /*MemcpyStrSrc*/,
1343  MachineFunction &/*MF*/) const {
1344  return MVT::Other;
1345  }
1346 
1347  /// Returns true if it's safe to use load / store of the specified type to
1348  /// expand memcpy / memset inline.
1349  ///
1350  /// This is mostly true for all types except for some special cases. For
1351  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1352  /// fstpl which also does type conversion. Note the specified type doesn't
1353  /// have to be legal as the hook is used before type legalization.
1354  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1355 
1356  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1357  bool usesUnderscoreSetJmp() const {
1358  return UseUnderscoreSetJmp;
1359  }
1360 
1361  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1362  bool usesUnderscoreLongJmp() const {
1363  return UseUnderscoreLongJmp;
1364  }
1365 
1366  /// Return lower limit for number of blocks in a jump table.
1367  virtual unsigned getMinimumJumpTableEntries() const;
1368 
1369  /// Return lower limit of the density in a jump table.
1370  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1371 
1372  /// Return upper limit for number of entries in a jump table.
1373  /// Zero if no limit.
1374  unsigned getMaximumJumpTableSize() const;
1375 
1376  virtual bool isJumpTableRelative() const {
1377  return TM.isPositionIndependent();
1378  }
1379 
1380  /// If a physical register, this specifies the register that
1381  /// llvm.savestack/llvm.restorestack should save and restore.
1383  return StackPointerRegisterToSaveRestore;
1384  }
1385 
1386  /// If a physical register, this returns the register that receives the
1387  /// exception address on entry to an EH pad.
1388  virtual unsigned
1389  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1390  // 0 is guaranteed to be the NoRegister value on all targets
1391  return 0;
1392  }
1393 
1394  /// If a physical register, this returns the register that receives the
1395  /// exception typeid on entry to a landing pad.
1396  virtual unsigned
1397  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1398  // 0 is guaranteed to be the NoRegister value on all targets
1399  return 0;
1400  }
1401 
1402  virtual bool needsFixedCatchObjects() const {
1403  report_fatal_error("Funclet EH is not implemented for this target");
1404  }
1405 
1406  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1407  /// 200)
1408  unsigned getJumpBufSize() const {
1409  return JumpBufSize;
1410  }
1411 
1412  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1413  /// is 0)
1414  unsigned getJumpBufAlignment() const {
1415  return JumpBufAlignment;
1416  }
1417 
1418  /// Return the minimum stack alignment of an argument.
1419  unsigned getMinStackArgumentAlignment() const {
1420  return MinStackArgumentAlignment;
1421  }
1422 
1423  /// Return the minimum function alignment.
1424  unsigned getMinFunctionAlignment() const {
1425  return MinFunctionAlignment;
1426  }
1427 
1428  /// Return the preferred function alignment.
1429  unsigned getPrefFunctionAlignment() const {
1430  return PrefFunctionAlignment;
1431  }
1432 
1433  /// Return the preferred loop alignment.
1434  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1435  return PrefLoopAlignment;
1436  }
1437 
1438  /// Should loops be aligned even when the function is marked OptSize (but not
1439  /// MinSize).
1440  virtual bool alignLoopsWithOptSize() const {
1441  return false;
1442  }
1443 
1444  /// If the target has a standard location for the stack protector guard,
1445  /// returns the address of that location. Otherwise, returns nullptr.
1446  /// DEPRECATED: please override useLoadStackGuardNode and customize
1447  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1448  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1449 
1450  /// Inserts necessary declarations for SSP (stack protection) purpose.
1451  /// Should be used only when getIRStackGuard returns nullptr.
1452  virtual void insertSSPDeclarations(Module &M) const;
1453 
1454  /// Return the variable that's previously inserted by insertSSPDeclarations,
1455  /// if any, otherwise return nullptr. Should be used only when
1456  /// getIRStackGuard returns nullptr.
1457  virtual Value *getSDagStackGuard(const Module &M) const;
1458 
1459  /// If this function returns true, stack protection checks should XOR the
1460  /// frame pointer (or whichever pointer is used to address locals) into the
1461  /// stack guard value before checking it. getIRStackGuard must return nullptr
1462  /// if this returns true.
1463  virtual bool useStackGuardXorFP() const { return false; }
1464 
1465  /// If the target has a standard stack protection check function that
1466  /// performs validation and error handling, returns the function. Otherwise,
1467  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1468  /// Should be used only when getIRStackGuard returns nullptr.
1469  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1470 
1471 protected:
1472  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1473  bool UseTLS) const;
1474 
1475 public:
1476  /// Returns the target-specific address of the unsafe stack pointer.
1477  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1478 
1479  /// Returns the name of the symbol used to emit stack probes or the empty
1480  /// string if not applicable.
1482  return "";
1483  }
1484 
1485  /// Returns true if a cast between SrcAS and DestAS is a noop.
1486  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1487  return false;
1488  }
1489 
1490  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1491  /// are happy to sink it into basic blocks.
1492  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1493  return isNoopAddrSpaceCast(SrcAS, DestAS);
1494  }
1495 
1496  /// Return true if the pointer arguments to CI should be aligned by aligning
1497  /// the object whose address is being passed. If so then MinSize is set to the
1498  /// minimum size the object must be to be aligned and PrefAlign is set to the
1499  /// preferred alignment.
1500  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1501  unsigned & /*PrefAlign*/) const {
1502  return false;
1503  }
1504 
1505  //===--------------------------------------------------------------------===//
1506  /// \name Helpers for TargetTransformInfo implementations
1507  /// @{
1508 
1509  /// Get the ISD node that corresponds to the Instruction class opcode.
1510  int InstructionOpcodeToISD(unsigned Opcode) const;
1511 
1512  /// Estimate the cost of type-legalization and the legalized type.
1513  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1514  Type *Ty) const;
1515 
1516  /// @}
1517 
1518  //===--------------------------------------------------------------------===//
1519  /// \name Helpers for atomic expansion.
1520  /// @{
1521 
1522  /// Returns the maximum atomic operation size (in bits) supported by
1523  /// the backend. Atomic operations greater than this size (as well
1524  /// as ones that are not naturally aligned), will be expanded by
1525  /// AtomicExpandPass into an __atomic_* library call.
1527  return MaxAtomicSizeInBitsSupported;
1528  }
1529 
1530  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1531  /// the backend supports. Any smaller operations are widened in
1532  /// AtomicExpandPass.
1533  ///
1534  /// Note that *unlike* operations above the maximum size, atomic ops
1535  /// are still natively supported below the minimum; they just
1536  /// require a more complex expansion.
1537  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1538 
1539  /// Whether the target supports unaligned atomic operations.
1540  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1541 
1542  /// Whether AtomicExpandPass should automatically insert fences and reduce
1543  /// ordering for this atomic. This should be true for most architectures with
1544  /// weak memory ordering. Defaults to false.
1545  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1546  return false;
1547  }
1548 
1549  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1550  /// corresponding pointee type. This may entail some non-trivial operations to
1551  /// truncate or reconstruct types that will be illegal in the backend. See
1552  /// ARMISelLowering for an example implementation.
1553  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1554  AtomicOrdering Ord) const {
1555  llvm_unreachable("Load linked unimplemented on this target");
1556  }
1557 
1558  /// Perform a store-conditional operation to Addr. Return the status of the
1559  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1560  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1561  Value *Addr, AtomicOrdering Ord) const {
1562  llvm_unreachable("Store conditional unimplemented on this target");
1563  }
1564 
1565  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1566  /// It is called by AtomicExpandPass before expanding an
1567  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1568  /// if shouldInsertFencesForAtomic returns true.
1569  ///
1570  /// Inst is the original atomic instruction, prior to other expansions that
1571  /// may be performed.
1572  ///
1573  /// This function should either return a nullptr, or a pointer to an IR-level
1574  /// Instruction*. Even complex fence sequences can be represented by a
1575  /// single Instruction* through an intrinsic to be lowered later.
1576  /// Backends should override this method to produce target-specific intrinsic
1577  /// for their fences.
1578  /// FIXME: Please note that the default implementation here in terms of
1579  /// IR-level fences exists for historical/compatibility reasons and is
1580  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1581  /// consistency. For example, consider the following example:
1582  /// atomic<int> x = y = 0;
1583  /// int r1, r2, r3, r4;
1584  /// Thread 0:
1585  /// x.store(1);
1586  /// Thread 1:
1587  /// y.store(1);
1588  /// Thread 2:
1589  /// r1 = x.load();
1590  /// r2 = y.load();
1591  /// Thread 3:
1592  /// r3 = y.load();
1593  /// r4 = x.load();
1594  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1595  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1596  /// IR-level fences can prevent it.
1597  /// @{
1599  AtomicOrdering Ord) const {
1600  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1601  return Builder.CreateFence(Ord);
1602  else
1603  return nullptr;
1604  }
1605 
1607  Instruction *Inst,
1608  AtomicOrdering Ord) const {
1609  if (isAcquireOrStronger(Ord))
1610  return Builder.CreateFence(Ord);
1611  else
1612  return nullptr;
1613  }
1614  /// @}
1615 
1616  // Emits code that executes when the comparison result in the ll/sc
1617  // expansion of a cmpxchg instruction is such that the store-conditional will
1618  // not execute. This makes it possible to balance out the load-linked with
1619  // a dedicated instruction, if desired.
1620  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1621  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1622  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1623 
1624  /// Returns true if the given (atomic) store should be expanded by the
1625  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1627  return false;
1628  }
1629 
1630  /// Returns true if arguments should be sign-extended in lib calls.
1631  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1632  return IsSigned;
1633  }
1634 
1635  /// Returns how the given (atomic) load should be expanded by the
1636  /// IR-level AtomicExpand pass.
1639  }
1640 
1641  /// Returns true if the given atomic cmpxchg should be expanded by the
1642  /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1643  /// (through emitLoadLinked() and emitStoreConditional()).
1645  return false;
1646  }
1647 
1648  /// Returns how the IR-level AtomicExpand pass should expand the given
1649  /// AtomicRMW, if at all. Default is to never expand.
1652  }
1653 
1654  /// On some platforms, an AtomicRMW that never actually modifies the value
1655  /// (such as fetch_add of 0) can be turned into a fence followed by an
1656  /// atomic load. This may sound useless, but it makes it possible for the
1657  /// processor to keep the cacheline shared, dramatically improving
1658  /// performance. And such idempotent RMWs are useful for implementing some
1659  /// kinds of locks, see for example (justification + benchmarks):
1660  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1661  /// This method tries doing that transformation, returning the atomic load if
1662  /// it succeeds, and nullptr otherwise.
1663  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1664  /// another round of expansion.
1665  virtual LoadInst *
1667  return nullptr;
1668  }
1669 
1670  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1671  /// SIGN_EXTEND, or ANY_EXTEND).
1673  return ISD::ZERO_EXTEND;
1674  }
1675 
1676  /// @}
1677 
1678  /// Returns true if we should normalize
1679  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1680  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1681  /// that it saves us from materializing N0 and N1 in an integer register.
1682  /// Targets that are able to perform and/or on flags should return false here.
1684  EVT VT) const {
1685  // If a target has multiple condition registers, then it likely has logical
1686  // operations on those registers.
1687  if (hasMultipleConditionRegisters())
1688  return false;
1689  // Only do the transform if the value won't be split into multiple
1690  // registers.
1691  LegalizeTypeAction Action = getTypeAction(Context, VT);
1692  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1693  Action != TypeSplitVector;
1694  }
1695 
1696  /// Return true if a select of constants (select Cond, C1, C2) should be
1697  /// transformed into simple math ops with the condition value. For example:
1698  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1699  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1700  return false;
1701  }
1702 
1703  //===--------------------------------------------------------------------===//
1704  // TargetLowering Configuration Methods - These methods should be invoked by
1705  // the derived class constructor to configure this object for the target.
1706  //
1707 protected:
1708  /// Specify how the target extends the result of integer and floating point
1709  /// boolean values from i1 to a wider type. See getBooleanContents.
1711  BooleanContents = Ty;
1712  BooleanFloatContents = Ty;
1713  }
1714 
1715  /// Specify how the target extends the result of integer and floating point
1716  /// boolean values from i1 to a wider type. See getBooleanContents.
1718  BooleanContents = IntTy;
1719  BooleanFloatContents = FloatTy;
1720  }
1721 
1722  /// Specify how the target extends the result of a vector boolean value from a
1723  /// vector of i1 to a wider type. See getBooleanContents.
1725  BooleanVectorContents = Ty;
1726  }
1727 
1728  /// Specify the target scheduling preference.
1730  SchedPreferenceInfo = Pref;
1731  }
1732 
1733  /// Indicate whether this target prefers to use _setjmp to implement
1734  /// llvm.setjmp or the version without _. Defaults to false.
1735  void setUseUnderscoreSetJmp(bool Val) {
1736  UseUnderscoreSetJmp = Val;
1737  }
1738 
1739  /// Indicate whether this target prefers to use _longjmp to implement
1740  /// llvm.longjmp or the version without _. Defaults to false.
1741  void setUseUnderscoreLongJmp(bool Val) {
1742  UseUnderscoreLongJmp = Val;
1743  }
1744 
1745  /// Indicate the minimum number of blocks to generate jump tables.
1746  void setMinimumJumpTableEntries(unsigned Val);
1747 
1748  /// Indicate the maximum number of entries in jump tables.
1749  /// Set to zero to generate unlimited jump tables.
1750  void setMaximumJumpTableSize(unsigned);
1751 
1752  /// If set to a physical register, this specifies the register that
1753  /// llvm.savestack/llvm.restorestack should save and restore.
1755  StackPointerRegisterToSaveRestore = R;
1756  }
1757 
1758  /// Tells the code generator that the target has multiple (allocatable)
1759  /// condition registers that can be used to store the results of comparisons
1760  /// for use by selects and conditional branches. With multiple condition
1761  /// registers, the code generator will not aggressively sink comparisons into
1762  /// the blocks of their users.
1763  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1764  HasMultipleConditionRegisters = hasManyRegs;
1765  }
1766 
1767  /// Tells the code generator that the target has BitExtract instructions.
1768  /// The code generator will aggressively sink "shift"s into the blocks of
1769  /// their users if the users will generate "and" instructions which can be
1770  /// combined with "shift" to BitExtract instructions.
1771  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1772  HasExtractBitsInsn = hasExtractInsn;
1773  }
1774 
1775  /// Tells the code generator not to expand logic operations on comparison
1776  /// predicates into separate sequences that increase the amount of flow
1777  /// control.
1778  void setJumpIsExpensive(bool isExpensive = true);
1779 
1780  /// Tells the code generator that this target supports floating point
1781  /// exceptions and cares about preserving floating point exception behavior.
1782  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1783  HasFloatingPointExceptions = FPExceptions;
1784  }
1785 
1786  /// Tells the code generator which bitwidths to bypass.
1787  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1788  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1789  }
1790 
1791  /// Add the specified register class as an available regclass for the
1792  /// specified value type. This indicates the selector can handle values of
1793  /// that class natively.
1795  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1796  RegClassForVT[VT.SimpleTy] = RC;
1797  }
1798 
1799  /// Return the largest legal super-reg register class of the register class
1800  /// for the specified type and its associated "cost".
1801  virtual std::pair<const TargetRegisterClass *, uint8_t>
1802  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1803 
1804  /// Once all of the register classes are added, this allows us to compute
1805  /// derived properties we expose.
1806  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1807 
1808  /// Indicate that the specified operation does not work with the specified
1809  /// type and indicate what to do about it. Note that VT may refer to either
1810  /// the type of a result or that of an operand of Op.
1811  void setOperationAction(unsigned Op, MVT VT,
1812  LegalizeAction Action) {
1813  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1814  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1815  }
1816 
1817  /// Indicate that the specified load with extension does not work with the
1818  /// specified type and indicate what to do about it.
1819  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1820  LegalizeAction Action) {
1821  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1822  MemVT.isValid() && "Table isn't big enough!");
1823  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1824  unsigned Shift = 4 * ExtType;
1825  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1826  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1827  }
1828 
1829  /// Indicate that the specified truncating store does not work with the
1830  /// specified type and indicate what to do about it.
1831  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1832  LegalizeAction Action) {
1833  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1834  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1835  }
1836 
1837  /// Indicate that the specified indexed load does or does not work with the
1838  /// specified type and indicate what to do abort it.
1839  ///
1840  /// NOTE: All indexed mode loads are initialized to Expand in
1841  /// TargetLowering.cpp
1842  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1843  LegalizeAction Action) {
1844  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1845  (unsigned)Action < 0xf && "Table isn't big enough!");
1846  // Load action are kept in the upper half.
1847  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1848  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1849  }
1850 
1851  /// Indicate that the specified indexed store does or does not work with the
1852  /// specified type and indicate what to do about it.
1853  ///
1854  /// NOTE: All indexed mode stores are initialized to Expand in
1855  /// TargetLowering.cpp
1856  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1857  LegalizeAction Action) {
1858  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1859  (unsigned)Action < 0xf && "Table isn't big enough!");
1860  // Store action are kept in the lower half.
1861  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1862  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1863  }
1864 
1865  /// Indicate that the specified condition code is or isn't supported on the
1866  /// target and indicate what to do about it.
1868  LegalizeAction Action) {
1869  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1870  "Table isn't big enough!");
1871  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1872  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1873  /// value and the upper 29 bits index into the second dimension of the array
1874  /// to select what 32-bit value to use.
1875  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1876  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1877  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1878  }
1879 
1880  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1881  /// to trying a larger integer/fp until it can find one that works. If that
1882  /// default is insufficient, this method can be used by the target to override
1883  /// the default.
1884  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1885  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1886  }
1887 
1888  /// Convenience method to set an operation to Promote and specify the type
1889  /// in a single call.
1890  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1891  setOperationAction(Opc, OrigVT, Promote);
1892  AddPromotedToType(Opc, OrigVT, DestVT);
1893  }
1894 
1895  /// Targets should invoke this method for each target independent node that
1896  /// they want to provide a custom DAG combiner for by implementing the
1897  /// PerformDAGCombine virtual method.
1899  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1900  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1901  }
1902 
1903  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1904  void setJumpBufSize(unsigned Size) {
1905  JumpBufSize = Size;
1906  }
1907 
1908  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1909  /// 0
1910  void setJumpBufAlignment(unsigned Align) {
1911  JumpBufAlignment = Align;
1912  }
1913 
1914  /// Set the target's minimum function alignment (in log2(bytes))
1916  MinFunctionAlignment = Align;
1917  }
1918 
1919  /// Set the target's preferred function alignment. This should be set if
1920  /// there is a performance benefit to higher-than-minimum alignment (in
1921  /// log2(bytes))
1923  PrefFunctionAlignment = Align;
1924  }
1925 
1926  /// Set the target's preferred loop alignment. Default alignment is zero, it
1927  /// means the target does not care about loop alignment. The alignment is
1928  /// specified in log2(bytes). The target may also override
1929  /// getPrefLoopAlignment to provide per-loop values.
1930  void setPrefLoopAlignment(unsigned Align) {
1931  PrefLoopAlignment = Align;
1932  }
1933 
1934  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1936  MinStackArgumentAlignment = Align;
1937  }
1938 
1939  /// Set the maximum atomic operation size supported by the
1940  /// backend. Atomic operations greater than this size (as well as
1941  /// ones that are not naturally aligned), will be expanded by
1942  /// AtomicExpandPass into an __atomic_* library call.
1943  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1944  MaxAtomicSizeInBitsSupported = SizeInBits;
1945  }
1946 
1947  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1948  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1949  MinCmpXchgSizeInBits = SizeInBits;
1950  }
1951 
1952  /// Sets whether unaligned atomic operations are supported.
1953  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1954  SupportsUnalignedAtomics = UnalignedSupported;
1955  }
1956 
1957 public:
1958  //===--------------------------------------------------------------------===//
1959  // Addressing mode description hooks (used by LSR etc).
1960  //
1961 
1962  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1963  /// instructions reading the address. This allows as much computation as
1964  /// possible to be done in the address mode for that operand. This hook lets
1965  /// targets also pass back when this should be done on intrinsics which
1966  /// load/store.
1967  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1968  SmallVectorImpl<Value*> &/*Ops*/,
1969  Type *&/*AccessTy*/) const {
1970  return false;
1971  }
1972 
1973  /// This represents an addressing mode of:
1974  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1975  /// If BaseGV is null, there is no BaseGV.
1976  /// If BaseOffs is zero, there is no base offset.
1977  /// If HasBaseReg is false, there is no base register.
1978  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1979  /// no scale.
1980  struct AddrMode {
1981  GlobalValue *BaseGV = nullptr;
1982  int64_t BaseOffs = 0;
1983  bool HasBaseReg = false;
1984  int64_t Scale = 0;
1985  AddrMode() = default;
1986  };
1987 
1988  /// Return true if the addressing mode represented by AM is legal for this
1989  /// target, for a load/store of the specified type.
1990  ///
1991  /// The type may be VoidTy, in which case only return true if the addressing
1992  /// mode is legal for a load/store of any legal type. TODO: Handle
1993  /// pre/postinc as well.
1994  ///
1995  /// If the address space cannot be determined, it will be -1.
1996  ///
1997  /// TODO: Remove default argument
1998  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1999  Type *Ty, unsigned AddrSpace,
2000  Instruction *I = nullptr) const;
2001 
2002  /// Return the cost of the scaling factor used in the addressing mode
2003  /// represented by AM for this target, for a load/store of the specified type.
2004  ///
2005  /// If the AM is supported, the return value must be >= 0.
2006  /// If the AM is not supported, it returns a negative value.
2007  /// TODO: Handle pre/postinc as well.
2008  /// TODO: Remove default argument
2009  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2010  Type *Ty, unsigned AS = 0) const {
2011  // Default: assume that any scaling factor used in a legal AM is free.
2012  if (isLegalAddressingMode(DL, AM, Ty, AS))
2013  return 0;
2014  return -1;
2015  }
2016 
2017  /// Return true if the specified immediate is legal icmp immediate, that is
2018  /// the target has icmp instructions which can compare a register against the
2019  /// immediate without having to materialize the immediate into a register.
2020  virtual bool isLegalICmpImmediate(int64_t) const {
2021  return true;
2022  }
2023 
2024  /// Return true if the specified immediate is legal add immediate, that is the
2025  /// target has add instructions which can add a register with the immediate
2026  /// without having to materialize the immediate into a register.
2027  virtual bool isLegalAddImmediate(int64_t) const {
2028  return true;
2029  }
2030 
2031  /// Return true if it's significantly cheaper to shift a vector by a uniform
2032  /// scalar than by an amount which will vary across each lane. On x86, for
2033  /// example, there is a "psllw" instruction for the former case, but no simple
2034  /// instruction for a general "a << b" operation on vectors.
2035  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2036  return false;
2037  }
2038 
2039  /// Returns true if the opcode is a commutative binary operation.
2040  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2041  // FIXME: This should get its info from the td file.
2042  switch (Opcode) {
2043  case ISD::ADD:
2044  case ISD::SMIN:
2045  case ISD::SMAX:
2046  case ISD::UMIN:
2047  case ISD::UMAX:
2048  case ISD::MUL:
2049  case ISD::MULHU:
2050  case ISD::MULHS:
2051  case ISD::SMUL_LOHI:
2052  case ISD::UMUL_LOHI:
2053  case ISD::FADD:
2054  case ISD::FMUL:
2055  case ISD::AND:
2056  case ISD::OR:
2057  case ISD::XOR:
2058  case ISD::SADDO:
2059  case ISD::UADDO:
2060  case ISD::ADDC:
2061  case ISD::ADDE:
2062  case ISD::FMINNUM:
2063  case ISD::FMAXNUM:
2064  case ISD::FMINNAN:
2065  case ISD::FMAXNAN:
2066  return true;
2067  default: return false;
2068  }
2069  }
2070 
2071  /// Return true if it's free to truncate a value of type FromTy to type
2072  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2073  /// by referencing its sub-register AX.
2074  /// Targets must return false when FromTy <= ToTy.
2075  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2076  return false;
2077  }
2078 
2079  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2080  /// whether a call is in tail position. Typically this means that both results
2081  /// would be assigned to the same register or stack slot, but it could mean
2082  /// the target performs adequate checks of its own before proceeding with the
2083  /// tail call. Targets must return false when FromTy <= ToTy.
2084  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2085  return false;
2086  }
2087 
2088  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2089  return false;
2090  }
2091 
2092  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2093 
2094  /// Return true if the extension represented by \p I is free.
2095  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2096  /// this method can use the context provided by \p I to decide
2097  /// whether or not \p I is free.
2098  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2099  /// In other words, if is[Z|FP]Free returns true, then this method
2100  /// returns true as well. The converse is not true.
2101  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2102  /// \pre \p I must be a sign, zero, or fp extension.
2103  bool isExtFree(const Instruction *I) const {
2104  switch (I->getOpcode()) {
2105  case Instruction::FPExt:
2106  if (isFPExtFree(EVT::getEVT(I->getType()),
2107  EVT::getEVT(I->getOperand(0)->getType())))
2108  return true;
2109  break;
2110  case Instruction::ZExt:
2111  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2112  return true;
2113  break;
2114  case Instruction::SExt:
2115  break;
2116  default:
2117  llvm_unreachable("Instruction is not an extension");
2118  }
2119  return isExtFreeImpl(I);
2120  }
2121 
2122  /// Return true if \p Load and \p Ext can form an ExtLoad.
2123  /// For example, in AArch64
2124  /// %L = load i8, i8* %ptr
2125  /// %E = zext i8 %L to i32
2126  /// can be lowered into one load instruction
2127  /// ldrb w0, [x0]
2128  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2129  const DataLayout &DL) const {
2130  EVT VT = getValueType(DL, Ext->getType());
2131  EVT LoadVT = getValueType(DL, Load->getType());
2132 
2133  // If the load has other users and the truncate is not free, the ext
2134  // probably isn't free.
2135  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2136  !isTruncateFree(Ext->getType(), Load->getType()))
2137  return false;
2138 
2139  // Check whether the target supports casts folded into loads.
2140  unsigned LType;
2141  if (isa<ZExtInst>(Ext))
2142  LType = ISD::ZEXTLOAD;
2143  else {
2144  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2145  LType = ISD::SEXTLOAD;
2146  }
2147 
2148  return isLoadExtLegal(LType, VT, LoadVT);
2149  }
2150 
2151  /// Return true if any actual instruction that defines a value of type FromTy
2152  /// implicitly zero-extends the value to ToTy in the result register.
2153  ///
2154  /// The function should return true when it is likely that the truncate can
2155  /// be freely folded with an instruction defining a value of FromTy. If
2156  /// the defining instruction is unknown (because you're looking at a
2157  /// function argument, PHI, etc.) then the target may require an
2158  /// explicit truncate, which is not necessarily free, but this function
2159  /// does not deal with those cases.
2160  /// Targets must return false when FromTy >= ToTy.
2161  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2162  return false;
2163  }
2164 
2165  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2166  return false;
2167  }
2168 
2169  /// Return true if the target supplies and combines to a paired load
2170  /// two loaded values of type LoadedType next to each other in memory.
2171  /// RequiredAlignment gives the minimal alignment constraints that must be met
2172  /// to be able to select this paired load.
2173  ///
2174  /// This information is *not* used to generate actual paired loads, but it is
2175  /// used to generate a sequence of loads that is easier to combine into a
2176  /// paired load.
2177  /// For instance, something like this:
2178  /// a = load i64* addr
2179  /// b = trunc i64 a to i32
2180  /// c = lshr i64 a, 32
2181  /// d = trunc i64 c to i32
2182  /// will be optimized into:
2183  /// b = load i32* addr1
2184  /// d = load i32* addr2
2185  /// Where addr1 = addr2 +/- sizeof(i32).
2186  ///
2187  /// In other words, unless the target performs a post-isel load combining,
2188  /// this information should not be provided because it will generate more
2189  /// loads.
2190  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2191  unsigned & /*RequiredAlignment*/) const {
2192  return false;
2193  }
2194 
2195  /// Return true if the target has a vector blend instruction.
2196  virtual bool hasVectorBlend() const { return false; }
2197 
2198  /// Get the maximum supported factor for interleaved memory accesses.
2199  /// Default to be the minimum interleave factor: 2.
2200  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2201 
2202  /// Lower an interleaved load to target specific intrinsics. Return
2203  /// true on success.
2204  ///
2205  /// \p LI is the vector load instruction.
2206  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2207  /// \p Indices is the corresponding indices for each shufflevector.
2208  /// \p Factor is the interleave factor.
2209  virtual bool lowerInterleavedLoad(LoadInst *LI,
2211  ArrayRef<unsigned> Indices,
2212  unsigned Factor) const {
2213  return false;
2214  }
2215 
2216  /// Lower an interleaved store to target specific intrinsics. Return
2217  /// true on success.
2218  ///
2219  /// \p SI is the vector store instruction.
2220  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2221  /// \p Factor is the interleave factor.
2223  unsigned Factor) const {
2224  return false;
2225  }
2226 
2227  /// Return true if zero-extending the specific node Val to type VT2 is free
2228  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2229  /// because it's folded such as X86 zero-extending loads).
2230  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2231  return isZExtFree(Val.getValueType(), VT2);
2232  }
2233 
2234  /// Return true if an fpext operation is free (for instance, because
2235  /// single-precision floating-point numbers are implicitly extended to
2236  /// double-precision).
2237  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2238  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2239  "invalid fpext types");
2240  return false;
2241  }
2242 
2243  /// Return true if an fpext operation input to an \p Opcode operation is free
2244  /// (for instance, because half-precision floating-point numbers are
2245  /// implicitly extended to float-precision) for an FMA instruction.
2246  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2247  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2248  "invalid fpext types");
2249  return isFPExtFree(DestVT, SrcVT);
2250  }
2251 
2252  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2253  /// extend node) is profitable.
2254  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2255 
2256  /// Return true if an fneg operation is free to the point where it is never
2257  /// worthwhile to replace it with a bitwise operation.
2258  virtual bool isFNegFree(EVT VT) const {
2259  assert(VT.isFloatingPoint());
2260  return false;
2261  }
2262 
2263  /// Return true if an fabs operation is free to the point where it is never
2264  /// worthwhile to replace it with a bitwise operation.
2265  virtual bool isFAbsFree(EVT VT) const {
2266  assert(VT.isFloatingPoint());
2267  return false;
2268  }
2269 
2270  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2271  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2272  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2273  ///
2274  /// NOTE: This may be called before legalization on types for which FMAs are
2275  /// not legal, but should return true if those types will eventually legalize
2276  /// to types that support FMAs. After legalization, it will only be called on
2277  /// types that support FMAs (via Legal or Custom actions)
2278  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2279  return false;
2280  }
2281 
2282  /// Return true if it's profitable to narrow operations of type VT1 to
2283  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2284  /// i32 to i16.
2285  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2286  return false;
2287  }
2288 
2289  /// Return true if it is beneficial to convert a load of a constant to
2290  /// just the constant itself.
2291  /// On some targets it might be more efficient to use a combination of
2292  /// arithmetic instructions to materialize the constant instead of loading it
2293  /// from a constant pool.
2294  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2295  Type *Ty) const {
2296  return false;
2297  }
2298 
2299  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2300  /// from this source type with this index. This is needed because
2301  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2302  /// the first element, and only the target knows which lowering is cheap.
2303  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2304  unsigned Index) const {
2305  return false;
2306  }
2307 
2308  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2309  // even if the vector itself has multiple uses.
2310  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2311  return false;
2312  }
2313 
2314  // Return true if CodeGenPrepare should consider splitting large offset of a
2315  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2316  // same blocks of its users.
2317  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2318 
2319  //===--------------------------------------------------------------------===//
2320  // Runtime Library hooks
2321  //
2322 
2323  /// Rename the default libcall routine name for the specified libcall.
2324  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2325  LibcallRoutineNames[Call] = Name;
2326  }
2327 
2328  /// Get the libcall routine name for the specified libcall.
2329  const char *getLibcallName(RTLIB::Libcall Call) const {
2330  return LibcallRoutineNames[Call];
2331  }
2332 
2333  /// Override the default CondCode to be used to test the result of the
2334  /// comparison libcall against zero.
2336  CmpLibcallCCs[Call] = CC;
2337  }
2338 
2339  /// Get the CondCode that's to be used to test the result of the comparison
2340  /// libcall against zero.
2342  return CmpLibcallCCs[Call];
2343  }
2344 
2345  /// Set the CallingConv that should be used for the specified libcall.
2347  LibcallCallingConvs[Call] = CC;
2348  }
2349 
2350  /// Get the CallingConv that should be used for the specified libcall.
2352  return LibcallCallingConvs[Call];
2353  }
2354 
2355  /// Execute target specific actions to finalize target lowering.
2356  /// This is used to set extra flags in MachineFrameInformation and freezing
2357  /// the set of reserved registers.
2358  /// The default implementation just freezes the set of reserved registers.
2359  virtual void finalizeLowering(MachineFunction &MF) const;
2360 
2361 private:
2362  const TargetMachine &TM;
2363 
2364  /// Tells the code generator that the target has multiple (allocatable)
2365  /// condition registers that can be used to store the results of comparisons
2366  /// for use by selects and conditional branches. With multiple condition
2367  /// registers, the code generator will not aggressively sink comparisons into
2368  /// the blocks of their users.
2369  bool HasMultipleConditionRegisters;
2370 
2371  /// Tells the code generator that the target has BitExtract instructions.
2372  /// The code generator will aggressively sink "shift"s into the blocks of
2373  /// their users if the users will generate "and" instructions which can be
2374  /// combined with "shift" to BitExtract instructions.
2375  bool HasExtractBitsInsn;
2376 
2377  /// Tells the code generator to bypass slow divide or remainder
2378  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2379  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2380  /// div/rem when the operands are positive and less than 256.
2381  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2382 
2383  /// Tells the code generator that it shouldn't generate extra flow control
2384  /// instructions and should attempt to combine flow control instructions via
2385  /// predication.
2386  bool JumpIsExpensive;
2387 
2388  /// Whether the target supports or cares about preserving floating point
2389  /// exception behavior.
2390  bool HasFloatingPointExceptions;
2391 
2392  /// This target prefers to use _setjmp to implement llvm.setjmp.
2393  ///
2394  /// Defaults to false.
2395  bool UseUnderscoreSetJmp;
2396 
2397  /// This target prefers to use _longjmp to implement llvm.longjmp.
2398  ///
2399  /// Defaults to false.
2400  bool UseUnderscoreLongJmp;
2401 
2402  /// Information about the contents of the high-bits in boolean values held in
2403  /// a type wider than i1. See getBooleanContents.
2404  BooleanContent BooleanContents;
2405 
2406  /// Information about the contents of the high-bits in boolean values held in
2407  /// a type wider than i1. See getBooleanContents.
2408  BooleanContent BooleanFloatContents;
2409 
2410  /// Information about the contents of the high-bits in boolean vector values
2411  /// when the element type is wider than i1. See getBooleanContents.
2412  BooleanContent BooleanVectorContents;
2413 
2414  /// The target scheduling preference: shortest possible total cycles or lowest
2415  /// register usage.
2416  Sched::Preference SchedPreferenceInfo;
2417 
2418  /// The size, in bytes, of the target's jmp_buf buffers
2419  unsigned JumpBufSize;
2420 
2421  /// The alignment, in bytes, of the target's jmp_buf buffers
2422  unsigned JumpBufAlignment;
2423 
2424  /// The minimum alignment that any argument on the stack needs to have.
2425  unsigned MinStackArgumentAlignment;
2426 
2427  /// The minimum function alignment (used when optimizing for size, and to
2428  /// prevent explicitly provided alignment from leading to incorrect code).
2429  unsigned MinFunctionAlignment;
2430 
2431  /// The preferred function alignment (used when alignment unspecified and
2432  /// optimizing for speed).
2433  unsigned PrefFunctionAlignment;
2434 
2435  /// The preferred loop alignment.
2436  unsigned PrefLoopAlignment;
2437 
2438  /// Size in bits of the maximum atomics size the backend supports.
2439  /// Accesses larger than this will be expanded by AtomicExpandPass.
2440  unsigned MaxAtomicSizeInBitsSupported;
2441 
2442  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2443  /// backend supports.
2444  unsigned MinCmpXchgSizeInBits;
2445 
2446  /// This indicates if the target supports unaligned atomic operations.
2447  bool SupportsUnalignedAtomics;
2448 
2449  /// If set to a physical register, this specifies the register that
2450  /// llvm.savestack/llvm.restorestack should save and restore.
2451  unsigned StackPointerRegisterToSaveRestore;
2452 
2453  /// This indicates the default register class to use for each ValueType the
2454  /// target supports natively.
2455  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2456  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2457  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2458 
2459  /// This indicates the "representative" register class to use for each
2460  /// ValueType the target supports natively. This information is used by the
2461  /// scheduler to track register pressure. By default, the representative
2462  /// register class is the largest legal super-reg register class of the
2463  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2464  /// representative class would be GR32.
2465  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2466 
2467  /// This indicates the "cost" of the "representative" register class for each
2468  /// ValueType. The cost is used by the scheduler to approximate register
2469  /// pressure.
2470  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2471 
2472  /// For any value types we are promoting or expanding, this contains the value
2473  /// type that we are changing to. For Expanded types, this contains one step
2474  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2475  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2476  /// the same type (e.g. i32 -> i32).
2477  MVT TransformToType[MVT::LAST_VALUETYPE];
2478 
2479  /// For each operation and each value type, keep a LegalizeAction that
2480  /// indicates how instruction selection should deal with the operation. Most
2481  /// operations are Legal (aka, supported natively by the target), but
2482  /// operations that are not should be described. Note that operations on
2483  /// non-legal value types are not described here.
2485 
2486  /// For each load extension type and each value type, keep a LegalizeAction
2487  /// that indicates how instruction selection should deal with a load of a
2488  /// specific value type and extension type. Uses 4-bits to store the action
2489  /// for each of the 4 load ext types.
2490  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2491 
2492  /// For each value type pair keep a LegalizeAction that indicates whether a
2493  /// truncating store of a specific value type and truncating type is legal.
2495 
2496  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2497  /// that indicates how instruction selection should deal with the load /
2498  /// store.
2499  ///
2500  /// The first dimension is the value_type for the reference. The second
2501  /// dimension represents the various modes for load store.
2502  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2503 
2504  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2505  /// indicates how instruction selection should deal with the condition code.
2506  ///
2507  /// Because each CC action takes up 4 bits, we need to have the array size be
2508  /// large enough to fit all of the value types. This can be done by rounding
2509  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2510  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2511 
2512 protected:
2514 
2515 private:
2516  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2517 
2518  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2519  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2520  /// array.
2521  unsigned char
2522  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2523 
2524  /// For operations that must be promoted to a specific type, this holds the
2525  /// destination type. This map should be sparse, so don't hold it as an
2526  /// array.
2527  ///
2528  /// Targets add entries to this map with AddPromotedToType(..), clients access
2529  /// this with getTypeToPromoteTo(..).
2530  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2531  PromoteToType;
2532 
2533  /// Stores the name each libcall.
2534  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2535 
2536  /// The ISD::CondCode that should be used to test the result of each of the
2537  /// comparison libcall against zero.
2538  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2539 
2540  /// Stores the CallingConv that should be used for each libcall.
2541  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2542 
2543  /// Set default libcall names and calling conventions.
2544  void InitLibcalls(const Triple &TT);
2545 
2546 protected:
2547  /// Return true if the extension represented by \p I is free.
2548  /// \pre \p I is a sign, zero, or fp extension and
2549  /// is[Z|FP]ExtFree of the related types is not true.
2550  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2551 
2552  /// Depth that GatherAllAliases should should continue looking for chain
2553  /// dependencies when trying to find a more preferable chain. As an
2554  /// approximation, this should be more than the number of consecutive stores
2555  /// expected to be merged.
2557 
2558  /// Specify maximum number of store instructions per memset call.
2559  ///
2560  /// When lowering \@llvm.memset this field specifies the maximum number of
2561  /// store operations that may be substituted for the call to memset. Targets
2562  /// must set this value based on the cost threshold for that target. Targets
2563  /// should assume that the memset will be done using as many of the largest
2564  /// store operations first, followed by smaller ones, if necessary, per
2565  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2566  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2567  /// store. This only applies to setting a constant array of a constant size.
2569 
2570  /// Maximum number of stores operations that may be substituted for the call
2571  /// to memset, used for functions with OptSize attribute.
2573 
2574  /// Specify maximum bytes of store instructions per memcpy call.
2575  ///
2576  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2577  /// store operations that may be substituted for a call to memcpy. Targets
2578  /// must set this value based on the cost threshold for that target. Targets
2579  /// should assume that the memcpy will be done using as many of the largest
2580  /// store operations first, followed by smaller ones, if necessary, per
2581  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2582  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2583  /// and one 1-byte store. This only applies to copying a constant array of
2584  /// constant size.
2586 
2587 
2588  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2589  ///
2590  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2591  /// of store instructions to keep together. This helps in pairing and
2592  // vectorization later on.
2593  unsigned MaxGluedStoresPerMemcpy = 0;
2594 
2595  /// Maximum number of store operations that may be substituted for a call to
2596  /// memcpy, used for functions with OptSize attribute.
2600 
2601  /// Specify maximum bytes of store instructions per memmove call.
2602  ///
2603  /// When lowering \@llvm.memmove this field specifies the maximum number of
2604  /// store instructions that may be substituted for a call to memmove. Targets
2605  /// must set this value based on the cost threshold for that target. Targets
2606  /// should assume that the memmove will be done using as many of the largest
2607  /// store operations first, followed by smaller ones, if necessary, per
2608  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2609  /// with 8-bit alignment would result in nine 1-byte stores. This only
2610  /// applies to copying a constant array of constant size.
2612 
2613  /// Maximum number of store instructions that may be substituted for a call to
2614  /// memmove, used for functions with OptSize attribute.
2616 
2617  /// Tells the code generator that select is more expensive than a branch if
2618  /// the branch is usually predicted right.
2620 
2621  /// \see enableExtLdPromotion.
2623 
2624  /// Return true if the value types that can be represented by the specified
2625  /// register class are all legal.
2626  bool isLegalRC(const TargetRegisterInfo &TRI,
2627  const TargetRegisterClass &RC) const;
2628 
2629  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2630  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2631  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2632  MachineBasicBlock *MBB) const;
2633 
2634  /// Replace/modify the XRay custom event operands with target-dependent
2635  /// details.
2636  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2637  MachineBasicBlock *MBB) const;
2638 
2639  /// Replace/modify the XRay typed event operands with target-dependent
2640  /// details.
2641  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2642  MachineBasicBlock *MBB) const;
2643 };
2644 
2645 /// This class defines information used to lower LLVM code to legal SelectionDAG
2646 /// operators that the target instruction selector can accept natively.
2647 ///
2648 /// This class also defines callbacks that targets must implement to lower
2649 /// target-specific constructs to SelectionDAG operators.
2651 public:
2652  struct DAGCombinerInfo;
2653 
2654  TargetLowering(const TargetLowering &) = delete;
2655  TargetLowering &operator=(const TargetLowering &) = delete;
2656 
2657  /// NOTE: The TargetMachine owns TLOF.
2658  explicit TargetLowering(const TargetMachine &TM);
2659 
2660  bool isPositionIndependent() const;
2661 
2662  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2663  FunctionLoweringInfo *FLI,
2664  LegacyDivergenceAnalysis *DA) const {
2665  return false;
2666  }
2667 
2668  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2669  return false;
2670  }
2671 
2672  /// Returns true by value, base pointer and offset pointer and addressing mode
2673  /// by reference if the node's address can be legally represented as
2674  /// pre-indexed load / store address.
2675  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2676  SDValue &/*Offset*/,
2677  ISD::MemIndexedMode &/*AM*/,
2678  SelectionDAG &/*DAG*/) const {
2679  return false;
2680  }
2681 
2682  /// Returns true by value, base pointer and offset pointer and addressing mode
2683  /// by reference if this node can be combined with a load / store to form a
2684  /// post-indexed load / store.
2685  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2686  SDValue &/*Base*/,
2687  SDValue &/*Offset*/,
2688  ISD::MemIndexedMode &/*AM*/,
2689  SelectionDAG &/*DAG*/) const {
2690  return false;
2691  }
2692 
2693  /// Return the entry encoding for a jump table in the current function. The
2694  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2695  virtual unsigned getJumpTableEncoding() const;
2696 
2697  virtual const MCExpr *
2699  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2700  MCContext &/*Ctx*/) const {
2701  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2702  }
2703 
2704  /// Returns relocation base for the given PIC jumptable.
2705  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2706  SelectionDAG &DAG) const;
2707 
2708  /// This returns the relocation base for the given PIC jumptable, the same as
2709  /// getPICJumpTableRelocBase, but as an MCExpr.
2710  virtual const MCExpr *
2711  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2712  unsigned JTI, MCContext &Ctx) const;
2713 
2714  /// Return true if folding a constant offset with the given GlobalAddress is
2715  /// legal. It is frequently not legal in PIC relocation models.
2716  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2717 
2718  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2719  SDValue &Chain) const;
2720 
2721  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2722  SDValue &NewRHS, ISD::CondCode &CCCode,
2723  const SDLoc &DL) const;
2724 
2725  /// Returns a pair of (return value, chain).
2726  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2727  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2728  EVT RetVT, ArrayRef<SDValue> Ops,
2729  bool isSigned, const SDLoc &dl,
2730  bool doesNotReturn = false,
2731  bool isReturnValueUsed = true) const;
2732 
2733  /// Check whether parameters to a call that are passed in callee saved
2734  /// registers are the same as from the calling function. This needs to be
2735  /// checked for tail call eligibility.
2736  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2737  const uint32_t *CallerPreservedMask,
2738  const SmallVectorImpl<CCValAssign> &ArgLocs,
2739  const SmallVectorImpl<SDValue> &OutVals) const;
2740 
2741  //===--------------------------------------------------------------------===//
2742  // TargetLowering Optimization Methods
2743  //
2744 
2745  /// A convenience struct that encapsulates a DAG, and two SDValues for
2746  /// returning information from TargetLowering to its clients that want to
2747  /// combine.
2750  bool LegalTys;
2751  bool LegalOps;
2754 
2756  bool LT, bool LO) :
2757  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2758 
2759  bool LegalTypes() const { return LegalTys; }
2760  bool LegalOperations() const { return LegalOps; }
2761 
2763  Old = O;
2764  New = N;
2765  return true;
2766  }
2767  };
2768 
2769  /// Check to see if the specified operand of the specified instruction is a
2770  /// constant integer. If so, check to see if there are any bits set in the
2771  /// constant that are not demanded. If so, shrink the constant and return
2772  /// true.
2773  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2774  TargetLoweringOpt &TLO) const;
2775 
2776  // Target hook to do target-specific const optimization, which is called by
2777  // ShrinkDemandedConstant. This function should return true if the target
2778  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2779  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2780  TargetLoweringOpt &TLO) const {
2781  return false;
2782  }
2783 
2784  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2785  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2786  /// generalized for targets with other types of implicit widening casts.
2787  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2788  TargetLoweringOpt &TLO) const;
2789 
2790  /// Helper for SimplifyDemandedBits that can simplify an operation with
2791  /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2792  /// then updates \p User with the simplified version. No other uses of
2793  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2794  /// function behaves exactly like function SimplifyDemandedBits declared
2795  /// below except that it also updates the DAG by calling
2796  /// DCI.CommitTargetLoweringOpt.
2797  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2798  DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2799 
2800  /// Look at Op. At this point, we know that only the DemandedMask bits of the
2801  /// result of Op are ever used downstream. If we can use this information to
2802  /// simplify Op, create a new simplified DAG node and return true, returning
2803  /// the original and new nodes in Old and New. Otherwise, analyze the
2804  /// expression and return a mask of KnownOne and KnownZero bits for the
2805  /// expression (used to simplify the caller). The KnownZero/One bits may only
2806  /// be accurate for those bits in the DemandedMask.
2807  /// \p AssumeSingleUse When this parameter is true, this function will
2808  /// attempt to simplify \p Op even if there are multiple uses.
2809  /// Callers are responsible for correctly updating the DAG based on the
2810  /// results of this function, because simply replacing replacing TLO.Old
2811  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2812  /// has multiple uses.
2813  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2814  KnownBits &Known,
2815  TargetLoweringOpt &TLO,
2816  unsigned Depth = 0,
2817  bool AssumeSingleUse = false) const;
2818 
2819  /// Helper wrapper around SimplifyDemandedBits
2820  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2821  DAGCombinerInfo &DCI) const;
2822 
2823  /// Look at Vector Op. At this point, we know that only the DemandedElts
2824  /// elements of the result of Op are ever used downstream. If we can use
2825  /// this information to simplify Op, create a new simplified DAG node and
2826  /// return true, storing the original and new nodes in TLO.
2827  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2828  /// KnownZero elements for the expression (used to simplify the caller).
2829  /// The KnownUndef/Zero elements may only be accurate for those bits
2830  /// in the DemandedMask.
2831  /// \p AssumeSingleUse When this parameter is true, this function will
2832  /// attempt to simplify \p Op even if there are multiple uses.
2833  /// Callers are responsible for correctly updating the DAG based on the
2834  /// results of this function, because simply replacing replacing TLO.Old
2835  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2836  /// has multiple uses.
2837  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2838  APInt &KnownUndef, APInt &KnownZero,
2839  TargetLoweringOpt &TLO, unsigned Depth = 0,
2840  bool AssumeSingleUse = false) const;
2841 
2842  /// Helper wrapper around SimplifyDemandedVectorElts
2843  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2844  APInt &KnownUndef, APInt &KnownZero,
2845  DAGCombinerInfo &DCI) const;
2846 
2847  /// Determine which of the bits specified in Mask are known to be either zero
2848  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2849  /// argument allows us to only collect the known bits that are shared by the
2850  /// requested vector elements.
2851  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2852  KnownBits &Known,
2853  const APInt &DemandedElts,
2854  const SelectionDAG &DAG,
2855  unsigned Depth = 0) const;
2856 
2857  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2858  /// Default implementation computes low bits based on alignment
2859  /// information. This should preserve known bits passed into it.
2860  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2861  KnownBits &Known,
2862  const APInt &DemandedElts,
2863  const SelectionDAG &DAG,
2864  unsigned Depth = 0) const;
2865 
2866  /// This method can be implemented by targets that want to expose additional
2867  /// information about sign bits to the DAG Combiner. The DemandedElts
2868  /// argument allows us to only collect the minimum sign bits that are shared
2869  /// by the requested vector elements.
2870  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2871  const APInt &DemandedElts,
2872  const SelectionDAG &DAG,
2873  unsigned Depth = 0) const;
2874 
2875  /// Attempt to simplify any target nodes based on the demanded vector
2876  /// elements, returning true on success. Otherwise, analyze the expression and
2877  /// return a mask of KnownUndef and KnownZero elements for the expression
2878  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2879  /// accurate for those bits in the DemandedMask
2880  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2881  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2882  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2883 
2884  /// If \p SNaN is false, \returns true if \p Op is known to never be any
2885  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
2886  /// NaN.
2887  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
2888  const SelectionDAG &DAG,
2889  bool SNaN = false,
2890  unsigned Depth = 0) const;
2892  void *DC; // The DAG Combiner object.
2895 
2896  public:
2898 
2899  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2900  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2901 
2902  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2903  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2904  bool isAfterLegalizeDAG() const {
2905  return Level == AfterLegalizeDAG;
2906  }
2908  bool isCalledByLegalizer() const { return CalledByLegalizer; }
2909 
2910  void AddToWorklist(SDNode *N);
2911  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2912  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2913  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2914 
2915  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2916  };
2917 
2918  /// Return if the N is a constant or constant vector equal to the true value
2919  /// from getBooleanContents().
2920  bool isConstTrueVal(const SDNode *N) const;
2921 
2922  /// Return if the N is a constant or constant vector equal to the false value
2923  /// from getBooleanContents().
2924  bool isConstFalseVal(const SDNode *N) const;
2925 
2926  /// Return if \p N is a True value when extended to \p VT.
2927  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
2928 
2929  /// Try to simplify a setcc built with the specified operands and cc. If it is
2930  /// unable to simplify it, return a null SDValue.
2931  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2932  bool foldBooleans, DAGCombinerInfo &DCI,
2933  const SDLoc &dl) const;
2934 
2935  // For targets which wrap address, unwrap for analysis.
2936  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2937 
2938  /// Returns true (and the GlobalValue and the offset) if the node is a
2939  /// GlobalAddress + offset.
2940  virtual bool
2941  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2942 
2943  /// This method will be invoked for all target nodes and for any
2944  /// target-independent nodes that the target has registered with invoke it
2945  /// for.
2946  ///
2947  /// The semantics are as follows:
2948  /// Return Value:
2949  /// SDValue.Val == 0 - No change was made
2950  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2951  /// otherwise - N should be replaced by the returned Operand.
2952  ///
2953  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2954  /// more complex transformations.
2955  ///
2956  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2957 
2958  /// Return true if it is profitable to move this shift by a constant amount
2959  /// though its operand, adjusting any immediate operands as necessary to
2960  /// preserve semantics. This transformation may not be desirable if it
2961  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
2962  /// extraction in AArch64). By default, it returns true.
2963  ///
2964  /// @param N the shift node
2965  /// @param Level the current DAGCombine legalization level.
2966  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
2967  CombineLevel Level) const {
2968  return true;
2969  }
2970 
2971  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2972  // to a shuffle and a truncate.
2973  // Example of such a combine:
2974  // v4i32 build_vector((extract_elt V, 1),
2975  // (extract_elt V, 3),
2976  // (extract_elt V, 5),
2977  // (extract_elt V, 7))
2978  // -->
2979  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2981  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2982  return false;
2983  }
2984 
2985  /// Return true if the target has native support for the specified value type
2986  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2987  /// i16 is legal, but undesirable since i16 instruction encodings are longer
2988  /// and some i16 instructions are slow.
2989  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2990  // By default, assume all legal types are desirable.
2991  return isTypeLegal(VT);
2992  }
2993 
2994  /// Return true if it is profitable for dag combiner to transform a floating
2995  /// point op of specified opcode to a equivalent op of an integer
2996  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2997  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2998  EVT /*VT*/) const {
2999  return false;
3000  }
3001 
3002  /// This method query the target whether it is beneficial for dag combiner to
3003  /// promote the specified node. If true, it should return the desired
3004  /// promotion type by reference.
3005  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3006  return false;
3007  }
3008 
3009  /// Return true if the target supports swifterror attribute. It optimizes
3010  /// loads and stores to reading and writing a specific register.
3011  virtual bool supportSwiftError() const {
3012  return false;
3013  }
3014 
3015  /// Return true if the target supports that a subset of CSRs for the given
3016  /// machine function is handled explicitly via copies.
3017  virtual bool supportSplitCSR(MachineFunction *MF) const {
3018  return false;
3019  }
3020 
3021  /// Perform necessary initialization to handle a subset of CSRs explicitly
3022  /// via copies. This function is called at the beginning of instruction
3023  /// selection.
3024  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3025  llvm_unreachable("Not Implemented");
3026  }
3027 
3028  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3029  /// CSRs to virtual registers in the entry block, and copy them back to
3030  /// physical registers in the exit blocks. This function is called at the end
3031  /// of instruction selection.
3032  virtual void insertCopiesSplitCSR(
3033  MachineBasicBlock *Entry,
3034  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3035  llvm_unreachable("Not Implemented");
3036  }
3037 
3038  //===--------------------------------------------------------------------===//
3039  // Lowering methods - These methods must be implemented by targets so that
3040  // the SelectionDAGBuilder code knows how to lower these.
3041  //
3042 
3043  /// This hook must be implemented to lower the incoming (formal) arguments,
3044  /// described by the Ins array, into the specified DAG. The implementation
3045  /// should fill in the InVals array with legal-type argument values, and
3046  /// return the resulting token chain value.
3048  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3049  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3050  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3051  llvm_unreachable("Not Implemented");
3052  }
3053 
3054  /// This structure contains all information that is necessary for lowering
3055  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3056  /// needs to lower a call, and targets will see this struct in their LowerCall
3057  /// implementation.
3060  Type *RetTy = nullptr;
3061  bool RetSExt : 1;
3062  bool RetZExt : 1;
3063  bool IsVarArg : 1;
3064  bool IsInReg : 1;
3065  bool DoesNotReturn : 1;
3067  bool IsConvergent : 1;
3068  bool IsPatchPoint : 1;
3069 
3070  // IsTailCall should be modified by implementations of
3071  // TargetLowering::LowerCall that perform tail call conversions.
3072  bool IsTailCall = false;
3073 
3074  // Is Call lowering done post SelectionDAG type legalization.
3075  bool IsPostTypeLegalization = false;
3076 
3077  unsigned NumFixedArgs = -1;
3080  ArgListTy Args;
3088 
3090  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3091  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3092  IsPatchPoint(false), DAG(DAG) {}
3093 
3095  DL = dl;
3096  return *this;
3097  }
3098 
3100  Chain = InChain;
3101  return *this;
3102  }
3103 
3104  // setCallee with target/module-specific attributes
3106  SDValue Target, ArgListTy &&ArgsList) {
3107  RetTy = ResultType;
3108  Callee = Target;
3109  CallConv = CC;
3110  NumFixedArgs = ArgsList.size();
3111  Args = std::move(ArgsList);
3112 
3114  &(DAG.getMachineFunction()), CC, Args);
3115  return *this;
3116  }
3117 
3119  SDValue Target, ArgListTy &&ArgsList) {
3120  RetTy = ResultType;
3121  Callee = Target;
3122  CallConv = CC;
3123  NumFixedArgs = ArgsList.size();
3124  Args = std::move(ArgsList);
3125  return *this;
3126  }
3127 
3129  SDValue Target, ArgListTy &&ArgsList,
3130  ImmutableCallSite Call) {
3131  RetTy = ResultType;
3132 
3133  IsInReg = Call.hasRetAttr(Attribute::InReg);
3134  DoesNotReturn =
3135  Call.doesNotReturn() ||
3136  (!Call.isInvoke() &&
3137  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3138  IsVarArg = FTy->isVarArg();
3139  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3140  RetSExt = Call.hasRetAttr(Attribute::SExt);
3141  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3142 
3143  Callee = Target;
3144 
3145  CallConv = Call.getCallingConv();
3146  NumFixedArgs = FTy->getNumParams();
3147  Args = std::move(ArgsList);
3148 
3149  CS = Call;
3150 
3151  return *this;
3152  }
3153 
3155  IsInReg = Value;
3156  return *this;
3157  }
3158 
3160  DoesNotReturn = Value;
3161  return *this;
3162  }
3163 
3165  IsVarArg = Value;
3166  return *this;
3167  }
3168 
3170  IsTailCall = Value;
3171  return *this;
3172  }
3173 
3175  IsReturnValueUsed = !Value;
3176  return *this;
3177  }
3178 
3180  IsConvergent = Value;
3181  return *this;
3182  }
3183 
3185  RetSExt = Value;
3186  return *this;
3187  }
3188 
3190  RetZExt = Value;
3191  return *this;
3192  }
3193 
3195  IsPatchPoint = Value;
3196  return *this;
3197  }
3198 
3200  IsPostTypeLegalization = Value;
3201  return *this;
3202  }
3203 
3204  ArgListTy &getArgs() {
3205  return Args;
3206  }
3207  };
3208 
3209  /// This function lowers an abstract call to a function into an actual call.
3210  /// This returns a pair of operands. The first element is the return value
3211  /// for the function (if RetTy is not VoidTy). The second element is the
3212  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3213  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3214 
3215  /// This hook must be implemented to lower calls into the specified
3216  /// DAG. The outgoing arguments to the call are described by the Outs array,
3217  /// and the values to be returned by the call are described by the Ins
3218  /// array. The implementation should fill in the InVals array with legal-type
3219  /// return values from the call, and return the resulting token chain value.
3220  virtual SDValue
3222  SmallVectorImpl<SDValue> &/*InVals*/) const {
3223  llvm_unreachable("Not Implemented");
3224  }
3225 
3226  /// Target-specific cleanup for formal ByVal parameters.
3227  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3228 
3229  /// This hook should be implemented to check whether the return values
3230  /// described by the Outs array can fit into the return registers. If false
3231  /// is returned, an sret-demotion is performed.
3232  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3233  MachineFunction &/*MF*/, bool /*isVarArg*/,
3234  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3235  LLVMContext &/*Context*/) const
3236  {
3237  // Return true by default to get preexisting behavior.
3238  return true;
3239  }
3240 
3241  /// This hook must be implemented to lower outgoing return values, described
3242  /// by the Outs array, into the specified DAG. The implementation should
3243  /// return the resulting token chain value.
3244  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3245  bool /*isVarArg*/,
3246  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3247  const SmallVectorImpl<SDValue> & /*OutVals*/,
3248  const SDLoc & /*dl*/,
3249  SelectionDAG & /*DAG*/) const {
3250  llvm_unreachable("Not Implemented");
3251  }
3252 
3253  /// Return true if result of the specified node is used by a return node
3254  /// only. It also compute and return the input chain for the tail call.
3255  ///
3256  /// This is used to determine whether it is possible to codegen a libcall as
3257  /// tail call at legalization time.
3258  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3259  return false;
3260  }
3261 
3262  /// Return true if the target may be able emit the call instruction as a tail
3263  /// call. This is used by optimization passes to determine if it's profitable
3264  /// to duplicate return instructions to enable tailcall optimization.
3265  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3266  return false;
3267  }
3268 
3269  /// Return the builtin name for the __builtin___clear_cache intrinsic
3270  /// Default is to invoke the clear cache library call
3271  virtual const char * getClearCacheBuiltinName() const {
3272  return "__clear_cache";
3273  }
3274 
3275  /// Return the register ID of the name passed in. Used by named register
3276  /// global variables extension. There is no target-independent behaviour
3277  /// so the default action is to bail.
3278  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3279  SelectionDAG &DAG) const {
3280  report_fatal_error("Named registers not implemented for this target");
3281  }
3282 
3283  /// Return the type that should be used to zero or sign extend a
3284  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3285  /// require the return type to be promoted, but this is not true all the time,
3286  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3287  /// conventions. The frontend should handle this and include all of the
3288  /// necessary information.
3290  ISD::NodeType /*ExtendKind*/) const {
3291  EVT MinVT = getRegisterType(Context, MVT::i32);
3292  return VT.bitsLT(MinVT) ? MinVT : VT;
3293  }
3294 
3295  /// For some targets, an LLVM struct type must be broken down into multiple
3296  /// simple types, but the calling convention specifies that the entire struct
3297  /// must be passed in a block of consecutive registers.
3298  virtual bool
3300  bool isVarArg) const {
3301  return false;
3302  }
3303 
3304  /// Returns a 0 terminated array of registers that can be safely used as
3305  /// scratch registers.
3306  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3307  return nullptr;
3308  }
3309 
3310  /// This callback is used to prepare for a volatile or atomic load.
3311  /// It takes a chain node as input and returns the chain for the load itself.
3312  ///
3313  /// Having a callback like this is necessary for targets like SystemZ,
3314  /// which allows a CPU to reuse the result of a previous load indefinitely,
3315  /// even if a cache-coherent store is performed by another CPU. The default
3316  /// implementation does nothing.
3318  SelectionDAG &DAG) const {
3319  return Chain;
3320  }
3321 
3322  /// This callback is used to inspect load/store instructions and add
3323  /// target-specific MachineMemOperand flags to them. The default
3324  /// implementation does nothing.
3327  }
3328 
3329  /// This callback is invoked by the type legalizer to legalize nodes with an
3330  /// illegal operand type but legal result types. It replaces the
3331  /// LowerOperation callback in the type Legalizer. The reason we can not do
3332  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3333  /// use this callback.
3334  ///
3335  /// TODO: Consider merging with ReplaceNodeResults.
3336  ///
3337  /// The target places new result values for the node in Results (their number
3338  /// and types must exactly match those of the original return values of
3339  /// the node), or leaves Results empty, which indicates that the node is not
3340  /// to be custom lowered after all.
3341  /// The default implementation calls LowerOperation.
3342  virtual void LowerOperationWrapper(SDNode *N,
3344  SelectionDAG &DAG) const;
3345 
3346  /// This callback is invoked for operations that are unsupported by the
3347  /// target, which are registered to use 'custom' lowering, and whose defined
3348  /// values are all legal. If the target has no operations that require custom
3349  /// lowering, it need not implement this. The default implementation of this
3350  /// aborts.
3351  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3352 
3353  /// This callback is invoked when a node result type is illegal for the
3354  /// target, and the operation was registered to use 'custom' lowering for that
3355  /// result type. The target places new result values for the node in Results
3356  /// (their number and types must exactly match those of the original return
3357  /// values of the node), or leaves Results empty, which indicates that the
3358  /// node is not to be custom lowered after all.
3359  ///
3360  /// If the target has no operations that require custom lowering, it need not
3361  /// implement this. The default implementation aborts.
3362  virtual void ReplaceNodeResults(SDNode * /*N*/,
3363  SmallVectorImpl<SDValue> &/*Results*/,
3364  SelectionDAG &/*DAG*/) const {
3365  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3366  }
3367 
3368  /// This method returns the name of a target specific DAG node.
3369  virtual const char *getTargetNodeName(unsigned Opcode) const;
3370 
3371  /// This method returns a target specific FastISel object, or null if the
3372  /// target does not support "fast" ISel.
3374  const TargetLibraryInfo *) const {
3375  return nullptr;
3376  }
3377 
3378  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3379  SelectionDAG &DAG) const;
3380 
3381  //===--------------------------------------------------------------------===//
3382  // Inline Asm Support hooks
3383  //
3384 
3385  /// This hook allows the target to expand an inline asm call to be explicit
3386  /// llvm code if it wants to. This is useful for turning simple inline asms
3387  /// into LLVM intrinsics, which gives the compiler more information about the
3388  /// behavior of the code.
3389  virtual bool ExpandInlineAsm(CallInst *) const {
3390  return false;
3391  }
3392 
3394  C_Register, // Constraint represents specific register(s).
3395  C_RegisterClass, // Constraint represents any of register(s) in class.
3396  C_Memory, // Memory constraint.
3397  C_Other, // Something else.
3398  C_Unknown // Unsupported constraint.
3399  };
3400 
3402  // Generic weights.
3403  CW_Invalid = -1, // No match.
3404  CW_Okay = 0, // Acceptable.
3405  CW_Good = 1, // Good weight.
3406  CW_Better = 2, // Better weight.
3407  CW_Best = 3, // Best weight.
3408 
3409  // Well-known weights.
3410  CW_SpecificReg = CW_Okay, // Specific register operands.
3411  CW_Register = CW_Good, // Register operands.
3412  CW_Memory = CW_Better, // Memory operands.
3413  CW_Constant = CW_Best, // Constant operand.
3414  CW_Default = CW_Okay // Default or don't know type.
3415  };
3416 
3417  /// This contains information for each constraint that we are lowering.
3419  /// This contains the actual string for the code, like "m". TargetLowering
3420  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3421  /// matches the operand.
3422  std::string ConstraintCode;
3423 
3424  /// Information about the constraint code, e.g. Register, RegisterClass,
3425  /// Memory, Other, Unknown.
3427 
3428  /// If this is the result output operand or a clobber, this is null,
3429  /// otherwise it is the incoming operand to the CallInst. This gets
3430  /// modified as the asm is processed.
3431  Value *CallOperandVal = nullptr;
3432 
3433  /// The ValueType for the operand value.
3434  MVT ConstraintVT = MVT::Other;
3435 
3436  /// Copy constructor for copying from a ConstraintInfo.
3438  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3439 
3440  /// Return true of this is an input operand that is a matching constraint
3441  /// like "4".
3442  bool isMatchingInputConstraint() const;
3443 
3444  /// If this is an input matching constraint, this method returns the output
3445  /// operand it matches.
3446  unsigned getMatchedOperand() const;
3447  };
3448 
3449  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3450 
3451  /// Split up the constraint string from the inline assembly value into the
3452  /// specific constraints and their prefixes, and also tie in the associated
3453  /// operand values. If this returns an empty vector, and if the constraint
3454  /// string itself isn't empty, there was an error parsing.
3455  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3456  const TargetRegisterInfo *TRI,
3457  ImmutableCallSite CS) const;
3458 
3459  /// Examine constraint type and operand type and determine a weight value.
3460  /// The operand object must already have been set up with the operand type.
3461  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3462  AsmOperandInfo &info, int maIndex) const;
3463 
3464  /// Examine constraint string and operand type and determine a weight value.
3465  /// The operand object must already have been set up with the operand type.
3466  virtual ConstraintWeight getSingleConstraintMatchWeight(
3467  AsmOperandInfo &info, const char *constraint) const;
3468 
3469  /// Determines the constraint code and constraint type to use for the specific
3470  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3471  /// If the actual operand being passed in is available, it can be passed in as
3472  /// Op, otherwise an empty SDValue can be passed.
3473  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3474  SDValue Op,
3475  SelectionDAG *DAG = nullptr) const;
3476 
3477  /// Given a constraint, return the type of constraint it is for this target.
3478  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3479 
3480  /// Given a physical register constraint (e.g. {edx}), return the register
3481  /// number and the register class for the register.
3482  ///
3483  /// Given a register class constraint, like 'r', if this corresponds directly
3484  /// to an LLVM register class, return a register of 0 and the register class
3485  /// pointer.
3486  ///
3487  /// This should only be used for C_Register constraints. On error, this
3488  /// returns a register number of 0 and a null register class pointer.
3489  virtual std::pair<unsigned, const TargetRegisterClass *>
3490  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3491  StringRef Constraint, MVT VT) const;
3492 
3493  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3494  if (ConstraintCode == "i")
3495  return InlineAsm::Constraint_i;
3496  else if (ConstraintCode == "m")
3497  return InlineAsm::Constraint_m;
3499  }
3500 
3501  /// Try to replace an X constraint, which matches anything, with another that
3502  /// has more specific requirements based on the type of the corresponding
3503  /// operand. This returns null if there is no replacement to make.
3504  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3505 
3506  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3507  /// add anything to Ops.
3508  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3509  std::vector<SDValue> &Ops,
3510  SelectionDAG &DAG) const;
3511 
3512  //===--------------------------------------------------------------------===//
3513  // Div utility functions
3514  //
3515  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3516  SmallVectorImpl<SDNode *> &Created) const;
3517  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3518  SmallVectorImpl<SDNode *> &Created) const;
3519 
3520  /// Targets may override this function to provide custom SDIV lowering for
3521  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3522  /// assumes SDIV is expensive and replaces it with a series of other integer
3523  /// operations.
3524  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3525  SelectionDAG &DAG,
3526  SmallVectorImpl<SDNode *> &Created) const;
3527 
3528  /// Indicate whether this target prefers to combine FDIVs with the same
3529  /// divisor. If the transform should never be done, return zero. If the
3530  /// transform should be done, return the minimum number of divisor uses
3531  /// that must exist.
3532  virtual unsigned combineRepeatedFPDivisors() const {
3533  return 0;
3534  }
3535 
3536  /// Hooks for building estimates in place of slower divisions and square
3537  /// roots.
3538 
3539  /// Return either a square root or its reciprocal estimate value for the input
3540  /// operand.
3541  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3542  /// 'Enabled' as set by a potential default override attribute.
3543  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3544  /// refinement iterations required to generate a sufficient (though not
3545  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3546  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3547  /// algorithm implementation that uses either one or two constants.
3548  /// The boolean Reciprocal is used to select whether the estimate is for the
3549  /// square root of the input operand or the reciprocal of its square root.
3550  /// A target may choose to implement its own refinement within this function.
3551  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3552  /// any further refinement of the estimate.
3553  /// An empty SDValue return means no estimate sequence can be created.
3555  int Enabled, int &RefinementSteps,
3556  bool &UseOneConstNR, bool Reciprocal) const {
3557  return SDValue();
3558  }
3559 
3560  /// Return a reciprocal estimate value for the input operand.
3561  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3562  /// 'Enabled' as set by a potential default override attribute.
3563  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3564  /// refinement iterations required to generate a sufficient (though not
3565  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3566  /// A target may choose to implement its own refinement within this function.
3567  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3568  /// any further refinement of the estimate.
3569  /// An empty SDValue return means no estimate sequence can be created.
3571  int Enabled, int &RefinementSteps) const {
3572  return SDValue();
3573  }
3574 
3575  //===--------------------------------------------------------------------===//
3576  // Legalization utility functions
3577  //
3578 
3579  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3580  /// respectively, each computing an n/2-bit part of the result.
3581  /// \param Result A vector that will be filled with the parts of the result
3582  /// in little-endian order.
3583  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3584  /// if you want to control how low bits are extracted from the LHS.
3585  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3586  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3587  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3588  /// \returns true if the node has been expanded, false if it has not
3589  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3592  SDValue LL = SDValue(), SDValue LH = SDValue(),
3593  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3594 
3595  /// Expand a MUL into two nodes. One that computes the high bits of
3596  /// the result and one that computes the low bits.
3597  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3598  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3599  /// if you want to control how low bits are extracted from the LHS.
3600  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3601  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3602  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3603  /// \returns true if the node has been expanded. false if it has not
3604  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3605  SelectionDAG &DAG, MulExpansionKind Kind,
3606  SDValue LL = SDValue(), SDValue LH = SDValue(),
3607  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3608 
3609  /// Expand float(f32) to SINT(i64) conversion
3610  /// \param N Node to expand
3611  /// \param Result output after conversion
3612  /// \returns True, if the expansion was successful, false otherwise
3613  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3614 
3615  /// Turn load of vector type into a load of the individual elements.
3616  /// \param LD load to expand
3617  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3618  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3619 
3620  // Turn a store of a vector type into stores of the individual elements.
3621  /// \param ST Store with a vector value type
3622  /// \returns MERGE_VALUs of the individual store chains.
3623  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3624 
3625  /// Expands an unaligned load to 2 half-size loads for an integer, and
3626  /// possibly more for vectors.
3627  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3628  SelectionDAG &DAG) const;
3629 
3630  /// Expands an unaligned store to 2 half-size stores for integer values, and
3631  /// possibly more for vectors.
3632  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3633 
3634  /// Increments memory address \p Addr according to the type of the value
3635  /// \p DataVT that should be stored. If the data is stored in compressed
3636  /// form, the memory address should be incremented according to the number of
3637  /// the stored elements. This number is equal to the number of '1's bits
3638  /// in the \p Mask.
3639  /// \p DataVT is a vector type. \p Mask is a vector value.
3640  /// \p DataVT and \p Mask have the same number of vector elements.
3641  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3642  EVT DataVT, SelectionDAG &DAG,
3643  bool IsCompressedMemory) const;
3644 
3645  /// Get a pointer to vector element \p Idx located in memory for a vector of
3646  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3647  /// bounds the returned pointer is unspecified, but will be within the vector
3648  /// bounds.
3649  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3650  SDValue Index) const;
3651 
3652  //===--------------------------------------------------------------------===//
3653  // Instruction Emitting Hooks
3654  //
3655 
3656  /// This method should be implemented by targets that mark instructions with
3657  /// the 'usesCustomInserter' flag. These instructions are special in various
3658  /// ways, which require special support to insert. The specified MachineInstr
3659  /// is created but not inserted into any basic blocks, and this method is
3660  /// called to expand it into a sequence of instructions, potentially also
3661  /// creating new basic blocks and control flow.
3662  /// As long as the returned basic block is different (i.e., we created a new
3663  /// one), the custom inserter is free to modify the rest of \p MBB.
3664  virtual MachineBasicBlock *
3665  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3666 
3667  /// This method should be implemented by targets that mark instructions with
3668  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3669  /// instruction selection by target hooks. e.g. To fill in optional defs for
3670  /// ARM 's' setting instructions.
3671  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3672  SDNode *Node) const;
3673 
3674  /// If this function returns true, SelectionDAGBuilder emits a
3675  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3676  virtual bool useLoadStackGuardNode() const {
3677  return false;
3678  }
3679 
3681  const SDLoc &DL) const {
3682  llvm_unreachable("not implemented for this target");
3683  }
3684 
3685  /// Lower TLS global address SDNode for target independent emulated TLS model.
3686  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3687  SelectionDAG &DAG) const;
3688 
3689  /// Expands target specific indirect branch for the case of JumpTable
3690  /// expanasion.
3692  SelectionDAG &DAG) const {
3693  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3694  }
3695 
3696  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3697  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3698  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3699  // combiner can fold the new nodes.
3700  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3701 
3702 private:
3703  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3704  ISD::CondCode Cond, DAGCombinerInfo &DCI,
3705  const SDLoc &DL) const;
3706 
3707  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3708  SDValue N1, ISD::CondCode Cond,
3709  DAGCombinerInfo &DCI,
3710  const SDLoc &DL) const;
3711 };
3712 
3713 /// Given an LLVM IR type and return type attributes, compute the return value
3714 /// EVTs and flags, and optionally also the offsets, if the return value is
3715 /// being lowered to memory.
3718  const TargetLowering &TLI, const DataLayout &DL);
3719 
3720 } // end namespace llvm
3721 
3722 #endif // LLVM_CODEGEN_TARGETLOWERING_H
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:837
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:562
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:365
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:273
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:312
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
virtual bool isFPImmLegal(const APFloat &, EVT) const
Returns true if the target can instruction select the specified FP immediate natively.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static ISD::NodeType getExtendForContent(BooleanContent Content)
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:266
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:168
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:360
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:681
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:258
void * PointerTy
Definition: GenericValue.h:22
bool doesNotReturn() const
Determine if the call cannot return.
Definition: CallSite.h:497
Definition: BitVector.h:921
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:731
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:359
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:63
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:126
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:310
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:919
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:170
Class to represent pointers.
Definition: DerivedTypes.h:467
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:42
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:894
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:16
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:598
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:471
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
bool isInvoke() const
Return true if a InvokeInst is enclosed.
Definition: CallSite.h:90
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:401
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
static const int LAST_LOADEXT_TYPE
Definition: ISDOpcodes.h:901
CCState - This class holds information needed while lowering arguments and return values...
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1023
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
virtual bool getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
unsigned getJumpBufSize() const
Returns the target&#39;s jmp_buf size in bytes (if never set, the default is 200)
virtual bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
Lower an interleaved load to target specific intrinsics.
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
virtual unsigned getMaxSupportedInterleaveFactor() const
Get the maximum supported factor for interleaved memory accesses.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Provides information about what library functions are available for the current target.
virtual bool shouldConsiderGEPOffsetSplit() const
TargetLoweringOpt(SelectionDAG &InDAG, bool LT, bool LO)
virtual bool isZExtFree(EVT FromTy, EVT ToTy) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:900
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths() const
Returns map of slow types for division or remainder with corresponding fast types.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
bool rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const
Check whether the range [Low,High] fits in a machine word.
virtual bool isZExtFree(SDValue Val, EVT VT2) const
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation has solution on this target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const
Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...
static bool Enabled
Definition: Statistic.cpp:51
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool enableExtLdPromotion() const
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Class to represent vector types.
Definition: DerivedTypes.h:393
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Target - Wrapper for Target specific information.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
Definition: APInt.h:70
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const
Returns the size of the platform&#39;s va_list object.
virtual bool preferShiftsToClearExtremeBits(SDValue X) const
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...
virtual bool hasAndNot(SDValue X) const
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
LegalizeTypeAction getTypeAction(MVT VT) const
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMaxExpandSizeMemcmp(bool OptSize) const
Get maximum # of load operations permitted for memcmp.
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:440
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:186
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:443
ValueTypeActionImpl ValueTypeActions
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
virtual bool needsFixedCatchObjects() const
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:565
Flags
Flags values. These may be or&#39;d together.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
virtual bool hasStandaloneRem(EVT VT) const
Return true if the target can handle a standalone remainder operation.
virtual bool useSoftFloat() const
CallLoweringInfo & setTailCall(bool Value=true)
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:598
Representation of each machine instruction.
Definition: MachineInstr.h:64
virtual bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const
Return true if it is profitable to move this shift by a constant amount though its operand...
CallLoweringInfo & setConvergent(bool Value=true)
SmallVector< SDValue, 32 > OutVals
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
virtual bool convertSelectOfConstantsToMath(EVT VT) const
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1353
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const
SelectSupportKind
Enum that describes what type of support for selects the target has.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
const ValueTypeActionImpl & getValueTypeActions() const
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
void setTypeAction(MVT VT, LegalizeTypeAction Action)
bool isPositionIndependent() const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const
Insert explicit copies in entry and exit blocks.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:574
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
Establish a view to a call site for examination.
Definition: CallSite.h:714
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
Return a reciprocal estimate value for the input operand.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that&#39;s to be used to test the result of the comparison libcall against zero...
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
unsigned getMinCmpXchgSizeInBits() const
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
uint32_t Size
Definition: Profile.cpp:47
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:882
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:309
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
const unsigned Kind
Multiway switch.
LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const