LLVM  6.0.0svn
TargetSchedule.cpp
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1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
22 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCSchedule.h"
28 #include <algorithm>
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
35  cl::desc("Use TargetSchedModel for latency lookup"));
36 
37 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
38  cl::desc("Use InstrItineraryData for latency lookup"));
39 
41  return EnableSchedModel && SchedModel.hasInstrSchedModel();
42 }
43 
45  return EnableSchedItins && !InstrItins.isEmpty();
46 }
47 
48 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
49  // Dividend and Divisor will be naturally swapped as needed.
50  while (Divisor) {
51  unsigned Rem = Dividend % Divisor;
52  Dividend = Divisor;
53  Divisor = Rem;
54  };
55  return Dividend;
56 }
57 
58 static unsigned lcm(unsigned A, unsigned B) {
59  unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
60  assert((LCM >= A && LCM >= B) && "LCM overflow");
61  return LCM;
62 }
63 
65  const TargetSubtargetInfo *sti,
66  const TargetInstrInfo *tii) {
67  SchedModel = sm;
68  STI = sti;
69  TII = tii;
70  STI->initInstrItins(InstrItins);
71 
72  unsigned NumRes = SchedModel.getNumProcResourceKinds();
73  ResourceFactors.resize(NumRes);
74  ResourceLCM = SchedModel.IssueWidth;
75  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
76  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
77  if (NumUnits > 0)
78  ResourceLCM = lcm(ResourceLCM, NumUnits);
79  }
80  MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
81  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
82  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
83  ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
84  }
85 }
86 
87 /// Returns true only if instruction is specified as single issue.
89  const MCSchedClassDesc *SC) const {
90  if (hasInstrSchedModel()) {
91  if (!SC)
92  SC = resolveSchedClass(MI);
93  if (SC->isValid())
94  return SC->BeginGroup;
95  }
96  return false;
97 }
98 
100  const MCSchedClassDesc *SC) const {
101  if (hasInstrSchedModel()) {
102  if (!SC)
103  SC = resolveSchedClass(MI);
104  if (SC->isValid())
105  return SC->EndGroup;
106  }
107  return false;
108 }
109 
111  const MCSchedClassDesc *SC) const {
112  if (hasInstrItineraries()) {
113  int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
114  return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
115  }
116  if (hasInstrSchedModel()) {
117  if (!SC)
118  SC = resolveSchedClass(MI);
119  if (SC->isValid())
120  return SC->NumMicroOps;
121  }
122  return MI->isTransient() ? 0 : 1;
123 }
124 
125 // The machine model may explicitly specify an invalid latency, which
126 // effectively means infinite latency. Since users of the TargetSchedule API
127 // don't know how to handle this, we convert it to a very large latency that is
128 // easy to distinguish when debugging the DAG but won't induce overflow.
129 static unsigned capLatency(int Cycles) {
130  return Cycles >= 0 ? Cycles : 1000;
131 }
132 
133 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
134 /// evaluation of predicates that depend on instruction operands or flags.
137  // Get the definition's scheduling class descriptor from this machine model.
138  unsigned SchedClass = MI->getDesc().getSchedClass();
139  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
140  if (!SCDesc->isValid())
141  return SCDesc;
142 
143 #ifndef NDEBUG
144  unsigned NIter = 0;
145 #endif
146  while (SCDesc->isVariant()) {
147  assert(++NIter < 6 && "Variants are nested deeper than the magic number");
148 
149  SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
150  SCDesc = SchedModel.getSchedClassDesc(SchedClass);
151  }
152  return SCDesc;
153 }
154 
155 /// Find the def index of this operand. This index maps to the machine model and
156 /// is independent of use operands. Def operands may be reordered with uses or
157 /// merged with uses without affecting the def index (e.g. before/after
158 /// regalloc). However, an instruction's def operands must never be reordered
159 /// with respect to each other.
160 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
161  unsigned DefIdx = 0;
162  for (unsigned i = 0; i != DefOperIdx; ++i) {
163  const MachineOperand &MO = MI->getOperand(i);
164  if (MO.isReg() && MO.isDef())
165  ++DefIdx;
166  }
167  return DefIdx;
168 }
169 
170 /// Find the use index of this operand. This is independent of the instruction's
171 /// def operands.
172 ///
173 /// Note that uses are not determined by the operand's isUse property, which
174 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
175 /// a "use". The machine model allows an operand to be both a Def and Use.
176 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
177  unsigned UseIdx = 0;
178  for (unsigned i = 0; i != UseOperIdx; ++i) {
179  const MachineOperand &MO = MI->getOperand(i);
180  if (MO.isReg() && MO.readsReg() && !MO.isDef())
181  ++UseIdx;
182  }
183  return UseIdx;
184 }
185 
186 // Top-level API for clients that know the operand indices.
188  const MachineInstr *DefMI, unsigned DefOperIdx,
189  const MachineInstr *UseMI, unsigned UseOperIdx) const {
190 
192  return TII->defaultDefLatency(SchedModel, *DefMI);
193 
194  if (hasInstrItineraries()) {
195  int OperLatency = 0;
196  if (UseMI) {
197  OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
198  *UseMI, UseOperIdx);
199  }
200  else {
201  unsigned DefClass = DefMI->getDesc().getSchedClass();
202  OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
203  }
204  if (OperLatency >= 0)
205  return OperLatency;
206 
207  // No operand latency was found.
208  unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
209 
210  // Expected latency is the max of the stage latency and itinerary props.
211  // Rather than directly querying InstrItins stage latency, we call a TII
212  // hook to allow subtargets to specialize latency. This hook is only
213  // applicable to the InstrItins model. InstrSchedModel should model all
214  // special cases without TII hooks.
215  InstrLatency =
216  std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
217  return InstrLatency;
218  }
219  // hasInstrSchedModel()
220  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
221  unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
222  if (DefIdx < SCDesc->NumWriteLatencyEntries) {
223  // Lookup the definition's write latency in SubtargetInfo.
224  const MCWriteLatencyEntry *WLEntry =
225  STI->getWriteLatencyEntry(SCDesc, DefIdx);
226  unsigned WriteID = WLEntry->WriteResourceID;
227  unsigned Latency = capLatency(WLEntry->Cycles);
228  if (!UseMI)
229  return Latency;
230 
231  // Lookup the use's latency adjustment in SubtargetInfo.
232  const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
233  if (UseDesc->NumReadAdvanceEntries == 0)
234  return Latency;
235  unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
236  int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
237  if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
238  return 0;
239  return Latency - Advance;
240  }
241  // If DefIdx does not exist in the model (e.g. implicit defs), then return
242  // unit latency (defaultDefLatency may be too conservative).
243 #ifndef NDEBUG
244  if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
245  && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
246  && SchedModel.isComplete()) {
247  errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
248  << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
249  llvm_unreachable("incomplete machine model");
250  }
251 #endif
252  // FIXME: Automatically giving all implicit defs defaultDefLatency is
253  // undesirable. We should only do it for defs that are known to the MC
254  // desc like flags. Truly implicit defs should get 1 cycle latency.
255  return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
256 }
257 
258 unsigned
259 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
260  unsigned Latency = 0;
261  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
262  DefIdx != DefEnd; ++DefIdx) {
263  // Lookup the definition's write latency in SubtargetInfo.
264  const MCWriteLatencyEntry *WLEntry =
265  STI->getWriteLatencyEntry(&SCDesc, DefIdx);
266  Latency = std::max(Latency, capLatency(WLEntry->Cycles));
267  }
268  return Latency;
269 }
270 
271 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
272  assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
273 
274  unsigned SCIdx = TII->get(Opcode).getSchedClass();
275  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
276 
277  if (SCDesc->isValid() && !SCDesc->isVariant())
278  return computeInstrLatency(*SCDesc);
279 
280  if (SCDesc->isValid()) {
281  assert (!SCDesc->isVariant() && "No MI sched latency: SCDesc->isVariant()");
282  return computeInstrLatency(*SCDesc);
283  }
284  return 0;
285 }
286 
287 unsigned
288 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
289  bool UseDefaultDefLatency) const {
290  // For the itinerary model, fall back to the old subtarget hook.
291  // Allow subtargets to compute Bundle latencies outside the machine model.
292  if (hasInstrItineraries() || MI->isBundle() ||
293  (!hasInstrSchedModel() && !UseDefaultDefLatency))
294  return TII->getInstrLatency(&InstrItins, *MI);
295 
296  if (hasInstrSchedModel()) {
297  const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
298  if (SCDesc->isValid())
299  return computeInstrLatency(*SCDesc);
300  }
301  return TII->defaultDefLatency(SchedModel, *MI);
302 }
303 
304 unsigned TargetSchedModel::
305 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
306  const MachineInstr *DepMI) const {
307  if (!SchedModel.isOutOfOrder())
308  return 1;
309 
310  // Out-of-order processor can dispatch WAW dependencies in the same cycle.
311 
312  // Treat predication as a data dependency for out-of-order cpus. In-order
313  // cpus do not need to treat predicated writes specially.
314  //
315  // TODO: The following hack exists because predication passes do not
316  // correctly append imp-use operands, and readsReg() strangely returns false
317  // for predicated defs.
318  unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
319  const MachineFunction &MF = *DefMI->getMF();
320  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
321  if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
322  return computeInstrLatency(DefMI);
323 
324  // If we have a per operand scheduling model, check if this def is writing
325  // an unbuffered resource. If so, it treated like an in-order cpu.
326  if (hasInstrSchedModel()) {
327  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
328  if (SCDesc->isValid()) {
329  for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
330  *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
331  if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
332  return 1;
333  }
334  }
335  }
336  return 0;
337 }
338 
339 static Optional<double>
340 getRThroughputFromItineraries(unsigned schedClass,
341  const InstrItineraryData *IID){
342  Optional<double> Throughput;
343 
344  for (const InstrStage *IS = IID->beginStage(schedClass),
345  *E = IID->endStage(schedClass);
346  IS != E; ++IS) {
347  if (IS->getCycles()) {
348  double Temp = countPopulation(IS->getUnits()) * 1.0 / IS->getCycles();
349  Throughput = Throughput.hasValue()
350  ? std::min(Throughput.getValue(), Temp)
351  : Temp;
352  }
353  }
354  if (Throughput.hasValue())
355  // We need reciprocal throughput that's why we return such value.
356  return 1 / Throughput.getValue();
357  return Throughput;
358 }
359 
360 static Optional<double>
362  const TargetSubtargetInfo *STI,
363  const MCSchedModel &SchedModel) {
364  Optional<double> Throughput;
365 
366  for (const MCWriteProcResEntry *WPR = STI->getWriteProcResBegin(SCDesc),
367  *WEnd = STI->getWriteProcResEnd(SCDesc);
368  WPR != WEnd; ++WPR) {
369  if (WPR->Cycles) {
370  unsigned NumUnits =
371  SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits;
372  double Temp = NumUnits * 1.0 / WPR->Cycles;
373  Throughput = Throughput.hasValue()
374  ? std::min(Throughput.getValue(), Temp)
375  : Temp;
376  }
377  }
378  if (Throughput.hasValue())
379  // We need reciprocal throughput that's why we return such value.
380  return 1 / Throughput.getValue();
381  return Throughput;
382 }
383 
386  if (hasInstrItineraries())
389  if (hasInstrSchedModel())
391  SchedModel);
392  return Optional<double>();
393 }
394 
397  unsigned SchedClass = TII->get(Opcode).getSchedClass();
398  if (hasInstrItineraries())
400  if (hasInstrSchedModel()) {
401  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
402  if (SCDesc->isValid() && !SCDesc->isVariant())
403  return getRThroughputFromInstrSchedModel(SCDesc, STI, SchedModel);
404  }
405  return Optional<double>();
406 }
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static unsigned lcm(unsigned A, unsigned B)
unsigned IssueWidth
Definition: MCSchedule.h:139
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned short NumMicroOps
Definition: MCSchedule.h:108
unsigned getReg() const
getReg - Returns the register number.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii)
Initialize the machine model for instruction scheduling.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:212
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:900
static unsigned gcd(unsigned Dividend, unsigned Divisor)
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:219
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:203
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
Reg
All possible values of the reg field in the ModR/M byte.
const InstrItineraryData * getInstrItineraries() const
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
static Optional< double > getRThroughputFromInstrSchedModel(const MCSchedClassDesc *SCDesc, const TargetSubtargetInfo *STI, const MCSchedModel &SchedModel)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
bool isBundle() const
Definition: MachineInstr.h:853
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:127
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Itinerary data supplied by a subtarget to be used by a target.
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
bool isValid() const
Definition: MCSchedule.h:118
unsigned NumReadAdvanceEntries
Definition: MCSchedule.h:116
TargetInstrInfo - Interface to description of machine instruction set.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
static Optional< double > getRThroughputFromItineraries(unsigned schedClass, const InstrItineraryData *IID)
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:565
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned NumWriteLatencyEntries
Definition: MCSchedule.h:114
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
MachineInstrBuilder & UseMI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if current group must end.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:199
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:512
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
MachineOperand class - Representation of each machine instruction operand.
bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if new group must begin.
MachineInstrBuilder MachineInstrBuilder & DefMI
CHAIN = SC CHAIN, Imm128 - System call.
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:206
bool isVariant() const
Definition: MCSchedule.h:121
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:927
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
bool isEmpty() const
Returns true if there are no itineraries.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:59
bool hasValue() const
Definition: Optional.h:137
These values represent a non-pipelined step in the execution of an instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
Optional< double > computeInstrRThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
static unsigned capLatency(int Cycles)
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:208
bool isImplicit() const
void resize(size_type N)
Definition: SmallVector.h:355