LLVM  9.0.0svn
TargetSubtargetInfo.cpp
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1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file describes the general parts of a Subtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Optional.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/Format.h"
21 #include <string>
22 
23 using namespace llvm;
24 
26  const Triple &TT, StringRef CPU, StringRef FS,
28  const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
29  const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
30  const InstrStage *IS, const unsigned *OC, const unsigned *FP)
31  : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
32 }
33 
35 
37  return true;
38 }
39 
41  return false;
42 }
43 
45  return false;
46 }
47 
49  return enableMachineScheduler();
50 }
51 
53  CodeGenOpt::Level OptLevel) const {
54  return true;
55 }
56 
58  return false;
59 }
60 
63 }
64 
66  return false;
67 }
68 
69 static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
70  static const char *SchedPrefix = " sched: [";
71  std::string Comment;
72  raw_string_ostream CS(Comment);
73  if (RThroughput != 0.0)
74  CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
75  << "]";
76  else
77  CS << SchedPrefix << Latency << ":?]";
78  CS.flush();
79  return Comment;
80 }
81 
82 /// Returns string representation of scheduler comment
84  if (MI.isPseudo() || MI.isTerminator())
85  return std::string();
86  // We don't cache TSchedModel because it depends on TargetInstrInfo
87  // that could be changed during the compilation
88  TargetSchedModel TSchedModel;
89  TSchedModel.init(this);
90  unsigned Latency = TSchedModel.computeInstrLatency(&MI);
91  double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
92  return createSchedInfoStr(Latency, RThroughput);
93 }
94 
95 /// Returns string representation of scheduler comment
96 std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
97  // We don't cache TSchedModel because it depends on TargetInstrInfo
98  // that could be changed during the compilation
99  TargetSchedModel TSchedModel;
100  TSchedModel.init(this);
101  unsigned Latency;
102  if (TSchedModel.hasInstrSchedModel())
103  Latency = TSchedModel.computeInstrLatency(MCI);
104  else if (TSchedModel.hasInstrItineraries()) {
105  auto *ItinData = TSchedModel.getInstrItineraries();
106  Latency = ItinData->getStageLatency(
107  getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
108  } else
109  return std::string();
110  double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
111  return createSchedInfoStr(Latency, RThroughput);
112 }
113 
115 }
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
double computeReciprocalThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
Used to provide key value pairs for CPU and arbitrary pointers.
SI optimize exec mask operations pre RA
Provide an instruction scheduling machine model to CodeGen passes.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
const InstrItineraryData * getInstrItineraries() const
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual const TargetInstrInfo * getInstrInfo() const
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
std::string getSchedInfoStr(const MachineInstr &MI) const
Returns string representation of scheduler comment.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:618
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
Representation of each machine instruction.
Definition: MachineInstr.h:63
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
These values represent a non-pipelined step in the execution of an instruction.
Generic base class for all target subtargets.
static std::string createSchedInfoStr(unsigned Latency, double RThroughput)
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual bool enableAdvancedRASplitCost() const
True if the subtarget should consider the cost of local intervals created by a split candidate when c...
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
IRTranslator LLVM IR MI
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.