LLVM  9.0.0svn
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1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file describes the general parts of a Subtarget.
10 //
11 //===----------------------------------------------------------------------===//
15 using namespace llvm;
18  const Triple &TT, StringRef CPU, StringRef FS,
20  const MCWriteProcResEntry *WPR,
21  const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
22  const InstrStage *IS, const unsigned *OC, const unsigned *FP)
23  : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
24 }
29  return true;
30 }
33  return false;
34 }
37  return false;
38 }
41  return enableMachineScheduler();
42 }
45  CodeGenOpt::Level OptLevel) const {
46  return true;
47 }
50  return false;
51 }
55 }
58  return false;
59 }
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SI optimize exec mask operations pre RA
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:64
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:95
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
These values represent a non-pipelined step in the execution of an instruction.
Generic base class for all target subtargets.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual bool enableAdvancedRASplitCost() const
True if the subtarget should consider the cost of local intervals created by a split candidate when c...
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.