LLVM  6.0.0svn
Thumb2SizeReduction.cpp
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1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARM.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMSubtarget.h"
14 #include "Thumb2InstrInfo.h"
15 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/StringRef.h"
29 #include "llvm/IR/DebugLoc.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
38 #include <algorithm>
39 #include <cassert>
40 #include <cstdint>
41 #include <functional>
42 #include <iterator>
43 #include <utility>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "t2-reduce-size"
48 
49 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
50 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
51 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
52 
53 static cl::opt<int> ReduceLimit("t2-reduce-limit",
54  cl::init(-1), cl::Hidden);
55 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
56  cl::init(-1), cl::Hidden);
57 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
58  cl::init(-1), cl::Hidden);
59 
60 namespace {
61 
62  /// ReduceTable - A static table with information on mapping from wide
63  /// opcodes to narrow
64  struct ReduceEntry {
65  uint16_t WideOpc; // Wide opcode
66  uint16_t NarrowOpc1; // Narrow opcode to transform to
67  uint16_t NarrowOpc2; // Narrow opcode when it's two-address
68  uint8_t Imm1Limit; // Limit of immediate field (bits)
69  uint8_t Imm2Limit; // Limit of immediate field when it's two-address
70  unsigned LowRegs1 : 1; // Only possible if low-registers are used
71  unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
72  unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
73  // 1 - No cc field.
74  // 2 - Always set CPSR.
75  unsigned PredCC2 : 2;
76  unsigned PartFlag : 1; // 16-bit instruction does partial flag update
77  unsigned Special : 1; // Needs to be dealt with specially
78  unsigned AvoidMovs: 1; // Avoid movs with shifter operand (for Swift)
79  };
80 
81  static const ReduceEntry ReduceTable[] = {
82  // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
83  { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84  { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85  { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86  { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
87  { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
88  { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
89  { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
90  { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
91  { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
92  //FIXME: Disable CMN, as CCodes are backwards from compare expectations
93  //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
94  { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
95  { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
96  { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
97  { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
98  // FIXME: adr.n immediate offset must be multiple of 4.
99  //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
100  { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
101  { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
102  { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
103  { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
104  { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
105  { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
106  // FIXME: Do we need the 16-bit 'S' variant?
107  { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
108  { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
109  { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
110  { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
111  { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
112  { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
113  { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
114  { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
115  { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
116  { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
117  { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
118  { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
119  { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
120  { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
121  { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
122  { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
123  { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
124  { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
125  { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
126  { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
127 
128  // FIXME: Clean this up after splitting each Thumb load / store opcode
129  // into multiple ones.
130  { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
131  { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
132  { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
133  { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
134  { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
135  { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
136  { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
137  { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
138  { ARM::t2LDR_POST,ARM::tLDMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
139  { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
140  { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
141  { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
142  { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
143  { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
144  { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
145  { ARM::t2STR_POST,ARM::tSTMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
146 
147  { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
148  { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
149  { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
150  // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
151  // tSTMIA_UPD is a change in semantics which can only be used if the base
152  // register is killed. This difference is correctly handled elsewhere.
153  { ARM::t2STMIA, ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
154  { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
155  { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
156  };
157 
158  class Thumb2SizeReduce : public MachineFunctionPass {
159  public:
160  static char ID;
161 
162  const Thumb2InstrInfo *TII;
163  const ARMSubtarget *STI;
164 
165  Thumb2SizeReduce(std::function<bool(const Function &)> Ftor);
166 
167  bool runOnMachineFunction(MachineFunction &MF) override;
168 
169  MachineFunctionProperties getRequiredProperties() const override {
172  }
173 
174  StringRef getPassName() const override {
175  return "Thumb2 instruction size reduction pass";
176  }
177 
178  private:
179  /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
180  DenseMap<unsigned, unsigned> ReduceOpcodeMap;
181 
182  bool canAddPseudoFlagDep(MachineInstr *Use, bool IsSelfLoop);
183 
184  bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
185  bool is2Addr, ARMCC::CondCodes Pred,
186  bool LiveCPSR, bool &HasCC, bool &CCDead);
187 
188  bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
189  const ReduceEntry &Entry);
190 
191  bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
192  const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
193 
194  /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
195  /// instruction.
196  bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
197  const ReduceEntry &Entry, bool LiveCPSR,
198  bool IsSelfLoop);
199 
200  /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
201  /// non-two-address instruction.
202  bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
203  const ReduceEntry &Entry, bool LiveCPSR,
204  bool IsSelfLoop);
205 
206  /// ReduceMI - Attempt to reduce MI, return true on success.
207  bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
208  bool LiveCPSR, bool IsSelfLoop);
209 
210  /// ReduceMBB - Reduce width of instructions in the specified basic block.
211  bool ReduceMBB(MachineBasicBlock &MBB);
212 
213  bool OptimizeSize;
214  bool MinimizeSize;
215 
216  // Last instruction to define CPSR in the current block.
217  MachineInstr *CPSRDef;
218  // Was CPSR last defined by a high latency instruction?
219  // When CPSRDef is null, this refers to CPSR defs in predecessors.
220  bool HighLatencyCPSR;
221 
222  struct MBBInfo {
223  // The flags leaving this block have high latency.
224  bool HighLatencyCPSR = false;
225  // Has this block been visited yet?
226  bool Visited = false;
227 
228  MBBInfo() = default;
229  };
230 
231  SmallVector<MBBInfo, 8> BlockInfo;
232 
233  std::function<bool(const Function &)> PredicateFtor;
234  };
235 
236  char Thumb2SizeReduce::ID = 0;
237 
238 } // end anonymous namespace
239 
240 Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
241  : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
242  OptimizeSize = MinimizeSize = false;
243  for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
244  unsigned FromOpc = ReduceTable[i].WideOpc;
245  if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
246  llvm_unreachable("Duplicated entries?");
247  }
248 }
249 
250 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
251  for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
252  if (*Regs == ARM::CPSR)
253  return true;
254  return false;
255 }
256 
257 // Check for a likely high-latency flag def.
259  switch(Def->getOpcode()) {
260  case ARM::FMSTAT:
261  case ARM::tMUL:
262  return true;
263  }
264  return false;
265 }
266 
267 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
268 /// the 's' 16-bit instruction partially update CPSR. Abort the
269 /// transformation to avoid adding false dependency on last CPSR setting
270 /// instruction which hurts the ability for out-of-order execution engine
271 /// to do register renaming magic.
272 /// This function checks if there is a read-of-write dependency between the
273 /// last instruction that defines the CPSR and the current instruction. If there
274 /// is, then there is no harm done since the instruction cannot be retired
275 /// before the CPSR setting instruction anyway.
276 /// Note, we are not doing full dependency analysis here for the sake of compile
277 /// time. We're not looking for cases like:
278 /// r0 = muls ...
279 /// r1 = add.w r0, ...
280 /// ...
281 /// = mul.w r1
282 /// In this case it would have been ok to narrow the mul.w to muls since there
283 /// are indirect RAW dependency between the muls and the mul.w
284 bool
285 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
286  // Disable the check for -Oz (aka OptimizeForSizeHarder).
287  if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
288  return false;
289 
290  if (!CPSRDef)
291  // If this BB loops back to itself, conservatively avoid narrowing the
292  // first instruction that does partial flag update.
293  return HighLatencyCPSR || FirstInSelfLoop;
294 
296  for (const MachineOperand &MO : CPSRDef->operands()) {
297  if (!MO.isReg() || MO.isUndef() || MO.isUse())
298  continue;
299  unsigned Reg = MO.getReg();
300  if (Reg == 0 || Reg == ARM::CPSR)
301  continue;
302  Defs.insert(Reg);
303  }
304 
305  for (const MachineOperand &MO : Use->operands()) {
306  if (!MO.isReg() || MO.isUndef() || MO.isDef())
307  continue;
308  unsigned Reg = MO.getReg();
309  if (Defs.count(Reg))
310  return false;
311  }
312 
313  // If the current CPSR has high latency, try to avoid the false dependency.
314  if (HighLatencyCPSR)
315  return true;
316 
317  // tMOVi8 usually doesn't start long dependency chains, and there are a lot
318  // of them, so always shrink them when CPSR doesn't have high latency.
319  if (Use->getOpcode() == ARM::t2MOVi ||
320  Use->getOpcode() == ARM::t2MOVi16)
321  return false;
322 
323  // No read-after-write dependency. The narrowing will add false dependency.
324  return true;
325 }
326 
327 bool
328 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
329  bool is2Addr, ARMCC::CondCodes Pred,
330  bool LiveCPSR, bool &HasCC, bool &CCDead) {
331  if ((is2Addr && Entry.PredCC2 == 0) ||
332  (!is2Addr && Entry.PredCC1 == 0)) {
333  if (Pred == ARMCC::AL) {
334  // Not predicated, must set CPSR.
335  if (!HasCC) {
336  // Original instruction was not setting CPSR, but CPSR is not
337  // currently live anyway. It's ok to set it. The CPSR def is
338  // dead though.
339  if (!LiveCPSR) {
340  HasCC = true;
341  CCDead = true;
342  return true;
343  }
344  return false;
345  }
346  } else {
347  // Predicated, must not set CPSR.
348  if (HasCC)
349  return false;
350  }
351  } else if ((is2Addr && Entry.PredCC2 == 2) ||
352  (!is2Addr && Entry.PredCC1 == 2)) {
353  /// Old opcode has an optional def of CPSR.
354  if (HasCC)
355  return true;
356  // If old opcode does not implicitly define CPSR, then it's not ok since
357  // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
358  if (!HasImplicitCPSRDef(MI->getDesc()))
359  return false;
360  HasCC = true;
361  } else {
362  // 16-bit instruction does not set CPSR.
363  if (HasCC)
364  return false;
365  }
366 
367  return true;
368 }
369 
370 static bool VerifyLowRegs(MachineInstr *MI) {
371  unsigned Opc = MI->getOpcode();
372  bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD);
373  bool isLROk = (Opc == ARM::t2STMDB_UPD);
374  bool isSPOk = isPCOk || isLROk;
375  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
376  const MachineOperand &MO = MI->getOperand(i);
377  if (!MO.isReg() || MO.isImplicit())
378  continue;
379  unsigned Reg = MO.getReg();
380  if (Reg == 0 || Reg == ARM::CPSR)
381  continue;
382  if (isPCOk && Reg == ARM::PC)
383  continue;
384  if (isLROk && Reg == ARM::LR)
385  continue;
386  if (Reg == ARM::SP) {
387  if (isSPOk)
388  continue;
389  if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
390  // Special case for these ldr / str with sp as base register.
391  continue;
392  }
393  if (!isARMLowRegister(Reg))
394  return false;
395  }
396  return true;
397 }
398 
399 bool
400 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
401  const ReduceEntry &Entry) {
402  if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
403  return false;
404 
405  unsigned Scale = 1;
406  bool HasImmOffset = false;
407  bool HasShift = false;
408  bool HasOffReg = true;
409  bool isLdStMul = false;
410  unsigned Opc = Entry.NarrowOpc1;
411  unsigned OpNum = 3; // First 'rest' of operands.
412  uint8_t ImmLimit = Entry.Imm1Limit;
413 
414  switch (Entry.WideOpc) {
415  default:
416  llvm_unreachable("Unexpected Thumb2 load / store opcode!");
417  case ARM::t2LDRi12:
418  case ARM::t2STRi12:
419  if (MI->getOperand(1).getReg() == ARM::SP) {
420  Opc = Entry.NarrowOpc2;
421  ImmLimit = Entry.Imm2Limit;
422  }
423 
424  Scale = 4;
425  HasImmOffset = true;
426  HasOffReg = false;
427  break;
428  case ARM::t2LDRBi12:
429  case ARM::t2STRBi12:
430  HasImmOffset = true;
431  HasOffReg = false;
432  break;
433  case ARM::t2LDRHi12:
434  case ARM::t2STRHi12:
435  Scale = 2;
436  HasImmOffset = true;
437  HasOffReg = false;
438  break;
439  case ARM::t2LDRs:
440  case ARM::t2LDRBs:
441  case ARM::t2LDRHs:
442  case ARM::t2LDRSBs:
443  case ARM::t2LDRSHs:
444  case ARM::t2STRs:
445  case ARM::t2STRBs:
446  case ARM::t2STRHs:
447  HasShift = true;
448  OpNum = 4;
449  break;
450  case ARM::t2LDR_POST:
451  case ARM::t2STR_POST: {
452  if (!MBB.getParent()->getFunction()->optForMinSize())
453  return false;
454 
455  if (!MI->hasOneMemOperand() ||
456  (*MI->memoperands_begin())->getAlignment() < 4)
457  return false;
458 
459  // We're creating a completely different type of load/store - LDM from LDR.
460  // For this reason we can't reuse the logic at the end of this function; we
461  // have to implement the MI building here.
462  bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
463  unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
464  unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
465  unsigned Offset = MI->getOperand(3).getImm();
466  unsigned PredImm = MI->getOperand(4).getImm();
467  unsigned PredReg = MI->getOperand(5).getReg();
470 
471  if (Offset != 4)
472  return false;
473 
474  // Add the 16-bit load / store instruction.
475  DebugLoc dl = MI->getDebugLoc();
476  auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
477  .addReg(Rn, RegState::Define)
478  .addReg(Rn)
479  .addImm(PredImm)
480  .addReg(PredReg)
481  .addReg(Rt, IsStore ? 0 : RegState::Define);
482 
483  // Transfer memoperands.
484  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
485 
486  // Transfer MI flags.
487  MIB.setMIFlags(MI->getFlags());
488 
489  // Kill the old instruction.
490  MI->eraseFromBundle();
491  ++NumLdSts;
492  return true;
493  }
494  case ARM::t2LDMIA: {
495  unsigned BaseReg = MI->getOperand(0).getReg();
496  assert(isARMLowRegister(BaseReg));
497 
498  // For the non-writeback version (this one), the base register must be
499  // one of the registers being loaded.
500  bool isOK = false;
501  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
502  if (MI->getOperand(i).getReg() == BaseReg) {
503  isOK = true;
504  break;
505  }
506  }
507 
508  if (!isOK)
509  return false;
510 
511  OpNum = 0;
512  isLdStMul = true;
513  break;
514  }
515  case ARM::t2STMIA:
516  // If the base register is killed, we don't care what its value is after the
517  // instruction, so we can use an updating STMIA.
518  if (!MI->getOperand(0).isKill())
519  return false;
520 
521  break;
522  case ARM::t2LDMIA_RET: {
523  unsigned BaseReg = MI->getOperand(1).getReg();
524  if (BaseReg != ARM::SP)
525  return false;
526  Opc = Entry.NarrowOpc2; // tPOP_RET
527  OpNum = 2;
528  isLdStMul = true;
529  break;
530  }
531  case ARM::t2LDMIA_UPD:
532  case ARM::t2STMIA_UPD:
533  case ARM::t2STMDB_UPD: {
534  OpNum = 0;
535 
536  unsigned BaseReg = MI->getOperand(1).getReg();
537  if (BaseReg == ARM::SP &&
538  (Entry.WideOpc == ARM::t2LDMIA_UPD ||
539  Entry.WideOpc == ARM::t2STMDB_UPD)) {
540  Opc = Entry.NarrowOpc2; // tPOP or tPUSH
541  OpNum = 2;
542  } else if (!isARMLowRegister(BaseReg) ||
543  (Entry.WideOpc != ARM::t2LDMIA_UPD &&
544  Entry.WideOpc != ARM::t2STMIA_UPD)) {
545  return false;
546  }
547 
548  isLdStMul = true;
549  break;
550  }
551  }
552 
553  unsigned OffsetReg = 0;
554  bool OffsetKill = false;
555  bool OffsetInternal = false;
556  if (HasShift) {
557  OffsetReg = MI->getOperand(2).getReg();
558  OffsetKill = MI->getOperand(2).isKill();
559  OffsetInternal = MI->getOperand(2).isInternalRead();
560 
561  if (MI->getOperand(3).getImm())
562  // Thumb1 addressing mode doesn't support shift.
563  return false;
564  }
565 
566  unsigned OffsetImm = 0;
567  if (HasImmOffset) {
568  OffsetImm = MI->getOperand(2).getImm();
569  unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
570 
571  if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
572  // Make sure the immediate field fits.
573  return false;
574  }
575 
576  // Add the 16-bit load / store instruction.
577  DebugLoc dl = MI->getDebugLoc();
578  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
579 
580  // tSTMIA_UPD takes a defining register operand. We've already checked that
581  // the register is killed, so mark it as dead here.
582  if (Entry.WideOpc == ARM::t2STMIA)
584 
585  if (!isLdStMul) {
586  MIB.add(MI->getOperand(0));
587  MIB.add(MI->getOperand(1));
588 
589  if (HasImmOffset)
590  MIB.addImm(OffsetImm / Scale);
591 
592  assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
593 
594  if (HasOffReg)
595  MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
596  getInternalReadRegState(OffsetInternal));
597  }
598 
599  // Transfer the rest of operands.
600  for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
601  MIB.add(MI->getOperand(OpNum));
602 
603  // Transfer memoperands.
604  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
605 
606  // Transfer MI flags.
607  MIB.setMIFlags(MI->getFlags());
608 
609  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
610 
611  MBB.erase_instr(MI);
612  ++NumLdSts;
613  return true;
614 }
615 
616 bool
617 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
618  const ReduceEntry &Entry,
619  bool LiveCPSR, bool IsSelfLoop) {
620  unsigned Opc = MI->getOpcode();
621  if (Opc == ARM::t2ADDri) {
622  // If the source register is SP, try to reduce to tADDrSPi, otherwise
623  // it's a normal reduce.
624  if (MI->getOperand(1).getReg() != ARM::SP) {
625  if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
626  return true;
627  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
628  }
629  // Try to reduce to tADDrSPi.
630  unsigned Imm = MI->getOperand(2).getImm();
631  // The immediate must be in range, the destination register must be a low
632  // reg, the predicate must be "always" and the condition flags must not
633  // be being set.
634  if (Imm & 3 || Imm > 1020)
635  return false;
636  if (!isARMLowRegister(MI->getOperand(0).getReg()))
637  return false;
638  if (MI->getOperand(3).getImm() != ARMCC::AL)
639  return false;
640  const MCInstrDesc &MCID = MI->getDesc();
641  if (MCID.hasOptionalDef() &&
642  MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
643  return false;
644 
645  MachineInstrBuilder MIB =
646  BuildMI(MBB, MI, MI->getDebugLoc(),
647  TII->get(ARM::tADDrSPi))
648  .add(MI->getOperand(0))
649  .add(MI->getOperand(1))
650  .addImm(Imm / 4) // The tADDrSPi has an implied scale by four.
651  .add(predOps(ARMCC::AL));
652 
653  // Transfer MI flags.
654  MIB.setMIFlags(MI->getFlags());
655 
656  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
657 
658  MBB.erase_instr(MI);
659  ++NumNarrows;
660  return true;
661  }
662 
663  if (Entry.LowRegs1 && !VerifyLowRegs(MI))
664  return false;
665 
666  if (MI->mayLoadOrStore())
667  return ReduceLoadStore(MBB, MI, Entry);
668 
669  switch (Opc) {
670  default: break;
671  case ARM::t2ADDSri:
672  case ARM::t2ADDSrr: {
673  unsigned PredReg = 0;
674  if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
675  switch (Opc) {
676  default: break;
677  case ARM::t2ADDSri:
678  if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
679  return true;
681  case ARM::t2ADDSrr:
682  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
683  }
684  }
685  break;
686  }
687  case ARM::t2RSBri:
688  case ARM::t2RSBSri:
689  case ARM::t2SXTB:
690  case ARM::t2SXTH:
691  case ARM::t2UXTB:
692  case ARM::t2UXTH:
693  if (MI->getOperand(2).getImm() == 0)
694  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
695  break;
696  case ARM::t2MOVi16:
697  // Can convert only 'pure' immediate operands, not immediates obtained as
698  // globals' addresses.
699  if (MI->getOperand(1).isImm())
700  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
701  break;
702  case ARM::t2CMPrr: {
703  // Try to reduce to the lo-reg only version first. Why there are two
704  // versions of the instruction is a mystery.
705  // It would be nice to just have two entries in the master table that
706  // are prioritized, but the table assumes a unique entry for each
707  // source insn opcode. So for now, we hack a local entry record to use.
708  static const ReduceEntry NarrowEntry =
709  { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
710  if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
711  return true;
712  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
713  }
714  }
715  return false;
716 }
717 
718 bool
719 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
720  const ReduceEntry &Entry,
721  bool LiveCPSR, bool IsSelfLoop) {
722  if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
723  return false;
724 
725  if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
726  // Don't issue movs with shifter operand for some CPUs unless we
727  // are optimizing for size.
728  return false;
729 
730  unsigned Reg0 = MI->getOperand(0).getReg();
731  unsigned Reg1 = MI->getOperand(1).getReg();
732  // t2MUL is "special". The tied source operand is second, not first.
733  if (MI->getOpcode() == ARM::t2MUL) {
734  unsigned Reg2 = MI->getOperand(2).getReg();
735  // Early exit if the regs aren't all low regs.
736  if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
737  || !isARMLowRegister(Reg2))
738  return false;
739  if (Reg0 != Reg2) {
740  // If the other operand also isn't the same as the destination, we
741  // can't reduce.
742  if (Reg1 != Reg0)
743  return false;
744  // Try to commute the operands to make it a 2-address instruction.
745  MachineInstr *CommutedMI = TII->commuteInstruction(*MI);
746  if (!CommutedMI)
747  return false;
748  }
749  } else if (Reg0 != Reg1) {
750  // Try to commute the operands to make it a 2-address instruction.
751  unsigned CommOpIdx1 = 1;
752  unsigned CommOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
753  if (!TII->findCommutedOpIndices(*MI, CommOpIdx1, CommOpIdx2) ||
754  MI->getOperand(CommOpIdx2).getReg() != Reg0)
755  return false;
756  MachineInstr *CommutedMI =
757  TII->commuteInstruction(*MI, false, CommOpIdx1, CommOpIdx2);
758  if (!CommutedMI)
759  return false;
760  }
761  if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
762  return false;
763  if (Entry.Imm2Limit) {
764  unsigned Imm = MI->getOperand(2).getImm();
765  unsigned Limit = (1 << Entry.Imm2Limit) - 1;
766  if (Imm > Limit)
767  return false;
768  } else {
769  unsigned Reg2 = MI->getOperand(2).getReg();
770  if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
771  return false;
772  }
773 
774  // Check if it's possible / necessary to transfer the predicate.
775  const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
776  unsigned PredReg = 0;
777  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
778  bool SkipPred = false;
779  if (Pred != ARMCC::AL) {
780  if (!NewMCID.isPredicable())
781  // Can't transfer predicate, fail.
782  return false;
783  } else {
784  SkipPred = !NewMCID.isPredicable();
785  }
786 
787  bool HasCC = false;
788  bool CCDead = false;
789  const MCInstrDesc &MCID = MI->getDesc();
790  if (MCID.hasOptionalDef()) {
791  unsigned NumOps = MCID.getNumOperands();
792  HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
793  if (HasCC && MI->getOperand(NumOps-1).isDead())
794  CCDead = true;
795  }
796  if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
797  return false;
798 
799  // Avoid adding a false dependency on partial flag update by some 16-bit
800  // instructions which has the 's' bit set.
801  if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
802  canAddPseudoFlagDep(MI, IsSelfLoop))
803  return false;
804 
805  // Add the 16-bit instruction.
806  DebugLoc dl = MI->getDebugLoc();
807  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
808  MIB.add(MI->getOperand(0));
809  if (NewMCID.hasOptionalDef())
810  MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
811 
812  // Transfer the rest of operands.
813  unsigned NumOps = MCID.getNumOperands();
814  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
815  if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
816  continue;
817  if (SkipPred && MCID.OpInfo[i].isPredicate())
818  continue;
819  MIB.add(MI->getOperand(i));
820  }
821 
822  // Transfer MI flags.
823  MIB.setMIFlags(MI->getFlags());
824 
825  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
826 
827  MBB.erase_instr(MI);
828  ++Num2Addrs;
829  return true;
830 }
831 
832 bool
833 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
834  const ReduceEntry &Entry,
835  bool LiveCPSR, bool IsSelfLoop) {
836  if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
837  return false;
838 
839  if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
840  // Don't issue movs with shifter operand for some CPUs unless we
841  // are optimizing for size.
842  return false;
843 
844  unsigned Limit = ~0U;
845  if (Entry.Imm1Limit)
846  Limit = (1 << Entry.Imm1Limit) - 1;
847 
848  const MCInstrDesc &MCID = MI->getDesc();
849  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
850  if (MCID.OpInfo[i].isPredicate())
851  continue;
852  const MachineOperand &MO = MI->getOperand(i);
853  if (MO.isReg()) {
854  unsigned Reg = MO.getReg();
855  if (!Reg || Reg == ARM::CPSR)
856  continue;
857  if (Entry.LowRegs1 && !isARMLowRegister(Reg))
858  return false;
859  } else if (MO.isImm() &&
860  !MCID.OpInfo[i].isPredicate()) {
861  if (((unsigned)MO.getImm()) > Limit)
862  return false;
863  }
864  }
865 
866  // Check if it's possible / necessary to transfer the predicate.
867  const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
868  unsigned PredReg = 0;
869  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
870  bool SkipPred = false;
871  if (Pred != ARMCC::AL) {
872  if (!NewMCID.isPredicable())
873  // Can't transfer predicate, fail.
874  return false;
875  } else {
876  SkipPred = !NewMCID.isPredicable();
877  }
878 
879  bool HasCC = false;
880  bool CCDead = false;
881  if (MCID.hasOptionalDef()) {
882  unsigned NumOps = MCID.getNumOperands();
883  HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
884  if (HasCC && MI->getOperand(NumOps-1).isDead())
885  CCDead = true;
886  }
887  if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
888  return false;
889 
890  // Avoid adding a false dependency on partial flag update by some 16-bit
891  // instructions which has the 's' bit set.
892  if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
893  canAddPseudoFlagDep(MI, IsSelfLoop))
894  return false;
895 
896  // Add the 16-bit instruction.
897  DebugLoc dl = MI->getDebugLoc();
898  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
899  MIB.add(MI->getOperand(0));
900  if (NewMCID.hasOptionalDef())
901  MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
902 
903  // Transfer the rest of operands.
904  unsigned NumOps = MCID.getNumOperands();
905  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
906  if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
907  continue;
908  if ((MCID.getOpcode() == ARM::t2RSBSri ||
909  MCID.getOpcode() == ARM::t2RSBri ||
910  MCID.getOpcode() == ARM::t2SXTB ||
911  MCID.getOpcode() == ARM::t2SXTH ||
912  MCID.getOpcode() == ARM::t2UXTB ||
913  MCID.getOpcode() == ARM::t2UXTH) && i == 2)
914  // Skip the zero immediate operand, it's now implicit.
915  continue;
916  bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
917  if (SkipPred && isPred)
918  continue;
919  const MachineOperand &MO = MI->getOperand(i);
920  if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
921  // Skip implicit def of CPSR. Either it's modeled as an optional
922  // def now or it's already an implicit def on the new instruction.
923  continue;
924  MIB.add(MO);
925  }
926  if (!MCID.isPredicable() && NewMCID.isPredicable())
927  MIB.add(predOps(ARMCC::AL));
928 
929  // Transfer MI flags.
930  MIB.setMIFlags(MI->getFlags());
931 
932  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
933 
934  MBB.erase_instr(MI);
935  ++NumNarrows;
936  return true;
937 }
938 
939 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
940  bool HasDef = false;
941  for (const MachineOperand &MO : MI.operands()) {
942  if (!MO.isReg() || MO.isUndef() || MO.isUse())
943  continue;
944  if (MO.getReg() != ARM::CPSR)
945  continue;
946 
947  DefCPSR = true;
948  if (!MO.isDead())
949  HasDef = true;
950  }
951 
952  return HasDef || LiveCPSR;
953 }
954 
955 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
956  for (const MachineOperand &MO : MI.operands()) {
957  if (!MO.isReg() || MO.isUndef() || MO.isDef())
958  continue;
959  if (MO.getReg() != ARM::CPSR)
960  continue;
961  assert(LiveCPSR && "CPSR liveness tracking is wrong!");
962  if (MO.isKill()) {
963  LiveCPSR = false;
964  break;
965  }
966  }
967 
968  return LiveCPSR;
969 }
970 
971 bool Thumb2SizeReduce::ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
972  bool LiveCPSR, bool IsSelfLoop) {
973  unsigned Opcode = MI->getOpcode();
974  DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
975  if (OPI == ReduceOpcodeMap.end())
976  return false;
977  const ReduceEntry &Entry = ReduceTable[OPI->second];
978 
979  // Don't attempt normal reductions on "special" cases for now.
980  if (Entry.Special)
981  return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
982 
983  // Try to transform to a 16-bit two-address instruction.
984  if (Entry.NarrowOpc2 &&
985  ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
986  return true;
987 
988  // Try to transform to a 16-bit non-two-address instruction.
989  if (Entry.NarrowOpc1 &&
990  ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
991  return true;
992 
993  return false;
994 }
995 
996 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
997  bool Modified = false;
998 
999  // Yes, CPSR could be livein.
1000  bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
1001  MachineInstr *BundleMI = nullptr;
1002 
1003  CPSRDef = nullptr;
1004  HighLatencyCPSR = false;
1005 
1006  // Check predecessors for the latest CPSRDef.
1007  for (auto *Pred : MBB.predecessors()) {
1008  const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
1009  if (!PInfo.Visited) {
1010  // Since blocks are visited in RPO, this must be a back-edge.
1011  continue;
1012  }
1013  if (PInfo.HighLatencyCPSR) {
1014  HighLatencyCPSR = true;
1015  break;
1016  }
1017  }
1018 
1019  // If this BB loops back to itself, conservatively avoid narrowing the
1020  // first instruction that does partial flag update.
1021  bool IsSelfLoop = MBB.isSuccessor(&MBB);
1024  for (; MII != E; MII = NextMII) {
1025  NextMII = std::next(MII);
1026 
1027  MachineInstr *MI = &*MII;
1028  if (MI->isBundle()) {
1029  BundleMI = MI;
1030  continue;
1031  }
1032  if (MI->isDebugValue())
1033  continue;
1034 
1035  LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
1036 
1037  // Does NextMII belong to the same bundle as MI?
1038  bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();
1039 
1040  if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
1041  Modified = true;
1042  MachineBasicBlock::instr_iterator I = std::prev(NextMII);
1043  MI = &*I;
1044  // Removing and reinserting the first instruction in a bundle will break
1045  // up the bundle. Fix the bundling if it was broken.
1046  if (NextInSameBundle && !NextMII->isBundledWithPred())
1047  NextMII->bundleWithPred();
1048  }
1049 
1050  if (BundleMI && !NextInSameBundle && MI->isInsideBundle()) {
1051  // FIXME: Since post-ra scheduler operates on bundles, the CPSR kill
1052  // marker is only on the BUNDLE instruction. Process the BUNDLE
1053  // instruction as we finish with the bundled instruction to work around
1054  // the inconsistency.
1055  if (BundleMI->killsRegister(ARM::CPSR))
1056  LiveCPSR = false;
1057  MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
1058  if (MO && !MO->isDead())
1059  LiveCPSR = true;
1060  MO = BundleMI->findRegisterUseOperand(ARM::CPSR);
1061  if (MO && !MO->isKill())
1062  LiveCPSR = true;
1063  }
1064 
1065  bool DefCPSR = false;
1066  LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
1067  if (MI->isCall()) {
1068  // Calls don't really set CPSR.
1069  CPSRDef = nullptr;
1070  HighLatencyCPSR = false;
1071  IsSelfLoop = false;
1072  } else if (DefCPSR) {
1073  // This is the last CPSR defining instruction.
1074  CPSRDef = MI;
1075  HighLatencyCPSR = isHighLatencyCPSR(CPSRDef);
1076  IsSelfLoop = false;
1077  }
1078  }
1079 
1080  MBBInfo &Info = BlockInfo[MBB.getNumber()];
1081  Info.HighLatencyCPSR = HighLatencyCPSR;
1082  Info.Visited = true;
1083  return Modified;
1084 }
1085 
1086 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
1087  if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
1088  return false;
1089 
1090  STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1091  if (STI->isThumb1Only() || STI->prefers32BitThumb())
1092  return false;
1093 
1094  TII = static_cast<const Thumb2InstrInfo *>(STI->getInstrInfo());
1095 
1096  // Optimizing / minimizing size? Minimizing size implies optimizing for size.
1097  OptimizeSize = MF.getFunction()->optForSize();
1098  MinimizeSize = MF.getFunction()->optForMinSize();
1099 
1100  BlockInfo.clear();
1101  BlockInfo.resize(MF.getNumBlockIDs());
1102 
1103  // Visit blocks in reverse post-order so LastCPSRDef is known for all
1104  // predecessors.
1106  bool Modified = false;
1108  I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
1109  Modified |= ReduceMBB(**I);
1110  return Modified;
1111 }
1112 
1113 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
1114 /// reduction pass.
1116  std::function<bool(const Function &)> Ftor) {
1117  return new Thumb2SizeReduce(std::move(Ftor));
1118 }
static bool VerifyLowRegs(MachineInstr *MI)
const MachineInstrBuilder & add(const MachineOperand &MO) const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
instr_iterator instr_begin()
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:579
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:989
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:578
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:649
unsigned getInternalReadRegState(bool B)
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
bool isThumb1Only() const
Definition: ARMSubtarget.h:673
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:581
static cl::opt< int > ReduceLimit2Addr("t2-reduce-limit2", cl::init(-1), cl::Hidden)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isInternalRead() const
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:455
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Definition: BitVector.h:920
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool isBundle() const
Definition: MachineInstr.h:853
const RegList & Regs
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:235
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:238
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:175
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:404
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:530
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
iterator_range< pred_iterator > predecessors()
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
Iterator for intrusive lists based on ilist_node.
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static cl::opt< int > ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:674
static cl::opt< int > ReduceLimitLdSt("t2-reduce-limit3", cl::init(-1), cl::Hidden)
int64_t getImm() const
static bool HasImplicitCPSRDef(const MCInstrDesc &MCID)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
static bool isHighLatencyCPSR(MachineInstr *Def)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR)
MachineFunctionProperties & set(Property P)
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:147
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:948
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:527
typename std::vector< NodeRef >::reverse_iterator rpo_iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
#define DEBUG(X)
Definition: Debug.h:118
print Print MemDeps of function
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr&#39;s memory reference descriptor list.
Properties which a MachineFunction may have at a given point in time.
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:390
bool isImplicit() const
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65