LLVM  7.0.0svn
Thumb2SizeReduction.cpp
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1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARM.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMSubtarget.h"
14 #include "Thumb2InstrInfo.h"
15 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/StringRef.h"
29 #include "llvm/IR/DebugLoc.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
38 #include <algorithm>
39 #include <cassert>
40 #include <cstdint>
41 #include <functional>
42 #include <iterator>
43 #include <utility>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "t2-reduce-size"
48 #define THUMB2_SIZE_REDUCE_NAME "Thumb2 instruction size reduce pass"
49 
50 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
51 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
52 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
53 
54 static cl::opt<int> ReduceLimit("t2-reduce-limit",
55  cl::init(-1), cl::Hidden);
56 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
57  cl::init(-1), cl::Hidden);
58 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
59  cl::init(-1), cl::Hidden);
60 
61 namespace {
62 
63  /// ReduceTable - A static table with information on mapping from wide
64  /// opcodes to narrow
65  struct ReduceEntry {
66  uint16_t WideOpc; // Wide opcode
67  uint16_t NarrowOpc1; // Narrow opcode to transform to
68  uint16_t NarrowOpc2; // Narrow opcode when it's two-address
69  uint8_t Imm1Limit; // Limit of immediate field (bits)
70  uint8_t Imm2Limit; // Limit of immediate field when it's two-address
71  unsigned LowRegs1 : 1; // Only possible if low-registers are used
72  unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
73  unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
74  // 1 - No cc field.
75  // 2 - Always set CPSR.
76  unsigned PredCC2 : 2;
77  unsigned PartFlag : 1; // 16-bit instruction does partial flag update
78  unsigned Special : 1; // Needs to be dealt with specially
79  unsigned AvoidMovs: 1; // Avoid movs with shifter operand (for Swift)
80  };
81 
82  static const ReduceEntry ReduceTable[] = {
83  // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
84  { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
85  { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86  { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87  { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
88  { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
89  { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
90  { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
91  { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
92  { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
93  //FIXME: Disable CMN, as CCodes are backwards from compare expectations
94  //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
95  { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
96  { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
97  { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
98  { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
99  // FIXME: adr.n immediate offset must be multiple of 4.
100  //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
101  { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
102  { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
103  { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
104  { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
105  { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
106  { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
107  // FIXME: Do we need the 16-bit 'S' variant?
108  { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
109  { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
110  { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
111  { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
112  { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
113  { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
114  { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
115  { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
116  { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117  { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
118  { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
119  { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
120  { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
121  { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
122  { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
123  { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
124  { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
125  { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
126  { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
127  { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
128 
129  // FIXME: Clean this up after splitting each Thumb load / store opcode
130  // into multiple ones.
131  { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
132  { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
133  { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
134  { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
135  { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
136  { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
137  { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
138  { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
139  { ARM::t2LDR_POST,ARM::tLDMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
140  { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
141  { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
142  { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
143  { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
144  { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
145  { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
146  { ARM::t2STR_POST,ARM::tSTMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
147 
148  { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
149  { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
150  { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
151  // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
152  // tSTMIA_UPD is a change in semantics which can only be used if the base
153  // register is killed. This difference is correctly handled elsewhere.
154  { ARM::t2STMIA, ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
155  { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
156  { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
157  };
158 
159  class Thumb2SizeReduce : public MachineFunctionPass {
160  public:
161  static char ID;
162 
163  const Thumb2InstrInfo *TII;
164  const ARMSubtarget *STI;
165 
166  Thumb2SizeReduce(std::function<bool(const Function &)> Ftor = nullptr);
167 
168  bool runOnMachineFunction(MachineFunction &MF) override;
169 
170  MachineFunctionProperties getRequiredProperties() const override {
173  }
174 
175  StringRef getPassName() const override {
177  }
178 
179  private:
180  /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
181  DenseMap<unsigned, unsigned> ReduceOpcodeMap;
182 
183  bool canAddPseudoFlagDep(MachineInstr *Use, bool IsSelfLoop);
184 
185  bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
186  bool is2Addr, ARMCC::CondCodes Pred,
187  bool LiveCPSR, bool &HasCC, bool &CCDead);
188 
189  bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
190  const ReduceEntry &Entry);
191 
192  bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
193  const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
194 
195  /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
196  /// instruction.
197  bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
198  const ReduceEntry &Entry, bool LiveCPSR,
199  bool IsSelfLoop);
200 
201  /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
202  /// non-two-address instruction.
203  bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
204  const ReduceEntry &Entry, bool LiveCPSR,
205  bool IsSelfLoop);
206 
207  /// ReduceMI - Attempt to reduce MI, return true on success.
208  bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
209  bool LiveCPSR, bool IsSelfLoop);
210 
211  /// ReduceMBB - Reduce width of instructions in the specified basic block.
212  bool ReduceMBB(MachineBasicBlock &MBB);
213 
214  bool OptimizeSize;
215  bool MinimizeSize;
216 
217  // Last instruction to define CPSR in the current block.
218  MachineInstr *CPSRDef;
219  // Was CPSR last defined by a high latency instruction?
220  // When CPSRDef is null, this refers to CPSR defs in predecessors.
221  bool HighLatencyCPSR;
222 
223  struct MBBInfo {
224  // The flags leaving this block have high latency.
225  bool HighLatencyCPSR = false;
226  // Has this block been visited yet?
227  bool Visited = false;
228 
229  MBBInfo() = default;
230  };
231 
232  SmallVector<MBBInfo, 8> BlockInfo;
233 
234  std::function<bool(const Function &)> PredicateFtor;
235  };
236 
237  char Thumb2SizeReduce::ID = 0;
238 
239 } // end anonymous namespace
240 
242  false)
243 
244 Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
245  : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
246  OptimizeSize = MinimizeSize = false;
247  for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
248  unsigned FromOpc = ReduceTable[i].WideOpc;
249  if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
250  llvm_unreachable("Duplicated entries?");
251  }
252 }
253 
254 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
255  for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
256  if (*Regs == ARM::CPSR)
257  return true;
258  return false;
259 }
260 
261 // Check for a likely high-latency flag def.
263  switch(Def->getOpcode()) {
264  case ARM::FMSTAT:
265  case ARM::tMUL:
266  return true;
267  }
268  return false;
269 }
270 
271 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
272 /// the 's' 16-bit instruction partially update CPSR. Abort the
273 /// transformation to avoid adding false dependency on last CPSR setting
274 /// instruction which hurts the ability for out-of-order execution engine
275 /// to do register renaming magic.
276 /// This function checks if there is a read-of-write dependency between the
277 /// last instruction that defines the CPSR and the current instruction. If there
278 /// is, then there is no harm done since the instruction cannot be retired
279 /// before the CPSR setting instruction anyway.
280 /// Note, we are not doing full dependency analysis here for the sake of compile
281 /// time. We're not looking for cases like:
282 /// r0 = muls ...
283 /// r1 = add.w r0, ...
284 /// ...
285 /// = mul.w r1
286 /// In this case it would have been ok to narrow the mul.w to muls since there
287 /// are indirect RAW dependency between the muls and the mul.w
288 bool
289 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
290  // Disable the check for -Oz (aka OptimizeForSizeHarder).
291  if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
292  return false;
293 
294  if (!CPSRDef)
295  // If this BB loops back to itself, conservatively avoid narrowing the
296  // first instruction that does partial flag update.
297  return HighLatencyCPSR || FirstInSelfLoop;
298 
300  for (const MachineOperand &MO : CPSRDef->operands()) {
301  if (!MO.isReg() || MO.isUndef() || MO.isUse())
302  continue;
303  unsigned Reg = MO.getReg();
304  if (Reg == 0 || Reg == ARM::CPSR)
305  continue;
306  Defs.insert(Reg);
307  }
308 
309  for (const MachineOperand &MO : Use->operands()) {
310  if (!MO.isReg() || MO.isUndef() || MO.isDef())
311  continue;
312  unsigned Reg = MO.getReg();
313  if (Defs.count(Reg))
314  return false;
315  }
316 
317  // If the current CPSR has high latency, try to avoid the false dependency.
318  if (HighLatencyCPSR)
319  return true;
320 
321  // tMOVi8 usually doesn't start long dependency chains, and there are a lot
322  // of them, so always shrink them when CPSR doesn't have high latency.
323  if (Use->getOpcode() == ARM::t2MOVi ||
324  Use->getOpcode() == ARM::t2MOVi16)
325  return false;
326 
327  // No read-after-write dependency. The narrowing will add false dependency.
328  return true;
329 }
330 
331 bool
332 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
333  bool is2Addr, ARMCC::CondCodes Pred,
334  bool LiveCPSR, bool &HasCC, bool &CCDead) {
335  if ((is2Addr && Entry.PredCC2 == 0) ||
336  (!is2Addr && Entry.PredCC1 == 0)) {
337  if (Pred == ARMCC::AL) {
338  // Not predicated, must set CPSR.
339  if (!HasCC) {
340  // Original instruction was not setting CPSR, but CPSR is not
341  // currently live anyway. It's ok to set it. The CPSR def is
342  // dead though.
343  if (!LiveCPSR) {
344  HasCC = true;
345  CCDead = true;
346  return true;
347  }
348  return false;
349  }
350  } else {
351  // Predicated, must not set CPSR.
352  if (HasCC)
353  return false;
354  }
355  } else if ((is2Addr && Entry.PredCC2 == 2) ||
356  (!is2Addr && Entry.PredCC1 == 2)) {
357  /// Old opcode has an optional def of CPSR.
358  if (HasCC)
359  return true;
360  // If old opcode does not implicitly define CPSR, then it's not ok since
361  // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
362  if (!HasImplicitCPSRDef(MI->getDesc()))
363  return false;
364  HasCC = true;
365  } else {
366  // 16-bit instruction does not set CPSR.
367  if (HasCC)
368  return false;
369  }
370 
371  return true;
372 }
373 
374 static bool VerifyLowRegs(MachineInstr *MI) {
375  unsigned Opc = MI->getOpcode();
376  bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD);
377  bool isLROk = (Opc == ARM::t2STMDB_UPD);
378  bool isSPOk = isPCOk || isLROk;
379  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
380  const MachineOperand &MO = MI->getOperand(i);
381  if (!MO.isReg() || MO.isImplicit())
382  continue;
383  unsigned Reg = MO.getReg();
384  if (Reg == 0 || Reg == ARM::CPSR)
385  continue;
386  if (isPCOk && Reg == ARM::PC)
387  continue;
388  if (isLROk && Reg == ARM::LR)
389  continue;
390  if (Reg == ARM::SP) {
391  if (isSPOk)
392  continue;
393  if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
394  // Special case for these ldr / str with sp as base register.
395  continue;
396  }
397  if (!isARMLowRegister(Reg))
398  return false;
399  }
400  return true;
401 }
402 
403 bool
404 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
405  const ReduceEntry &Entry) {
406  if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
407  return false;
408 
409  unsigned Scale = 1;
410  bool HasImmOffset = false;
411  bool HasShift = false;
412  bool HasOffReg = true;
413  bool isLdStMul = false;
414  unsigned Opc = Entry.NarrowOpc1;
415  unsigned OpNum = 3; // First 'rest' of operands.
416  uint8_t ImmLimit = Entry.Imm1Limit;
417 
418  switch (Entry.WideOpc) {
419  default:
420  llvm_unreachable("Unexpected Thumb2 load / store opcode!");
421  case ARM::t2LDRi12:
422  case ARM::t2STRi12:
423  if (MI->getOperand(1).getReg() == ARM::SP) {
424  Opc = Entry.NarrowOpc2;
425  ImmLimit = Entry.Imm2Limit;
426  }
427 
428  Scale = 4;
429  HasImmOffset = true;
430  HasOffReg = false;
431  break;
432  case ARM::t2LDRBi12:
433  case ARM::t2STRBi12:
434  HasImmOffset = true;
435  HasOffReg = false;
436  break;
437  case ARM::t2LDRHi12:
438  case ARM::t2STRHi12:
439  Scale = 2;
440  HasImmOffset = true;
441  HasOffReg = false;
442  break;
443  case ARM::t2LDRs:
444  case ARM::t2LDRBs:
445  case ARM::t2LDRHs:
446  case ARM::t2LDRSBs:
447  case ARM::t2LDRSHs:
448  case ARM::t2STRs:
449  case ARM::t2STRBs:
450  case ARM::t2STRHs:
451  HasShift = true;
452  OpNum = 4;
453  break;
454  case ARM::t2LDR_POST:
455  case ARM::t2STR_POST: {
456  if (!MBB.getParent()->getFunction().optForMinSize())
457  return false;
458 
459  if (!MI->hasOneMemOperand() ||
460  (*MI->memoperands_begin())->getAlignment() < 4)
461  return false;
462 
463  // We're creating a completely different type of load/store - LDM from LDR.
464  // For this reason we can't reuse the logic at the end of this function; we
465  // have to implement the MI building here.
466  bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
467  unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
468  unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
469  unsigned Offset = MI->getOperand(3).getImm();
470  unsigned PredImm = MI->getOperand(4).getImm();
471  unsigned PredReg = MI->getOperand(5).getReg();
474 
475  if (Offset != 4)
476  return false;
477 
478  // Add the 16-bit load / store instruction.
479  DebugLoc dl = MI->getDebugLoc();
480  auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
481  .addReg(Rn, RegState::Define)
482  .addReg(Rn)
483  .addImm(PredImm)
484  .addReg(PredReg)
485  .addReg(Rt, IsStore ? 0 : RegState::Define);
486 
487  // Transfer memoperands.
488  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
489 
490  // Transfer MI flags.
491  MIB.setMIFlags(MI->getFlags());
492 
493  // Kill the old instruction.
494  MI->eraseFromBundle();
495  ++NumLdSts;
496  return true;
497  }
498  case ARM::t2LDMIA: {
499  unsigned BaseReg = MI->getOperand(0).getReg();
500  assert(isARMLowRegister(BaseReg));
501 
502  // For the non-writeback version (this one), the base register must be
503  // one of the registers being loaded.
504  bool isOK = false;
505  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
506  if (MI->getOperand(i).getReg() == BaseReg) {
507  isOK = true;
508  break;
509  }
510  }
511 
512  if (!isOK)
513  return false;
514 
515  OpNum = 0;
516  isLdStMul = true;
517  break;
518  }
519  case ARM::t2STMIA:
520  // If the base register is killed, we don't care what its value is after the
521  // instruction, so we can use an updating STMIA.
522  if (!MI->getOperand(0).isKill())
523  return false;
524 
525  break;
526  case ARM::t2LDMIA_RET: {
527  unsigned BaseReg = MI->getOperand(1).getReg();
528  if (BaseReg != ARM::SP)
529  return false;
530  Opc = Entry.NarrowOpc2; // tPOP_RET
531  OpNum = 2;
532  isLdStMul = true;
533  break;
534  }
535  case ARM::t2LDMIA_UPD:
536  case ARM::t2STMIA_UPD:
537  case ARM::t2STMDB_UPD: {
538  OpNum = 0;
539 
540  unsigned BaseReg = MI->getOperand(1).getReg();
541  if (BaseReg == ARM::SP &&
542  (Entry.WideOpc == ARM::t2LDMIA_UPD ||
543  Entry.WideOpc == ARM::t2STMDB_UPD)) {
544  Opc = Entry.NarrowOpc2; // tPOP or tPUSH
545  OpNum = 2;
546  } else if (!isARMLowRegister(BaseReg) ||
547  (Entry.WideOpc != ARM::t2LDMIA_UPD &&
548  Entry.WideOpc != ARM::t2STMIA_UPD)) {
549  return false;
550  }
551 
552  isLdStMul = true;
553  break;
554  }
555  }
556 
557  unsigned OffsetReg = 0;
558  bool OffsetKill = false;
559  bool OffsetInternal = false;
560  if (HasShift) {
561  OffsetReg = MI->getOperand(2).getReg();
562  OffsetKill = MI->getOperand(2).isKill();
563  OffsetInternal = MI->getOperand(2).isInternalRead();
564 
565  if (MI->getOperand(3).getImm())
566  // Thumb1 addressing mode doesn't support shift.
567  return false;
568  }
569 
570  unsigned OffsetImm = 0;
571  if (HasImmOffset) {
572  OffsetImm = MI->getOperand(2).getImm();
573  unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
574 
575  if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
576  // Make sure the immediate field fits.
577  return false;
578  }
579 
580  // Add the 16-bit load / store instruction.
581  DebugLoc dl = MI->getDebugLoc();
582  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
583 
584  // tSTMIA_UPD takes a defining register operand. We've already checked that
585  // the register is killed, so mark it as dead here.
586  if (Entry.WideOpc == ARM::t2STMIA)
588 
589  if (!isLdStMul) {
590  MIB.add(MI->getOperand(0));
591  MIB.add(MI->getOperand(1));
592 
593  if (HasImmOffset)
594  MIB.addImm(OffsetImm / Scale);
595 
596  assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
597 
598  if (HasOffReg)
599  MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
600  getInternalReadRegState(OffsetInternal));
601  }
602 
603  // Transfer the rest of operands.
604  for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
605  MIB.add(MI->getOperand(OpNum));
606 
607  // Transfer memoperands.
608  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
609 
610  // Transfer MI flags.
611  MIB.setMIFlags(MI->getFlags());
612 
613  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
614 
615  MBB.erase_instr(MI);
616  ++NumLdSts;
617  return true;
618 }
619 
620 bool
621 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
622  const ReduceEntry &Entry,
623  bool LiveCPSR, bool IsSelfLoop) {
624  unsigned Opc = MI->getOpcode();
625  if (Opc == ARM::t2ADDri) {
626  // If the source register is SP, try to reduce to tADDrSPi, otherwise
627  // it's a normal reduce.
628  if (MI->getOperand(1).getReg() != ARM::SP) {
629  if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
630  return true;
631  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
632  }
633  // Try to reduce to tADDrSPi.
634  unsigned Imm = MI->getOperand(2).getImm();
635  // The immediate must be in range, the destination register must be a low
636  // reg, the predicate must be "always" and the condition flags must not
637  // be being set.
638  if (Imm & 3 || Imm > 1020)
639  return false;
640  if (!isARMLowRegister(MI->getOperand(0).getReg()))
641  return false;
642  if (MI->getOperand(3).getImm() != ARMCC::AL)
643  return false;
644  const MCInstrDesc &MCID = MI->getDesc();
645  if (MCID.hasOptionalDef() &&
646  MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
647  return false;
648 
649  MachineInstrBuilder MIB =
650  BuildMI(MBB, MI, MI->getDebugLoc(),
651  TII->get(ARM::tADDrSPi))
652  .add(MI->getOperand(0))
653  .add(MI->getOperand(1))
654  .addImm(Imm / 4) // The tADDrSPi has an implied scale by four.
655  .add(predOps(ARMCC::AL));
656 
657  // Transfer MI flags.
658  MIB.setMIFlags(MI->getFlags());
659 
660  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
661 
662  MBB.erase_instr(MI);
663  ++NumNarrows;
664  return true;
665  }
666 
667  if (Entry.LowRegs1 && !VerifyLowRegs(MI))
668  return false;
669 
670  if (MI->mayLoadOrStore())
671  return ReduceLoadStore(MBB, MI, Entry);
672 
673  switch (Opc) {
674  default: break;
675  case ARM::t2ADDSri:
676  case ARM::t2ADDSrr: {
677  unsigned PredReg = 0;
678  if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
679  switch (Opc) {
680  default: break;
681  case ARM::t2ADDSri:
682  if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
683  return true;
685  case ARM::t2ADDSrr:
686  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
687  }
688  }
689  break;
690  }
691  case ARM::t2RSBri:
692  case ARM::t2RSBSri:
693  case ARM::t2SXTB:
694  case ARM::t2SXTH:
695  case ARM::t2UXTB:
696  case ARM::t2UXTH:
697  if (MI->getOperand(2).getImm() == 0)
698  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
699  break;
700  case ARM::t2MOVi16:
701  // Can convert only 'pure' immediate operands, not immediates obtained as
702  // globals' addresses.
703  if (MI->getOperand(1).isImm())
704  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
705  break;
706  case ARM::t2CMPrr: {
707  // Try to reduce to the lo-reg only version first. Why there are two
708  // versions of the instruction is a mystery.
709  // It would be nice to just have two entries in the master table that
710  // are prioritized, but the table assumes a unique entry for each
711  // source insn opcode. So for now, we hack a local entry record to use.
712  static const ReduceEntry NarrowEntry =
713  { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
714  if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
715  return true;
716  return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
717  }
718  }
719  return false;
720 }
721 
722 bool
723 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
724  const ReduceEntry &Entry,
725  bool LiveCPSR, bool IsSelfLoop) {
726  if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
727  return false;
728 
729  if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
730  // Don't issue movs with shifter operand for some CPUs unless we
731  // are optimizing for size.
732  return false;
733 
734  unsigned Reg0 = MI->getOperand(0).getReg();
735  unsigned Reg1 = MI->getOperand(1).getReg();
736  // t2MUL is "special". The tied source operand is second, not first.
737  if (MI->getOpcode() == ARM::t2MUL) {
738  unsigned Reg2 = MI->getOperand(2).getReg();
739  // Early exit if the regs aren't all low regs.
740  if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
741  || !isARMLowRegister(Reg2))
742  return false;
743  if (Reg0 != Reg2) {
744  // If the other operand also isn't the same as the destination, we
745  // can't reduce.
746  if (Reg1 != Reg0)
747  return false;
748  // Try to commute the operands to make it a 2-address instruction.
749  MachineInstr *CommutedMI = TII->commuteInstruction(*MI);
750  if (!CommutedMI)
751  return false;
752  }
753  } else if (Reg0 != Reg1) {
754  // Try to commute the operands to make it a 2-address instruction.
755  unsigned CommOpIdx1 = 1;
756  unsigned CommOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
757  if (!TII->findCommutedOpIndices(*MI, CommOpIdx1, CommOpIdx2) ||
758  MI->getOperand(CommOpIdx2).getReg() != Reg0)
759  return false;
760  MachineInstr *CommutedMI =
761  TII->commuteInstruction(*MI, false, CommOpIdx1, CommOpIdx2);
762  if (!CommutedMI)
763  return false;
764  }
765  if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
766  return false;
767  if (Entry.Imm2Limit) {
768  unsigned Imm = MI->getOperand(2).getImm();
769  unsigned Limit = (1 << Entry.Imm2Limit) - 1;
770  if (Imm > Limit)
771  return false;
772  } else {
773  unsigned Reg2 = MI->getOperand(2).getReg();
774  if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
775  return false;
776  }
777 
778  // Check if it's possible / necessary to transfer the predicate.
779  const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
780  unsigned PredReg = 0;
781  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
782  bool SkipPred = false;
783  if (Pred != ARMCC::AL) {
784  if (!NewMCID.isPredicable())
785  // Can't transfer predicate, fail.
786  return false;
787  } else {
788  SkipPred = !NewMCID.isPredicable();
789  }
790 
791  bool HasCC = false;
792  bool CCDead = false;
793  const MCInstrDesc &MCID = MI->getDesc();
794  if (MCID.hasOptionalDef()) {
795  unsigned NumOps = MCID.getNumOperands();
796  HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
797  if (HasCC && MI->getOperand(NumOps-1).isDead())
798  CCDead = true;
799  }
800  if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
801  return false;
802 
803  // Avoid adding a false dependency on partial flag update by some 16-bit
804  // instructions which has the 's' bit set.
805  if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
806  canAddPseudoFlagDep(MI, IsSelfLoop))
807  return false;
808 
809  // Add the 16-bit instruction.
810  DebugLoc dl = MI->getDebugLoc();
811  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
812  MIB.add(MI->getOperand(0));
813  if (NewMCID.hasOptionalDef())
814  MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
815 
816  // Transfer the rest of operands.
817  unsigned NumOps = MCID.getNumOperands();
818  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
819  if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
820  continue;
821  if (SkipPred && MCID.OpInfo[i].isPredicate())
822  continue;
823  MIB.add(MI->getOperand(i));
824  }
825 
826  // Transfer MI flags.
827  MIB.setMIFlags(MI->getFlags());
828 
829  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
830 
831  MBB.erase_instr(MI);
832  ++Num2Addrs;
833  return true;
834 }
835 
836 bool
837 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
838  const ReduceEntry &Entry,
839  bool LiveCPSR, bool IsSelfLoop) {
840  if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
841  return false;
842 
843  if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
844  // Don't issue movs with shifter operand for some CPUs unless we
845  // are optimizing for size.
846  return false;
847 
848  unsigned Limit = ~0U;
849  if (Entry.Imm1Limit)
850  Limit = (1 << Entry.Imm1Limit) - 1;
851 
852  const MCInstrDesc &MCID = MI->getDesc();
853  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
854  if (MCID.OpInfo[i].isPredicate())
855  continue;
856  const MachineOperand &MO = MI->getOperand(i);
857  if (MO.isReg()) {
858  unsigned Reg = MO.getReg();
859  if (!Reg || Reg == ARM::CPSR)
860  continue;
861  if (Entry.LowRegs1 && !isARMLowRegister(Reg))
862  return false;
863  } else if (MO.isImm() &&
864  !MCID.OpInfo[i].isPredicate()) {
865  if (((unsigned)MO.getImm()) > Limit)
866  return false;
867  }
868  }
869 
870  // Check if it's possible / necessary to transfer the predicate.
871  const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
872  unsigned PredReg = 0;
873  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
874  bool SkipPred = false;
875  if (Pred != ARMCC::AL) {
876  if (!NewMCID.isPredicable())
877  // Can't transfer predicate, fail.
878  return false;
879  } else {
880  SkipPred = !NewMCID.isPredicable();
881  }
882 
883  bool HasCC = false;
884  bool CCDead = false;
885  if (MCID.hasOptionalDef()) {
886  unsigned NumOps = MCID.getNumOperands();
887  HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
888  if (HasCC && MI->getOperand(NumOps-1).isDead())
889  CCDead = true;
890  }
891  if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
892  return false;
893 
894  // Avoid adding a false dependency on partial flag update by some 16-bit
895  // instructions which has the 's' bit set.
896  if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
897  canAddPseudoFlagDep(MI, IsSelfLoop))
898  return false;
899 
900  // Add the 16-bit instruction.
901  DebugLoc dl = MI->getDebugLoc();
902  MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
903  MIB.add(MI->getOperand(0));
904  if (NewMCID.hasOptionalDef())
905  MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
906 
907  // Transfer the rest of operands.
908  unsigned NumOps = MCID.getNumOperands();
909  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
910  if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
911  continue;
912  if ((MCID.getOpcode() == ARM::t2RSBSri ||
913  MCID.getOpcode() == ARM::t2RSBri ||
914  MCID.getOpcode() == ARM::t2SXTB ||
915  MCID.getOpcode() == ARM::t2SXTH ||
916  MCID.getOpcode() == ARM::t2UXTB ||
917  MCID.getOpcode() == ARM::t2UXTH) && i == 2)
918  // Skip the zero immediate operand, it's now implicit.
919  continue;
920  bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
921  if (SkipPred && isPred)
922  continue;
923  const MachineOperand &MO = MI->getOperand(i);
924  if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
925  // Skip implicit def of CPSR. Either it's modeled as an optional
926  // def now or it's already an implicit def on the new instruction.
927  continue;
928  MIB.add(MO);
929  }
930  if (!MCID.isPredicable() && NewMCID.isPredicable())
931  MIB.add(predOps(ARMCC::AL));
932 
933  // Transfer MI flags.
934  MIB.setMIFlags(MI->getFlags());
935 
936  DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
937 
938  MBB.erase_instr(MI);
939  ++NumNarrows;
940  return true;
941 }
942 
943 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
944  bool HasDef = false;
945  for (const MachineOperand &MO : MI.operands()) {
946  if (!MO.isReg() || MO.isUndef() || MO.isUse())
947  continue;
948  if (MO.getReg() != ARM::CPSR)
949  continue;
950 
951  DefCPSR = true;
952  if (!MO.isDead())
953  HasDef = true;
954  }
955 
956  return HasDef || LiveCPSR;
957 }
958 
959 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
960  for (const MachineOperand &MO : MI.operands()) {
961  if (!MO.isReg() || MO.isUndef() || MO.isDef())
962  continue;
963  if (MO.getReg() != ARM::CPSR)
964  continue;
965  assert(LiveCPSR && "CPSR liveness tracking is wrong!");
966  if (MO.isKill()) {
967  LiveCPSR = false;
968  break;
969  }
970  }
971 
972  return LiveCPSR;
973 }
974 
975 bool Thumb2SizeReduce::ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
976  bool LiveCPSR, bool IsSelfLoop) {
977  unsigned Opcode = MI->getOpcode();
978  DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
979  if (OPI == ReduceOpcodeMap.end())
980  return false;
981  const ReduceEntry &Entry = ReduceTable[OPI->second];
982 
983  // Don't attempt normal reductions on "special" cases for now.
984  if (Entry.Special)
985  return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
986 
987  // Try to transform to a 16-bit two-address instruction.
988  if (Entry.NarrowOpc2 &&
989  ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
990  return true;
991 
992  // Try to transform to a 16-bit non-two-address instruction.
993  if (Entry.NarrowOpc1 &&
994  ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
995  return true;
996 
997  return false;
998 }
999 
1000 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
1001  bool Modified = false;
1002 
1003  // Yes, CPSR could be livein.
1004  bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
1005  MachineInstr *BundleMI = nullptr;
1006 
1007  CPSRDef = nullptr;
1008  HighLatencyCPSR = false;
1009 
1010  // Check predecessors for the latest CPSRDef.
1011  for (auto *Pred : MBB.predecessors()) {
1012  const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
1013  if (!PInfo.Visited) {
1014  // Since blocks are visited in RPO, this must be a back-edge.
1015  continue;
1016  }
1017  if (PInfo.HighLatencyCPSR) {
1018  HighLatencyCPSR = true;
1019  break;
1020  }
1021  }
1022 
1023  // If this BB loops back to itself, conservatively avoid narrowing the
1024  // first instruction that does partial flag update.
1025  bool IsSelfLoop = MBB.isSuccessor(&MBB);
1028  for (; MII != E; MII = NextMII) {
1029  NextMII = std::next(MII);
1030 
1031  MachineInstr *MI = &*MII;
1032  if (MI->isBundle()) {
1033  BundleMI = MI;
1034  continue;
1035  }
1036  if (MI->isDebugValue())
1037  continue;
1038 
1039  LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
1040 
1041  // Does NextMII belong to the same bundle as MI?
1042  bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();
1043 
1044  if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
1045  Modified = true;
1046  MachineBasicBlock::instr_iterator I = std::prev(NextMII);
1047  MI = &*I;
1048  // Removing and reinserting the first instruction in a bundle will break
1049  // up the bundle. Fix the bundling if it was broken.
1050  if (NextInSameBundle && !NextMII->isBundledWithPred())
1051  NextMII->bundleWithPred();
1052  }
1053 
1054  if (BundleMI && !NextInSameBundle && MI->isInsideBundle()) {
1055  // FIXME: Since post-ra scheduler operates on bundles, the CPSR kill
1056  // marker is only on the BUNDLE instruction. Process the BUNDLE
1057  // instruction as we finish with the bundled instruction to work around
1058  // the inconsistency.
1059  if (BundleMI->killsRegister(ARM::CPSR))
1060  LiveCPSR = false;
1061  MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
1062  if (MO && !MO->isDead())
1063  LiveCPSR = true;
1064  MO = BundleMI->findRegisterUseOperand(ARM::CPSR);
1065  if (MO && !MO->isKill())
1066  LiveCPSR = true;
1067  }
1068 
1069  bool DefCPSR = false;
1070  LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
1071  if (MI->isCall()) {
1072  // Calls don't really set CPSR.
1073  CPSRDef = nullptr;
1074  HighLatencyCPSR = false;
1075  IsSelfLoop = false;
1076  } else if (DefCPSR) {
1077  // This is the last CPSR defining instruction.
1078  CPSRDef = MI;
1079  HighLatencyCPSR = isHighLatencyCPSR(CPSRDef);
1080  IsSelfLoop = false;
1081  }
1082  }
1083 
1084  MBBInfo &Info = BlockInfo[MBB.getNumber()];
1085  Info.HighLatencyCPSR = HighLatencyCPSR;
1086  Info.Visited = true;
1087  return Modified;
1088 }
1089 
1090 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
1091  if (PredicateFtor && !PredicateFtor(MF.getFunction()))
1092  return false;
1093 
1094  STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1095  if (STI->isThumb1Only() || STI->prefers32BitThumb())
1096  return false;
1097 
1098  TII = static_cast<const Thumb2InstrInfo *>(STI->getInstrInfo());
1099 
1100  // Optimizing / minimizing size? Minimizing size implies optimizing for size.
1101  OptimizeSize = MF.getFunction().optForSize();
1102  MinimizeSize = MF.getFunction().optForMinSize();
1103 
1104  BlockInfo.clear();
1105  BlockInfo.resize(MF.getNumBlockIDs());
1106 
1107  // Visit blocks in reverse post-order so LastCPSRDef is known for all
1108  // predecessors.
1110  bool Modified = false;
1112  I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
1113  Modified |= ReduceMBB(**I);
1114  return Modified;
1115 }
1116 
1117 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
1118 /// reduction pass.
1120  std::function<bool(const Function &)> Ftor) {
1121  return new Thumb2SizeReduce(std::move(Ftor));
1122 }
static bool VerifyLowRegs(MachineInstr *MI)
const MachineInstrBuilder & add(const MachineOperand &MO) const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
instr_iterator instr_begin()
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:461
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:584
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID&#39;s allocated.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:994
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:583
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:652
unsigned getInternalReadRegState(bool B)
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
bool isThumb1Only() const
Definition: ARMSubtarget.h:678
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:586
static cl::opt< int > ReduceLimit2Addr("t2-reduce-limit2", cl::init(-1), cl::Hidden)
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isInternalRead() const
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:459
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Definition: BitVector.h:921
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
#define THUMB2_SIZE_REDUCE_NAME
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool isBundle() const
Definition: MachineInstr.h:856
const RegList & Regs
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
#define DEBUG_TYPE
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:238
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
static const unsigned CommuteAnyOperandIndex
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:534
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:238
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:178
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:407
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:579
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:301
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
iterator_range< pred_iterator > predecessors()
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
Iterator for intrusive lists based on ilist_node.
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static cl::opt< int > ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:392
bool isDebugValue() const
Definition: MachineInstr.h:819
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:725
static cl::opt< int > ReduceLimitLdSt("t2-reduce-limit3", cl::init(-1), cl::Hidden)
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static bool HasImplicitCPSRDef(const MCInstrDesc &MCID)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
static bool isHighLatencyCPSR(MachineInstr *Def)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR)
MachineFunctionProperties & set(Property P)
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:147
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:953
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:576
typename std::vector< NodeRef >::reverse_iterator rpo_iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
#define DEBUG(X)
Definition: Debug.h:118
print Print MemDeps of function
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
INITIALIZE_PASS(Thumb2SizeReduce, DEBUG_TYPE, THUMB2_SIZE_REDUCE_NAME, false, false) Thumb2SizeReduce
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr&#39;s memory reference descriptor list.
Properties which a MachineFunction may have at a given point in time.
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:393
bool isImplicit() const
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65