LLVM  6.0.0svn
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API of helper functions used throughout the
11 /// GlobalISel pipeline.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
17 
18 #include "llvm/ADT/StringRef.h"
19 
20 namespace llvm {
21 
22 class MachineFunction;
23 class MachineInstr;
24 class MachineOptimizationRemarkEmitter;
25 class MachineOptimizationRemarkMissed;
26 class MachineRegisterInfo;
27 class MCInstrDesc;
28 class RegisterBankInfo;
29 class TargetInstrInfo;
30 class TargetPassConfig;
31 class TargetRegisterInfo;
32 class TargetRegisterClass;
33 class Twine;
34 class ConstantFP;
35 
36 /// Try to constrain Reg to the specified register class. If this fails,
37 /// create a new virtual register in the correct class and insert a COPY before
38 /// \p InsertPt. The debug location of \p InsertPt is used for the new copy.
39 ///
40 /// \return The virtual register constrained to the right register class.
41 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
42  const TargetInstrInfo &TII,
43  const RegisterBankInfo &RBI,
44  MachineInstr &InsertPt, unsigned Reg,
45  const TargetRegisterClass &RegClass);
46 
47 /// Try to constrain Reg so that it is usable by argument OpIdx of the
48 /// provided MCInstrDesc \p II. If this fails, create a new virtual
49 /// register in the correct class and insert a COPY before \p InsertPt.
50 /// This is equivalent to constrainRegToClass() with RegClass obtained from the
51 /// MCInstrDesc. The debug location of \p InsertPt is used for the new copy.
52 ///
53 /// \return The virtual register constrained to the right register class.
54 unsigned constrainOperandRegClass(const MachineFunction &MF,
55  const TargetRegisterInfo &TRI,
56  MachineRegisterInfo &MRI,
57  const TargetInstrInfo &TII,
58  const RegisterBankInfo &RBI,
59  MachineInstr &InsertPt, const MCInstrDesc &II,
60  unsigned Reg, unsigned OpIdx);
61 
62 /// Check whether an instruction \p MI is dead: it only defines dead virtual
63 /// registers, and doesn't have other side effects.
64 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
65 
66 /// Report an ISel error as a missed optimization remark to the LLVMContext's
67 /// diagnostic stream. Set the FailedISel MachineFunction property.
68 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
69  MachineOptimizationRemarkEmitter &MORE,
70  MachineOptimizationRemarkMissed &R);
71 
72 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
73  MachineOptimizationRemarkEmitter &MORE,
74  const char *PassName, StringRef Msg,
75  const MachineInstr &MI);
76 
77 Optional<int64_t> getConstantVRegVal(unsigned VReg,
78  const MachineRegisterInfo &MRI);
79 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
80  const MachineRegisterInfo &MRI);
81 
82 } // End namespace llvm.
83 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:125
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
unsigned const MachineRegisterInfo * MRI
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:29
#define MORE()
Definition: regcomp.c:124
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:109
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:59
IRTranslator LLVM IR MI
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:80