LLVM  7.0.0svn
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API of helper functions used throughout the
11 /// GlobalISel pipeline.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
17 
18 #include "llvm/ADT/StringRef.h"
19 
20 namespace llvm {
21 
22 class MachineFunction;
23 class MachineInstr;
24 class MachineOperand;
25 class MachineOptimizationRemarkEmitter;
26 class MachineOptimizationRemarkMissed;
27 class MachineRegisterInfo;
28 class MCInstrDesc;
29 class RegisterBankInfo;
30 class TargetInstrInfo;
31 class TargetPassConfig;
32 class TargetRegisterInfo;
33 class TargetRegisterClass;
34 class Twine;
35 class ConstantFP;
36 class APFloat;
37 
38 /// Try to constrain Reg to the specified register class. If this fails,
39 /// create a new virtual register in the correct class and insert a COPY before
40 /// \p InsertPt. The debug location of \p InsertPt is used for the new copy.
41 ///
42 /// \return The virtual register constrained to the right register class.
43 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
44  const TargetInstrInfo &TII,
45  const RegisterBankInfo &RBI,
46  MachineInstr &InsertPt, unsigned Reg,
47  const TargetRegisterClass &RegClass);
48 
49 /// Try to constrain Reg so that it is usable by argument OpIdx of the
50 /// provided MCInstrDesc \p II. If this fails, create a new virtual
51 /// register in the correct class and insert a COPY before \p InsertPt.
52 /// This is equivalent to constrainRegToClass() with RegClass obtained from the
53 /// MCInstrDesc. The debug location of \p InsertPt is used for the new copy.
54 ///
55 /// \return The virtual register constrained to the right register class.
56 unsigned constrainOperandRegClass(const MachineFunction &MF,
57  const TargetRegisterInfo &TRI,
58  MachineRegisterInfo &MRI,
59  const TargetInstrInfo &TII,
60  const RegisterBankInfo &RBI,
61  MachineInstr &InsertPt, const MCInstrDesc &II,
62  const MachineOperand &RegMO, unsigned OpIdx);
63 
64 /// Mutate the newly-selected instruction \p I to constrain its (possibly
65 /// generic) virtual register operands to the instruction's register class.
66 /// This could involve inserting COPYs before (for uses) or after (for defs).
67 /// This requires the number of operands to match the instruction description.
68 /// \returns whether operand regclass constraining succeeded.
69 ///
70 // FIXME: Not all instructions have the same number of operands. We should
71 // probably expose a constrain helper per operand and let the target selector
72 // constrain individual registers, like fast-isel.
73 bool constrainSelectedInstRegOperands(MachineInstr &I,
74  const TargetInstrInfo &TII,
75  const TargetRegisterInfo &TRI,
76  const RegisterBankInfo &RBI);
77 /// Check whether an instruction \p MI is dead: it only defines dead virtual
78 /// registers, and doesn't have other side effects.
79 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
80 
81 /// Report an ISel error as a missed optimization remark to the LLVMContext's
82 /// diagnostic stream. Set the FailedISel MachineFunction property.
83 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
84  MachineOptimizationRemarkEmitter &MORE,
85  MachineOptimizationRemarkMissed &R);
86 
87 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
88  MachineOptimizationRemarkEmitter &MORE,
89  const char *PassName, StringRef Msg,
90  const MachineInstr &MI);
91 
92 Optional<int64_t> getConstantVRegVal(unsigned VReg,
93  const MachineRegisterInfo &MRI);
94 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
95  const MachineRegisterInfo &MRI);
96 
97 /// See if Reg is defined by an single def instruction that is
98 /// Opcode. Also try to do trivial folding if it's a COPY with
99 /// same types. Returns null otherwise.
100 MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg,
101  const MachineRegisterInfo &MRI);
102 
103 /// Returns an APFloat from Val converted to the appropriate size.
104 APFloat getAPFloatFromSize(double Val, unsigned Size);
105 } // End namespace llvm.
106 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:193
const HexagonInstrInfo * TII
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:217
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:201
ArrayRef< MachineBasicBlock * > unsigned const TargetRegisterInfo * TRI
unsigned const MachineRegisterInfo * MRI
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
#define MORE()
Definition: regcomp.c:256
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:80
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:177
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:127
ArrayRef< MachineBasicBlock * > unsigned Reg
#define I(x, y, z)
Definition: MD5.cpp:58
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:148