LLVM  9.0.0svn
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1 //- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that WebAssembly uses to lower LLVM
11 /// code into a selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
20 namespace llvm {
22 namespace WebAssemblyISD {
24 enum NodeType : unsigned {
27 #include "WebAssemblyISD.def"
29 };
31 } // end namespace WebAssemblyISD
33 class WebAssemblySubtarget;
34 class WebAssemblyTargetMachine;
37 public:
39  const WebAssemblySubtarget &STI);
41 private:
42  /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
43  /// right decision when generating code for different targets.
44  const WebAssemblySubtarget *Subtarget;
46  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
48  const TargetLibraryInfo *LibInfo) const override;
49  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
51  EmitInstrWithCustomInserter(MachineInstr &MI,
52  MachineBasicBlock *MBB) const override;
53  const char *getTargetNodeName(unsigned Opcode) const override;
54  std::pair<unsigned, const TargetRegisterClass *>
55  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
56  StringRef Constraint, MVT VT) const override;
57  bool isCheapToSpeculateCttz() const override;
58  bool isCheapToSpeculateCtlz() const override;
59  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
60  unsigned AS,
61  Instruction *I = nullptr) const override;
62  bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
63  bool *Fast) const override;
64  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
66  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
67  EVT VT) const override;
68  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
69  MachineFunction &MF,
70  unsigned Intrinsic) const override;
72  SDValue LowerCall(CallLoweringInfo &CLI,
73  SmallVectorImpl<SDValue> &InVals) const override;
74  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
75  bool isVarArg,
77  LLVMContext &Context) const override;
78  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
80  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
81  SelectionDAG &DAG) const override;
82  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
83  bool IsVarArg,
85  const SDLoc &DL, SelectionDAG &DAG,
86  SmallVectorImpl<SDValue> &InVals) const override;
88  // Custom lowering hooks.
89  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
90  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
95  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
96  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
97  SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
102  SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
104 };
106 namespace WebAssembly {
108  const TargetLibraryInfo *libInfo);
109 } // end namespace WebAssembly
111 } // end namespace llvm
113 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:886
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
Provides information about what library functions are available for the current target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.