LLVM  8.0.0svn
WebAssemblyMachineFunctionInfo.h
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1 // WebAssemblyMachineFunctionInfo.h-WebAssembly machine function info-*- C++ -*-
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file declares WebAssembly-specific per-machine-function
12 /// information.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
17 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
18 
21 
22 namespace llvm {
23 
24 /// This class is derived from MachineFunctionInfo and contains private
25 /// WebAssembly-specific information for each MachineFunction.
27  MachineFunction &MF;
28 
29  std::vector<MVT> Params;
30  std::vector<MVT> Results;
31  std::vector<MVT> Locals;
32 
33  /// A mapping from CodeGen vreg index to WebAssembly register number.
34  std::vector<unsigned> WARegs;
35 
36  /// A mapping from CodeGen vreg index to a boolean value indicating whether
37  /// the given register is considered to be "stackified", meaning it has been
38  /// determined or made to meet the stack requirements:
39  /// - single use (per path)
40  /// - single def (per path)
41  /// - defined and used in LIFO order with other stack registers
42  BitVector VRegStackified;
43 
44  // A virtual register holding the pointer to the vararg buffer for vararg
45  // functions. It is created and set in TLI::LowerFormalArguments and read by
46  // TLI::LowerVASTART
47  unsigned VarargVreg = -1U;
48 
49  // A virtual register holding the base pointer for functions that have
50  // overaligned values on the user stack.
51  unsigned BasePtrVreg = -1U;
52 
53  public:
54  explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
55  ~WebAssemblyFunctionInfo() override;
56 
57  void addParam(MVT VT) { Params.push_back(VT); }
58  const std::vector<MVT> &getParams() const { return Params; }
59 
60  void addResult(MVT VT) { Results.push_back(VT); }
61  const std::vector<MVT> &getResults() const { return Results; }
62 
63  void clearParamsAndResults() { Params.clear(); Results.clear(); }
64 
65  void setNumLocals(size_t NumLocals) { Locals.resize(NumLocals, MVT::i32); }
66  void setLocal(size_t i, MVT VT) { Locals[i] = VT; }
67  void addLocal(MVT VT) { Locals.push_back(VT); }
68  const std::vector<MVT> &getLocals() const { return Locals; }
69 
70  unsigned getVarargBufferVreg() const {
71  assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
72  return VarargVreg;
73  }
74  void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
75 
76  unsigned getBasePointerVreg() const {
77  assert(BasePtrVreg != -1U && "Base ptr vreg hasn't been set");
78  return BasePtrVreg;
79  }
80  void setBasePointerVreg(unsigned Reg) { BasePtrVreg = Reg; }
81 
82  static const unsigned UnusedReg = -1u;
83 
84  void stackifyVReg(unsigned VReg) {
85  assert(MF.getRegInfo().getUniqueVRegDef(VReg));
87  if (I >= VRegStackified.size())
88  VRegStackified.resize(I + 1);
89  VRegStackified.set(I);
90  }
91  bool isVRegStackified(unsigned VReg) const {
93  if (I >= VRegStackified.size())
94  return false;
95  return VRegStackified.test(I);
96  }
97 
98  void initWARegs();
99  void setWAReg(unsigned VReg, unsigned WAReg) {
100  assert(WAReg != UnusedReg);
102  assert(I < WARegs.size());
103  WARegs[I] = WAReg;
104  }
105  unsigned getWAReg(unsigned VReg) const {
107  assert(I < WARegs.size());
108  return WARegs[I];
109  }
110 
111  // For a given stackified WAReg, return the id number to print with push/pop.
112  static unsigned getWARegStackId(unsigned Reg) {
113  assert(Reg & INT32_MIN);
114  return Reg & INT32_MAX;
115  }
116 };
117 
118 void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
119  Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
120 
121 void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
122  SmallVectorImpl<MVT> &Params,
123  SmallVectorImpl<MVT> &Results);
124 
125 } // end namespace llvm
126 
127 #endif
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:372
BitVector & set()
Definition: BitVector.h:398
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const std::vector< MVT > & getLocals() const
unsigned Reg
bool test(unsigned Idx) const
Definition: BitVector.h:502
void setWAReg(unsigned VReg, unsigned WAReg)
F(f)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM, Type *Ty, SmallVectorImpl< MVT > &ValueVTs)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
void ComputeSignatureVTs(const Function &F, const TargetMachine &TM, SmallVectorImpl< MVT > &Params, SmallVectorImpl< MVT > &Results)
This file provides WebAssembly-specific target descriptions.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
#define I(x, y, z)
Definition: MD5.cpp:58
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:170
const std::vector< MVT > & getResults() const
unsigned getWAReg(unsigned VReg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
const std::vector< MVT > & getParams() const
static unsigned getWARegStackId(unsigned Reg)