LLVM  7.0.0svn
X86DisassemblerDecoder.cpp
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1 //===-- X86DisassemblerDecoder.cpp - Disassembler decoder -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler.
11 // It contains the implementation of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include <cstdarg> /* for va_*() */
17 #include <cstdio> /* for vsnprintf() */
18 #include <cstdlib> /* for exit() */
19 #include <cstring> /* for memset() */
20 
21 #include "X86DisassemblerDecoder.h"
22 
23 using namespace llvm::X86Disassembler;
24 
25 /// Specifies whether a ModR/M byte is needed and (if so) which
26 /// instruction each possible value of the ModR/M byte corresponds to. Once
27 /// this information is known, we have narrowed down to a single instruction.
28 struct ModRMDecision {
29  uint8_t modrm_type;
30  uint16_t instructionIDs;
31 };
32 
33 /// Specifies which set of ModR/M->instruction tables to look at
34 /// given a particular opcode.
36  ModRMDecision modRMDecisions[256];
37 };
38 
39 /// Specifies which opcode->instruction tables to look at given
40 /// a particular context (set of attributes). Since there are many possible
41 /// contexts, the decoder first uses CONTEXTS_SYM to determine which context
42 /// applies given a specific set of attributes. Hence there are only IC_max
43 /// entries in this table, rather than 2^(ATTR_max).
45  OpcodeDecision opcodeDecisions[IC_max];
46 };
47 
48 #include "X86GenDisassemblerTables.inc"
49 
50 #ifndef NDEBUG
51 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
52 #else
53 #define debug(s) do { } while (0)
54 #endif
55 
56 /*
57  * contextForAttrs - Client for the instruction context table. Takes a set of
58  * attributes and returns the appropriate decode context.
59  *
60  * @param attrMask - Attributes, from the enumeration attributeBits.
61  * @return - The InstructionContext to use when looking up an
62  * an instruction with these attributes.
63  */
64 static InstructionContext contextForAttrs(uint16_t attrMask) {
65  return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
66 }
67 
68 /*
69  * modRMRequired - Reads the appropriate instruction table to determine whether
70  * the ModR/M byte is required to decode a particular instruction.
71  *
72  * @param type - The opcode type (i.e., how many bytes it has).
73  * @param insnContext - The context for the instruction, as returned by
74  * contextForAttrs.
75  * @param opcode - The last byte of the instruction's opcode, not counting
76  * ModR/M extensions and escapes.
77  * @return - true if the ModR/M byte is required, false otherwise.
78  */
79 static int modRMRequired(OpcodeType type,
80  InstructionContext insnContext,
81  uint16_t opcode) {
82  const struct ContextDecision* decision = nullptr;
83 
84  switch (type) {
85  case ONEBYTE:
86  decision = &ONEBYTE_SYM;
87  break;
88  case TWOBYTE:
89  decision = &TWOBYTE_SYM;
90  break;
91  case THREEBYTE_38:
92  decision = &THREEBYTE38_SYM;
93  break;
94  case THREEBYTE_3A:
95  decision = &THREEBYTE3A_SYM;
96  break;
97  case XOP8_MAP:
98  decision = &XOP8_MAP_SYM;
99  break;
100  case XOP9_MAP:
101  decision = &XOP9_MAP_SYM;
102  break;
103  case XOPA_MAP:
104  decision = &XOPA_MAP_SYM;
105  break;
106  case THREEDNOW_MAP:
107  decision = &THREEDNOW_MAP_SYM;
108  break;
109  }
110 
111  return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
112  modrm_type != MODRM_ONEENTRY;
113 }
114 
115 /*
116  * decode - Reads the appropriate instruction table to obtain the unique ID of
117  * an instruction.
118  *
119  * @param type - See modRMRequired().
120  * @param insnContext - See modRMRequired().
121  * @param opcode - See modRMRequired().
122  * @param modRM - The ModR/M byte if required, or any value if not.
123  * @return - The UID of the instruction, or 0 on failure.
124  */
126  InstructionContext insnContext,
127  uint8_t opcode,
128  uint8_t modRM) {
129  const struct ModRMDecision* dec = nullptr;
130 
131  switch (type) {
132  case ONEBYTE:
133  dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
134  break;
135  case TWOBYTE:
136  dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
137  break;
138  case THREEBYTE_38:
139  dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
140  break;
141  case THREEBYTE_3A:
142  dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143  break;
144  case XOP8_MAP:
145  dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
146  break;
147  case XOP9_MAP:
148  dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
149  break;
150  case XOPA_MAP:
151  dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152  break;
153  case THREEDNOW_MAP:
154  dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155  break;
156  }
157 
158  switch (dec->modrm_type) {
159  default:
160  debug("Corrupt table! Unknown modrm_type");
161  return 0;
162  case MODRM_ONEENTRY:
163  return modRMTable[dec->instructionIDs];
164  case MODRM_SPLITRM:
165  if (modFromModRM(modRM) == 0x3)
166  return modRMTable[dec->instructionIDs+1];
167  return modRMTable[dec->instructionIDs];
168  case MODRM_SPLITREG:
169  if (modFromModRM(modRM) == 0x3)
170  return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
171  return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
172  case MODRM_SPLITMISC:
173  if (modFromModRM(modRM) == 0x3)
174  return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
175  return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
176  case MODRM_FULL:
177  return modRMTable[dec->instructionIDs+modRM];
178  }
179 }
180 
181 /*
182  * specifierForUID - Given a UID, returns the name and operand specification for
183  * that instruction.
184  *
185  * @param uid - The unique ID for the instruction. This should be returned by
186  * decode(); specifierForUID will not check bounds.
187  * @return - A pointer to the specification for that instruction.
188  */
189 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
190  return &INSTRUCTIONS_SYM[uid];
191 }
192 
193 /*
194  * consumeByte - Uses the reader function provided by the user to consume one
195  * byte from the instruction's memory and advance the cursor.
196  *
197  * @param insn - The instruction with the reader function to use. The cursor
198  * for this instruction is advanced.
199  * @param byte - A pointer to a pre-allocated memory buffer to be populated
200  * with the data read.
201  * @return - 0 if the read was successful; nonzero otherwise.
202  */
203 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
204  int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
205 
206  if (!ret)
207  ++(insn->readerCursor);
208 
209  return ret;
210 }
211 
212 /*
213  * lookAtByte - Like consumeByte, but does not advance the cursor.
214  *
215  * @param insn - See consumeByte().
216  * @param byte - See consumeByte().
217  * @return - See consumeByte().
218  */
219 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
220  return insn->reader(insn->readerArg, byte, insn->readerCursor);
221 }
222 
223 static void unconsumeByte(struct InternalInstruction* insn) {
224  insn->readerCursor--;
225 }
226 
227 #define CONSUME_FUNC(name, type) \
228  static int name(struct InternalInstruction* insn, type* ptr) { \
229  type combined = 0; \
230  unsigned offset; \
231  for (offset = 0; offset < sizeof(type); ++offset) { \
232  uint8_t byte; \
233  int ret = insn->reader(insn->readerArg, \
234  &byte, \
235  insn->readerCursor + offset); \
236  if (ret) \
237  return ret; \
238  combined = combined | ((uint64_t)byte << (offset * 8)); \
239  } \
240  *ptr = combined; \
241  insn->readerCursor += sizeof(type); \
242  return 0; \
243  }
244 
245 /*
246  * consume* - Use the reader function provided by the user to consume data
247  * values of various sizes from the instruction's memory and advance the
248  * cursor appropriately. These readers perform endian conversion.
249  *
250  * @param insn - See consumeByte().
251  * @param ptr - A pointer to a pre-allocated memory of appropriate size to
252  * be populated with the data read.
253  * @return - See consumeByte().
254  */
255 CONSUME_FUNC(consumeInt8, int8_t)
256 CONSUME_FUNC(consumeInt16, int16_t)
257 CONSUME_FUNC(consumeInt32, int32_t)
258 CONSUME_FUNC(consumeUInt16, uint16_t)
259 CONSUME_FUNC(consumeUInt32, uint32_t)
260 CONSUME_FUNC(consumeUInt64, uint64_t)
261 
262 /*
263  * dbgprintf - Uses the logging function provided by the user to log a single
264  * message, typically without a carriage-return.
265  *
266  * @param insn - The instruction containing the logging function.
267  * @param format - See printf().
268  * @param ... - See printf().
269  */
270 static void dbgprintf(struct InternalInstruction* insn,
271  const char* format,
272  ...) {
273  char buffer[256];
274  va_list ap;
275 
276  if (!insn->dlog)
277  return;
278 
279  va_start(ap, format);
280  (void)vsnprintf(buffer, sizeof(buffer), format, ap);
281  va_end(ap);
282 
283  insn->dlog(insn->dlogArg, buffer);
284 }
285 
286 static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
287  if (insn->mode == MODE_64BIT)
288  return prefix >= 0x40 && prefix <= 0x4f;
289  return false;
290 }
291 
292 /*
293  * setPrefixPresent - Marks that a particular prefix is present as mandatory
294  *
295  * @param insn - The instruction to be marked as having the prefix.
296  * @param prefix - The prefix that is present.
297  */
298 static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) {
299  uint8_t nextByte;
300  switch (prefix) {
301  case 0xf2:
302  case 0xf3:
303  if (lookAtByte(insn, &nextByte))
304  break;
305  // TODO:
306  // 1. There could be several 0x66
307  // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
308  // it's not mandatory prefix
309  // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
310  // 0x0f exactly after it to be mandatory prefix
311  if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
312  // The last of 0xf2 /0xf3 is mandatory prefix
313  insn->mandatoryPrefix = prefix;
314  insn->repeatPrefix = prefix;
315  break;
316  case 0x66:
317  if (lookAtByte(insn, &nextByte))
318  break;
319  // 0x66 can't overwrite existing mandatory prefix and should be ignored
320  if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
321  insn->mandatoryPrefix = prefix;
322  break;
323  }
324 }
325 
326 /*
327  * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
328  * instruction as having them. Also sets the instruction's default operand,
329  * address, and other relevant data sizes to report operands correctly.
330  *
331  * @param insn - The instruction whose prefixes are to be read.
332  * @return - 0 if the instruction could be read until the end of the prefix
333  * bytes, and no prefixes conflicted; nonzero otherwise.
334  */
335 static int readPrefixes(struct InternalInstruction* insn) {
336  bool isPrefix = true;
337  uint8_t byte = 0;
338  uint8_t nextByte;
339 
340  dbgprintf(insn, "readPrefixes()");
341 
342  while (isPrefix) {
343  /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
344  if (consumeByte(insn, &byte))
345  break;
346 
347  /*
348  * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
349  * break and let it be disassembled as a normal "instruction".
350  */
351  if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
352  break;
353 
354  if ((byte == 0xf2 || byte == 0xf3) && !lookAtByte(insn, &nextByte)) {
355  /*
356  * If the byte is 0xf2 or 0xf3, and any of the following conditions are
357  * met:
358  * - it is followed by a LOCK (0xf0) prefix
359  * - it is followed by an xchg instruction
360  * then it should be disassembled as a xacquire/xrelease not repne/rep.
361  */
362  if (((nextByte == 0xf0) ||
363  ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
364  insn->xAcquireRelease = true;
365  if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
366  break;
367  }
368  /*
369  * Also if the byte is 0xf3, and the following condition is met:
370  * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
371  * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
372  * then it should be disassembled as an xrelease not rep.
373  */
374  if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
375  nextByte == 0xc6 || nextByte == 0xc7)) {
376  insn->xAcquireRelease = true;
377  if (nextByte != 0x90) // PAUSE instruction support
378  break;
379  }
380  if (isREX(insn, nextByte)) {
381  uint8_t nnextByte;
382  // Go to REX prefix after the current one
383  if (consumeByte(insn, &nnextByte))
384  return -1;
385  // We should be able to read next byte after REX prefix
386  if (lookAtByte(insn, &nnextByte))
387  return -1;
388  unconsumeByte(insn);
389  }
390  }
391 
392  switch (byte) {
393  case 0xf0: /* LOCK */
394  case 0xf2: /* REPNE/REPNZ */
395  case 0xf3: /* REP or REPE/REPZ */
396  setPrefixPresent(insn, byte);
397  break;
398  case 0x2e: /* CS segment override -OR- Branch not taken */
399  case 0x36: /* SS segment override -OR- Branch taken */
400  case 0x3e: /* DS segment override */
401  case 0x26: /* ES segment override */
402  case 0x64: /* FS segment override */
403  case 0x65: /* GS segment override */
404  switch (byte) {
405  case 0x2e:
407  break;
408  case 0x36:
410  break;
411  case 0x3e:
413  break;
414  case 0x26:
416  break;
417  case 0x64:
419  break;
420  case 0x65:
422  break;
423  default:
424  debug("Unhandled override");
425  return -1;
426  }
427  setPrefixPresent(insn, byte);
428  break;
429  case 0x66: /* Operand-size override */
430  insn->hasOpSize = true;
431  setPrefixPresent(insn, byte);
432  break;
433  case 0x67: /* Address-size override */
434  insn->hasAdSize = true;
435  setPrefixPresent(insn, byte);
436  break;
437  default: /* Not a prefix byte */
438  isPrefix = false;
439  break;
440  }
441 
442  if (isPrefix)
443  dbgprintf(insn, "Found prefix 0x%hhx", byte);
444  }
445 
447 
448  if (byte == 0x62) {
449  uint8_t byte1, byte2;
450 
451  if (consumeByte(insn, &byte1)) {
452  dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
453  return -1;
454  }
455 
456  if (lookAtByte(insn, &byte2)) {
457  dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
458  return -1;
459  }
460 
461  if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
462  ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
464  } else {
465  unconsumeByte(insn); /* unconsume byte1 */
466  unconsumeByte(insn); /* unconsume byte */
467  }
468 
469  if (insn->vectorExtensionType == TYPE_EVEX) {
470  insn->vectorExtensionPrefix[0] = byte;
471  insn->vectorExtensionPrefix[1] = byte1;
472  if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
473  dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
474  return -1;
475  }
476  if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
477  dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
478  return -1;
479  }
480 
481  /* We simulate the REX prefix for simplicity's sake */
482  if (insn->mode == MODE_64BIT) {
483  insn->rexPrefix = 0x40
484  | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
485  | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
486  | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
487  | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
488  }
489 
490  dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
491  insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
492  insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
493  }
494  } else if (byte == 0xc4) {
495  uint8_t byte1;
496 
497  if (lookAtByte(insn, &byte1)) {
498  dbgprintf(insn, "Couldn't read second byte of VEX");
499  return -1;
500  }
501 
502  if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
504  else
505  unconsumeByte(insn);
506 
507  if (insn->vectorExtensionType == TYPE_VEX_3B) {
508  insn->vectorExtensionPrefix[0] = byte;
509  consumeByte(insn, &insn->vectorExtensionPrefix[1]);
510  consumeByte(insn, &insn->vectorExtensionPrefix[2]);
511 
512  /* We simulate the REX prefix for simplicity's sake */
513 
514  if (insn->mode == MODE_64BIT)
515  insn->rexPrefix = 0x40
516  | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
517  | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
518  | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
519  | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
520 
521  dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
522  insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
523  insn->vectorExtensionPrefix[2]);
524  }
525  } else if (byte == 0xc5) {
526  uint8_t byte1;
527 
528  if (lookAtByte(insn, &byte1)) {
529  dbgprintf(insn, "Couldn't read second byte of VEX");
530  return -1;
531  }
532 
533  if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
535  else
536  unconsumeByte(insn);
537 
538  if (insn->vectorExtensionType == TYPE_VEX_2B) {
539  insn->vectorExtensionPrefix[0] = byte;
540  consumeByte(insn, &insn->vectorExtensionPrefix[1]);
541 
542  if (insn->mode == MODE_64BIT)
543  insn->rexPrefix = 0x40
544  | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
545 
546  switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
547  default:
548  break;
549  case VEX_PREFIX_66:
550  insn->hasOpSize = true;
551  break;
552  }
553 
554  dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
555  insn->vectorExtensionPrefix[0],
556  insn->vectorExtensionPrefix[1]);
557  }
558  } else if (byte == 0x8f) {
559  uint8_t byte1;
560 
561  if (lookAtByte(insn, &byte1)) {
562  dbgprintf(insn, "Couldn't read second byte of XOP");
563  return -1;
564  }
565 
566  if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */
568  else
569  unconsumeByte(insn);
570 
571  if (insn->vectorExtensionType == TYPE_XOP) {
572  insn->vectorExtensionPrefix[0] = byte;
573  consumeByte(insn, &insn->vectorExtensionPrefix[1]);
574  consumeByte(insn, &insn->vectorExtensionPrefix[2]);
575 
576  /* We simulate the REX prefix for simplicity's sake */
577 
578  if (insn->mode == MODE_64BIT)
579  insn->rexPrefix = 0x40
580  | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
581  | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
582  | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
583  | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
584 
585  switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
586  default:
587  break;
588  case VEX_PREFIX_66:
589  insn->hasOpSize = true;
590  break;
591  }
592 
593  dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
594  insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
595  insn->vectorExtensionPrefix[2]);
596  }
597  } else if (isREX(insn, byte)) {
598  if (lookAtByte(insn, &nextByte))
599  return -1;
600  insn->rexPrefix = byte;
601  dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
602  } else
603  unconsumeByte(insn);
604 
605  if (insn->mode == MODE_16BIT) {
606  insn->registerSize = (insn->hasOpSize ? 4 : 2);
607  insn->addressSize = (insn->hasAdSize ? 4 : 2);
608  insn->displacementSize = (insn->hasAdSize ? 4 : 2);
609  insn->immediateSize = (insn->hasOpSize ? 4 : 2);
610  } else if (insn->mode == MODE_32BIT) {
611  insn->registerSize = (insn->hasOpSize ? 2 : 4);
612  insn->addressSize = (insn->hasAdSize ? 2 : 4);
613  insn->displacementSize = (insn->hasAdSize ? 2 : 4);
614  insn->immediateSize = (insn->hasOpSize ? 2 : 4);
615  } else if (insn->mode == MODE_64BIT) {
616  if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
617  insn->registerSize = 8;
618  insn->addressSize = (insn->hasAdSize ? 4 : 8);
619  insn->displacementSize = 4;
620  insn->immediateSize = 4;
621  } else {
622  insn->registerSize = (insn->hasOpSize ? 2 : 4);
623  insn->addressSize = (insn->hasAdSize ? 4 : 8);
624  insn->displacementSize = (insn->hasOpSize ? 2 : 4);
625  insn->immediateSize = (insn->hasOpSize ? 2 : 4);
626  }
627  }
628 
629  return 0;
630 }
631 
632 static int readModRM(struct InternalInstruction* insn);
633 
634 /*
635  * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
636  * extended or escape opcodes).
637  *
638  * @param insn - The instruction whose opcode is to be read.
639  * @return - 0 if the opcode could be read successfully; nonzero otherwise.
640  */
641 static int readOpcode(struct InternalInstruction* insn) {
642  /* Determine the length of the primary opcode */
643 
644  uint8_t current;
645 
646  dbgprintf(insn, "readOpcode()");
647 
648  insn->opcodeType = ONEBYTE;
649 
650  if (insn->vectorExtensionType == TYPE_EVEX) {
651  switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
652  default:
653  dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
655  return -1;
656  case VEX_LOB_0F:
657  insn->opcodeType = TWOBYTE;
658  return consumeByte(insn, &insn->opcode);
659  case VEX_LOB_0F38:
660  insn->opcodeType = THREEBYTE_38;
661  return consumeByte(insn, &insn->opcode);
662  case VEX_LOB_0F3A:
663  insn->opcodeType = THREEBYTE_3A;
664  return consumeByte(insn, &insn->opcode);
665  }
666  } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
667  switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
668  default:
669  dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
671  return -1;
672  case VEX_LOB_0F:
673  insn->opcodeType = TWOBYTE;
674  return consumeByte(insn, &insn->opcode);
675  case VEX_LOB_0F38:
676  insn->opcodeType = THREEBYTE_38;
677  return consumeByte(insn, &insn->opcode);
678  case VEX_LOB_0F3A:
679  insn->opcodeType = THREEBYTE_3A;
680  return consumeByte(insn, &insn->opcode);
681  }
682  } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
683  insn->opcodeType = TWOBYTE;
684  return consumeByte(insn, &insn->opcode);
685  } else if (insn->vectorExtensionType == TYPE_XOP) {
686  switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
687  default:
688  dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
690  return -1;
691  case XOP_MAP_SELECT_8:
692  insn->opcodeType = XOP8_MAP;
693  return consumeByte(insn, &insn->opcode);
694  case XOP_MAP_SELECT_9:
695  insn->opcodeType = XOP9_MAP;
696  return consumeByte(insn, &insn->opcode);
697  case XOP_MAP_SELECT_A:
698  insn->opcodeType = XOPA_MAP;
699  return consumeByte(insn, &insn->opcode);
700  }
701  }
702 
703  if (consumeByte(insn, &current))
704  return -1;
705 
706  if (current == 0x0f) {
707  dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
708 
709  if (consumeByte(insn, &current))
710  return -1;
711 
712  if (current == 0x38) {
713  dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
714 
715  if (consumeByte(insn, &current))
716  return -1;
717 
718  insn->opcodeType = THREEBYTE_38;
719  } else if (current == 0x3a) {
720  dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
721 
722  if (consumeByte(insn, &current))
723  return -1;
724 
725  insn->opcodeType = THREEBYTE_3A;
726  } else if (current == 0x0f) {
727  dbgprintf(insn, "Found a 3dnow escape prefix (0x%hhx)", current);
728 
729  // Consume operands before the opcode to comply with the 3DNow encoding
730  if (readModRM(insn))
731  return -1;
732 
733  if (consumeByte(insn, &current))
734  return -1;
735 
736  insn->opcodeType = THREEDNOW_MAP;
737  } else {
738  dbgprintf(insn, "Didn't find a three-byte escape prefix");
739 
740  insn->opcodeType = TWOBYTE;
741  }
742  } else if (insn->mandatoryPrefix)
743  // The opcode with mandatory prefix must start with opcode escape.
744  // If not it's legacy repeat prefix
745  insn->mandatoryPrefix = 0;
746 
747  /*
748  * At this point we have consumed the full opcode.
749  * Anything we consume from here on must be unconsumed.
750  */
751 
752  insn->opcode = current;
753 
754  return 0;
755 }
756 
757 /*
758  * getIDWithAttrMask - Determines the ID of an instruction, consuming
759  * the ModR/M byte as appropriate for extended and escape opcodes,
760  * and using a supplied attribute mask.
761  *
762  * @param instructionID - A pointer whose target is filled in with the ID of the
763  * instruction.
764  * @param insn - The instruction whose ID is to be determined.
765  * @param attrMask - The attribute mask to search.
766  * @return - 0 if the ModR/M could be read when needed or was not
767  * needed; nonzero otherwise.
768  */
769 static int getIDWithAttrMask(uint16_t* instructionID,
770  struct InternalInstruction* insn,
771  uint16_t attrMask) {
772  bool hasModRMExtension;
773 
774  InstructionContext instructionClass = contextForAttrs(attrMask);
775 
776  hasModRMExtension = modRMRequired(insn->opcodeType,
777  instructionClass,
778  insn->opcode);
779 
780  if (hasModRMExtension) {
781  if (readModRM(insn))
782  return -1;
783 
784  *instructionID = decode(insn->opcodeType,
785  instructionClass,
786  insn->opcode,
787  insn->modRM);
788  } else {
789  *instructionID = decode(insn->opcodeType,
790  instructionClass,
791  insn->opcode,
792  0);
793  }
794 
795  return 0;
796 }
797 
798 /*
799  * is16BitEquivalent - Determines whether two instruction names refer to
800  * equivalent instructions but one is 16-bit whereas the other is not.
801  *
802  * @param orig - The instruction that is not 16-bit
803  * @param equiv - The instruction that is 16-bit
804  */
805 static bool is16BitEquivalent(const char *orig, const char *equiv) {
806  off_t i;
807 
808  for (i = 0;; i++) {
809  if (orig[i] == '\0' && equiv[i] == '\0')
810  return true;
811  if (orig[i] == '\0' || equiv[i] == '\0')
812  return false;
813  if (orig[i] != equiv[i]) {
814  if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
815  continue;
816  if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
817  continue;
818  if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
819  continue;
820  return false;
821  }
822  }
823 }
824 
825 /*
826  * is64Bit - Determines whether this instruction is a 64-bit instruction.
827  *
828  * @param name - The instruction that is not 16-bit
829  */
830 static bool is64Bit(const char *name) {
831  off_t i;
832 
833  for (i = 0;; ++i) {
834  if (name[i] == '\0')
835  return false;
836  if (name[i] == '6' && name[i+1] == '4')
837  return true;
838  }
839 }
840 
841 /*
842  * getID - Determines the ID of an instruction, consuming the ModR/M byte as
843  * appropriate for extended and escape opcodes. Determines the attributes and
844  * context for the instruction before doing so.
845  *
846  * @param insn - The instruction whose ID is to be determined.
847  * @return - 0 if the ModR/M could be read when needed or was not needed;
848  * nonzero otherwise.
849  */
850 static int getID(struct InternalInstruction* insn, const void *miiArg) {
851  uint16_t attrMask;
852  uint16_t instructionID;
853 
854  dbgprintf(insn, "getID()");
855 
856  attrMask = ATTR_NONE;
857 
858  if (insn->mode == MODE_64BIT)
859  attrMask |= ATTR_64BIT;
860 
861  if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
862  attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
863 
864  if (insn->vectorExtensionType == TYPE_EVEX) {
865  switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
866  case VEX_PREFIX_66:
867  attrMask |= ATTR_OPSIZE;
868  break;
869  case VEX_PREFIX_F3:
870  attrMask |= ATTR_XS;
871  break;
872  case VEX_PREFIX_F2:
873  attrMask |= ATTR_XD;
874  break;
875  }
876 
877  if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
878  attrMask |= ATTR_EVEXKZ;
879  if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
880  attrMask |= ATTR_EVEXB;
882  attrMask |= ATTR_EVEXK;
883  if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
884  attrMask |= ATTR_EVEXL;
886  attrMask |= ATTR_EVEXL2;
887  } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
888  switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
889  case VEX_PREFIX_66:
890  attrMask |= ATTR_OPSIZE;
891  break;
892  case VEX_PREFIX_F3:
893  attrMask |= ATTR_XS;
894  break;
895  case VEX_PREFIX_F2:
896  attrMask |= ATTR_XD;
897  break;
898  }
899 
900  if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
901  attrMask |= ATTR_VEXL;
902  } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
903  switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
904  case VEX_PREFIX_66:
905  attrMask |= ATTR_OPSIZE;
906  break;
907  case VEX_PREFIX_F3:
908  attrMask |= ATTR_XS;
909  break;
910  case VEX_PREFIX_F2:
911  attrMask |= ATTR_XD;
912  break;
913  }
914 
915  if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
916  attrMask |= ATTR_VEXL;
917  } else if (insn->vectorExtensionType == TYPE_XOP) {
918  switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
919  case VEX_PREFIX_66:
920  attrMask |= ATTR_OPSIZE;
921  break;
922  case VEX_PREFIX_F3:
923  attrMask |= ATTR_XS;
924  break;
925  case VEX_PREFIX_F2:
926  attrMask |= ATTR_XD;
927  break;
928  }
929 
930  if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
931  attrMask |= ATTR_VEXL;
932  } else {
933  return -1;
934  }
935  } else if (!insn->mandatoryPrefix) {
936  // If we don't have mandatory prefix we should use legacy prefixes here
937  if (insn->hasOpSize && (insn->mode != MODE_16BIT))
938  attrMask |= ATTR_OPSIZE;
939  if (insn->hasAdSize)
940  attrMask |= ATTR_ADSIZE;
941  if (insn->opcodeType == ONEBYTE) {
942  if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
943  // Special support for PAUSE
944  attrMask |= ATTR_XS;
945  } else {
946  if (insn->repeatPrefix == 0xf2)
947  attrMask |= ATTR_XD;
948  else if (insn->repeatPrefix == 0xf3)
949  attrMask |= ATTR_XS;
950  }
951  } else {
952  switch (insn->mandatoryPrefix) {
953  case 0xf2:
954  attrMask |= ATTR_XD;
955  break;
956  case 0xf3:
957  attrMask |= ATTR_XS;
958  break;
959  case 0x66:
960  if (insn->mode != MODE_16BIT)
961  attrMask |= ATTR_OPSIZE;
962  break;
963  case 0x67:
964  attrMask |= ATTR_ADSIZE;
965  break;
966  }
967 
968  }
969 
970  if (insn->rexPrefix & 0x08) {
971  attrMask |= ATTR_REXW;
972  attrMask &= ~ATTR_ADSIZE;
973  }
974 
975  /*
976  * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
977  * of the AdSize prefix is inverted w.r.t. 32-bit mode.
978  */
979  if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE &&
980  insn->opcode == 0xE3)
981  attrMask ^= ATTR_ADSIZE;
982 
983  /*
984  * In 64-bit mode all f64 superscripted opcodes ignore opcode size prefix
985  * CALL/JMP/JCC instructions need to ignore 0x66 and consume 4 bytes
986  */
987 
988  if ((insn->mode == MODE_64BIT) && insn->hasOpSize) {
989  switch (insn->opcode) {
990  case 0xE8:
991  case 0xE9:
992  // Take care of psubsb and other mmx instructions.
993  if (insn->opcodeType == ONEBYTE) {
994  attrMask ^= ATTR_OPSIZE;
995  insn->immediateSize = 4;
996  insn->displacementSize = 4;
997  }
998  break;
999  case 0x82:
1000  case 0x83:
1001  case 0x84:
1002  case 0x85:
1003  case 0x86:
1004  case 0x87:
1005  case 0x88:
1006  case 0x89:
1007  case 0x8A:
1008  case 0x8B:
1009  case 0x8C:
1010  case 0x8D:
1011  case 0x8E:
1012  case 0x8F:
1013  // Take care of lea and three byte ops.
1014  if (insn->opcodeType == TWOBYTE) {
1015  attrMask ^= ATTR_OPSIZE;
1016  insn->immediateSize = 4;
1017  insn->displacementSize = 4;
1018  }
1019  break;
1020  }
1021  }
1022 
1023  if (getIDWithAttrMask(&instructionID, insn, attrMask))
1024  return -1;
1025 
1026  /* The following clauses compensate for limitations of the tables. */
1027 
1028  if (insn->mode != MODE_64BIT &&
1030  /*
1031  * The tables can't distinquish between cases where the W-bit is used to
1032  * select register size and cases where its a required part of the opcode.
1033  */
1034  if ((insn->vectorExtensionType == TYPE_EVEX &&
1035  wFromEVEX3of4(insn->vectorExtensionPrefix[2])) ||
1036  (insn->vectorExtensionType == TYPE_VEX_3B &&
1037  wFromVEX3of3(insn->vectorExtensionPrefix[2])) ||
1038  (insn->vectorExtensionType == TYPE_XOP &&
1039  wFromXOP3of3(insn->vectorExtensionPrefix[2]))) {
1040 
1041  uint16_t instructionIDWithREXW;
1042  if (getIDWithAttrMask(&instructionIDWithREXW,
1043  insn, attrMask | ATTR_REXW)) {
1044  insn->instructionID = instructionID;
1045  insn->spec = specifierForUID(instructionID);
1046  return 0;
1047  }
1048 
1049  auto SpecName = GetInstrName(instructionIDWithREXW, miiArg);
1050  // If not a 64-bit instruction. Switch the opcode.
1051  if (!is64Bit(SpecName.data())) {
1052  insn->instructionID = instructionIDWithREXW;
1053  insn->spec = specifierForUID(instructionIDWithREXW);
1054  return 0;
1055  }
1056  }
1057  }
1058 
1059  /*
1060  * Absolute moves and umonitor need special handling.
1061  * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1062  * inverted w.r.t.
1063  * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1064  * any position.
1065  */
1066  if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1067  (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE))) {
1068  /* Make sure we observed the prefixes in any position. */
1069  if (insn->hasAdSize)
1070  attrMask |= ATTR_ADSIZE;
1071  if (insn->hasOpSize)
1072  attrMask |= ATTR_OPSIZE;
1073 
1074  /* In 16-bit, invert the attributes. */
1075  if (insn->mode == MODE_16BIT) {
1076  attrMask ^= ATTR_ADSIZE;
1077  /* The OpSize attribute is only valid with the absolute moves. */
1078  if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1079  attrMask ^= ATTR_OPSIZE;
1080  }
1081 
1082  if (getIDWithAttrMask(&instructionID, insn, attrMask))
1083  return -1;
1084 
1085  insn->instructionID = instructionID;
1086  insn->spec = specifierForUID(instructionID);
1087  return 0;
1088  }
1089 
1090  if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1091  !(attrMask & ATTR_OPSIZE)) {
1092  /*
1093  * The instruction tables make no distinction between instructions that
1094  * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1095  * particular spot (i.e., many MMX operations). In general we're
1096  * conservative, but in the specific case where OpSize is present but not
1097  * in the right place we check if there's a 16-bit operation.
1098  */
1099 
1100  const struct InstructionSpecifier *spec;
1101  uint16_t instructionIDWithOpsize;
1102  llvm::StringRef specName, specWithOpSizeName;
1103 
1104  spec = specifierForUID(instructionID);
1105 
1106  if (getIDWithAttrMask(&instructionIDWithOpsize,
1107  insn,
1108  attrMask | ATTR_OPSIZE)) {
1109  /*
1110  * ModRM required with OpSize but not present; give up and return version
1111  * without OpSize set
1112  */
1113 
1114  insn->instructionID = instructionID;
1115  insn->spec = spec;
1116  return 0;
1117  }
1118 
1119  specName = GetInstrName(instructionID, miiArg);
1120  specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1121 
1122  if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1123  (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1124  insn->instructionID = instructionIDWithOpsize;
1125  insn->spec = specifierForUID(instructionIDWithOpsize);
1126  } else {
1127  insn->instructionID = instructionID;
1128  insn->spec = spec;
1129  }
1130  return 0;
1131  }
1132 
1133  if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1134  insn->rexPrefix & 0x01) {
1135  /*
1136  * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1137  * it should decode as XCHG %r8, %eax.
1138  */
1139 
1140  const struct InstructionSpecifier *spec;
1141  uint16_t instructionIDWithNewOpcode;
1142  const struct InstructionSpecifier *specWithNewOpcode;
1143 
1144  spec = specifierForUID(instructionID);
1145 
1146  /* Borrow opcode from one of the other XCHGar opcodes */
1147  insn->opcode = 0x91;
1148 
1149  if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1150  insn,
1151  attrMask)) {
1152  insn->opcode = 0x90;
1153 
1154  insn->instructionID = instructionID;
1155  insn->spec = spec;
1156  return 0;
1157  }
1158 
1159  specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1160 
1161  /* Change back */
1162  insn->opcode = 0x90;
1163 
1164  insn->instructionID = instructionIDWithNewOpcode;
1165  insn->spec = specWithNewOpcode;
1166 
1167  return 0;
1168  }
1169 
1170  insn->instructionID = instructionID;
1171  insn->spec = specifierForUID(insn->instructionID);
1172 
1173  return 0;
1174 }
1175 
1176 /*
1177  * readSIB - Consumes the SIB byte to determine addressing information for an
1178  * instruction.
1179  *
1180  * @param insn - The instruction whose SIB byte is to be read.
1181  * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1182  */
1183 static int readSIB(struct InternalInstruction* insn) {
1184  SIBBase sibBaseBase = SIB_BASE_NONE;
1185  uint8_t index, base;
1186 
1187  dbgprintf(insn, "readSIB()");
1188 
1189  if (insn->consumedSIB)
1190  return 0;
1191 
1192  insn->consumedSIB = true;
1193 
1194  switch (insn->addressSize) {
1195  case 2:
1196  dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1197  return -1;
1198  case 4:
1199  insn->sibIndexBase = SIB_INDEX_EAX;
1200  sibBaseBase = SIB_BASE_EAX;
1201  break;
1202  case 8:
1203  insn->sibIndexBase = SIB_INDEX_RAX;
1204  sibBaseBase = SIB_BASE_RAX;
1205  break;
1206  }
1207 
1208  if (consumeByte(insn, &insn->sib))
1209  return -1;
1210 
1211  index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1212 
1213  if (index == 0x4) {
1214  insn->sibIndex = SIB_INDEX_NONE;
1215  } else {
1216  insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
1217  }
1218 
1219  insn->sibScale = 1 << scaleFromSIB(insn->sib);
1220 
1221  base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1222 
1223  switch (base) {
1224  case 0x5:
1225  case 0xd:
1226  switch (modFromModRM(insn->modRM)) {
1227  case 0x0:
1228  insn->eaDisplacement = EA_DISP_32;
1229  insn->sibBase = SIB_BASE_NONE;
1230  break;
1231  case 0x1:
1232  insn->eaDisplacement = EA_DISP_8;
1233  insn->sibBase = (SIBBase)(sibBaseBase + base);
1234  break;
1235  case 0x2:
1236  insn->eaDisplacement = EA_DISP_32;
1237  insn->sibBase = (SIBBase)(sibBaseBase + base);
1238  break;
1239  case 0x3:
1240  debug("Cannot have Mod = 0b11 and a SIB byte");
1241  return -1;
1242  }
1243  break;
1244  default:
1245  insn->sibBase = (SIBBase)(sibBaseBase + base);
1246  break;
1247  }
1248 
1249  return 0;
1250 }
1251 
1252 /*
1253  * readDisplacement - Consumes the displacement of an instruction.
1254  *
1255  * @param insn - The instruction whose displacement is to be read.
1256  * @return - 0 if the displacement byte was successfully read; nonzero
1257  * otherwise.
1258  */
1259 static int readDisplacement(struct InternalInstruction* insn) {
1260  int8_t d8;
1261  int16_t d16;
1262  int32_t d32;
1263 
1264  dbgprintf(insn, "readDisplacement()");
1265 
1266  if (insn->consumedDisplacement)
1267  return 0;
1268 
1269  insn->consumedDisplacement = true;
1270  insn->displacementOffset = insn->readerCursor - insn->startLocation;
1271 
1272  switch (insn->eaDisplacement) {
1273  case EA_DISP_NONE:
1274  insn->consumedDisplacement = false;
1275  break;
1276  case EA_DISP_8:
1277  if (consumeInt8(insn, &d8))
1278  return -1;
1279  insn->displacement = d8;
1280  break;
1281  case EA_DISP_16:
1282  if (consumeInt16(insn, &d16))
1283  return -1;
1284  insn->displacement = d16;
1285  break;
1286  case EA_DISP_32:
1287  if (consumeInt32(insn, &d32))
1288  return -1;
1289  insn->displacement = d32;
1290  break;
1291  }
1292 
1293  insn->consumedDisplacement = true;
1294  return 0;
1295 }
1296 
1297 /*
1298  * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1299  * displacement) for an instruction and interprets it.
1300  *
1301  * @param insn - The instruction whose addressing information is to be read.
1302  * @return - 0 if the information was successfully read; nonzero otherwise.
1303  */
1304 static int readModRM(struct InternalInstruction* insn) {
1305  uint8_t mod, rm, reg;
1306 
1307  dbgprintf(insn, "readModRM()");
1308 
1309  if (insn->consumedModRM)
1310  return 0;
1311 
1312  if (consumeByte(insn, &insn->modRM))
1313  return -1;
1314  insn->consumedModRM = true;
1315 
1316  mod = modFromModRM(insn->modRM);
1317  rm = rmFromModRM(insn->modRM);
1318  reg = regFromModRM(insn->modRM);
1319 
1320  /*
1321  * This goes by insn->registerSize to pick the correct register, which messes
1322  * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1323  * fixupReg().
1324  */
1325  switch (insn->registerSize) {
1326  case 2:
1327  insn->regBase = MODRM_REG_AX;
1328  insn->eaRegBase = EA_REG_AX;
1329  break;
1330  case 4:
1331  insn->regBase = MODRM_REG_EAX;
1332  insn->eaRegBase = EA_REG_EAX;
1333  break;
1334  case 8:
1335  insn->regBase = MODRM_REG_RAX;
1336  insn->eaRegBase = EA_REG_RAX;
1337  break;
1338  }
1339 
1340  reg |= rFromREX(insn->rexPrefix) << 3;
1341  rm |= bFromREX(insn->rexPrefix) << 3;
1342  if (insn->vectorExtensionType == TYPE_EVEX) {
1343  reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1344  rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1345  }
1346 
1347  insn->reg = (Reg)(insn->regBase + reg);
1348 
1349  switch (insn->addressSize) {
1350  case 2:
1351  insn->eaBaseBase = EA_BASE_BX_SI;
1352 
1353  switch (mod) {
1354  case 0x0:
1355  if (rm == 0x6) {
1356  insn->eaBase = EA_BASE_NONE;
1357  insn->eaDisplacement = EA_DISP_16;
1358  if (readDisplacement(insn))
1359  return -1;
1360  } else {
1361  insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1362  insn->eaDisplacement = EA_DISP_NONE;
1363  }
1364  break;
1365  case 0x1:
1366  insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1367  insn->eaDisplacement = EA_DISP_8;
1368  insn->displacementSize = 1;
1369  if (readDisplacement(insn))
1370  return -1;
1371  break;
1372  case 0x2:
1373  insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1374  insn->eaDisplacement = EA_DISP_16;
1375  if (readDisplacement(insn))
1376  return -1;
1377  break;
1378  case 0x3:
1379  insn->eaBase = (EABase)(insn->eaRegBase + rm);
1380  if (readDisplacement(insn))
1381  return -1;
1382  break;
1383  }
1384  break;
1385  case 4:
1386  case 8:
1387  insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1388 
1389  switch (mod) {
1390  case 0x0:
1391  insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1392  // In determining whether RIP-relative mode is used (rm=5),
1393  // or whether a SIB byte is present (rm=4),
1394  // the extension bits (REX.b and EVEX.x) are ignored.
1395  switch (rm & 7) {
1396  case 0x4: // SIB byte is present
1397  insn->eaBase = (insn->addressSize == 4 ?
1398  EA_BASE_sib : EA_BASE_sib64);
1399  if (readSIB(insn) || readDisplacement(insn))
1400  return -1;
1401  break;
1402  case 0x5: // RIP-relative
1403  insn->eaBase = EA_BASE_NONE;
1404  insn->eaDisplacement = EA_DISP_32;
1405  if (readDisplacement(insn))
1406  return -1;
1407  break;
1408  default:
1409  insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1410  break;
1411  }
1412  break;
1413  case 0x1:
1414  insn->displacementSize = 1;
1415  /* FALLTHROUGH */
1416  case 0x2:
1417  insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1418  switch (rm & 7) {
1419  case 0x4: // SIB byte is present
1420  insn->eaBase = EA_BASE_sib;
1421  if (readSIB(insn) || readDisplacement(insn))
1422  return -1;
1423  break;
1424  default:
1425  insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1426  if (readDisplacement(insn))
1427  return -1;
1428  break;
1429  }
1430  break;
1431  case 0x3:
1432  insn->eaDisplacement = EA_DISP_NONE;
1433  insn->eaBase = (EABase)(insn->eaRegBase + rm);
1434  break;
1435  }
1436  break;
1437  } /* switch (insn->addressSize) */
1438 
1439  return 0;
1440 }
1441 
1442 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1443  static uint16_t name(struct InternalInstruction *insn, \
1444  OperandType type, \
1445  uint8_t index, \
1446  uint8_t *valid) { \
1447  *valid = 1; \
1448  switch (type) { \
1449  default: \
1450  debug("Unhandled register type"); \
1451  *valid = 0; \
1452  return 0; \
1453  case TYPE_Rv: \
1454  return base + index; \
1455  case TYPE_R8: \
1456  if (insn->rexPrefix && \
1457  index >= 4 && index <= 7) { \
1458  return prefix##_SPL + (index - 4); \
1459  } else { \
1460  return prefix##_AL + index; \
1461  } \
1462  case TYPE_R16: \
1463  return prefix##_AX + index; \
1464  case TYPE_R32: \
1465  return prefix##_EAX + index; \
1466  case TYPE_R64: \
1467  return prefix##_RAX + index; \
1468  case TYPE_ZMM: \
1469  return prefix##_ZMM0 + index; \
1470  case TYPE_YMM: \
1471  return prefix##_YMM0 + index; \
1472  case TYPE_XMM: \
1473  return prefix##_XMM0 + index; \
1474  case TYPE_VK: \
1475  if (index > 7) \
1476  *valid = 0; \
1477  return prefix##_K0 + index; \
1478  case TYPE_MM64: \
1479  return prefix##_MM0 + (index & 0x7); \
1480  case TYPE_SEGMENTREG: \
1481  if ((index & 7) > 5) \
1482  *valid = 0; \
1483  return prefix##_ES + (index & 7); \
1484  case TYPE_DEBUGREG: \
1485  return prefix##_DR0 + index; \
1486  case TYPE_CONTROLREG: \
1487  return prefix##_CR0 + index; \
1488  case TYPE_BNDR: \
1489  if (index > 3) \
1490  *valid = 0; \
1491  return prefix##_BND0 + index; \
1492  case TYPE_MVSIBX: \
1493  return prefix##_XMM0 + index; \
1494  case TYPE_MVSIBY: \
1495  return prefix##_YMM0 + index; \
1496  case TYPE_MVSIBZ: \
1497  return prefix##_ZMM0 + index; \
1498  } \
1499  }
1500 
1501 /*
1502  * fixup*Value - Consults an operand type to determine the meaning of the
1503  * reg or R/M field. If the operand is an XMM operand, for example, an
1504  * operand would be XMM0 instead of AX, which readModRM() would otherwise
1505  * misinterpret it as.
1506  *
1507  * @param insn - The instruction containing the operand.
1508  * @param type - The operand type.
1509  * @param index - The existing value of the field as reported by readModRM().
1510  * @param valid - The address of a uint8_t. The target is set to 1 if the
1511  * field is valid for the register class; 0 if not.
1512  * @return - The proper value.
1513  */
1514 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1515 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1516 
1517 /*
1518  * fixupReg - Consults an operand specifier to determine which of the
1519  * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1520  *
1521  * @param insn - See fixup*Value().
1522  * @param op - The operand specifier.
1523  * @return - 0 if fixup was successful; -1 if the register returned was
1524  * invalid for its class.
1525  */
1526 static int fixupReg(struct InternalInstruction *insn,
1527  const struct OperandSpecifier *op) {
1528  uint8_t valid;
1529 
1530  dbgprintf(insn, "fixupReg()");
1531 
1532  switch ((OperandEncoding)op->encoding) {
1533  default:
1534  debug("Expected a REG or R/M encoding in fixupReg");
1535  return -1;
1536  case ENCODING_VVVV:
1537  insn->vvvv = (Reg)fixupRegValue(insn,
1538  (OperandType)op->type,
1539  insn->vvvv,
1540  &valid);
1541  if (!valid)
1542  return -1;
1543  break;
1544  case ENCODING_REG:
1545  insn->reg = (Reg)fixupRegValue(insn,
1546  (OperandType)op->type,
1547  insn->reg - insn->regBase,
1548  &valid);
1549  if (!valid)
1550  return -1;
1551  break;
1553  if (insn->eaBase >= insn->eaRegBase) {
1554  insn->eaBase = (EABase)fixupRMValue(insn,
1555  (OperandType)op->type,
1556  insn->eaBase - insn->eaRegBase,
1557  &valid);
1558  if (!valid)
1559  return -1;
1560  }
1561  break;
1562  }
1563 
1564  return 0;
1565 }
1566 
1567 /*
1568  * readOpcodeRegister - Reads an operand from the opcode field of an
1569  * instruction and interprets it appropriately given the operand width.
1570  * Handles AddRegFrm instructions.
1571  *
1572  * @param insn - the instruction whose opcode field is to be read.
1573  * @param size - The width (in bytes) of the register being specified.
1574  * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1575  * RAX.
1576  * @return - 0 on success; nonzero otherwise.
1577  */
1578 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1579  dbgprintf(insn, "readOpcodeRegister()");
1580 
1581  if (size == 0)
1582  size = insn->registerSize;
1583 
1584  switch (size) {
1585  case 1:
1586  insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1587  | (insn->opcode & 7)));
1588  if (insn->rexPrefix &&
1589  insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1590  insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1591  insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1592  + (insn->opcodeRegister - MODRM_REG_AL - 4));
1593  }
1594 
1595  break;
1596  case 2:
1597  insn->opcodeRegister = (Reg)(MODRM_REG_AX
1598  + ((bFromREX(insn->rexPrefix) << 3)
1599  | (insn->opcode & 7)));
1600  break;
1601  case 4:
1602  insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1603  + ((bFromREX(insn->rexPrefix) << 3)
1604  | (insn->opcode & 7)));
1605  break;
1606  case 8:
1607  insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1608  + ((bFromREX(insn->rexPrefix) << 3)
1609  | (insn->opcode & 7)));
1610  break;
1611  }
1612 
1613  return 0;
1614 }
1615 
1616 /*
1617  * readImmediate - Consumes an immediate operand from an instruction, given the
1618  * desired operand size.
1619  *
1620  * @param insn - The instruction whose operand is to be read.
1621  * @param size - The width (in bytes) of the operand.
1622  * @return - 0 if the immediate was successfully consumed; nonzero
1623  * otherwise.
1624  */
1625 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1626  uint8_t imm8;
1627  uint16_t imm16;
1628  uint32_t imm32;
1629  uint64_t imm64;
1630 
1631  dbgprintf(insn, "readImmediate()");
1632 
1633  if (insn->numImmediatesConsumed == 2) {
1634  debug("Already consumed two immediates");
1635  return -1;
1636  }
1637 
1638  if (size == 0)
1639  size = insn->immediateSize;
1640  else
1641  insn->immediateSize = size;
1642  insn->immediateOffset = insn->readerCursor - insn->startLocation;
1643 
1644  switch (size) {
1645  case 1:
1646  if (consumeByte(insn, &imm8))
1647  return -1;
1648  insn->immediates[insn->numImmediatesConsumed] = imm8;
1649  break;
1650  case 2:
1651  if (consumeUInt16(insn, &imm16))
1652  return -1;
1653  insn->immediates[insn->numImmediatesConsumed] = imm16;
1654  break;
1655  case 4:
1656  if (consumeUInt32(insn, &imm32))
1657  return -1;
1658  insn->immediates[insn->numImmediatesConsumed] = imm32;
1659  break;
1660  case 8:
1661  if (consumeUInt64(insn, &imm64))
1662  return -1;
1663  insn->immediates[insn->numImmediatesConsumed] = imm64;
1664  break;
1665  }
1666 
1667  insn->numImmediatesConsumed++;
1668 
1669  return 0;
1670 }
1671 
1672 /*
1673  * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1674  *
1675  * @param insn - The instruction whose operand is to be read.
1676  * @return - 0 if the vvvv was successfully consumed; nonzero
1677  * otherwise.
1678  */
1679 static int readVVVV(struct InternalInstruction* insn) {
1680  dbgprintf(insn, "readVVVV()");
1681 
1682  int vvvv;
1683  if (insn->vectorExtensionType == TYPE_EVEX)
1684  vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1686  else if (insn->vectorExtensionType == TYPE_VEX_3B)
1687  vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1688  else if (insn->vectorExtensionType == TYPE_VEX_2B)
1689  vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1690  else if (insn->vectorExtensionType == TYPE_XOP)
1691  vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1692  else
1693  return -1;
1694 
1695  if (insn->mode != MODE_64BIT)
1696  vvvv &= 0x7;
1697 
1698  insn->vvvv = static_cast<Reg>(vvvv);
1699  return 0;
1700 }
1701 
1702 /*
1703  * readMaskRegister - Reads an mask register from the opcode field of an
1704  * instruction.
1705  *
1706  * @param insn - The instruction whose opcode field is to be read.
1707  * @return - 0 on success; nonzero otherwise.
1708  */
1709 static int readMaskRegister(struct InternalInstruction* insn) {
1710  dbgprintf(insn, "readMaskRegister()");
1711 
1712  if (insn->vectorExtensionType != TYPE_EVEX)
1713  return -1;
1714 
1715  insn->writemask =
1716  static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1717  return 0;
1718 }
1719 
1720 /*
1721  * readOperands - Consults the specifier for an instruction and consumes all
1722  * operands for that instruction, interpreting them as it goes.
1723  *
1724  * @param insn - The instruction whose operands are to be read and interpreted.
1725  * @return - 0 if all operands could be read; nonzero otherwise.
1726  */
1727 static int readOperands(struct InternalInstruction* insn) {
1728  int hasVVVV, needVVVV;
1729  int sawRegImm = 0;
1730 
1731  dbgprintf(insn, "readOperands()");
1732 
1733  /* If non-zero vvvv specified, need to make sure one of the operands
1734  uses it. */
1735  hasVVVV = !readVVVV(insn);
1736  needVVVV = hasVVVV && (insn->vvvv != 0);
1737 
1738  for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1739  switch (Op.encoding) {
1740  case ENCODING_NONE:
1741  case ENCODING_SI:
1742  case ENCODING_DI:
1743  break;
1745  // VSIB can use the V2 bit so check only the other bits.
1746  if (needVVVV)
1747  needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1748  if (readModRM(insn))
1749  return -1;
1750 
1751  // Reject if SIB wasn't used.
1752  if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1753  return -1;
1754 
1755  // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1756  if (insn->sibIndex == SIB_INDEX_NONE)
1757  insn->sibIndex = (SIBIndex)4;
1758 
1759  // If EVEX.v2 is set this is one of the 16-31 registers.
1760  if (insn->vectorExtensionType == TYPE_EVEX &&
1762  insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1763 
1764  // Adjust the index register to the correct size.
1765  switch ((OperandType)Op.type) {
1766  default:
1767  debug("Unhandled VSIB index type");
1768  return -1;
1769  case TYPE_MVSIBX:
1770  insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 +
1771  (insn->sibIndex - insn->sibIndexBase));
1772  break;
1773  case TYPE_MVSIBY:
1774  insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 +
1775  (insn->sibIndex - insn->sibIndexBase));
1776  break;
1777  case TYPE_MVSIBZ:
1778  insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 +
1779  (insn->sibIndex - insn->sibIndexBase));
1780  break;
1781  }
1782 
1783  // Apply the AVX512 compressed displacement scaling factor.
1784  if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1785  insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1786  break;
1787  case ENCODING_REG:
1789  if (readModRM(insn))
1790  return -1;
1791  if (fixupReg(insn, &Op))
1792  return -1;
1793  // Apply the AVX512 compressed displacement scaling factor.
1794  if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1795  insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1796  break;
1797  case ENCODING_IB:
1798  if (sawRegImm) {
1799  /* Saw a register immediate so don't read again and instead split the
1800  previous immediate. FIXME: This is a hack. */
1801  insn->immediates[insn->numImmediatesConsumed] =
1802  insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1803  ++insn->numImmediatesConsumed;
1804  break;
1805  }
1806  if (readImmediate(insn, 1))
1807  return -1;
1808  if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1809  sawRegImm = 1;
1810  break;
1811  case ENCODING_IW:
1812  if (readImmediate(insn, 2))
1813  return -1;
1814  break;
1815  case ENCODING_ID:
1816  if (readImmediate(insn, 4))
1817  return -1;
1818  break;
1819  case ENCODING_IO:
1820  if (readImmediate(insn, 8))
1821  return -1;
1822  break;
1823  case ENCODING_Iv:
1824  if (readImmediate(insn, insn->immediateSize))
1825  return -1;
1826  break;
1827  case ENCODING_Ia:
1828  if (readImmediate(insn, insn->addressSize))
1829  return -1;
1830  break;
1831  case ENCODING_IRC:
1832  insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1834  break;
1835  case ENCODING_RB:
1836  if (readOpcodeRegister(insn, 1))
1837  return -1;
1838  break;
1839  case ENCODING_RW:
1840  if (readOpcodeRegister(insn, 2))
1841  return -1;
1842  break;
1843  case ENCODING_RD:
1844  if (readOpcodeRegister(insn, 4))
1845  return -1;
1846  break;
1847  case ENCODING_RO:
1848  if (readOpcodeRegister(insn, 8))
1849  return -1;
1850  break;
1851  case ENCODING_Rv:
1852  if (readOpcodeRegister(insn, 0))
1853  return -1;
1854  break;
1855  case ENCODING_FP:
1856  break;
1857  case ENCODING_VVVV:
1858  needVVVV = 0; /* Mark that we have found a VVVV operand. */
1859  if (!hasVVVV)
1860  return -1;
1861  if (fixupReg(insn, &Op))
1862  return -1;
1863  break;
1864  case ENCODING_WRITEMASK:
1865  if (readMaskRegister(insn))
1866  return -1;
1867  break;
1868  case ENCODING_DUP:
1869  break;
1870  default:
1871  dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1872  return -1;
1873  }
1874  }
1875 
1876  /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1877  if (needVVVV) return -1;
1878 
1879  return 0;
1880 }
1881 
1882 /*
1883  * decodeInstruction - Reads and interprets a full instruction provided by the
1884  * user.
1885  *
1886  * @param insn - A pointer to the instruction to be populated. Must be
1887  * pre-allocated.
1888  * @param reader - The function to be used to read the instruction's bytes.
1889  * @param readerArg - A generic argument to be passed to the reader to store
1890  * any internal state.
1891  * @param logger - If non-NULL, the function to be used to write log messages
1892  * and warnings.
1893  * @param loggerArg - A generic argument to be passed to the logger to store
1894  * any internal state.
1895  * @param startLoc - The address (in the reader's address space) of the first
1896  * byte in the instruction.
1897  * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1898  * decode the instruction in.
1899  * @return - 0 if the instruction's memory could be read; nonzero if
1900  * not.
1901  */
1903  struct InternalInstruction *insn, byteReader_t reader,
1904  const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1905  uint64_t startLoc, DisassemblerMode mode) {
1906  memset(insn, 0, sizeof(struct InternalInstruction));
1907 
1908  insn->reader = reader;
1909  insn->readerArg = readerArg;
1910  insn->dlog = logger;
1911  insn->dlogArg = loggerArg;
1912  insn->startLocation = startLoc;
1913  insn->readerCursor = startLoc;
1914  insn->mode = mode;
1915  insn->numImmediatesConsumed = 0;
1916 
1917  if (readPrefixes(insn) ||
1918  readOpcode(insn) ||
1919  getID(insn, miiArg) ||
1920  insn->instructionID == 0 ||
1921  readOperands(insn))
1922  return -1;
1923 
1924  insn->operands = x86OperandSets[insn->spec->operands];
1925 
1926  insn->length = insn->readerCursor - insn->startLocation;
1927 
1928  dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1929  startLoc, insn->readerCursor, insn->length);
1930 
1931  if (insn->length > 15)
1932  dbgprintf(insn, "Instruction exceeds 15-byte limit");
1933 
1934  return 0;
1935 }
#define bFromEVEX4of4(evex)
static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix)
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
#define rFromREX(rex)
#define XOP9_MAP_SYM
#define wFromEVEX3of4(evex)
The specification for how to extract and interpret a full instruction and its operands.
#define bFromVEX2of3(vex)
static int consumeByte(struct InternalInstruction *insn, uint8_t *byte)
int(* byteReader_t)(const void *arg, uint8_t *byte, uint64_t address)
Type for the byte reader that the consumer must provide to the decoder.
#define rmFromModRM(modRM)
static int readSIB(struct InternalInstruction *insn)
#define zFromEVEX4of4(evex)
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
#define vvvvFromVEX2of2(vex)
#define vvvvFromEVEX3of4(evex)
static int readDisplacement(struct InternalInstruction *insn)
#define r2FromEVEX2of4(evex)
#define op(i)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
#define aaaFromEVEX4of4(evex)
amode Optimize addressing mode
#define bFromEVEX2of4(evex)
SIBIndex
All possible values of the SIB index field.
static int readOpcode(struct InternalInstruction *insn)
#define rFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define rFromVEX2of2(vex)
Reg
All possible values of the reg field in the ModR/M byte.
#define lFromVEX2of2(vex)
static int readVVVV(struct InternalInstruction *insn)
static int lookAtByte(struct InternalInstruction *insn, uint8_t *byte)
#define xFromXOP2of3(xop)
#define v2FromEVEX4of4(evex)
static int getID(struct InternalInstruction *insn, const void *miiArg)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
#define THREEDNOW_MAP_SYM
ModRMDecision modRMDecisions[256]
static void unconsumeByte(struct InternalInstruction *insn)
#define ppFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
EABase
All possible values of the base field for effective-address computations, a.k.a.
#define vvvvFromVEX3of3(vex)
The specification for how to extract and interpret one operand.
static bool is64Bit(const char *name)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
#define CASE_ENCODING_RM
#define bFromXOP2of3(xop)
#define baseFromSIB(sib)
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
#define wFromREX(rex)
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
#define lFromVEX3of3(vex)
#define ppFromVEX2of2(vex)
static int modRMRequired(OpcodeType type, InstructionContext insnContext, uint16_t opcode)
The x86 internal instruction, which is produced by the decoder.
static int readPrefixes(struct InternalInstruction *insn)
#define THREEBYTE3A_SYM
static void dbgprintf(struct InternalInstruction *insn, const char *format,...)
StringRef GetInstrName(unsigned Opcode, const void *mii)
#define ONEBYTE_SYM
#define lFromXOP3of3(xop)
#define bFromREX(rex)
#define mmmmmFromVEX2of3(vex)
#define ppFromEVEX3of4(evex)
#define scaleFromSIB(sib)
static int readOperands(struct InternalInstruction *insn)
#define xFromVEX2of3(vex)
static bool is16BitEquivalent(const char *orig, const char *equiv)
#define rFromXOP2of3(xop)
#define CONSUME_FUNC(name, type)
#define INSTRUCTIONS_SYM
#define THREEBYTE38_SYM
#define TWOBYTE_SYM
#define CASE_ENCODING_VSIB
static bool isPrefix(const IndicesVector &Prefix, const IndicesVector &Longer)
Returns true if Prefix is a prefix of longer.
#define lFromEVEX4of4(evex)
static InstructionContext contextForAttrs(uint16_t attrMask)
#define l2FromEVEX4of4(evex)
#define wFromVEX3of3(vex)
#define wFromXOP3of3(xop)
#define debug(s)
#define xFromREX(rex)
#define indexFromSIB(sib)
SIBBase
All possible values of the SIB base field.
static int readModRM(struct InternalInstruction *insn)
#define mmFromEVEX2of4(evex)
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
#define XOP8_MAP_SYM
#define rFromVEX2of3(vex)
Specifies which opcode->instruction tables to look at given a particular context (set of attributes)...
#define regFromModRM(modRM)
static const struct InstructionSpecifier * specifierForUID(InstrUID uid)
#define modFromModRM(modRM)
OpcodeDecision opcodeDecisions[IC_max]
static int readMaskRegister(struct InternalInstruction *insn)
aarch64 promote const
static const char * name
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
#define XOPA_MAP_SYM
#define CONTEXTS_SYM
#define vvvvFromXOP3of3(vex)
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int getIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
#define ppFromXOP3of3(xop)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
Specifies which set of ModR/M->instruction tables to look at given a particular opcode.
DisassemblerMode
Decoding mode for the Intel disassembler.
Specifies whether a ModR/M byte is needed and (if so) which instruction each possible value of the Mo...