LLVM 19.0.0git
X86Disassembler.cpp
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1//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the X86 Disassembler.
10// It contains code to translate the data produced by the decoder into
11// MCInsts.
12//
13//
14// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15// 64-bit X86 instruction sets. The main decode sequence for an assembly
16// instruction in this disassembler is:
17//
18// 1. Read the prefix bytes and determine the attributes of the instruction.
19// These attributes, recorded in enum attributeBits
20// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
21// provides a mapping from bitmasks to contexts, which are represented by
22// enum InstructionContext (ibid.).
23//
24// 2. Read the opcode, and determine what kind of opcode it is. The
25// disassembler distinguishes four kinds of opcodes, which are enumerated in
26// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
27// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
28// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
29//
30// 3. Depending on the opcode type, look in one of four ClassDecision structures
31// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
32// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
33// a ModRMDecision (ibid.).
34//
35// 4. Some instructions, such as escape opcodes or extended opcodes, or even
36// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
37// ModR/M byte to complete decode. The ModRMDecision's type is an entry from
38// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
39// ModR/M byte is required and how to interpret it.
40//
41// 5. After resolving the ModRMDecision, the disassembler has a unique ID
42// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
43// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
44// meanings of its operands.
45//
46// 6. For each operand, its encoding is an entry from OperandEncoding
47// (X86DisassemblerDecoderCommon.h) and its type is an entry from
48// OperandType (ibid.). The encoding indicates how to read it from the
49// instruction; the type indicates how to interpret the value once it has
50// been read. For example, a register operand could be stored in the R/M
51// field of the ModR/M byte, the REG field of the ModR/M byte, or added to
52// the main opcode. This is orthogonal from its meaning (an GPR or an XMM
53// register, for instance). Given this information, the operands can be
54// extracted and interpreted.
55//
56// 7. As the last step, the disassembler translates the instruction information
57// and operands into a format understandable by the client - in this case, an
58// MCInst for use by the MC infrastructure.
59//
60// The disassembler is broken broadly into two parts: the table emitter that
61// emits the instruction decode tables discussed above during compilation, and
62// the disassembler itself. The table emitter is documented in more detail in
63// utils/TableGen/X86DisassemblerEmitter.h.
64//
65// X86Disassembler.cpp contains the code responsible for step 7, and for
66// invoking the decoder to execute steps 1-6.
67// X86DisassemblerDecoderCommon.h contains the definitions needed by both the
68// table emitter and the disassembler.
69// X86DisassemblerDecoder.h contains the public interface of the decoder,
70// factored out into C for possible use by other projects.
71// X86DisassemblerDecoder.c contains the source code of the decoder, which is
72// responsible for steps 1-6.
73//
74//===----------------------------------------------------------------------===//
75
80#include "llvm/MC/MCContext.h"
82#include "llvm/MC/MCExpr.h"
83#include "llvm/MC/MCInst.h"
84#include "llvm/MC/MCInstrInfo.h"
87#include "llvm/Support/Debug.h"
88#include "llvm/Support/Format.h"
90
91using namespace llvm;
92using namespace llvm::X86Disassembler;
93
94#define DEBUG_TYPE "x86-disassembler"
95
96#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
97
98// Specifies whether a ModR/M byte is needed and (if so) which
99// instruction each possible value of the ModR/M byte corresponds to. Once
100// this information is known, we have narrowed down to a single instruction.
102 uint8_t modrm_type;
104};
105
106// Specifies which set of ModR/M->instruction tables to look at
107// given a particular opcode.
110};
111
112// Specifies which opcode->instruction tables to look at given
113// a particular context (set of attributes). Since there are many possible
114// contexts, the decoder first uses CONTEXTS_SYM to determine which context
115// applies given a specific set of attributes. Hence there are only IC_max
116// entries in this table, rather than 2^(ATTR_max).
119};
120
121#include "X86GenDisassemblerTables.inc"
122
124 uint8_t opcode, uint8_t modRM) {
125 const struct ModRMDecision *dec;
126
127 switch (type) {
128 case ONEBYTE:
129 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
130 break;
131 case TWOBYTE:
132 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 break;
134 case THREEBYTE_38:
135 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 break;
137 case THREEBYTE_3A:
138 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 break;
140 case XOP8_MAP:
141 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
142 break;
143 case XOP9_MAP:
144 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
145 break;
146 case XOPA_MAP:
147 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
148 break;
149 case THREEDNOW_MAP:
150 dec =
151 &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152 break;
153 case MAP4:
154 dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155 break;
156 case MAP5:
157 dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
158 break;
159 case MAP6:
160 dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
161 break;
162 case MAP7:
163 dec = &MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
164 break;
165 }
166
167 switch (dec->modrm_type) {
168 default:
169 llvm_unreachable("Corrupt table! Unknown modrm_type");
170 return 0;
171 case MODRM_ONEENTRY:
172 return modRMTable[dec->instructionIDs];
173 case MODRM_SPLITRM:
174 if (modFromModRM(modRM) == 0x3)
175 return modRMTable[dec->instructionIDs + 1];
176 return modRMTable[dec->instructionIDs];
177 case MODRM_SPLITREG:
178 if (modFromModRM(modRM) == 0x3)
179 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
180 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
181 case MODRM_SPLITMISC:
182 if (modFromModRM(modRM) == 0x3)
183 return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
184 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
185 case MODRM_FULL:
186 return modRMTable[dec->instructionIDs + modRM];
187 }
188}
189
190static bool peek(struct InternalInstruction *insn, uint8_t &byte) {
191 uint64_t offset = insn->readerCursor - insn->startLocation;
192 if (offset >= insn->bytes.size())
193 return true;
194 byte = insn->bytes[offset];
195 return false;
196}
197
198template <typename T> static bool consume(InternalInstruction *insn, T &ptr) {
199 auto r = insn->bytes;
200 uint64_t offset = insn->readerCursor - insn->startLocation;
201 if (offset + sizeof(T) > r.size())
202 return true;
203 ptr = support::endian::read<T>(&r[offset], llvm::endianness::little);
204 insn->readerCursor += sizeof(T);
205 return false;
206}
207
208static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
209 return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
210}
211
212static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) {
213 return insn->mode == MODE_64BIT && prefix == 0xd5;
214}
215
216// Consumes all of an instruction's prefix bytes, and marks the
217// instruction as having them. Also sets the instruction's default operand,
218// address, and other relevant data sizes to report operands correctly.
219//
220// insn must not be empty.
221static int readPrefixes(struct InternalInstruction *insn) {
222 bool isPrefix = true;
223 uint8_t byte = 0;
224 uint8_t nextByte;
225
226 LLVM_DEBUG(dbgs() << "readPrefixes()");
227
228 while (isPrefix) {
229 // If we fail reading prefixes, just stop here and let the opcode reader
230 // deal with it.
231 if (consume(insn, byte))
232 break;
233
234 // If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
235 // break and let it be disassembled as a normal "instruction".
236 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
237 break;
238
239 if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) {
240 // If the byte is 0xf2 or 0xf3, and any of the following conditions are
241 // met:
242 // - it is followed by a LOCK (0xf0) prefix
243 // - it is followed by an xchg instruction
244 // then it should be disassembled as a xacquire/xrelease not repne/rep.
245 if (((nextByte == 0xf0) ||
246 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
247 insn->xAcquireRelease = true;
248 if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
249 break;
250 }
251 // Also if the byte is 0xf3, and the following condition is met:
252 // - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
253 // "mov mem, imm" (opcode 0xc6/0xc7) instructions.
254 // then it should be disassembled as an xrelease not rep.
255 if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
256 nextByte == 0xc6 || nextByte == 0xc7)) {
257 insn->xAcquireRelease = true;
258 break;
259 }
260 if (isREX(insn, nextByte)) {
261 uint8_t nnextByte;
262 // Go to REX prefix after the current one
263 if (consume(insn, nnextByte))
264 return -1;
265 // We should be able to read next byte after REX prefix
266 if (peek(insn, nnextByte))
267 return -1;
268 --insn->readerCursor;
269 }
270 }
271
272 switch (byte) {
273 case 0xf0: // LOCK
274 insn->hasLockPrefix = true;
275 break;
276 case 0xf2: // REPNE/REPNZ
277 case 0xf3: { // REP or REPE/REPZ
278 uint8_t nextByte;
279 if (peek(insn, nextByte))
280 break;
281 // TODO:
282 // 1. There could be several 0x66
283 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
284 // it's not mandatory prefix
285 // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
286 // 0x0f exactly after it to be mandatory prefix
287 if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
288 // The last of 0xf2 /0xf3 is mandatory prefix
289 insn->mandatoryPrefix = byte;
290 insn->repeatPrefix = byte;
291 break;
292 }
293 case 0x2e: // CS segment override -OR- Branch not taken
295 break;
296 case 0x36: // SS segment override -OR- Branch taken
298 break;
299 case 0x3e: // DS segment override
301 break;
302 case 0x26: // ES segment override
304 break;
305 case 0x64: // FS segment override
307 break;
308 case 0x65: // GS segment override
310 break;
311 case 0x66: { // Operand-size override {
312 uint8_t nextByte;
313 insn->hasOpSize = true;
314 if (peek(insn, nextByte))
315 break;
316 // 0x66 can't overwrite existing mandatory prefix and should be ignored
317 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
318 insn->mandatoryPrefix = byte;
319 break;
320 }
321 case 0x67: // Address-size override
322 insn->hasAdSize = true;
323 break;
324 default: // Not a prefix byte
325 isPrefix = false;
326 break;
327 }
328
329 if (isPrefix)
330 LLVM_DEBUG(dbgs() << format("Found prefix 0x%hhx", byte));
331 }
332
334
335 if (byte == 0x62) {
336 uint8_t byte1, byte2;
337 if (consume(insn, byte1)) {
338 LLVM_DEBUG(dbgs() << "Couldn't read second byte of EVEX prefix");
339 return -1;
340 }
341
342 if (peek(insn, byte2)) {
343 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
344 return -1;
345 }
346
347 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) {
349 } else {
350 --insn->readerCursor; // unconsume byte1
351 --insn->readerCursor; // unconsume byte
352 }
353
354 if (insn->vectorExtensionType == TYPE_EVEX) {
355 insn->vectorExtensionPrefix[0] = byte;
356 insn->vectorExtensionPrefix[1] = byte1;
357 if (consume(insn, insn->vectorExtensionPrefix[2])) {
358 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
359 return -1;
360 }
361 if (consume(insn, insn->vectorExtensionPrefix[3])) {
362 LLVM_DEBUG(dbgs() << "Couldn't read fourth byte of EVEX prefix");
363 return -1;
364 }
365
366 if (insn->mode == MODE_64BIT) {
367 // We simulate the REX prefix for simplicity's sake
368 insn->rexPrefix = 0x40 |
369 (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) |
370 (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) |
371 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) |
372 (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
373
374 // We simulate the REX2 prefix for simplicity's sake
375 insn->rex2ExtensionPrefix[1] =
376 (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) |
377 (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) |
378 (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4);
379 }
380
382 dbgs() << format(
383 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
385 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]));
386 }
387 } else if (byte == 0xc4) {
388 uint8_t byte1;
389 if (peek(insn, byte1)) {
390 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
391 return -1;
392 }
393
394 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
396 else
397 --insn->readerCursor;
398
399 if (insn->vectorExtensionType == TYPE_VEX_3B) {
400 insn->vectorExtensionPrefix[0] = byte;
401 consume(insn, insn->vectorExtensionPrefix[1]);
402 consume(insn, insn->vectorExtensionPrefix[2]);
403
404 // We simulate the REX prefix for simplicity's sake
405
406 if (insn->mode == MODE_64BIT)
407 insn->rexPrefix = 0x40 |
408 (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) |
409 (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) |
410 (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) |
411 (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
412
413 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
414 insn->vectorExtensionPrefix[0],
415 insn->vectorExtensionPrefix[1],
416 insn->vectorExtensionPrefix[2]));
417 }
418 } else if (byte == 0xc5) {
419 uint8_t byte1;
420 if (peek(insn, byte1)) {
421 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
422 return -1;
423 }
424
425 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
427 else
428 --insn->readerCursor;
429
430 if (insn->vectorExtensionType == TYPE_VEX_2B) {
431 insn->vectorExtensionPrefix[0] = byte;
432 consume(insn, insn->vectorExtensionPrefix[1]);
433
434 if (insn->mode == MODE_64BIT)
435 insn->rexPrefix =
436 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
437
438 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
439 default:
440 break;
441 case VEX_PREFIX_66:
442 insn->hasOpSize = true;
443 break;
444 }
445
446 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx",
447 insn->vectorExtensionPrefix[0],
448 insn->vectorExtensionPrefix[1]));
449 }
450 } else if (byte == 0x8f) {
451 uint8_t byte1;
452 if (peek(insn, byte1)) {
453 LLVM_DEBUG(dbgs() << "Couldn't read second byte of XOP");
454 return -1;
455 }
456
457 if ((byte1 & 0x38) != 0x0) // 0 in these 3 bits is a POP instruction.
459 else
460 --insn->readerCursor;
461
462 if (insn->vectorExtensionType == TYPE_XOP) {
463 insn->vectorExtensionPrefix[0] = byte;
464 consume(insn, insn->vectorExtensionPrefix[1]);
465 consume(insn, insn->vectorExtensionPrefix[2]);
466
467 // We simulate the REX prefix for simplicity's sake
468
469 if (insn->mode == MODE_64BIT)
470 insn->rexPrefix = 0x40 |
471 (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) |
472 (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) |
473 (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) |
474 (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
475
476 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
477 default:
478 break;
479 case VEX_PREFIX_66:
480 insn->hasOpSize = true;
481 break;
482 }
483
484 LLVM_DEBUG(dbgs() << format("Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
485 insn->vectorExtensionPrefix[0],
486 insn->vectorExtensionPrefix[1],
487 insn->vectorExtensionPrefix[2]));
488 }
489 } else if (isREX2(insn, byte)) {
490 uint8_t byte1;
491 if (peek(insn, byte1)) {
492 LLVM_DEBUG(dbgs() << "Couldn't read second byte of REX2");
493 return -1;
494 }
495 insn->rex2ExtensionPrefix[0] = byte;
496 consume(insn, insn->rex2ExtensionPrefix[1]);
497
498 // We simulate the REX prefix for simplicity's sake
499 insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) |
500 (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) |
501 (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) |
502 (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0);
503 LLVM_DEBUG(dbgs() << format("Found REX2 prefix 0x%hhx 0x%hhx",
504 insn->rex2ExtensionPrefix[0],
505 insn->rex2ExtensionPrefix[1]));
506 } else if (isREX(insn, byte)) {
507 if (peek(insn, nextByte))
508 return -1;
509 insn->rexPrefix = byte;
510 LLVM_DEBUG(dbgs() << format("Found REX prefix 0x%hhx", byte));
511 } else
512 --insn->readerCursor;
513
514 if (insn->mode == MODE_16BIT) {
515 insn->registerSize = (insn->hasOpSize ? 4 : 2);
516 insn->addressSize = (insn->hasAdSize ? 4 : 2);
517 insn->displacementSize = (insn->hasAdSize ? 4 : 2);
518 insn->immediateSize = (insn->hasOpSize ? 4 : 2);
519 } else if (insn->mode == MODE_32BIT) {
520 insn->registerSize = (insn->hasOpSize ? 2 : 4);
521 insn->addressSize = (insn->hasAdSize ? 2 : 4);
522 insn->displacementSize = (insn->hasAdSize ? 2 : 4);
523 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
524 } else if (insn->mode == MODE_64BIT) {
525 insn->displacementSize = 4;
526 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
527 insn->registerSize = 8;
528 insn->addressSize = (insn->hasAdSize ? 4 : 8);
529 insn->immediateSize = 4;
530 insn->hasOpSize = false;
531 } else {
532 insn->registerSize = (insn->hasOpSize ? 2 : 4);
533 insn->addressSize = (insn->hasAdSize ? 4 : 8);
534 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
535 }
536 }
537
538 return 0;
539}
540
541// Consumes the SIB byte to determine addressing information.
542static int readSIB(struct InternalInstruction *insn) {
543 SIBBase sibBaseBase = SIB_BASE_NONE;
544 uint8_t index, base;
545
546 LLVM_DEBUG(dbgs() << "readSIB()");
547 switch (insn->addressSize) {
548 case 2:
549 default:
550 llvm_unreachable("SIB-based addressing doesn't work in 16-bit mode");
551 case 4:
552 insn->sibIndexBase = SIB_INDEX_EAX;
553 sibBaseBase = SIB_BASE_EAX;
554 break;
555 case 8:
556 insn->sibIndexBase = SIB_INDEX_RAX;
557 sibBaseBase = SIB_BASE_RAX;
558 break;
559 }
560
561 if (consume(insn, insn->sib))
562 return -1;
563
564 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) |
565 (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
566
567 if (index == 0x4) {
568 insn->sibIndex = SIB_INDEX_NONE;
569 } else {
570 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
571 }
572
573 insn->sibScale = 1 << scaleFromSIB(insn->sib);
574
575 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) |
576 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
577
578 switch (base) {
579 case 0x5:
580 case 0xd:
581 switch (modFromModRM(insn->modRM)) {
582 case 0x0:
584 insn->sibBase = SIB_BASE_NONE;
585 break;
586 case 0x1:
588 insn->sibBase = (SIBBase)(sibBaseBase + base);
589 break;
590 case 0x2:
592 insn->sibBase = (SIBBase)(sibBaseBase + base);
593 break;
594 default:
595 llvm_unreachable("Cannot have Mod = 0b11 and a SIB byte");
596 }
597 break;
598 default:
599 insn->sibBase = (SIBBase)(sibBaseBase + base);
600 break;
601 }
602
603 return 0;
604}
605
606static int readDisplacement(struct InternalInstruction *insn) {
607 int8_t d8;
608 int16_t d16;
609 int32_t d32;
610 LLVM_DEBUG(dbgs() << "readDisplacement()");
611
612 insn->displacementOffset = insn->readerCursor - insn->startLocation;
613 switch (insn->eaDisplacement) {
614 case EA_DISP_NONE:
615 break;
616 case EA_DISP_8:
617 if (consume(insn, d8))
618 return -1;
619 insn->displacement = d8;
620 break;
621 case EA_DISP_16:
622 if (consume(insn, d16))
623 return -1;
624 insn->displacement = d16;
625 break;
626 case EA_DISP_32:
627 if (consume(insn, d32))
628 return -1;
629 insn->displacement = d32;
630 break;
631 }
632
633 return 0;
634}
635
636// Consumes all addressing information (ModR/M byte, SIB byte, and displacement.
637static int readModRM(struct InternalInstruction *insn) {
638 uint8_t mod, rm, reg;
639 LLVM_DEBUG(dbgs() << "readModRM()");
640
641 if (insn->consumedModRM)
642 return 0;
643
644 if (consume(insn, insn->modRM))
645 return -1;
646 insn->consumedModRM = true;
647
648 mod = modFromModRM(insn->modRM);
649 rm = rmFromModRM(insn->modRM);
650 reg = regFromModRM(insn->modRM);
651
652 // This goes by insn->registerSize to pick the correct register, which messes
653 // up if we're using (say) XMM or 8-bit register operands. That gets fixed in
654 // fixupReg().
655 switch (insn->registerSize) {
656 case 2:
657 insn->regBase = MODRM_REG_AX;
658 insn->eaRegBase = EA_REG_AX;
659 break;
660 case 4:
661 insn->regBase = MODRM_REG_EAX;
662 insn->eaRegBase = EA_REG_EAX;
663 break;
664 case 8:
665 insn->regBase = MODRM_REG_RAX;
666 insn->eaRegBase = EA_REG_RAX;
667 break;
668 }
669
670 reg |= (rFromREX(insn->rexPrefix) << 3) |
671 (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
672 rm |= (bFromREX(insn->rexPrefix) << 3) |
673 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
674
675 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT)
676 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
677
678 insn->reg = (Reg)(insn->regBase + reg);
679
680 switch (insn->addressSize) {
681 case 2: {
682 EABase eaBaseBase = EA_BASE_BX_SI;
683
684 switch (mod) {
685 case 0x0:
686 if (rm == 0x6) {
687 insn->eaBase = EA_BASE_NONE;
689 if (readDisplacement(insn))
690 return -1;
691 } else {
692 insn->eaBase = (EABase)(eaBaseBase + rm);
694 }
695 break;
696 case 0x1:
697 insn->eaBase = (EABase)(eaBaseBase + rm);
699 insn->displacementSize = 1;
700 if (readDisplacement(insn))
701 return -1;
702 break;
703 case 0x2:
704 insn->eaBase = (EABase)(eaBaseBase + rm);
706 if (readDisplacement(insn))
707 return -1;
708 break;
709 case 0x3:
710 insn->eaBase = (EABase)(insn->eaRegBase + rm);
711 if (readDisplacement(insn))
712 return -1;
713 break;
714 }
715 break;
716 }
717 case 4:
718 case 8: {
719 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
720
721 switch (mod) {
722 case 0x0:
723 insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this
724 // In determining whether RIP-relative mode is used (rm=5),
725 // or whether a SIB byte is present (rm=4),
726 // the extension bits (REX.b and EVEX.x) are ignored.
727 switch (rm & 7) {
728 case 0x4: // SIB byte is present
729 insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64);
730 if (readSIB(insn) || readDisplacement(insn))
731 return -1;
732 break;
733 case 0x5: // RIP-relative
734 insn->eaBase = EA_BASE_NONE;
736 if (readDisplacement(insn))
737 return -1;
738 break;
739 default:
740 insn->eaBase = (EABase)(eaBaseBase + rm);
741 break;
742 }
743 break;
744 case 0x1:
745 insn->displacementSize = 1;
746 [[fallthrough]];
747 case 0x2:
748 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
749 switch (rm & 7) {
750 case 0x4: // SIB byte is present
751 insn->eaBase = EA_BASE_sib;
752 if (readSIB(insn) || readDisplacement(insn))
753 return -1;
754 break;
755 default:
756 insn->eaBase = (EABase)(eaBaseBase + rm);
757 if (readDisplacement(insn))
758 return -1;
759 break;
760 }
761 break;
762 case 0x3:
764 insn->eaBase = (EABase)(insn->eaRegBase + rm);
765 break;
766 }
767 break;
768 }
769 } // switch (insn->addressSize)
770
771 return 0;
772}
773
774#define GENERIC_FIXUP_FUNC(name, base, prefix) \
775 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
776 uint8_t index, uint8_t *valid) { \
777 *valid = 1; \
778 switch (type) { \
779 default: \
780 debug("Unhandled register type"); \
781 *valid = 0; \
782 return 0; \
783 case TYPE_Rv: \
784 return base + index; \
785 case TYPE_R8: \
786 if (insn->rexPrefix && index >= 4 && index <= 7) \
787 return prefix##_SPL + (index - 4); \
788 else \
789 return prefix##_AL + index; \
790 case TYPE_R16: \
791 return prefix##_AX + index; \
792 case TYPE_R32: \
793 return prefix##_EAX + index; \
794 case TYPE_R64: \
795 return prefix##_RAX + index; \
796 case TYPE_ZMM: \
797 return prefix##_ZMM0 + index; \
798 case TYPE_YMM: \
799 return prefix##_YMM0 + index; \
800 case TYPE_XMM: \
801 return prefix##_XMM0 + index; \
802 case TYPE_TMM: \
803 if (index > 7) \
804 *valid = 0; \
805 return prefix##_TMM0 + index; \
806 case TYPE_VK: \
807 index &= 0xf; \
808 if (index > 7) \
809 *valid = 0; \
810 return prefix##_K0 + index; \
811 case TYPE_VK_PAIR: \
812 if (index > 7) \
813 *valid = 0; \
814 return prefix##_K0_K1 + (index / 2); \
815 case TYPE_MM64: \
816 return prefix##_MM0 + (index & 0x7); \
817 case TYPE_SEGMENTREG: \
818 if ((index & 7) > 5) \
819 *valid = 0; \
820 return prefix##_ES + (index & 7); \
821 case TYPE_DEBUGREG: \
822 if (index > 15) \
823 *valid = 0; \
824 return prefix##_DR0 + index; \
825 case TYPE_CONTROLREG: \
826 if (index > 15) \
827 *valid = 0; \
828 return prefix##_CR0 + index; \
829 case TYPE_MVSIBX: \
830 return prefix##_XMM0 + index; \
831 case TYPE_MVSIBY: \
832 return prefix##_YMM0 + index; \
833 case TYPE_MVSIBZ: \
834 return prefix##_ZMM0 + index; \
835 } \
836 }
837
838// Consult an operand type to determine the meaning of the reg or R/M field. If
839// the operand is an XMM operand, for example, an operand would be XMM0 instead
840// of AX, which readModRM() would otherwise misinterpret it as.
841//
842// @param insn - The instruction containing the operand.
843// @param type - The operand type.
844// @param index - The existing value of the field as reported by readModRM().
845// @param valid - The address of a uint8_t. The target is set to 1 if the
846// field is valid for the register class; 0 if not.
847// @return - The proper value.
848GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
849GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
850
851// Consult an operand specifier to determine which of the fixup*Value functions
852// to use in correcting readModRM()'ss interpretation.
853//
854// @param insn - See fixup*Value().
855// @param op - The operand specifier.
856// @return - 0 if fixup was successful; -1 if the register returned was
857// invalid for its class.
858static int fixupReg(struct InternalInstruction *insn,
859 const struct OperandSpecifier *op) {
860 uint8_t valid;
861 LLVM_DEBUG(dbgs() << "fixupReg()");
862
863 switch ((OperandEncoding)op->encoding) {
864 default:
865 debug("Expected a REG or R/M encoding in fixupReg");
866 return -1;
867 case ENCODING_VVVV:
868 insn->vvvv =
869 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
870 if (!valid)
871 return -1;
872 break;
873 case ENCODING_REG:
874 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type,
875 insn->reg - insn->regBase, &valid);
876 if (!valid)
877 return -1;
878 break;
880 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
881 modFromModRM(insn->modRM) == 3) {
882 // EVEX_X can extend the register id to 32 for a non-GPR register that is
883 // encoded in RM.
884 // mode : MODE_64_BIT
885 // Only 8 vector registers are available in 32 bit mode
886 // mod : 3
887 // RM encodes a register
888 switch (op->type) {
889 case TYPE_Rv:
890 case TYPE_R8:
891 case TYPE_R16:
892 case TYPE_R32:
893 case TYPE_R64:
894 break;
895 default:
896 insn->eaBase =
897 (EABase)(insn->eaBase +
898 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4));
899 break;
900 }
901 }
902 [[fallthrough]];
903 case ENCODING_SIB:
904 if (insn->eaBase >= insn->eaRegBase) {
905 insn->eaBase = (EABase)fixupRMValue(
906 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid);
907 if (!valid)
908 return -1;
909 }
910 break;
911 }
912
913 return 0;
914}
915
916// Read the opcode (except the ModR/M byte in the case of extended or escape
917// opcodes).
918static bool readOpcode(struct InternalInstruction *insn) {
919 uint8_t current;
920 LLVM_DEBUG(dbgs() << "readOpcode()");
921
922 insn->opcodeType = ONEBYTE;
923 if (insn->vectorExtensionType == TYPE_EVEX) {
924 switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
925 default:
927 dbgs() << format("Unhandled mmm field for instruction (0x%hhx)",
929 return true;
930 case VEX_LOB_0F:
931 insn->opcodeType = TWOBYTE;
932 return consume(insn, insn->opcode);
933 case VEX_LOB_0F38:
934 insn->opcodeType = THREEBYTE_38;
935 return consume(insn, insn->opcode);
936 case VEX_LOB_0F3A:
937 insn->opcodeType = THREEBYTE_3A;
938 return consume(insn, insn->opcode);
939 case VEX_LOB_MAP4:
940 insn->opcodeType = MAP4;
941 return consume(insn, insn->opcode);
942 case VEX_LOB_MAP5:
943 insn->opcodeType = MAP5;
944 return consume(insn, insn->opcode);
945 case VEX_LOB_MAP6:
946 insn->opcodeType = MAP6;
947 return consume(insn, insn->opcode);
948 case VEX_LOB_MAP7:
949 insn->opcodeType = MAP7;
950 return consume(insn, insn->opcode);
951 }
952 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
953 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
954 default:
956 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
958 return true;
959 case VEX_LOB_0F:
960 insn->opcodeType = TWOBYTE;
961 return consume(insn, insn->opcode);
962 case VEX_LOB_0F38:
963 insn->opcodeType = THREEBYTE_38;
964 return consume(insn, insn->opcode);
965 case VEX_LOB_0F3A:
966 insn->opcodeType = THREEBYTE_3A;
967 return consume(insn, insn->opcode);
968 case VEX_LOB_MAP5:
969 insn->opcodeType = MAP5;
970 return consume(insn, insn->opcode);
971 case VEX_LOB_MAP6:
972 insn->opcodeType = MAP6;
973 return consume(insn, insn->opcode);
974 case VEX_LOB_MAP7:
975 insn->opcodeType = MAP7;
976 return consume(insn, insn->opcode);
977 }
978 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
979 insn->opcodeType = TWOBYTE;
980 return consume(insn, insn->opcode);
981 } else if (insn->vectorExtensionType == TYPE_XOP) {
982 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
983 default:
985 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
987 return true;
988 case XOP_MAP_SELECT_8:
989 insn->opcodeType = XOP8_MAP;
990 return consume(insn, insn->opcode);
991 case XOP_MAP_SELECT_9:
992 insn->opcodeType = XOP9_MAP;
993 return consume(insn, insn->opcode);
994 case XOP_MAP_SELECT_A:
995 insn->opcodeType = XOPA_MAP;
996 return consume(insn, insn->opcode);
997 }
998 } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) {
999 // m bit indicates opcode map 1
1000 insn->opcodeType = TWOBYTE;
1001 return consume(insn, insn->opcode);
1002 }
1003
1004 if (consume(insn, current))
1005 return true;
1006
1007 if (current == 0x0f) {
1008 LLVM_DEBUG(
1009 dbgs() << format("Found a two-byte escape prefix (0x%hhx)", current));
1010 if (consume(insn, current))
1011 return true;
1012
1013 if (current == 0x38) {
1014 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1015 current));
1016 if (consume(insn, current))
1017 return true;
1018
1019 insn->opcodeType = THREEBYTE_38;
1020 } else if (current == 0x3a) {
1021 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1022 current));
1023 if (consume(insn, current))
1024 return true;
1025
1026 insn->opcodeType = THREEBYTE_3A;
1027 } else if (current == 0x0f) {
1028 LLVM_DEBUG(
1029 dbgs() << format("Found a 3dnow escape prefix (0x%hhx)", current));
1030
1031 // Consume operands before the opcode to comply with the 3DNow encoding
1032 if (readModRM(insn))
1033 return true;
1034
1035 if (consume(insn, current))
1036 return true;
1037
1038 insn->opcodeType = THREEDNOW_MAP;
1039 } else {
1040 LLVM_DEBUG(dbgs() << "Didn't find a three-byte escape prefix");
1041 insn->opcodeType = TWOBYTE;
1042 }
1043 } else if (insn->mandatoryPrefix)
1044 // The opcode with mandatory prefix must start with opcode escape.
1045 // If not it's legacy repeat prefix
1046 insn->mandatoryPrefix = 0;
1047
1048 // At this point we have consumed the full opcode.
1049 // Anything we consume from here on must be unconsumed.
1050 insn->opcode = current;
1051
1052 return false;
1053}
1054
1055// Determine whether equiv is the 16-bit equivalent of orig (32-bit or 64-bit).
1056static bool is16BitEquivalent(const char *orig, const char *equiv) {
1057 for (int i = 0;; i++) {
1058 if (orig[i] == '\0' && equiv[i] == '\0')
1059 return true;
1060 if (orig[i] == '\0' || equiv[i] == '\0')
1061 return false;
1062 if (orig[i] != equiv[i]) {
1063 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
1064 continue;
1065 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
1066 continue;
1067 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
1068 continue;
1069 return false;
1070 }
1071 }
1072}
1073
1074// Determine whether this instruction is a 64-bit instruction.
1075static bool is64Bit(const char *name) {
1076 for (int i = 0;; ++i) {
1077 if (name[i] == '\0')
1078 return false;
1079 if (name[i] == '6' && name[i + 1] == '4')
1080 return true;
1081 }
1082}
1083
1084// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1085// for extended and escape opcodes, and using a supplied attribute mask.
1086static int getInstructionIDWithAttrMask(uint16_t *instructionID,
1087 struct InternalInstruction *insn,
1088 uint16_t attrMask) {
1089 auto insnCtx = InstructionContext(x86DisassemblerContexts[attrMask]);
1090 const ContextDecision *decision;
1091 switch (insn->opcodeType) {
1092 case ONEBYTE:
1093 decision = &ONEBYTE_SYM;
1094 break;
1095 case TWOBYTE:
1096 decision = &TWOBYTE_SYM;
1097 break;
1098 case THREEBYTE_38:
1099 decision = &THREEBYTE38_SYM;
1100 break;
1101 case THREEBYTE_3A:
1102 decision = &THREEBYTE3A_SYM;
1103 break;
1104 case XOP8_MAP:
1105 decision = &XOP8_MAP_SYM;
1106 break;
1107 case XOP9_MAP:
1108 decision = &XOP9_MAP_SYM;
1109 break;
1110 case XOPA_MAP:
1111 decision = &XOPA_MAP_SYM;
1112 break;
1113 case THREEDNOW_MAP:
1114 decision = &THREEDNOW_MAP_SYM;
1115 break;
1116 case MAP4:
1117 decision = &MAP4_SYM;
1118 break;
1119 case MAP5:
1120 decision = &MAP5_SYM;
1121 break;
1122 case MAP6:
1123 decision = &MAP6_SYM;
1124 break;
1125 case MAP7:
1126 decision = &MAP7_SYM;
1127 break;
1128 }
1129
1130 if (decision->opcodeDecisions[insnCtx]
1131 .modRMDecisions[insn->opcode]
1132 .modrm_type != MODRM_ONEENTRY) {
1133 if (readModRM(insn))
1134 return -1;
1135 *instructionID =
1136 decode(insn->opcodeType, insnCtx, insn->opcode, insn->modRM);
1137 } else {
1138 *instructionID = decode(insn->opcodeType, insnCtx, insn->opcode, 0);
1139 }
1140
1141 return 0;
1142}
1143
1145 if (insn->opcodeType != MAP4)
1146 return false;
1147 if (insn->opcode == 0x83 && regFromModRM(insn->modRM) == 7)
1148 return true;
1149 switch (insn->opcode & 0xfe) {
1150 default:
1151 return false;
1152 case 0x38:
1153 case 0x3a:
1154 case 0x84:
1155 return true;
1156 case 0x80:
1157 return regFromModRM(insn->modRM) == 7;
1158 case 0xf6:
1159 return regFromModRM(insn->modRM) == 0;
1160 }
1161}
1162
1163static bool isNF(InternalInstruction *insn) {
1165 return false;
1166 if (insn->opcodeType == MAP4)
1167 return true;
1168 // Below NF instructions are not in map4.
1169 if (insn->opcodeType == THREEBYTE_38 &&
1171 switch (insn->opcode) {
1172 case 0xf2: // ANDN
1173 case 0xf3: // BLSI, BLSR, BLSMSK
1174 case 0xf5: // BZHI
1175 case 0xf7: // BEXTR
1176 return true;
1177 default:
1178 break;
1179 }
1180 }
1181 return false;
1182}
1183
1184// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1185// for extended and escape opcodes. Determines the attributes and context for
1186// the instruction before doing so.
1188 const MCInstrInfo *mii) {
1189 uint16_t attrMask;
1190 uint16_t instructionID;
1191
1192 LLVM_DEBUG(dbgs() << "getID()");
1193
1194 attrMask = ATTR_NONE;
1195
1196 if (insn->mode == MODE_64BIT)
1197 attrMask |= ATTR_64BIT;
1198
1199 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
1200 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
1201
1202 if (insn->vectorExtensionType == TYPE_EVEX) {
1203 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
1204 case VEX_PREFIX_66:
1205 attrMask |= ATTR_OPSIZE;
1206 break;
1207 case VEX_PREFIX_F3:
1208 attrMask |= ATTR_XS;
1209 break;
1210 case VEX_PREFIX_F2:
1211 attrMask |= ATTR_XD;
1212 break;
1213 }
1214
1216 attrMask |= ATTR_EVEXKZ;
1218 attrMask |= ATTR_EVEXB;
1219 if (isNF(insn) && !readModRM(insn) &&
1220 !isCCMPOrCTEST(insn)) // NF bit is the MSB of aaa.
1221 attrMask |= ATTR_EVEXNF;
1222 // aaa is not used a opmask in MAP4
1223 else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]) &&
1224 (insn->opcodeType != MAP4))
1225 attrMask |= ATTR_EVEXK;
1227 attrMask |= ATTR_VEXL;
1229 attrMask |= ATTR_EVEXL2;
1230 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
1231 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
1232 case VEX_PREFIX_66:
1233 attrMask |= ATTR_OPSIZE;
1234 break;
1235 case VEX_PREFIX_F3:
1236 attrMask |= ATTR_XS;
1237 break;
1238 case VEX_PREFIX_F2:
1239 attrMask |= ATTR_XD;
1240 break;
1241 }
1242
1243 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
1244 attrMask |= ATTR_VEXL;
1245 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
1246 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
1247 case VEX_PREFIX_66:
1248 attrMask |= ATTR_OPSIZE;
1249 if (insn->hasAdSize)
1250 attrMask |= ATTR_ADSIZE;
1251 break;
1252 case VEX_PREFIX_F3:
1253 attrMask |= ATTR_XS;
1254 break;
1255 case VEX_PREFIX_F2:
1256 attrMask |= ATTR_XD;
1257 break;
1258 }
1259
1260 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
1261 attrMask |= ATTR_VEXL;
1262 } else if (insn->vectorExtensionType == TYPE_XOP) {
1263 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
1264 case VEX_PREFIX_66:
1265 attrMask |= ATTR_OPSIZE;
1266 break;
1267 case VEX_PREFIX_F3:
1268 attrMask |= ATTR_XS;
1269 break;
1270 case VEX_PREFIX_F2:
1271 attrMask |= ATTR_XD;
1272 break;
1273 }
1274
1275 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
1276 attrMask |= ATTR_VEXL;
1277 } else {
1278 return -1;
1279 }
1280 } else if (!insn->mandatoryPrefix) {
1281 // If we don't have mandatory prefix we should use legacy prefixes here
1282 if (insn->hasOpSize && (insn->mode != MODE_16BIT))
1283 attrMask |= ATTR_OPSIZE;
1284 if (insn->hasAdSize)
1285 attrMask |= ATTR_ADSIZE;
1286 if (insn->opcodeType == ONEBYTE) {
1287 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
1288 // Special support for PAUSE
1289 attrMask |= ATTR_XS;
1290 } else {
1291 if (insn->repeatPrefix == 0xf2)
1292 attrMask |= ATTR_XD;
1293 else if (insn->repeatPrefix == 0xf3)
1294 attrMask |= ATTR_XS;
1295 }
1296 } else {
1297 switch (insn->mandatoryPrefix) {
1298 case 0xf2:
1299 attrMask |= ATTR_XD;
1300 break;
1301 case 0xf3:
1302 attrMask |= ATTR_XS;
1303 break;
1304 case 0x66:
1305 if (insn->mode != MODE_16BIT)
1306 attrMask |= ATTR_OPSIZE;
1307 if (insn->hasAdSize)
1308 attrMask |= ATTR_ADSIZE;
1309 break;
1310 case 0x67:
1311 attrMask |= ATTR_ADSIZE;
1312 break;
1313 }
1314 }
1315
1316 if (insn->rexPrefix & 0x08) {
1317 attrMask |= ATTR_REXW;
1318 attrMask &= ~ATTR_ADSIZE;
1319 }
1320
1321 // Absolute jump and pushp/popp need special handling
1322 if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE &&
1323 (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50))
1324 attrMask |= ATTR_REX2;
1325
1326 if (insn->mode == MODE_16BIT) {
1327 // JCXZ/JECXZ need special handling for 16-bit mode because the meaning
1328 // of the AdSize prefix is inverted w.r.t. 32-bit mode.
1329 if (insn->opcodeType == ONEBYTE && insn->opcode == 0xE3)
1330 attrMask ^= ATTR_ADSIZE;
1331 // If we're in 16-bit mode and this is one of the relative jumps and opsize
1332 // prefix isn't present, we need to force the opsize attribute since the
1333 // prefix is inverted relative to 32-bit mode.
1334 if (!insn->hasOpSize && insn->opcodeType == ONEBYTE &&
1335 (insn->opcode == 0xE8 || insn->opcode == 0xE9))
1336 attrMask |= ATTR_OPSIZE;
1337
1338 if (!insn->hasOpSize && insn->opcodeType == TWOBYTE &&
1339 insn->opcode >= 0x80 && insn->opcode <= 0x8F)
1340 attrMask |= ATTR_OPSIZE;
1341 }
1342
1343
1344 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1345 return -1;
1346
1347 // The following clauses compensate for limitations of the tables.
1348
1349 if (insn->mode != MODE_64BIT &&
1351 // The tables can't distinquish between cases where the W-bit is used to
1352 // select register size and cases where its a required part of the opcode.
1353 if ((insn->vectorExtensionType == TYPE_EVEX &&
1355 (insn->vectorExtensionType == TYPE_VEX_3B &&
1357 (insn->vectorExtensionType == TYPE_XOP &&
1359
1360 uint16_t instructionIDWithREXW;
1361 if (getInstructionIDWithAttrMask(&instructionIDWithREXW, insn,
1362 attrMask | ATTR_REXW)) {
1363 insn->instructionID = instructionID;
1364 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1365 return 0;
1366 }
1367
1368 auto SpecName = mii->getName(instructionIDWithREXW);
1369 // If not a 64-bit instruction. Switch the opcode.
1370 if (!is64Bit(SpecName.data())) {
1371 insn->instructionID = instructionIDWithREXW;
1372 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithREXW];
1373 return 0;
1374 }
1375 }
1376 }
1377
1378 // Absolute moves, umonitor, and movdir64b need special handling.
1379 // -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1380 // inverted w.r.t.
1381 // -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1382 // any position.
1383 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1384 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1385 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) ||
1386 (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) {
1387 // Make sure we observed the prefixes in any position.
1388 if (insn->hasAdSize)
1389 attrMask |= ATTR_ADSIZE;
1390 if (insn->hasOpSize)
1391 attrMask |= ATTR_OPSIZE;
1392
1393 // In 16-bit, invert the attributes.
1394 if (insn->mode == MODE_16BIT) {
1395 attrMask ^= ATTR_ADSIZE;
1396
1397 // The OpSize attribute is only valid with the absolute moves.
1398 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1399 attrMask ^= ATTR_OPSIZE;
1400 }
1401
1402 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1403 return -1;
1404
1405 insn->instructionID = instructionID;
1406 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1407 return 0;
1408 }
1409
1410 if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1411 !(attrMask & ATTR_OPSIZE)) {
1412 // The instruction tables make no distinction between instructions that
1413 // allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1414 // particular spot (i.e., many MMX operations). In general we're
1415 // conservative, but in the specific case where OpSize is present but not in
1416 // the right place we check if there's a 16-bit operation.
1417 const struct InstructionSpecifier *spec;
1418 uint16_t instructionIDWithOpsize;
1419 llvm::StringRef specName, specWithOpSizeName;
1420
1421 spec = &INSTRUCTIONS_SYM[instructionID];
1422
1423 if (getInstructionIDWithAttrMask(&instructionIDWithOpsize, insn,
1424 attrMask | ATTR_OPSIZE)) {
1425 // ModRM required with OpSize but not present. Give up and return the
1426 // version without OpSize set.
1427 insn->instructionID = instructionID;
1428 insn->spec = spec;
1429 return 0;
1430 }
1431
1432 specName = mii->getName(instructionID);
1433 specWithOpSizeName = mii->getName(instructionIDWithOpsize);
1434
1435 if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1436 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1437 insn->instructionID = instructionIDWithOpsize;
1438 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithOpsize];
1439 } else {
1440 insn->instructionID = instructionID;
1441 insn->spec = spec;
1442 }
1443 return 0;
1444 }
1445
1446 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1447 insn->rexPrefix & 0x01) {
1448 // NOOP shouldn't decode as NOOP if REX.b is set. Instead it should decode
1449 // as XCHG %r8, %eax.
1450 const struct InstructionSpecifier *spec;
1451 uint16_t instructionIDWithNewOpcode;
1452 const struct InstructionSpecifier *specWithNewOpcode;
1453
1454 spec = &INSTRUCTIONS_SYM[instructionID];
1455
1456 // Borrow opcode from one of the other XCHGar opcodes
1457 insn->opcode = 0x91;
1458
1459 if (getInstructionIDWithAttrMask(&instructionIDWithNewOpcode, insn,
1460 attrMask)) {
1461 insn->opcode = 0x90;
1462
1463 insn->instructionID = instructionID;
1464 insn->spec = spec;
1465 return 0;
1466 }
1467
1468 specWithNewOpcode = &INSTRUCTIONS_SYM[instructionIDWithNewOpcode];
1469
1470 // Change back
1471 insn->opcode = 0x90;
1472
1473 insn->instructionID = instructionIDWithNewOpcode;
1474 insn->spec = specWithNewOpcode;
1475
1476 return 0;
1477 }
1478
1479 insn->instructionID = instructionID;
1480 insn->spec = &INSTRUCTIONS_SYM[insn->instructionID];
1481
1482 return 0;
1483}
1484
1485// Read an operand from the opcode field of an instruction and interprets it
1486// appropriately given the operand width. Handles AddRegFrm instructions.
1487//
1488// @param insn - the instruction whose opcode field is to be read.
1489// @param size - The width (in bytes) of the register being specified.
1490// 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1491// RAX.
1492// @return - 0 on success; nonzero otherwise.
1493static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) {
1494 LLVM_DEBUG(dbgs() << "readOpcodeRegister()");
1495
1496 if (size == 0)
1497 size = insn->registerSize;
1498
1499 auto setOpcodeRegister = [&](unsigned base) {
1500 insn->opcodeRegister =
1501 (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) |
1502 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) |
1503 (insn->opcode & 7)));
1504 };
1505
1506 switch (size) {
1507 case 1:
1508 setOpcodeRegister(MODRM_REG_AL);
1509 if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1510 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1511 insn->opcodeRegister =
1512 (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4));
1513 }
1514
1515 break;
1516 case 2:
1517 setOpcodeRegister(MODRM_REG_AX);
1518 break;
1519 case 4:
1520 setOpcodeRegister(MODRM_REG_EAX);
1521 break;
1522 case 8:
1523 setOpcodeRegister(MODRM_REG_RAX);
1524 break;
1525 }
1526
1527 return 0;
1528}
1529
1530// Consume an immediate operand from an instruction, given the desired operand
1531// size.
1532//
1533// @param insn - The instruction whose operand is to be read.
1534// @param size - The width (in bytes) of the operand.
1535// @return - 0 if the immediate was successfully consumed; nonzero
1536// otherwise.
1537static int readImmediate(struct InternalInstruction *insn, uint8_t size) {
1538 uint8_t imm8;
1539 uint16_t imm16;
1540 uint32_t imm32;
1541 uint64_t imm64;
1542
1543 LLVM_DEBUG(dbgs() << "readImmediate()");
1544
1545 assert(insn->numImmediatesConsumed < 2 && "Already consumed two immediates");
1546
1547 insn->immediateSize = size;
1548 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1549
1550 switch (size) {
1551 case 1:
1552 if (consume(insn, imm8))
1553 return -1;
1554 insn->immediates[insn->numImmediatesConsumed] = imm8;
1555 break;
1556 case 2:
1557 if (consume(insn, imm16))
1558 return -1;
1559 insn->immediates[insn->numImmediatesConsumed] = imm16;
1560 break;
1561 case 4:
1562 if (consume(insn, imm32))
1563 return -1;
1564 insn->immediates[insn->numImmediatesConsumed] = imm32;
1565 break;
1566 case 8:
1567 if (consume(insn, imm64))
1568 return -1;
1569 insn->immediates[insn->numImmediatesConsumed] = imm64;
1570 break;
1571 default:
1572 llvm_unreachable("invalid size");
1573 }
1574
1575 insn->numImmediatesConsumed++;
1576
1577 return 0;
1578}
1579
1580// Consume vvvv from an instruction if it has a VEX prefix.
1581static int readVVVV(struct InternalInstruction *insn) {
1582 LLVM_DEBUG(dbgs() << "readVVVV()");
1583
1584 int vvvv;
1585 if (insn->vectorExtensionType == TYPE_EVEX)
1586 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1588 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1589 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1590 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1591 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1592 else if (insn->vectorExtensionType == TYPE_XOP)
1593 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1594 else
1595 return -1;
1596
1597 if (insn->mode != MODE_64BIT)
1598 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1599
1600 insn->vvvv = static_cast<Reg>(vvvv);
1601 return 0;
1602}
1603
1604// Read an mask register from the opcode field of an instruction.
1605//
1606// @param insn - The instruction whose opcode field is to be read.
1607// @return - 0 on success; nonzero otherwise.
1608static int readMaskRegister(struct InternalInstruction *insn) {
1609 LLVM_DEBUG(dbgs() << "readMaskRegister()");
1610
1611 if (insn->vectorExtensionType != TYPE_EVEX)
1612 return -1;
1613
1614 insn->writemask =
1615 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1616 return 0;
1617}
1618
1619// Consults the specifier for an instruction and consumes all
1620// operands for that instruction, interpreting them as it goes.
1621static int readOperands(struct InternalInstruction *insn) {
1622 int hasVVVV, needVVVV;
1623 int sawRegImm = 0;
1624
1625 LLVM_DEBUG(dbgs() << "readOperands()");
1626
1627 // If non-zero vvvv specified, make sure one of the operands uses it.
1628 hasVVVV = !readVVVV(insn);
1629 needVVVV = hasVVVV && (insn->vvvv != 0);
1630
1631 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1632 switch (Op.encoding) {
1633 case ENCODING_NONE:
1634 case ENCODING_SI:
1635 case ENCODING_DI:
1636 break;
1638 // VSIB can use the V2 bit so check only the other bits.
1639 if (needVVVV)
1640 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1641 if (readModRM(insn))
1642 return -1;
1643
1644 // Reject if SIB wasn't used.
1645 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1646 return -1;
1647
1648 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1649 if (insn->sibIndex == SIB_INDEX_NONE)
1650 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4);
1651
1652 // If EVEX.v2 is set this is one of the 16-31 registers.
1653 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
1655 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1656
1657 // Adjust the index register to the correct size.
1658 switch ((OperandType)Op.type) {
1659 default:
1660 debug("Unhandled VSIB index type");
1661 return -1;
1662 case TYPE_MVSIBX:
1663 insn->sibIndex =
1664 (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase));
1665 break;
1666 case TYPE_MVSIBY:
1667 insn->sibIndex =
1668 (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase));
1669 break;
1670 case TYPE_MVSIBZ:
1671 insn->sibIndex =
1672 (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase));
1673 break;
1674 }
1675
1676 // Apply the AVX512 compressed displacement scaling factor.
1677 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1678 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1679 break;
1680 case ENCODING_SIB:
1681 // Reject if SIB wasn't used.
1682 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1683 return -1;
1684 if (readModRM(insn))
1685 return -1;
1686 if (fixupReg(insn, &Op))
1687 return -1;
1688 break;
1689 case ENCODING_REG:
1691 if (readModRM(insn))
1692 return -1;
1693 if (fixupReg(insn, &Op))
1694 return -1;
1695 // Apply the AVX512 compressed displacement scaling factor.
1696 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1697 insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1698 break;
1699 case ENCODING_IB:
1700 if (sawRegImm) {
1701 // Saw a register immediate so don't read again and instead split the
1702 // previous immediate. FIXME: This is a hack.
1703 insn->immediates[insn->numImmediatesConsumed] =
1704 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1705 ++insn->numImmediatesConsumed;
1706 break;
1707 }
1708 if (readImmediate(insn, 1))
1709 return -1;
1710 if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1711 sawRegImm = 1;
1712 break;
1713 case ENCODING_IW:
1714 if (readImmediate(insn, 2))
1715 return -1;
1716 break;
1717 case ENCODING_ID:
1718 if (readImmediate(insn, 4))
1719 return -1;
1720 break;
1721 case ENCODING_IO:
1722 if (readImmediate(insn, 8))
1723 return -1;
1724 break;
1725 case ENCODING_Iv:
1726 if (readImmediate(insn, insn->immediateSize))
1727 return -1;
1728 break;
1729 case ENCODING_Ia:
1730 if (readImmediate(insn, insn->addressSize))
1731 return -1;
1732 break;
1733 case ENCODING_IRC:
1734 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1736 break;
1737 case ENCODING_RB:
1738 if (readOpcodeRegister(insn, 1))
1739 return -1;
1740 break;
1741 case ENCODING_RW:
1742 if (readOpcodeRegister(insn, 2))
1743 return -1;
1744 break;
1745 case ENCODING_RD:
1746 if (readOpcodeRegister(insn, 4))
1747 return -1;
1748 break;
1749 case ENCODING_RO:
1750 if (readOpcodeRegister(insn, 8))
1751 return -1;
1752 break;
1753 case ENCODING_Rv:
1754 if (readOpcodeRegister(insn, 0))
1755 return -1;
1756 break;
1757 case ENCODING_CF:
1759 needVVVV = false; // oszc shares the same bits with VVVV
1760 break;
1761 case ENCODING_CC:
1762 if (isCCMPOrCTEST(insn))
1763 insn->immediates[2] = scFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1764 else
1765 insn->immediates[1] = insn->opcode & 0xf;
1766 break;
1767 case ENCODING_FP:
1768 break;
1769 case ENCODING_VVVV:
1770 needVVVV = 0; // Mark that we have found a VVVV operand.
1771 if (!hasVVVV)
1772 return -1;
1773 if (insn->mode != MODE_64BIT)
1774 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1775 if (fixupReg(insn, &Op))
1776 return -1;
1777 break;
1778 case ENCODING_WRITEMASK:
1779 if (readMaskRegister(insn))
1780 return -1;
1781 break;
1782 case ENCODING_DUP:
1783 break;
1784 default:
1785 LLVM_DEBUG(dbgs() << "Encountered an operand with an unknown encoding.");
1786 return -1;
1787 }
1788 }
1789
1790 // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
1791 if (needVVVV)
1792 return -1;
1793
1794 return 0;
1795}
1796
1797namespace llvm {
1798
1799// Fill-ins to make the compiler happy. These constants are never actually
1800// assigned; they are just filler to make an automatically-generated switch
1801// statement work.
1802namespace X86 {
1803 enum {
1804 BX_SI = 500,
1805 BX_DI = 501,
1806 BP_SI = 502,
1807 BP_DI = 503,
1808 sib = 504,
1809 sib64 = 505
1811} // namespace X86
1812
1813} // namespace llvm
1814
1815static bool translateInstruction(MCInst &target,
1816 InternalInstruction &source,
1817 const MCDisassembler *Dis);
1818
1819namespace {
1820
1821/// Generic disassembler for all X86 platforms. All each platform class should
1822/// have to do is subclass the constructor, and provide a different
1823/// disassemblerMode value.
1824class X86GenericDisassembler : public MCDisassembler {
1825 std::unique_ptr<const MCInstrInfo> MII;
1826public:
1827 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
1828 std::unique_ptr<const MCInstrInfo> MII);
1829public:
1831 ArrayRef<uint8_t> Bytes, uint64_t Address,
1832 raw_ostream &cStream) const override;
1833
1834private:
1835 DisassemblerMode fMode;
1836};
1837
1838} // namespace
1839
1840X86GenericDisassembler::X86GenericDisassembler(
1841 const MCSubtargetInfo &STI,
1842 MCContext &Ctx,
1843 std::unique_ptr<const MCInstrInfo> MII)
1844 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
1845 const FeatureBitset &FB = STI.getFeatureBits();
1846 if (FB[X86::Is16Bit]) {
1847 fMode = MODE_16BIT;
1848 return;
1849 } else if (FB[X86::Is32Bit]) {
1850 fMode = MODE_32BIT;
1851 return;
1852 } else if (FB[X86::Is64Bit]) {
1853 fMode = MODE_64BIT;
1854 return;
1855 }
1856
1857 llvm_unreachable("Invalid CPU mode");
1858}
1859
1860MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
1862 raw_ostream &CStream) const {
1863 CommentStream = &CStream;
1864
1866 memset(&Insn, 0, sizeof(InternalInstruction));
1867 Insn.bytes = Bytes;
1868 Insn.startLocation = Address;
1869 Insn.readerCursor = Address;
1870 Insn.mode = fMode;
1871
1872 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) ||
1873 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 ||
1874 readOperands(&Insn)) {
1875 Size = Insn.readerCursor - Address;
1876 return Fail;
1877 }
1878
1879 Insn.operands = x86OperandSets[Insn.spec->operands];
1880 Insn.length = Insn.readerCursor - Insn.startLocation;
1881 Size = Insn.length;
1882 if (Size > 15)
1883 LLVM_DEBUG(dbgs() << "Instruction exceeds 15-byte limit");
1884
1885 bool Ret = translateInstruction(Instr, Insn, this);
1886 if (!Ret) {
1887 unsigned Flags = X86::IP_NO_PREFIX;
1888 if (Insn.hasAdSize)
1890 if (!Insn.mandatoryPrefix) {
1891 if (Insn.hasOpSize)
1893 if (Insn.repeatPrefix == 0xf2)
1895 else if (Insn.repeatPrefix == 0xf3 &&
1896 // It should not be 'pause' f3 90
1897 Insn.opcode != 0x90)
1899 if (Insn.hasLockPrefix)
1901 }
1902 Instr.setFlags(Flags);
1903 }
1904 return (!Ret) ? Success : Fail;
1905}
1906
1907//
1908// Private code that translates from struct InternalInstructions to MCInsts.
1909//
1910
1911/// translateRegister - Translates an internal register to the appropriate LLVM
1912/// register, and appends it as an operand to an MCInst.
1913///
1914/// @param mcInst - The MCInst to append to.
1915/// @param reg - The Reg to append.
1916static void translateRegister(MCInst &mcInst, Reg reg) {
1917#define ENTRY(x) X86::x,
1918 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
1919#undef ENTRY
1920
1921 MCPhysReg llvmRegnum = llvmRegnums[reg];
1922 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
1923}
1924
1925static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
1926 0, // SEG_OVERRIDE_NONE
1927 X86::CS,
1928 X86::SS,
1929 X86::DS,
1930 X86::ES,
1931 X86::FS,
1932 X86::GS
1933};
1934
1935/// translateSrcIndex - Appends a source index operand to an MCInst.
1936///
1937/// @param mcInst - The MCInst to append to.
1938/// @param insn - The internal instruction.
1939static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
1940 unsigned baseRegNo;
1941
1942 if (insn.mode == MODE_64BIT)
1943 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI;
1944 else if (insn.mode == MODE_32BIT)
1945 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI;
1946 else {
1947 assert(insn.mode == MODE_16BIT);
1948 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI;
1949 }
1950 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1951 mcInst.addOperand(baseReg);
1952
1953 MCOperand segmentReg;
1955 mcInst.addOperand(segmentReg);
1956 return false;
1957}
1958
1959/// translateDstIndex - Appends a destination index operand to an MCInst.
1960///
1961/// @param mcInst - The MCInst to append to.
1962/// @param insn - The internal instruction.
1963
1964static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
1965 unsigned baseRegNo;
1966
1967 if (insn.mode == MODE_64BIT)
1968 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
1969 else if (insn.mode == MODE_32BIT)
1970 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI;
1971 else {
1972 assert(insn.mode == MODE_16BIT);
1973 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI;
1974 }
1975 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1976 mcInst.addOperand(baseReg);
1977 return false;
1978}
1979
1980/// translateImmediate - Appends an immediate operand to an MCInst.
1981///
1982/// @param mcInst - The MCInst to append to.
1983/// @param immediate - The immediate value to append.
1984/// @param operand - The operand, as stored in the descriptor table.
1985/// @param insn - The internal instruction.
1986static void translateImmediate(MCInst &mcInst, uint64_t immediate,
1987 const OperandSpecifier &operand,
1988 InternalInstruction &insn,
1989 const MCDisassembler *Dis) {
1990 // Sign-extend the immediate if necessary.
1991
1992 OperandType type = (OperandType)operand.type;
1993
1994 bool isBranch = false;
1995 uint64_t pcrel = 0;
1996 if (type == TYPE_REL) {
1997 isBranch = true;
1998 pcrel = insn.startLocation + insn.length;
1999 switch (operand.encoding) {
2000 default:
2001 break;
2002 case ENCODING_Iv:
2003 switch (insn.displacementSize) {
2004 default:
2005 break;
2006 case 1:
2007 if(immediate & 0x80)
2008 immediate |= ~(0xffull);
2009 break;
2010 case 2:
2011 if(immediate & 0x8000)
2012 immediate |= ~(0xffffull);
2013 break;
2014 case 4:
2015 if(immediate & 0x80000000)
2016 immediate |= ~(0xffffffffull);
2017 break;
2018 case 8:
2019 break;
2020 }
2021 break;
2022 case ENCODING_IB:
2023 if(immediate & 0x80)
2024 immediate |= ~(0xffull);
2025 break;
2026 case ENCODING_IW:
2027 if(immediate & 0x8000)
2028 immediate |= ~(0xffffull);
2029 break;
2030 case ENCODING_ID:
2031 if(immediate & 0x80000000)
2032 immediate |= ~(0xffffffffull);
2033 break;
2034 }
2035 }
2036 // By default sign-extend all X86 immediates based on their encoding.
2037 else if (type == TYPE_IMM) {
2038 switch (operand.encoding) {
2039 default:
2040 break;
2041 case ENCODING_IB:
2042 if(immediate & 0x80)
2043 immediate |= ~(0xffull);
2044 break;
2045 case ENCODING_IW:
2046 if(immediate & 0x8000)
2047 immediate |= ~(0xffffull);
2048 break;
2049 case ENCODING_ID:
2050 if(immediate & 0x80000000)
2051 immediate |= ~(0xffffffffull);
2052 break;
2053 case ENCODING_IO:
2054 break;
2055 }
2056 }
2057
2058 switch (type) {
2059 case TYPE_XMM:
2060 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
2061 return;
2062 case TYPE_YMM:
2063 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
2064 return;
2065 case TYPE_ZMM:
2066 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
2067 return;
2068 default:
2069 // operand is 64 bits wide. Do nothing.
2070 break;
2071 }
2072
2073 if (!Dis->tryAddingSymbolicOperand(
2074 mcInst, immediate + pcrel, insn.startLocation, isBranch,
2075 insn.immediateOffset, insn.immediateSize, insn.length))
2076 mcInst.addOperand(MCOperand::createImm(immediate));
2077
2078 if (type == TYPE_MOFFS) {
2079 MCOperand segmentReg;
2081 mcInst.addOperand(segmentReg);
2082 }
2083}
2084
2085/// translateRMRegister - Translates a register stored in the R/M field of the
2086/// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
2087/// @param mcInst - The MCInst to append to.
2088/// @param insn - The internal instruction to extract the R/M field
2089/// from.
2090/// @return - 0 on success; -1 otherwise
2091static bool translateRMRegister(MCInst &mcInst,
2092 InternalInstruction &insn) {
2093 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2094 debug("A R/M register operand may not have a SIB byte");
2095 return true;
2096 }
2097
2098 switch (insn.eaBase) {
2099 default:
2100 debug("Unexpected EA base register");
2101 return true;
2102 case EA_BASE_NONE:
2103 debug("EA_BASE_NONE for ModR/M base");
2104 return true;
2105#define ENTRY(x) case EA_BASE_##x:
2107#undef ENTRY
2108 debug("A R/M register operand may not have a base; "
2109 "the operand must be a register.");
2110 return true;
2111#define ENTRY(x) \
2112 case EA_REG_##x: \
2113 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2114 ALL_REGS
2115#undef ENTRY
2116 }
2117
2118 return false;
2119}
2120
2121/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
2122/// fields of an internal instruction (and possibly its SIB byte) to a memory
2123/// operand in LLVM's format, and appends it to an MCInst.
2124///
2125/// @param mcInst - The MCInst to append to.
2126/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2127/// from.
2128/// @param ForceSIB - The instruction must use SIB.
2129/// @return - 0 on success; nonzero otherwise
2131 const MCDisassembler *Dis,
2132 bool ForceSIB = false) {
2133 // Addresses in an MCInst are represented as five operands:
2134 // 1. basereg (register) The R/M base, or (if there is a SIB) the
2135 // SIB base
2136 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
2137 // scale amount
2138 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
2139 // the index (which is multiplied by the
2140 // scale amount)
2141 // 4. displacement (immediate) 0, or the displacement if there is one
2142 // 5. segmentreg (register) x86_registerNONE for now, but could be set
2143 // if we have segment overrides
2144
2145 MCOperand baseReg;
2146 MCOperand scaleAmount;
2147 MCOperand indexReg;
2148 MCOperand displacement;
2149 MCOperand segmentReg;
2150 uint64_t pcrel = 0;
2151
2152 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2153 if (insn.sibBase != SIB_BASE_NONE) {
2154 switch (insn.sibBase) {
2155 default:
2156 debug("Unexpected sibBase");
2157 return true;
2158#define ENTRY(x) \
2159 case SIB_BASE_##x: \
2160 baseReg = MCOperand::createReg(X86::x); break;
2162#undef ENTRY
2163 }
2164 } else {
2165 baseReg = MCOperand::createReg(X86::NoRegister);
2166 }
2167
2168 if (insn.sibIndex != SIB_INDEX_NONE) {
2169 switch (insn.sibIndex) {
2170 default:
2171 debug("Unexpected sibIndex");
2172 return true;
2173#define ENTRY(x) \
2174 case SIB_INDEX_##x: \
2175 indexReg = MCOperand::createReg(X86::x); break;
2178 REGS_XMM
2179 REGS_YMM
2180 REGS_ZMM
2181#undef ENTRY
2182 }
2183 } else {
2184 // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
2185 // but no index is used and modrm alone should have been enough.
2186 // -No base register in 32-bit mode. In 64-bit mode this is used to
2187 // avoid rip-relative addressing.
2188 // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
2189 // base always requires a SIB byte.
2190 // -A scale other than 1 is used.
2191 if (!ForceSIB &&
2192 (insn.sibScale != 1 ||
2193 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
2194 (insn.sibBase != SIB_BASE_NONE &&
2195 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
2196 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) {
2197 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
2198 X86::RIZ);
2199 } else
2200 indexReg = MCOperand::createReg(X86::NoRegister);
2201 }
2202
2203 scaleAmount = MCOperand::createImm(insn.sibScale);
2204 } else {
2205 switch (insn.eaBase) {
2206 case EA_BASE_NONE:
2207 if (insn.eaDisplacement == EA_DISP_NONE) {
2208 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
2209 return true;
2210 }
2211 if (insn.mode == MODE_64BIT){
2212 pcrel = insn.startLocation + insn.length;
2214 insn.startLocation +
2215 insn.displacementOffset);
2216 // Section 2.2.1.6
2217 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :
2218 X86::RIP);
2219 }
2220 else
2221 baseReg = MCOperand::createReg(X86::NoRegister);
2222
2223 indexReg = MCOperand::createReg(X86::NoRegister);
2224 break;
2225 case EA_BASE_BX_SI:
2226 baseReg = MCOperand::createReg(X86::BX);
2227 indexReg = MCOperand::createReg(X86::SI);
2228 break;
2229 case EA_BASE_BX_DI:
2230 baseReg = MCOperand::createReg(X86::BX);
2231 indexReg = MCOperand::createReg(X86::DI);
2232 break;
2233 case EA_BASE_BP_SI:
2234 baseReg = MCOperand::createReg(X86::BP);
2235 indexReg = MCOperand::createReg(X86::SI);
2236 break;
2237 case EA_BASE_BP_DI:
2238 baseReg = MCOperand::createReg(X86::BP);
2239 indexReg = MCOperand::createReg(X86::DI);
2240 break;
2241 default:
2242 indexReg = MCOperand::createReg(X86::NoRegister);
2243 switch (insn.eaBase) {
2244 default:
2245 debug("Unexpected eaBase");
2246 return true;
2247 // Here, we will use the fill-ins defined above. However,
2248 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
2249 // sib and sib64 were handled in the top-level if, so they're only
2250 // placeholders to keep the compiler happy.
2251#define ENTRY(x) \
2252 case EA_BASE_##x: \
2253 baseReg = MCOperand::createReg(X86::x); break;
2255#undef ENTRY
2256#define ENTRY(x) case EA_REG_##x:
2257 ALL_REGS
2258#undef ENTRY
2259 debug("A R/M memory operand may not be a register; "
2260 "the base field must be a base.");
2261 return true;
2262 }
2263 }
2264
2265 scaleAmount = MCOperand::createImm(1);
2266 }
2267
2268 displacement = MCOperand::createImm(insn.displacement);
2269
2271
2272 mcInst.addOperand(baseReg);
2273 mcInst.addOperand(scaleAmount);
2274 mcInst.addOperand(indexReg);
2275
2276 const uint8_t dispSize =
2277 (insn.eaDisplacement == EA_DISP_NONE) ? 0 : insn.displacementSize;
2278
2280 mcInst, insn.displacement + pcrel, insn.startLocation, false,
2281 insn.displacementOffset, dispSize, insn.length))
2282 mcInst.addOperand(displacement);
2283 mcInst.addOperand(segmentReg);
2284 return false;
2285}
2286
2287/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
2288/// byte of an instruction to LLVM form, and appends it to an MCInst.
2289///
2290/// @param mcInst - The MCInst to append to.
2291/// @param operand - The operand, as stored in the descriptor table.
2292/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2293/// from.
2294/// @return - 0 on success; nonzero otherwise
2295static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
2296 InternalInstruction &insn, const MCDisassembler *Dis) {
2297 switch (operand.type) {
2298 default:
2299 debug("Unexpected type for a R/M operand");
2300 return true;
2301 case TYPE_R8:
2302 case TYPE_R16:
2303 case TYPE_R32:
2304 case TYPE_R64:
2305 case TYPE_Rv:
2306 case TYPE_MM64:
2307 case TYPE_XMM:
2308 case TYPE_YMM:
2309 case TYPE_ZMM:
2310 case TYPE_TMM:
2311 case TYPE_VK_PAIR:
2312 case TYPE_VK:
2313 case TYPE_DEBUGREG:
2314 case TYPE_CONTROLREG:
2315 case TYPE_BNDR:
2316 return translateRMRegister(mcInst, insn);
2317 case TYPE_M:
2318 case TYPE_MVSIBX:
2319 case TYPE_MVSIBY:
2320 case TYPE_MVSIBZ:
2321 return translateRMMemory(mcInst, insn, Dis);
2322 case TYPE_MSIB:
2323 return translateRMMemory(mcInst, insn, Dis, true);
2324 }
2325}
2326
2327/// translateFPRegister - Translates a stack position on the FPU stack to its
2328/// LLVM form, and appends it to an MCInst.
2329///
2330/// @param mcInst - The MCInst to append to.
2331/// @param stackPos - The stack position to translate.
2332static void translateFPRegister(MCInst &mcInst,
2333 uint8_t stackPos) {
2334 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
2335}
2336
2337/// translateMaskRegister - Translates a 3-bit mask register number to
2338/// LLVM form, and appends it to an MCInst.
2339///
2340/// @param mcInst - The MCInst to append to.
2341/// @param maskRegNum - Number of mask register from 0 to 7.
2342/// @return - false on success; true otherwise.
2343static bool translateMaskRegister(MCInst &mcInst,
2344 uint8_t maskRegNum) {
2345 if (maskRegNum >= 8) {
2346 debug("Invalid mask register number");
2347 return true;
2348 }
2349
2350 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
2351 return false;
2352}
2353
2354/// translateOperand - Translates an operand stored in an internal instruction
2355/// to LLVM's format and appends it to an MCInst.
2356///
2357/// @param mcInst - The MCInst to append to.
2358/// @param operand - The operand, as stored in the descriptor table.
2359/// @param insn - The internal instruction.
2360/// @return - false on success; true otherwise.
2361static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
2362 InternalInstruction &insn,
2363 const MCDisassembler *Dis) {
2364 switch (operand.encoding) {
2365 default:
2366 debug("Unhandled operand encoding during translation");
2367 return true;
2368 case ENCODING_REG:
2369 translateRegister(mcInst, insn.reg);
2370 return false;
2371 case ENCODING_WRITEMASK:
2372 return translateMaskRegister(mcInst, insn.writemask);
2373 case ENCODING_SIB:
2376 return translateRM(mcInst, operand, insn, Dis);
2377 case ENCODING_IB:
2378 case ENCODING_IW:
2379 case ENCODING_ID:
2380 case ENCODING_IO:
2381 case ENCODING_Iv:
2382 case ENCODING_Ia:
2383 translateImmediate(mcInst,
2385 operand,
2386 insn,
2387 Dis);
2388 return false;
2389 case ENCODING_IRC:
2390 mcInst.addOperand(MCOperand::createImm(insn.RC));
2391 return false;
2392 case ENCODING_SI:
2393 return translateSrcIndex(mcInst, insn);
2394 case ENCODING_DI:
2395 return translateDstIndex(mcInst, insn);
2396 case ENCODING_RB:
2397 case ENCODING_RW:
2398 case ENCODING_RD:
2399 case ENCODING_RO:
2400 case ENCODING_Rv:
2401 translateRegister(mcInst, insn.opcodeRegister);
2402 return false;
2403 case ENCODING_CF:
2405 return false;
2406 case ENCODING_CC:
2407 if (isCCMPOrCTEST(&insn))
2409 else
2411 return false;
2412 case ENCODING_FP:
2413 translateFPRegister(mcInst, insn.modRM & 7);
2414 return false;
2415 case ENCODING_VVVV:
2416 translateRegister(mcInst, insn.vvvv);
2417 return false;
2418 case ENCODING_DUP:
2419 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
2420 insn, Dis);
2421 }
2422}
2423
2424/// translateInstruction - Translates an internal instruction and all its
2425/// operands to an MCInst.
2426///
2427/// @param mcInst - The MCInst to populate with the instruction's data.
2428/// @param insn - The internal instruction.
2429/// @return - false on success; true otherwise.
2430static bool translateInstruction(MCInst &mcInst,
2431 InternalInstruction &insn,
2432 const MCDisassembler *Dis) {
2433 if (!insn.spec) {
2434 debug("Instruction has no specification");
2435 return true;
2436 }
2437
2438 mcInst.clear();
2439 mcInst.setOpcode(insn.instructionID);
2440 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
2441 // prefix bytes should be disassembled as xrelease and xacquire then set the
2442 // opcode to those instead of the rep and repne opcodes.
2443 if (insn.xAcquireRelease) {
2444 if(mcInst.getOpcode() == X86::REP_PREFIX)
2445 mcInst.setOpcode(X86::XRELEASE_PREFIX);
2446 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
2447 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
2448 }
2449
2450 insn.numImmediatesTranslated = 0;
2451
2452 for (const auto &Op : insn.operands) {
2453 if (Op.encoding != ENCODING_NONE) {
2454 if (translateOperand(mcInst, Op, insn, Dis)) {
2455 return true;
2456 }
2457 }
2458 }
2459
2460 return false;
2461}
2462
2464 const MCSubtargetInfo &STI,
2465 MCContext &Ctx) {
2466 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
2467 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
2468}
2469
2471 // Register the disassembler.
2476}
#define Fail
#define Success
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
aarch64 promote const
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
#define op(i)
if(VerifyEach)
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const char * name
Definition: SMEABIPass.cpp:49
static uint8_t readOpcode(WasmObjectFile::ReadContext &Ctx)
static int nextByte(ArrayRef< uint8_t > Bytes, uint64_t &Size)
static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
#define TWOBYTE_SYM
#define MAP4_SYM
#define CASE_ENCODING_VSIB
#define XOP9_MAP_SYM
#define CASE_ENCODING_RM
#define THREEDNOW_MAP_SYM
#define INSTRUCTIONS_SYM
#define THREEBYTE3A_SYM
#define XOP8_MAP_SYM
#define THREEBYTE38_SYM
#define XOPA_MAP_SYM
#define MAP6_SYM
#define MAP7_SYM
#define ONEBYTE_SYM
#define MAP5_SYM
#define rFromEVEX2of4(evex)
#define lFromEVEX4of4(evex)
#define l2FromEVEX4of4(evex)
#define rFromVEX2of3(vex)
#define zFromEVEX4of4(evex)
#define wFromREX2(rex2)
#define rFromREX(rex)
#define bFromXOP2of3(xop)
#define xFromVEX2of3(vex)
#define mmmmmFromVEX2of3(vex)
#define rmFromModRM(modRM)
#define bFromREX2(rex2)
#define baseFromSIB(sib)
#define bFromEVEX4of4(evex)
#define rFromVEX2of2(vex)
#define ppFromEVEX3of4(evex)
#define v2FromEVEX4of4(evex)
#define modFromModRM(modRM)
#define rFromXOP2of3(xop)
#define wFromREX(rex)
#define lFromXOP3of3(xop)
#define EA_BASES_64BIT
#define lFromVEX2of2(vex)
#define REGS_YMM
#define x2FromREX2(rex2)
#define scFromEVEX4of4(evex)
#define scaleFromSIB(sib)
#define REGS_XMM
#define rFromREX2(rex2)
#define regFromModRM(modRM)
#define b2FromEVEX2of4(evex)
#define b2FromREX2(rex2)
#define vvvvFromVEX2of2(vex)
#define nfFromEVEX4of4(evex)
#define ALL_REGS
#define ppFromXOP3of3(xop)
#define ALL_SIB_BASES
#define vvvvFromVEX3of3(vex)
#define r2FromEVEX2of4(evex)
#define xFromREX2(rex2)
#define EA_BASES_32BIT
#define x2FromEVEX3of4(evex)
#define xFromXOP2of3(xop)
#define wFromEVEX3of4(evex)
#define bFromVEX2of3(vex)
#define wFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
#define aaaFromEVEX4of4(evex)
#define lFromVEX3of3(vex)
#define mmmFromEVEX2of4(evex)
#define ppFromVEX3of3(vex)
#define bFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define REGS_ZMM
#define ppFromVEX2of2(vex)
#define indexFromSIB(sib)
#define ALL_EA_BASES
#define mFromREX2(rex2)
#define vvvvFromXOP3of3(xop)
#define wFromXOP3of3(xop)
#define r2FromREX2(rex2)
#define oszcFromEVEX3of4(evex)
#define vvvvFromEVEX3of4(evex)
#define xFromREX(rex)
#define bFromREX(rex)
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register,...
static bool isREX2(struct InternalInstruction *insn, uint8_t prefix)
static int getInstructionID(struct InternalInstruction *insn, const MCInstrInfo *mii)
static bool readOpcode(struct InternalInstruction *insn)
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Disassembler()
static int readOperands(struct InternalInstruction *insn)
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form,...
static bool is64Bit(const char *name)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
static int getInstructionIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
static int readSIB(struct InternalInstruction *insn)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
static int readVVVV(struct InternalInstruction *insn)
static bool isNF(InternalInstruction *insn)
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int readMaskRegister(struct InternalInstruction *insn)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
static int readDisplacement(struct InternalInstruction *insn)
static bool isCCMPOrCTEST(InternalInstruction *insn)
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
#define debug(s)
static int readModRM(struct InternalInstruction *insn)
static bool is16BitEquivalent(const char *orig, const char *equiv)
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis, bool ForceSIB=false)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
static int readPrefixes(struct InternalInstruction *insn)
static bool peek(struct InternalInstruction *insn, uint8_t &byte)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
void clear()
Definition: MCInst.h:215
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:70
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86
Windows x64, Windows Itanium (IA-64)
EABase
All possible values of the base field for effective-address computations, a.k.a.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
SIBIndex
All possible values of the SIB index field.
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:53
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:52
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
NodeAddr< InstrNode * > Instr
Definition: RDFGraph.h:389
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1689
Target & getTheX86_32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
Target & getTheX86_64Target()
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
OpcodeDecision opcodeDecisions[IC_max]
uint16_t instructionIDs
ModRMDecision modRMDecisions[256]
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
The specification for how to extract and interpret one operand.