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X86Disassembler.cpp
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1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler.
10 // It contains code to translate the data produced by the decoder into
11 // MCInsts.
12 //
13 //
14 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15 // 64-bit X86 instruction sets. The main decode sequence for an assembly
16 // instruction in this disassembler is:
17 //
18 // 1. Read the prefix bytes and determine the attributes of the instruction.
19 // These attributes, recorded in enum attributeBits
20 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
21 // provides a mapping from bitmasks to contexts, which are represented by
22 // enum InstructionContext (ibid.).
23 //
24 // 2. Read the opcode, and determine what kind of opcode it is. The
25 // disassembler distinguishes four kinds of opcodes, which are enumerated in
26 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
27 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
28 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
29 //
30 // 3. Depending on the opcode type, look in one of four ClassDecision structures
31 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
32 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
33 // a ModRMDecision (ibid.).
34 //
35 // 4. Some instructions, such as escape opcodes or extended opcodes, or even
36 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
37 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from
38 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
39 // ModR/M byte is required and how to interpret it.
40 //
41 // 5. After resolving the ModRMDecision, the disassembler has a unique ID
42 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
43 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
44 // meanings of its operands.
45 //
46 // 6. For each operand, its encoding is an entry from OperandEncoding
47 // (X86DisassemblerDecoderCommon.h) and its type is an entry from
48 // OperandType (ibid.). The encoding indicates how to read it from the
49 // instruction; the type indicates how to interpret the value once it has
50 // been read. For example, a register operand could be stored in the R/M
51 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to
52 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM
53 // register, for instance). Given this information, the operands can be
54 // extracted and interpreted.
55 //
56 // 7. As the last step, the disassembler translates the instruction information
57 // and operands into a format understandable by the client - in this case, an
58 // MCInst for use by the MC infrastructure.
59 //
60 // The disassembler is broken broadly into two parts: the table emitter that
61 // emits the instruction decode tables discussed above during compilation, and
62 // the disassembler itself. The table emitter is documented in more detail in
63 // utils/TableGen/X86DisassemblerEmitter.h.
64 //
65 // X86Disassembler.cpp contains the code responsible for step 7, and for
66 // invoking the decoder to execute steps 1-6.
67 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the
68 // table emitter and the disassembler.
69 // X86DisassemblerDecoder.h contains the public interface of the decoder,
70 // factored out into C for possible use by other projects.
71 // X86DisassemblerDecoder.c contains the source code of the decoder, which is
72 // responsible for steps 1-6.
73 //
74 //===----------------------------------------------------------------------===//
75 
78 #include "X86DisassemblerDecoder.h"
79 #include "llvm/MC/MCContext.h"
81 #include "llvm/MC/MCExpr.h"
82 #include "llvm/MC/MCInst.h"
83 #include "llvm/MC/MCInstrInfo.h"
85 #include "llvm/Support/Debug.h"
88 
89 using namespace llvm;
90 using namespace llvm::X86Disassembler;
91 
92 #define DEBUG_TYPE "x86-disassembler"
93 
94 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
95  const char *s) {
96  dbgs() << file << ":" << line << ": " << s;
97 }
98 
100  const void *mii) {
101  const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
102  return MII->getName(Opcode);
103 }
104 
105 #define debug(s) LLVM_DEBUG(Debug(__FILE__, __LINE__, s));
106 
107 namespace llvm {
108 
109 // Fill-ins to make the compiler happy. These constants are never actually
110 // assigned; they are just filler to make an automatically-generated switch
111 // statement work.
112 namespace X86 {
113  enum {
114  BX_SI = 500,
115  BX_DI = 501,
116  BP_SI = 502,
117  BP_DI = 503,
118  sib = 504,
119  sib64 = 505
120  };
121 }
122 
123 }
124 
125 static bool translateInstruction(MCInst &target,
126  InternalInstruction &source,
127  const MCDisassembler *Dis);
128 
129 namespace {
130 
131 /// Generic disassembler for all X86 platforms. All each platform class should
132 /// have to do is subclass the constructor, and provide a different
133 /// disassemblerMode value.
134 class X86GenericDisassembler : public MCDisassembler {
135  std::unique_ptr<const MCInstrInfo> MII;
136 public:
137  X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
138  std::unique_ptr<const MCInstrInfo> MII);
139 public:
140  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
141  ArrayRef<uint8_t> Bytes, uint64_t Address,
142  raw_ostream &vStream,
143  raw_ostream &cStream) const override;
144 
145 private:
146  DisassemblerMode fMode;
147 };
148 
149 }
150 
151 X86GenericDisassembler::X86GenericDisassembler(
152  const MCSubtargetInfo &STI,
153  MCContext &Ctx,
154  std::unique_ptr<const MCInstrInfo> MII)
155  : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
156  const FeatureBitset &FB = STI.getFeatureBits();
157  if (FB[X86::Mode16Bit]) {
158  fMode = MODE_16BIT;
159  return;
160  } else if (FB[X86::Mode32Bit]) {
161  fMode = MODE_32BIT;
162  return;
163  } else if (FB[X86::Mode64Bit]) {
164  fMode = MODE_64BIT;
165  return;
166  }
167 
168  llvm_unreachable("Invalid CPU mode");
169 }
170 
171 namespace {
172 struct Region {
173  ArrayRef<uint8_t> Bytes;
174  uint64_t Base;
175  Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {}
176 };
177 } // end anonymous namespace
178 
179 /// A callback function that wraps the readByte method from Region.
180 ///
181 /// @param Arg - The generic callback parameter. In this case, this should
182 /// be a pointer to a Region.
183 /// @param Byte - A pointer to the byte to be read.
184 /// @param Address - The address to be read.
185 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) {
186  auto *R = static_cast<const Region *>(Arg);
187  ArrayRef<uint8_t> Bytes = R->Bytes;
188  unsigned Index = Address - R->Base;
189  if (Bytes.size() <= Index)
190  return -1;
191  *Byte = Bytes[Index];
192  return 0;
193 }
194 
195 /// logger - a callback function that wraps the operator<< method from
196 /// raw_ostream.
197 ///
198 /// @param arg - The generic callback parameter. This should be a pointe
199 /// to a raw_ostream.
200 /// @param log - A string to be logged. logger() adds a newline.
201 static void logger(void* arg, const char* log) {
202  if (!arg)
203  return;
204 
205  raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
206  vStream << log << "\n";
207 }
208 
209 //
210 // Public interface for the disassembler
211 //
212 
213 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
214  MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
215  raw_ostream &VStream, raw_ostream &CStream) const {
216  CommentStream = &CStream;
217 
218  InternalInstruction InternalInstr;
219 
220  dlog_t LoggerFn = logger;
221  if (&VStream == &nulls())
222  LoggerFn = nullptr; // Disable logging completely if it's going to nulls().
223 
224  Region R(Bytes, Address);
225 
226  int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R,
227  LoggerFn, (void *)&VStream,
228  (const void *)MII.get(), Address, fMode);
229 
230  if (Ret) {
231  Size = InternalInstr.readerCursor - Address;
232  return Fail;
233  } else {
234  Size = InternalInstr.length;
235  bool Ret = translateInstruction(Instr, InternalInstr, this);
236  if (!Ret) {
237  unsigned Flags = X86::IP_NO_PREFIX;
238  if (InternalInstr.hasAdSize)
239  Flags |= X86::IP_HAS_AD_SIZE;
240  if (!InternalInstr.mandatoryPrefix) {
241  if (InternalInstr.hasOpSize)
242  Flags |= X86::IP_HAS_OP_SIZE;
243  if (InternalInstr.repeatPrefix == 0xf2)
244  Flags |= X86::IP_HAS_REPEAT_NE;
245  else if (InternalInstr.repeatPrefix == 0xf3 &&
246  // It should not be 'pause' f3 90
247  InternalInstr.opcode != 0x90)
248  Flags |= X86::IP_HAS_REPEAT;
249  if (InternalInstr.hasLockPrefix)
250  Flags |= X86::IP_HAS_LOCK;
251  }
252  Instr.setFlags(Flags);
253  }
254  return (!Ret) ? Success : Fail;
255  }
256 }
257 
258 //
259 // Private code that translates from struct InternalInstructions to MCInsts.
260 //
261 
262 /// translateRegister - Translates an internal register to the appropriate LLVM
263 /// register, and appends it as an operand to an MCInst.
264 ///
265 /// @param mcInst - The MCInst to append to.
266 /// @param reg - The Reg to append.
267 static void translateRegister(MCInst &mcInst, Reg reg) {
268 #define ENTRY(x) X86::x,
269  static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
270 #undef ENTRY
271 
272  MCPhysReg llvmRegnum = llvmRegnums[reg];
273  mcInst.addOperand(MCOperand::createReg(llvmRegnum));
274 }
275 
276 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
277 /// immediate Value in the MCInst.
278 ///
279 /// @param Value - The immediate Value, has had any PC adjustment made by
280 /// the caller.
281 /// @param isBranch - If the instruction is a branch instruction
282 /// @param Address - The starting address of the instruction
283 /// @param Offset - The byte offset to this immediate in the instruction
284 /// @param Width - The byte width of this immediate in the instruction
285 ///
286 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
287 /// called then that function is called to get any symbolic information for the
288 /// immediate in the instruction using the Address, Offset and Width. If that
289 /// returns non-zero then the symbolic information it returns is used to create
290 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
291 /// returns zero and isBranch is true then a symbol look up for immediate Value
292 /// is done and if a symbol is found an MCExpr is created with that, else
293 /// an MCExpr with the immediate Value is created. This function returns true
294 /// if it adds an operand to the MCInst and false otherwise.
295 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
296  uint64_t Address, uint64_t Offset,
297  uint64_t Width, MCInst &MI,
298  const MCDisassembler *Dis) {
299  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
300  Offset, Width);
301 }
302 
303 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
304 /// referenced by a load instruction with the base register that is the rip.
305 /// These can often be addresses in a literal pool. The Address of the
306 /// instruction and its immediate Value are used to determine the address
307 /// being referenced in the literal pool entry. The SymbolLookUp call back will
308 /// return a pointer to a literal 'C' string if the referenced address is an
309 /// address into a section with 'C' string literals.
310 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
311  const void *Decoder) {
312  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
313  Dis->tryAddingPcLoadReferenceComment(Value, Address);
314 }
315 
316 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
317  0, // SEG_OVERRIDE_NONE
318  X86::CS,
319  X86::SS,
320  X86::DS,
321  X86::ES,
322  X86::FS,
323  X86::GS
324 };
325 
326 /// translateSrcIndex - Appends a source index operand to an MCInst.
327 ///
328 /// @param mcInst - The MCInst to append to.
329 /// @param insn - The internal instruction.
330 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
331  unsigned baseRegNo;
332 
333  if (insn.mode == MODE_64BIT)
334  baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI;
335  else if (insn.mode == MODE_32BIT)
336  baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI;
337  else {
338  assert(insn.mode == MODE_16BIT);
339  baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI;
340  }
341  MCOperand baseReg = MCOperand::createReg(baseRegNo);
342  mcInst.addOperand(baseReg);
343 
344  MCOperand segmentReg;
345  segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
346  mcInst.addOperand(segmentReg);
347  return false;
348 }
349 
350 /// translateDstIndex - Appends a destination index operand to an MCInst.
351 ///
352 /// @param mcInst - The MCInst to append to.
353 /// @param insn - The internal instruction.
354 
355 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
356  unsigned baseRegNo;
357 
358  if (insn.mode == MODE_64BIT)
359  baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
360  else if (insn.mode == MODE_32BIT)
361  baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI;
362  else {
363  assert(insn.mode == MODE_16BIT);
364  baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI;
365  }
366  MCOperand baseReg = MCOperand::createReg(baseRegNo);
367  mcInst.addOperand(baseReg);
368  return false;
369 }
370 
371 /// translateImmediate - Appends an immediate operand to an MCInst.
372 ///
373 /// @param mcInst - The MCInst to append to.
374 /// @param immediate - The immediate value to append.
375 /// @param operand - The operand, as stored in the descriptor table.
376 /// @param insn - The internal instruction.
377 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
378  const OperandSpecifier &operand,
379  InternalInstruction &insn,
380  const MCDisassembler *Dis) {
381  // Sign-extend the immediate if necessary.
382 
383  OperandType type = (OperandType)operand.type;
384 
385  bool isBranch = false;
386  uint64_t pcrel = 0;
387  if (type == TYPE_REL) {
388  isBranch = true;
389  pcrel = insn.startLocation +
390  insn.immediateOffset + insn.immediateSize;
391  switch (operand.encoding) {
392  default:
393  break;
394  case ENCODING_Iv:
395  switch (insn.displacementSize) {
396  default:
397  break;
398  case 1:
399  if(immediate & 0x80)
400  immediate |= ~(0xffull);
401  break;
402  case 2:
403  if(immediate & 0x8000)
404  immediate |= ~(0xffffull);
405  break;
406  case 4:
407  if(immediate & 0x80000000)
408  immediate |= ~(0xffffffffull);
409  break;
410  case 8:
411  break;
412  }
413  break;
414  case ENCODING_IB:
415  if(immediate & 0x80)
416  immediate |= ~(0xffull);
417  break;
418  case ENCODING_IW:
419  if(immediate & 0x8000)
420  immediate |= ~(0xffffull);
421  break;
422  case ENCODING_ID:
423  if(immediate & 0x80000000)
424  immediate |= ~(0xffffffffull);
425  break;
426  }
427  }
428  // By default sign-extend all X86 immediates based on their encoding.
429  else if (type == TYPE_IMM) {
430  switch (operand.encoding) {
431  default:
432  break;
433  case ENCODING_IB:
434  if(immediate & 0x80)
435  immediate |= ~(0xffull);
436  break;
437  case ENCODING_IW:
438  if(immediate & 0x8000)
439  immediate |= ~(0xffffull);
440  break;
441  case ENCODING_ID:
442  if(immediate & 0x80000000)
443  immediate |= ~(0xffffffffull);
444  break;
445  case ENCODING_IO:
446  break;
447  }
448  } else if (type == TYPE_IMM3) {
449  // Check for immediates that printSSECC can't handle.
450  if (immediate >= 8) {
451  unsigned NewOpc;
452  switch (mcInst.getOpcode()) {
453  default: llvm_unreachable("unexpected opcode");
454  case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
455  case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
456  case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
457  case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
458  case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
459  case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
460  case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
461  case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
462  case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break;
463  case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break;
464  case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break;
465  case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break;
466  case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break;
467  case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break;
468  case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break;
469  case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break;
470  case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break;
471  case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break;
472  case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break;
473  case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break;
474  case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break;
475  case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break;
476  case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break;
477  case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break;
478  }
479  // Switch opcode to the one that doesn't get special printing.
480  mcInst.setOpcode(NewOpc);
481  }
482  } else if (type == TYPE_IMM5) {
483  // Check for immediates that printAVXCC can't handle.
484  if (immediate >= 32) {
485  unsigned NewOpc;
486  switch (mcInst.getOpcode()) {
487  default: llvm_unreachable("unexpected opcode");
488  case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break;
489  case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break;
490  case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break;
491  case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break;
492  case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break;
493  case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break;
494  case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break;
495  case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break;
496  case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break;
497  case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break;
498  case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break;
499  case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break;
500  case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break;
501  case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break;
502  case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break;
503  case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break;
504  case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break;
505  case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break;
506  case X86::VCMPPDZ128rmi: NewOpc = X86::VCMPPDZ128rmi_alt; break;
507  case X86::VCMPPDZ128rri: NewOpc = X86::VCMPPDZ128rri_alt; break;
508  case X86::VCMPPSZ128rmi: NewOpc = X86::VCMPPSZ128rmi_alt; break;
509  case X86::VCMPPSZ128rri: NewOpc = X86::VCMPPSZ128rri_alt; break;
510  case X86::VCMPPDZ256rmi: NewOpc = X86::VCMPPDZ256rmi_alt; break;
511  case X86::VCMPPDZ256rri: NewOpc = X86::VCMPPDZ256rri_alt; break;
512  case X86::VCMPPSZ256rmi: NewOpc = X86::VCMPPSZ256rmi_alt; break;
513  case X86::VCMPPSZ256rri: NewOpc = X86::VCMPPSZ256rri_alt; break;
514  case X86::VCMPSDZrm_Int: NewOpc = X86::VCMPSDZrmi_alt; break;
515  case X86::VCMPSDZrr_Int: NewOpc = X86::VCMPSDZrri_alt; break;
516  case X86::VCMPSDZrrb_Int: NewOpc = X86::VCMPSDZrrb_alt; break;
517  case X86::VCMPSSZrm_Int: NewOpc = X86::VCMPSSZrmi_alt; break;
518  case X86::VCMPSSZrr_Int: NewOpc = X86::VCMPSSZrri_alt; break;
519  case X86::VCMPSSZrrb_Int: NewOpc = X86::VCMPSSZrrb_alt; break;
520  }
521  // Switch opcode to the one that doesn't get special printing.
522  mcInst.setOpcode(NewOpc);
523  }
524  } else if (type == TYPE_AVX512ICC) {
525  if (immediate >= 8 || ((immediate & 0x3) == 3)) {
526  unsigned NewOpc;
527  switch (mcInst.getOpcode()) {
528  default: llvm_unreachable("unexpected opcode");
529  case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break;
530  case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break;
531  case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break;
532  case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break;
533  case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break;
534  case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break;
535  case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break;
536  case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break;
537  case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break;
538  case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break;
539  case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break;
540  case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break;
541  case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break;
542  case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break;
543  case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break;
544  case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break;
545  case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break;
546  case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break;
547  case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break;
548  case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break;
549  case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break;
550  case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break;
551  case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break;
552  case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break;
553  case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break;
554  case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break;
555  case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break;
556  case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break;
557  case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break;
558  case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break;
559  case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break;
560  case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break;
561  case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break;
562  case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break;
563  case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break;
564  case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break;
565  case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break;
566  case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break;
567  case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break;
568  case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break;
569  case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break;
570  case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break;
571  case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break;
572  case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break;
573  case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break;
574  case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break;
575  case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break;
576  case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break;
577  case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break;
578  case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break;
579  case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break;
580  case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break;
581  case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break;
582  case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break;
583  case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break;
584  case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break;
585  case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break;
586  case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break;
587  case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break;
588  case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break;
589  case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break;
590  case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break;
591  case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break;
592  case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break;
593  case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break;
594  case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break;
595  case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break;
596  case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break;
597  case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break;
598  case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break;
599  case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break;
600  case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break;
601  case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break;
602  case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break;
603  case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break;
604  case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break;
605  case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break;
606  case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break;
607  case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break;
608  case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break;
609  case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break;
610  case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break;
611  case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break;
612  case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break;
613  case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break;
614  case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break;
615  case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break;
616  case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break;
617  case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break;
618  case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break;
619  case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break;
620  case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break;
621  case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break;
622  case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break;
623  case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break;
624  case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break;
625  case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break;
626  case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break;
627  case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break;
628  case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break;
629  case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break;
630  case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break;
631  case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break;
632  case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break;
633  case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break;
634  case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break;
635  case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break;
636  case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break;
637  case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break;
638  case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break;
639  case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break;
640  case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break;
641  case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break;
642  case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break;
643  case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break;
644  case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break;
645  case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break;
646  case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break;
647  case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break;
648  case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break;
649  }
650  // Switch opcode to the one that doesn't get special printing.
651  mcInst.setOpcode(NewOpc);
652  }
653  }
654 
655  switch (type) {
656  case TYPE_XMM:
657  mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
658  return;
659  case TYPE_YMM:
660  mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
661  return;
662  case TYPE_ZMM:
663  mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
664  return;
665  default:
666  // operand is 64 bits wide. Do nothing.
667  break;
668  }
669 
670  if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
671  insn.immediateOffset, insn.immediateSize,
672  mcInst, Dis))
673  mcInst.addOperand(MCOperand::createImm(immediate));
674 
675  if (type == TYPE_MOFFS) {
676  MCOperand segmentReg;
677  segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
678  mcInst.addOperand(segmentReg);
679  }
680 }
681 
682 /// translateRMRegister - Translates a register stored in the R/M field of the
683 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
684 /// @param mcInst - The MCInst to append to.
685 /// @param insn - The internal instruction to extract the R/M field
686 /// from.
687 /// @return - 0 on success; -1 otherwise
688 static bool translateRMRegister(MCInst &mcInst,
689  InternalInstruction &insn) {
690  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
691  debug("A R/M register operand may not have a SIB byte");
692  return true;
693  }
694 
695  switch (insn.eaBase) {
696  default:
697  debug("Unexpected EA base register");
698  return true;
699  case EA_BASE_NONE:
700  debug("EA_BASE_NONE for ModR/M base");
701  return true;
702 #define ENTRY(x) case EA_BASE_##x:
704 #undef ENTRY
705  debug("A R/M register operand may not have a base; "
706  "the operand must be a register.");
707  return true;
708 #define ENTRY(x) \
709  case EA_REG_##x: \
710  mcInst.addOperand(MCOperand::createReg(X86::x)); break;
711  ALL_REGS
712 #undef ENTRY
713  }
714 
715  return false;
716 }
717 
718 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
719 /// fields of an internal instruction (and possibly its SIB byte) to a memory
720 /// operand in LLVM's format, and appends it to an MCInst.
721 ///
722 /// @param mcInst - The MCInst to append to.
723 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
724 /// from.
725 /// @return - 0 on success; nonzero otherwise
726 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
727  const MCDisassembler *Dis) {
728  // Addresses in an MCInst are represented as five operands:
729  // 1. basereg (register) The R/M base, or (if there is a SIB) the
730  // SIB base
731  // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
732  // scale amount
733  // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
734  // the index (which is multiplied by the
735  // scale amount)
736  // 4. displacement (immediate) 0, or the displacement if there is one
737  // 5. segmentreg (register) x86_registerNONE for now, but could be set
738  // if we have segment overrides
739 
740  MCOperand baseReg;
741  MCOperand scaleAmount;
742  MCOperand indexReg;
743  MCOperand displacement;
744  MCOperand segmentReg;
745  uint64_t pcrel = 0;
746 
747  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
748  if (insn.sibBase != SIB_BASE_NONE) {
749  switch (insn.sibBase) {
750  default:
751  debug("Unexpected sibBase");
752  return true;
753 #define ENTRY(x) \
754  case SIB_BASE_##x: \
755  baseReg = MCOperand::createReg(X86::x); break;
757 #undef ENTRY
758  }
759  } else {
760  baseReg = MCOperand::createReg(X86::NoRegister);
761  }
762 
763  if (insn.sibIndex != SIB_INDEX_NONE) {
764  switch (insn.sibIndex) {
765  default:
766  debug("Unexpected sibIndex");
767  return true;
768 #define ENTRY(x) \
769  case SIB_INDEX_##x: \
770  indexReg = MCOperand::createReg(X86::x); break;
773  REGS_XMM
774  REGS_YMM
775  REGS_ZMM
776 #undef ENTRY
777  }
778  } else {
779  // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
780  // but no index is used and modrm alone should have been enough.
781  // -No base register in 32-bit mode. In 64-bit mode this is used to
782  // avoid rip-relative addressing.
783  // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
784  // base always requires a SIB byte.
785  // -A scale other than 1 is used.
786  if (insn.sibScale != 1 ||
787  (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
788  (insn.sibBase != SIB_BASE_NONE &&
789  insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
790  insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12)) {
791  indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
792  X86::RIZ);
793  } else
794  indexReg = MCOperand::createReg(X86::NoRegister);
795  }
796 
797  scaleAmount = MCOperand::createImm(insn.sibScale);
798  } else {
799  switch (insn.eaBase) {
800  case EA_BASE_NONE:
801  if (insn.eaDisplacement == EA_DISP_NONE) {
802  debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
803  return true;
804  }
805  if (insn.mode == MODE_64BIT){
806  pcrel = insn.startLocation +
809  insn.displacementOffset,
810  insn.displacement + pcrel, Dis);
811  // Section 2.2.1.6
812  baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :
813  X86::RIP);
814  }
815  else
816  baseReg = MCOperand::createReg(X86::NoRegister);
817 
818  indexReg = MCOperand::createReg(X86::NoRegister);
819  break;
820  case EA_BASE_BX_SI:
821  baseReg = MCOperand::createReg(X86::BX);
822  indexReg = MCOperand::createReg(X86::SI);
823  break;
824  case EA_BASE_BX_DI:
825  baseReg = MCOperand::createReg(X86::BX);
826  indexReg = MCOperand::createReg(X86::DI);
827  break;
828  case EA_BASE_BP_SI:
829  baseReg = MCOperand::createReg(X86::BP);
830  indexReg = MCOperand::createReg(X86::SI);
831  break;
832  case EA_BASE_BP_DI:
833  baseReg = MCOperand::createReg(X86::BP);
834  indexReg = MCOperand::createReg(X86::DI);
835  break;
836  default:
837  indexReg = MCOperand::createReg(X86::NoRegister);
838  switch (insn.eaBase) {
839  default:
840  debug("Unexpected eaBase");
841  return true;
842  // Here, we will use the fill-ins defined above. However,
843  // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
844  // sib and sib64 were handled in the top-level if, so they're only
845  // placeholders to keep the compiler happy.
846 #define ENTRY(x) \
847  case EA_BASE_##x: \
848  baseReg = MCOperand::createReg(X86::x); break;
850 #undef ENTRY
851 #define ENTRY(x) case EA_REG_##x:
852  ALL_REGS
853 #undef ENTRY
854  debug("A R/M memory operand may not be a register; "
855  "the base field must be a base.");
856  return true;
857  }
858  }
859 
860  scaleAmount = MCOperand::createImm(1);
861  }
862 
863  displacement = MCOperand::createImm(insn.displacement);
864 
865  segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
866 
867  mcInst.addOperand(baseReg);
868  mcInst.addOperand(scaleAmount);
869  mcInst.addOperand(indexReg);
870  if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
872  insn.displacementSize, mcInst, Dis))
873  mcInst.addOperand(displacement);
874  mcInst.addOperand(segmentReg);
875  return false;
876 }
877 
878 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
879 /// byte of an instruction to LLVM form, and appends it to an MCInst.
880 ///
881 /// @param mcInst - The MCInst to append to.
882 /// @param operand - The operand, as stored in the descriptor table.
883 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
884 /// from.
885 /// @return - 0 on success; nonzero otherwise
886 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
887  InternalInstruction &insn, const MCDisassembler *Dis) {
888  switch (operand.type) {
889  default:
890  debug("Unexpected type for a R/M operand");
891  return true;
892  case TYPE_R8:
893  case TYPE_R16:
894  case TYPE_R32:
895  case TYPE_R64:
896  case TYPE_Rv:
897  case TYPE_MM64:
898  case TYPE_XMM:
899  case TYPE_YMM:
900  case TYPE_ZMM:
901  case TYPE_VK:
902  case TYPE_DEBUGREG:
903  case TYPE_CONTROLREG:
904  case TYPE_BNDR:
905  return translateRMRegister(mcInst, insn);
906  case TYPE_M:
907  case TYPE_MVSIBX:
908  case TYPE_MVSIBY:
909  case TYPE_MVSIBZ:
910  return translateRMMemory(mcInst, insn, Dis);
911  }
912 }
913 
914 /// translateFPRegister - Translates a stack position on the FPU stack to its
915 /// LLVM form, and appends it to an MCInst.
916 ///
917 /// @param mcInst - The MCInst to append to.
918 /// @param stackPos - The stack position to translate.
919 static void translateFPRegister(MCInst &mcInst,
920  uint8_t stackPos) {
921  mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
922 }
923 
924 /// translateMaskRegister - Translates a 3-bit mask register number to
925 /// LLVM form, and appends it to an MCInst.
926 ///
927 /// @param mcInst - The MCInst to append to.
928 /// @param maskRegNum - Number of mask register from 0 to 7.
929 /// @return - false on success; true otherwise.
930 static bool translateMaskRegister(MCInst &mcInst,
931  uint8_t maskRegNum) {
932  if (maskRegNum >= 8) {
933  debug("Invalid mask register number");
934  return true;
935  }
936 
937  mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
938  return false;
939 }
940 
941 /// translateOperand - Translates an operand stored in an internal instruction
942 /// to LLVM's format and appends it to an MCInst.
943 ///
944 /// @param mcInst - The MCInst to append to.
945 /// @param operand - The operand, as stored in the descriptor table.
946 /// @param insn - The internal instruction.
947 /// @return - false on success; true otherwise.
948 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
949  InternalInstruction &insn,
950  const MCDisassembler *Dis) {
951  switch (operand.encoding) {
952  default:
953  debug("Unhandled operand encoding during translation");
954  return true;
955  case ENCODING_REG:
956  translateRegister(mcInst, insn.reg);
957  return false;
958  case ENCODING_WRITEMASK:
959  return translateMaskRegister(mcInst, insn.writemask);
962  return translateRM(mcInst, operand, insn, Dis);
963  case ENCODING_IB:
964  case ENCODING_IW:
965  case ENCODING_ID:
966  case ENCODING_IO:
967  case ENCODING_Iv:
968  case ENCODING_Ia:
969  translateImmediate(mcInst,
970  insn.immediates[insn.numImmediatesTranslated++],
971  operand,
972  insn,
973  Dis);
974  return false;
975  case ENCODING_IRC:
976  mcInst.addOperand(MCOperand::createImm(insn.RC));
977  return false;
978  case ENCODING_SI:
979  return translateSrcIndex(mcInst, insn);
980  case ENCODING_DI:
981  return translateDstIndex(mcInst, insn);
982  case ENCODING_RB:
983  case ENCODING_RW:
984  case ENCODING_RD:
985  case ENCODING_RO:
986  case ENCODING_Rv:
987  translateRegister(mcInst, insn.opcodeRegister);
988  return false;
989  case ENCODING_FP:
990  translateFPRegister(mcInst, insn.modRM & 7);
991  return false;
992  case ENCODING_VVVV:
993  translateRegister(mcInst, insn.vvvv);
994  return false;
995  case ENCODING_DUP:
996  return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
997  insn, Dis);
998  }
999 }
1000 
1001 /// translateInstruction - Translates an internal instruction and all its
1002 /// operands to an MCInst.
1003 ///
1004 /// @param mcInst - The MCInst to populate with the instruction's data.
1005 /// @param insn - The internal instruction.
1006 /// @return - false on success; true otherwise.
1007 static bool translateInstruction(MCInst &mcInst,
1008  InternalInstruction &insn,
1009  const MCDisassembler *Dis) {
1010  if (!insn.spec) {
1011  debug("Instruction has no specification");
1012  return true;
1013  }
1014 
1015  mcInst.clear();
1016  mcInst.setOpcode(insn.instructionID);
1017  // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
1018  // prefix bytes should be disassembled as xrelease and xacquire then set the
1019  // opcode to those instead of the rep and repne opcodes.
1020  if (insn.xAcquireRelease) {
1021  if(mcInst.getOpcode() == X86::REP_PREFIX)
1022  mcInst.setOpcode(X86::XRELEASE_PREFIX);
1023  else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
1024  mcInst.setOpcode(X86::XACQUIRE_PREFIX);
1025  }
1026 
1027  insn.numImmediatesTranslated = 0;
1028 
1029  for (const auto &Op : insn.operands) {
1030  if (Op.encoding != ENCODING_NONE) {
1031  if (translateOperand(mcInst, Op, insn, Dis)) {
1032  return true;
1033  }
1034  }
1035  }
1036 
1037  return false;
1038 }
1039 
1041  const MCSubtargetInfo &STI,
1042  MCContext &Ctx) {
1043  std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
1044  return new X86GenericDisassembler(STI, Ctx, std::move(MII));
1045 }
1046 
1048  // Register the disassembler.
1053 }
*ViewGraph Emit a dot run run gv on the postscript file
Definition: GraphWriter.h:362
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
#define ALL_REGS
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: BitVector.h:937
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
#define Fail
const FeatureBitset & getFeatureBits() const
Reg
All possible values of the reg field in the ModR/M byte.
#define ALL_EA_BASES
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst...
#define EA_BASES_64BIT
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form, and appends it to an MCInst.
Context object for machine code objects.
Definition: MCContext.h:62
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst.
static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM&#39;s format and appen...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
The specification for how to extract and interpret one operand.
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
Container class for subtarget features.
static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address)
A callback function that wraps the readByte method from Region.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
#define ALL_SIB_BASES
#define CASE_ENCODING_RM
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
void Debug(const char *file, unsigned line, const char *s)
Print a message to debugs()
The x86 internal instruction, which is produced by the decoder.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:50
StringRef GetInstrName(unsigned Opcode, const void *mii)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setFlags(unsigned F)
Definition: MCInst.h:173
void setOpcode(unsigned Op)
Definition: MCInst.h:170
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
#define CASE_ENCODING_VSIB
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void LLVMInitializeX86Disassembler()
#define debug(s)
Target - Wrapper for Target specific information.
#define Success
#define REGS_ZMM
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Generic base class for all target subtargets.
#define REGS_XMM
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
Definition: Value.h:72
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Dis)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
#define REGS_YMM
unsigned getOpcode() const
Definition: MCInst.h:171
#define EA_BASES_32BIT
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
Target & getTheX86_64Target()
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
DisassemblerMode
Decoding mode for the Intel disassembler.