53 #include "X86GenEVEX2VEXTables.inc" 55 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible" 56 #define EVEX2VEX_NAME "x86-evex-to-vex-compress" 58 #define DEBUG_TYPE EVEX2VEX_NAME 101 bool Changed =
false;
109 Changed |= CompressEvexToVexImpl(
MI);
116 auto isHiRegIdx = [](
unsigned Reg) {
118 if (
Reg >= X86::XMM16 &&
Reg <= X86::XMM31)
122 if (
Reg >= X86::YMM16 &&
Reg <= X86::YMM31)
136 assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
137 "ZMM instructions should not be in the EVEX->VEX tables");
151 case X86::VALIGNDZ128rri:
152 case X86::VALIGNDZ128rmi:
153 case X86::VALIGNQZ128rri:
154 case X86::VALIGNQZ128rmi: {
155 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
156 "Unexpected new opcode!");
157 unsigned Scale = (Opc == X86::VALIGNQZ128rri ||
158 Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
163 case X86::VSHUFF32X4Z256rmi:
164 case X86::VSHUFF32X4Z256rri:
165 case X86::VSHUFF64X2Z256rmi:
166 case X86::VSHUFF64X2Z256rri:
167 case X86::VSHUFI32X4Z256rmi:
168 case X86::VSHUFI32X4Z256rri:
169 case X86::VSHUFI64X2Z256rmi:
170 case X86::VSHUFI64X2Z256rri: {
171 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
172 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
173 "Unexpected new opcode!");
175 int64_t ImmVal = Imm.
getImm();
177 Imm.
setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
180 case X86::VRNDSCALEPDZ128rri:
181 case X86::VRNDSCALEPDZ128rmi:
182 case X86::VRNDSCALEPSZ128rri:
183 case X86::VRNDSCALEPSZ128rmi:
184 case X86::VRNDSCALEPDZ256rri:
185 case X86::VRNDSCALEPDZ256rmi:
186 case X86::VRNDSCALEPSZ256rri:
187 case X86::VRNDSCALEPSZ256rmi:
188 case X86::VRNDSCALESDZr:
189 case X86::VRNDSCALESDZm:
190 case X86::VRNDSCALESSZr:
191 case X86::VRNDSCALESSZm:
192 case X86::VRNDSCALESDZr_Int:
193 case X86::VRNDSCALESDZm_Int:
194 case X86::VRNDSCALESSZr_Int:
195 case X86::VRNDSCALESSZm_Int:
197 int64_t ImmVal = Imm.
getImm();
199 if ((ImmVal & 0xf) != ImmVal)
210 bool EvexToVexInstPass::CompressEvexToVexImpl(
MachineInstr &
MI)
const {
238 static std::atomic<bool> TableChecked(
false);
239 if (!TableChecked.load(std::memory_order_relaxed)) {
241 std::end(X86EvexToVex128CompressTable)) &&
242 "X86EvexToVex128CompressTable is not sorted!");
244 std::end(X86EvexToVex256CompressTable)) &&
245 "X86EvexToVex256CompressTable is not sorted!");
246 TableChecked.store(
true, std::memory_order_relaxed);
259 unsigned NewOpc =
I->VexOpcode;
275 return new EvexToVexInstPass();
auto lower_bound(R &&Range, T &&Value) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
const_iterator end(StringRef path)
Get end iterator over path.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
This class represents lattice values for constants.
iterator_range< mop_iterator > explicit_operands()
Describe properties that are true of each instruction in the target description file.
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
bool operator<(const X86EvexToVexCompressTableEntry &RHS) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
static bool usesExtendedRegister(const MachineInstr &MI)
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
friend bool operator<(const X86EvexToVexCompressTableEntry &TE, unsigned Opc)
StringRef - Represent a constant reference to a string, i.e.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
const MachineOperand & getOperand(unsigned i) const
Properties which a MachineFunction may have at a given point in time.
Wrapper class representing virtual and physical registers.