LLVM  7.0.0svn
X86FixupLEAs.cpp
Go to the documentation of this file.
1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass that finds instructions that can be
11 // re-written as LEA instructions in order to reduce pipeline delays.
12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86.h"
17 #include "X86InstrInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Support/Debug.h"
26 using namespace llvm;
27 
28 namespace llvm {
30 }
31 
32 #define FIXUPLEA_DESC "X86 LEA Fixup"
33 #define FIXUPLEA_NAME "x86-fixup-LEAs"
34 
35 #define DEBUG_TYPE FIXUPLEA_NAME
36 
37 STATISTIC(NumLEAs, "Number of LEA instructions created");
38 
39 namespace {
40 class FixupLEAPass : public MachineFunctionPass {
41  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
42 
43  /// \brief Loop over all of the instructions in the basic block
44  /// replacing applicable instructions with LEA instructions,
45  /// where appropriate.
46  bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
47 
48 
49  /// \brief Given a machine register, look for the instruction
50  /// which writes it in the current basic block. If found,
51  /// try to replace it with an equivalent LEA instruction.
52  /// If replacement succeeds, then also process the newly created
53  /// instruction.
54  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
56 
57  /// \brief Given a memory access or LEA instruction
58  /// whose address mode uses a base and/or index register, look for
59  /// an opportunity to replace the instruction which sets the base or index
60  /// register with an equivalent LEA instruction.
61  void processInstruction(MachineBasicBlock::iterator &I,
63 
64  /// \brief Given a LEA instruction which is unprofitable
65  /// on Silvermont try to replace it with an equivalent ADD instruction
66  void processInstructionForSLM(MachineBasicBlock::iterator &I,
68 
69 
70  /// \brief Given a LEA instruction which is unprofitable
71  /// on SNB+ try to replace it with other instructions.
72  /// According to Intel's Optimization Reference Manual:
73  /// " For LEA instructions with three source operands and some specific
74  /// situations, instruction latency has increased to 3 cycles, and must
75  /// dispatch via port 1:
76  /// - LEA that has all three source operands: base, index, and offset
77  /// - LEA that uses base and index registers where the base is EBP, RBP,
78  /// or R13
79  /// - LEA that uses RIP relative addressing mode
80  /// - LEA that uses 16-bit addressing mode "
81  /// This function currently handles the first 2 cases only.
82  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
84 
85  /// \brief Look for LEAs that add 1 to reg or subtract 1 from reg
86  /// and convert them to INC or DEC respectively.
87  bool fixupIncDec(MachineBasicBlock::iterator &I,
88  MachineFunction::iterator MFI) const;
89 
90  /// \brief Determine if an instruction references a machine register
91  /// and, if so, whether it reads or writes the register.
92  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
93 
94  /// \brief Step backwards through a basic block, looking
95  /// for an instruction which writes a register within
96  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
100 
101  /// \brief if an instruction can be converted to an
102  /// equivalent LEA, insert the new instruction into the basic block
103  /// and return a pointer to it. Otherwise, return zero.
104  MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
105  MachineBasicBlock::iterator &MBBI) const;
106 
107 public:
108  static char ID;
109 
110  StringRef getPassName() const override { return FIXUPLEA_DESC; }
111 
112  FixupLEAPass() : MachineFunctionPass(ID) {
114  }
115 
116  /// \brief Loop over all of the basic blocks,
117  /// replacing instructions by equivalent LEA instructions
118  /// if needed and when possible.
119  bool runOnMachineFunction(MachineFunction &MF) override;
120 
121  // This pass runs after regalloc and doesn't support VReg operands.
122  MachineFunctionProperties getRequiredProperties() const override {
125  }
126 
127 private:
128  MachineFunction *MF;
129  const X86InstrInfo *TII; // Machine instruction info.
130  bool OptIncDec;
131  bool OptLEA;
132 };
133 }
134 
135 char FixupLEAPass::ID = 0;
136 
137 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
138 
139 MachineInstr *
140 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
141  MachineBasicBlock::iterator &MBBI) const {
142  MachineInstr &MI = *MBBI;
143  switch (MI.getOpcode()) {
144  case X86::MOV32rr:
145  case X86::MOV64rr: {
146  const MachineOperand &Src = MI.getOperand(1);
147  const MachineOperand &Dest = MI.getOperand(0);
148  MachineInstr *NewMI =
149  BuildMI(*MF, MI.getDebugLoc(),
150  TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
151  : X86::LEA64r))
152  .add(Dest)
153  .add(Src)
154  .addImm(1)
155  .addReg(0)
156  .addImm(0)
157  .addReg(0);
158  MFI->insert(MBBI, NewMI); // Insert the new inst
159  return NewMI;
160  }
161  case X86::ADD64ri32:
162  case X86::ADD64ri8:
163  case X86::ADD64ri32_DB:
164  case X86::ADD64ri8_DB:
165  case X86::ADD32ri:
166  case X86::ADD32ri8:
167  case X86::ADD32ri_DB:
168  case X86::ADD32ri8_DB:
169  case X86::ADD16ri:
170  case X86::ADD16ri8:
171  case X86::ADD16ri_DB:
172  case X86::ADD16ri8_DB:
173  if (!MI.getOperand(2).isImm()) {
174  // convertToThreeAddress will call getImm()
175  // which requires isImm() to be true
176  return nullptr;
177  }
178  break;
179  case X86::ADD16rr:
180  case X86::ADD16rr_DB:
181  if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
182  // if src1 != src2, then convertToThreeAddress will
183  // need to create a Virtual register, which we cannot do
184  // after register allocation.
185  return nullptr;
186  }
187  }
188  return TII->convertToThreeAddress(MFI, MI, nullptr);
189 }
190 
191 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
192 
193 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
194  if (skipFunction(Func.getFunction()))
195  return false;
196 
197  MF = &Func;
198  const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
199  OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize();
200  OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
201 
202  if (!OptLEA && !OptIncDec)
203  return false;
204 
205  TII = ST.getInstrInfo();
206 
207  DEBUG(dbgs() << "Start X86FixupLEAs\n";);
208  // Process all basic blocks.
209  for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
210  processBasicBlock(Func, I);
211  DEBUG(dbgs() << "End X86FixupLEAs\n";);
212 
213  return true;
214 }
215 
216 FixupLEAPass::RegUsageState
217 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
218  RegUsageState RegUsage = RU_NotUsed;
219  MachineInstr &MI = *I;
220 
221  for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
222  MachineOperand &opnd = MI.getOperand(i);
223  if (opnd.isReg() && opnd.getReg() == p.getReg()) {
224  if (opnd.isDef())
225  return RU_Write;
226  RegUsage = RU_Read;
227  }
228  }
229  return RegUsage;
230 }
231 
232 /// getPreviousInstr - Given a reference to an instruction in a basic
233 /// block, return a reference to the previous instruction in the block,
234 /// wrapping around to the last instruction of the block if the block
235 /// branches to itself.
238  if (I == MFI->begin()) {
239  if (MFI->isPredecessor(&*MFI)) {
240  I = --MFI->end();
241  return true;
242  } else
243  return false;
244  }
245  --I;
246  return true;
247 }
248 
250 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
252  int InstrDistance = 1;
254  static const int INSTR_DISTANCE_THRESHOLD = 5;
255 
256  CurInst = I;
257  bool Found;
258  Found = getPreviousInstr(CurInst, MFI);
259  while (Found && I != CurInst) {
260  if (CurInst->isCall() || CurInst->isInlineAsm())
261  break;
262  if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
263  break; // too far back to make a difference
264  if (usesRegister(p, CurInst) == RU_Write) {
265  return CurInst;
266  }
267  InstrDistance += TII->getInstrLatency(
268  MF->getSubtarget().getInstrItineraryData(), *CurInst);
269  Found = getPreviousInstr(CurInst, MFI);
270  }
272 }
273 
274 static inline bool isLEA(const int Opcode) {
275  return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
276  Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
277 }
278 
279 static inline bool isInefficientLEAReg(unsigned int Reg) {
280  return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
281 }
282 
283 static inline bool isRegOperand(const MachineOperand &Op) {
284  return Op.isReg() && Op.getReg() != X86::NoRegister;
285 }
286 /// hasIneffecientLEARegs - LEA that uses base and index registers
287 /// where the base is EBP, RBP, or R13
288 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
289  const MachineOperand &Index) {
290  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
291  isRegOperand(Index);
292 }
293 
294 static inline bool hasLEAOffset(const MachineOperand &Offset) {
295  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
296 }
297 
298 // LEA instruction that has all three operands: offset, base and index
299 static inline bool isThreeOperandsLEA(const MachineOperand &Base,
300  const MachineOperand &Index,
301  const MachineOperand &Offset) {
302  return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
303 }
304 
305 static inline int getADDrrFromLEA(int LEAOpcode) {
306  switch (LEAOpcode) {
307  default:
308  llvm_unreachable("Unexpected LEA instruction");
309  case X86::LEA16r:
310  return X86::ADD16rr;
311  case X86::LEA32r:
312  return X86::ADD32rr;
313  case X86::LEA64_32r:
314  case X86::LEA64r:
315  return X86::ADD64rr;
316  }
317 }
318 
319 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
320  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
321  switch (LEAOpcode) {
322  default:
323  llvm_unreachable("Unexpected LEA instruction");
324  case X86::LEA16r:
325  return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
326  case X86::LEA32r:
327  case X86::LEA64_32r:
328  return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
329  case X86::LEA64r:
330  return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
331  }
332 }
333 
334 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
335 /// lea %reg, 1(%reg)
336 /// lea %reg, -1(%reg)
337 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
338  unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
339  unsigned DstReg = LEA.getOperand(0).getReg();
340  unsigned AddrDispOp = 1 + X86::AddrDisp;
341  return SrcReg == DstReg &&
342  LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
343  LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
344  LEA.getOperand(AddrDispOp).isImm() &&
345  (LEA.getOperand(AddrDispOp).getImm() == 1 ||
346  LEA.getOperand(AddrDispOp).getImm() == -1);
347 }
348 
349 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
350  MachineFunction::iterator MFI) const {
351  MachineInstr &MI = *I;
352  int Opcode = MI.getOpcode();
353  if (!isLEA(Opcode))
354  return false;
355 
356  if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
357  int NewOpcode;
358  bool isINC = MI.getOperand(4).getImm() == 1;
359  switch (Opcode) {
360  case X86::LEA16r:
361  NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
362  break;
363  case X86::LEA32r:
364  case X86::LEA64_32r:
365  NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
366  break;
367  case X86::LEA64r:
368  NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
369  break;
370  }
371 
372  MachineInstr *NewMI =
373  BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
374  .add(MI.getOperand(0))
375  .add(MI.getOperand(1));
376  MFI->erase(I);
377  I = static_cast<MachineBasicBlock::iterator>(NewMI);
378  return true;
379  }
380  return false;
381 }
382 
383 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
385  // Process a load, store, or LEA instruction.
386  MachineInstr &MI = *I;
387  const MCInstrDesc &Desc = MI.getDesc();
388  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
389  if (AddrOffset >= 0) {
390  AddrOffset += X86II::getOperandBias(Desc);
391  MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
392  if (p.isReg() && p.getReg() != X86::ESP) {
393  seekLEAFixup(p, I, MFI);
394  }
395  MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
396  if (q.isReg() && q.getReg() != X86::ESP) {
397  seekLEAFixup(q, I, MFI);
398  }
399  }
400 }
401 
402 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
405  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
406  if (MBI != MachineBasicBlock::iterator()) {
407  MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
408  if (NewMI) {
409  ++NumLEAs;
410  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
411  // now to replace with an equivalent LEA...
412  DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
413  MFI->erase(MBI);
415  static_cast<MachineBasicBlock::iterator>(NewMI);
416  processInstruction(J, MFI);
417  }
418  }
419 }
420 
421 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
423  MachineInstr &MI = *I;
424  const int Opcode = MI.getOpcode();
425  if (!isLEA(Opcode))
426  return;
427  if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
428  !TII->isSafeToClobberEFLAGS(*MFI, I))
429  return;
430  const unsigned DstR = MI.getOperand(0).getReg();
431  const unsigned SrcR1 = MI.getOperand(1).getReg();
432  const unsigned SrcR2 = MI.getOperand(3).getReg();
433  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
434  return;
435  if (MI.getOperand(2).getImm() > 1)
436  return;
437  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
438  DEBUG(dbgs() << "FixLEA: Replaced by: ";);
439  MachineInstr *NewMI = nullptr;
440  // Make ADD instruction for two registers writing to LEA's destination
441  if (SrcR1 != 0 && SrcR2 != 0) {
442  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
443  const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
444  NewMI =
445  BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
446  DEBUG(NewMI->dump(););
447  }
448  // Make ADD instruction for immediate
449  if (MI.getOperand(4).getImm() != 0) {
450  const MCInstrDesc &ADDri =
451  TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
452  const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
453  NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
454  .add(SrcR)
455  .addImm(MI.getOperand(4).getImm());
456  DEBUG(NewMI->dump(););
457  }
458  if (NewMI) {
459  MFI->erase(I);
460  I = NewMI;
461  }
462 }
463 
464 MachineInstr *
465 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
467 
468  const int LEAOpcode = MI.getOpcode();
469  if (!isLEA(LEAOpcode))
470  return nullptr;
471 
472  const MachineOperand &Dst = MI.getOperand(0);
473  const MachineOperand &Base = MI.getOperand(1);
474  const MachineOperand &Scale = MI.getOperand(2);
475  const MachineOperand &Index = MI.getOperand(3);
476  const MachineOperand &Offset = MI.getOperand(4);
477  const MachineOperand &Segment = MI.getOperand(5);
478 
479  if (!(isThreeOperandsLEA(Base, Index, Offset) ||
480  hasInefficientLEABaseReg(Base, Index)) ||
481  !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
482  Segment.getReg() != X86::NoRegister)
483  return nullptr;
484 
485  unsigned int DstR = Dst.getReg();
486  unsigned int BaseR = Base.getReg();
487  unsigned int IndexR = Index.getReg();
488  unsigned SSDstR =
489  (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
490  bool IsScale1 = Scale.getImm() == 1;
491  bool IsInefficientBase = isInefficientLEAReg(BaseR);
492  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
493 
494  // Skip these cases since it takes more than 2 instructions
495  // to replace the LEA instruction.
496  if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
497  return nullptr;
498  if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
499  (IsInefficientIndex || !IsScale1))
500  return nullptr;
501 
502  const DebugLoc DL = MI.getDebugLoc();
503  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
504  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
505 
506  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
507  DEBUG(dbgs() << "FixLEA: Replaced by: ";);
508 
509  // First try to replace LEA with one or two (for the 3-op LEA case)
510  // add instructions:
511  // 1.lea (%base,%index,1), %base => add %index,%base
512  // 2.lea (%base,%index,1), %index => add %base,%index
513  if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
514  const MachineOperand &Src = DstR == BaseR ? Index : Base;
515  MachineInstr *NewMI =
516  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
517  DEBUG(NewMI->dump(););
518  // Create ADD instruction for the Offset in case of 3-Ops LEA.
519  if (hasLEAOffset(Offset)) {
520  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
521  DEBUG(NewMI->dump(););
522  }
523  return NewMI;
524  }
525  // If the base is inefficient try switching the index and base operands,
526  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
527  // lea offset(%base,%index,scale),%dst =>
528  // lea (%base,%index,scale); add offset,%dst
529  if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
530  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
531  .add(Dst)
532  .add(IsInefficientBase ? Index : Base)
533  .add(Scale)
534  .add(IsInefficientBase ? Base : Index)
535  .addImm(0)
536  .add(Segment);
537  DEBUG(NewMI->dump(););
538  // Create ADD instruction for the Offset in case of 3-Ops LEA.
539  if (hasLEAOffset(Offset)) {
540  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
541  DEBUG(NewMI->dump(););
542  }
543  return NewMI;
544  }
545  // Handle the rest of the cases with inefficient base register:
546  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
547  assert(IsInefficientBase && "efficient base should be handled already!");
548 
549  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
550  if (IsScale1 && !hasLEAOffset(Offset)) {
551  bool BIK = Base.isKill() && BaseR != IndexR;
552  TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK);
553  DEBUG(MI.getPrevNode()->dump(););
554 
555  MachineInstr *NewMI =
556  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
557  DEBUG(NewMI->dump(););
558  return NewMI;
559  }
560  // lea offset(%base,%index,scale), %dst =>
561  // lea offset( ,%index,scale), %dst; add %base,%dst
562  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
563  .add(Dst)
564  .addReg(0)
565  .add(Scale)
566  .add(Index)
567  .add(Offset)
568  .add(Segment);
569  DEBUG(NewMI->dump(););
570 
571  NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
572  DEBUG(NewMI->dump(););
573  return NewMI;
574 }
575 
576 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
578 
579  for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
580  if (OptIncDec)
581  if (fixupIncDec(I, MFI))
582  continue;
583 
584  if (OptLEA) {
585  if (MF.getSubtarget<X86Subtarget>().isSLM())
586  processInstructionForSLM(I, MFI);
587 
588  else {
589  if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
590  if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
591  MFI->erase(I);
592  I = NewMI;
593  }
594  } else
595  processInstruction(I, MFI);
596  }
597  }
598  }
599  return false;
600 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static bool isRegOperand(const MachineOperand &Op)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isLEASimpleIncOrDec(MachineInstr &LEA)
isLEASimpleIncOrDec - Does this LEA have one these forms: lea reg, 1(reg) lea reg, -1(reg)
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:446
bool slowLEA() const
Definition: X86Subtarget.h:606
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool getPreviousInstr(MachineBasicBlock::iterator &I, MachineFunction::iterator MFI)
getPreviousInstr - Given a reference to an instruction in a basic block, return a reference to the pr...
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:295
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
static bool isLEA(const int Opcode)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static int getADDrrFromLEA(int LEAOpcode)
static bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index)
hasIneffecientLEARegs - LEA that uses base and index registers where the base is EBP, RBP, or R13
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:296
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
bool slow3OpsLEA() const
Definition: X86Subtarget.h:607
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
static int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
bool isSLM() const
Definition: X86Subtarget.h:658
static bool isInefficientLEAReg(unsigned int Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void initializeFixupLEAPassPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:649
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool slowIncDec() const
Definition: X86Subtarget.h:608
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
#define FIXUPLEA_DESC
Iterator for intrusive lists based on ilist_node.
bool LEAusesAG() const
Definition: X86Subtarget.h:605
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isThreeOperandsLEA(const MachineOperand &Base, const MachineOperand &Index, const MachineOperand &Offset)
#define FIXUPLEA_NAME
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool hasLEAOffset(const MachineOperand &Offset)
#define I(x, y, z)
Definition: MD5.cpp:58
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:573
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
Properties which a MachineFunction may have at a given point in time.
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:678