LLVM  6.0.0svn
X86FixupLEAs.cpp
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1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass that finds instructions that can be
11 // re-written as LEA instructions in order to reduce pipeline delays.
12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86.h"
17 #include "X86InstrInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Support/Debug.h"
28 using namespace llvm;
29 
30 namespace llvm {
32 }
33 
34 #define FIXUPLEA_DESC "X86 LEA Fixup"
35 #define FIXUPLEA_NAME "x86-fixup-LEAs"
36 
37 #define DEBUG_TYPE FIXUPLEA_NAME
38 
39 STATISTIC(NumLEAs, "Number of LEA instructions created");
40 
41 namespace {
42 class FixupLEAPass : public MachineFunctionPass {
43  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
44 
45  /// \brief Loop over all of the instructions in the basic block
46  /// replacing applicable instructions with LEA instructions,
47  /// where appropriate.
48  bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
49 
50 
51  /// \brief Given a machine register, look for the instruction
52  /// which writes it in the current basic block. If found,
53  /// try to replace it with an equivalent LEA instruction.
54  /// If replacement succeeds, then also process the newly created
55  /// instruction.
56  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
58 
59  /// \brief Given a memory access or LEA instruction
60  /// whose address mode uses a base and/or index register, look for
61  /// an opportunity to replace the instruction which sets the base or index
62  /// register with an equivalent LEA instruction.
63  void processInstruction(MachineBasicBlock::iterator &I,
65 
66  /// \brief Given a LEA instruction which is unprofitable
67  /// on Silvermont try to replace it with an equivalent ADD instruction
68  void processInstructionForSLM(MachineBasicBlock::iterator &I,
70 
71 
72  /// \brief Given a LEA instruction which is unprofitable
73  /// on SNB+ try to replace it with other instructions.
74  /// According to Intel's Optimization Reference Manual:
75  /// " For LEA instructions with three source operands and some specific
76  /// situations, instruction latency has increased to 3 cycles, and must
77  /// dispatch via port 1:
78  /// - LEA that has all three source operands: base, index, and offset
79  /// - LEA that uses base and index registers where the base is EBP, RBP,
80  /// or R13
81  /// - LEA that uses RIP relative addressing mode
82  /// - LEA that uses 16-bit addressing mode "
83  /// This function currently handles the first 2 cases only.
84  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
86 
87  /// \brief Look for LEAs that add 1 to reg or subtract 1 from reg
88  /// and convert them to INC or DEC respectively.
89  bool fixupIncDec(MachineBasicBlock::iterator &I,
90  MachineFunction::iterator MFI) const;
91 
92  /// \brief Determine if an instruction references a machine register
93  /// and, if so, whether it reads or writes the register.
94  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
95 
96  /// \brief Step backwards through a basic block, looking
97  /// for an instruction which writes a register within
98  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
102 
103  /// \brief if an instruction can be converted to an
104  /// equivalent LEA, insert the new instruction into the basic block
105  /// and return a pointer to it. Otherwise, return zero.
106  MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
107  MachineBasicBlock::iterator &MBBI) const;
108 
109 public:
110  static char ID;
111 
112  StringRef getPassName() const override { return FIXUPLEA_DESC; }
113 
114  FixupLEAPass() : MachineFunctionPass(ID) {
116  }
117 
118  /// \brief Loop over all of the basic blocks,
119  /// replacing instructions by equivalent LEA instructions
120  /// if needed and when possible.
121  bool runOnMachineFunction(MachineFunction &MF) override;
122 
123  // This pass runs after regalloc and doesn't support VReg operands.
124  MachineFunctionProperties getRequiredProperties() const override {
127  }
128 
129 private:
130  MachineFunction *MF;
131  const X86InstrInfo *TII; // Machine instruction info.
132  bool OptIncDec;
133  bool OptLEA;
134 };
135 }
136 
137 char FixupLEAPass::ID = 0;
138 
139 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
140 
141 MachineInstr *
142 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
143  MachineBasicBlock::iterator &MBBI) const {
144  MachineInstr &MI = *MBBI;
145  switch (MI.getOpcode()) {
146  case X86::MOV32rr:
147  case X86::MOV64rr: {
148  const MachineOperand &Src = MI.getOperand(1);
149  const MachineOperand &Dest = MI.getOperand(0);
150  MachineInstr *NewMI =
151  BuildMI(*MF, MI.getDebugLoc(),
152  TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
153  : X86::LEA64r))
154  .add(Dest)
155  .add(Src)
156  .addImm(1)
157  .addReg(0)
158  .addImm(0)
159  .addReg(0);
160  MFI->insert(MBBI, NewMI); // Insert the new inst
161  return NewMI;
162  }
163  case X86::ADD64ri32:
164  case X86::ADD64ri8:
165  case X86::ADD64ri32_DB:
166  case X86::ADD64ri8_DB:
167  case X86::ADD32ri:
168  case X86::ADD32ri8:
169  case X86::ADD32ri_DB:
170  case X86::ADD32ri8_DB:
171  case X86::ADD16ri:
172  case X86::ADD16ri8:
173  case X86::ADD16ri_DB:
174  case X86::ADD16ri8_DB:
175  if (!MI.getOperand(2).isImm()) {
176  // convertToThreeAddress will call getImm()
177  // which requires isImm() to be true
178  return nullptr;
179  }
180  break;
181  case X86::ADD16rr:
182  case X86::ADD16rr_DB:
183  if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
184  // if src1 != src2, then convertToThreeAddress will
185  // need to create a Virtual register, which we cannot do
186  // after register allocation.
187  return nullptr;
188  }
189  }
190  return TII->convertToThreeAddress(MFI, MI, nullptr);
191 }
192 
193 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
194 
195 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
196  if (skipFunction(*Func.getFunction()))
197  return false;
198 
199  MF = &Func;
200  const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
201  OptIncDec = !ST.slowIncDec() || Func.getFunction()->optForMinSize();
202  OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
203 
204  if (!OptLEA && !OptIncDec)
205  return false;
206 
207  TII = ST.getInstrInfo();
208 
209  DEBUG(dbgs() << "Start X86FixupLEAs\n";);
210  // Process all basic blocks.
211  for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
212  processBasicBlock(Func, I);
213  DEBUG(dbgs() << "End X86FixupLEAs\n";);
214 
215  return true;
216 }
217 
218 FixupLEAPass::RegUsageState
219 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
220  RegUsageState RegUsage = RU_NotUsed;
221  MachineInstr &MI = *I;
222 
223  for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
224  MachineOperand &opnd = MI.getOperand(i);
225  if (opnd.isReg() && opnd.getReg() == p.getReg()) {
226  if (opnd.isDef())
227  return RU_Write;
228  RegUsage = RU_Read;
229  }
230  }
231  return RegUsage;
232 }
233 
234 /// getPreviousInstr - Given a reference to an instruction in a basic
235 /// block, return a reference to the previous instruction in the block,
236 /// wrapping around to the last instruction of the block if the block
237 /// branches to itself.
240  if (I == MFI->begin()) {
241  if (MFI->isPredecessor(&*MFI)) {
242  I = --MFI->end();
243  return true;
244  } else
245  return false;
246  }
247  --I;
248  return true;
249 }
250 
252 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
254  int InstrDistance = 1;
256  static const int INSTR_DISTANCE_THRESHOLD = 5;
257 
258  CurInst = I;
259  bool Found;
260  Found = getPreviousInstr(CurInst, MFI);
261  while (Found && I != CurInst) {
262  if (CurInst->isCall() || CurInst->isInlineAsm())
263  break;
264  if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
265  break; // too far back to make a difference
266  if (usesRegister(p, CurInst) == RU_Write) {
267  return CurInst;
268  }
269  InstrDistance += TII->getInstrLatency(
270  MF->getSubtarget().getInstrItineraryData(), *CurInst);
271  Found = getPreviousInstr(CurInst, MFI);
272  }
274 }
275 
276 static inline bool isLEA(const int Opcode) {
277  return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
278  Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
279 }
280 
281 static inline bool isInefficientLEAReg(unsigned int Reg) {
282  return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
283 }
284 
285 static inline bool isRegOperand(const MachineOperand &Op) {
286  return Op.isReg() && Op.getReg() != X86::NoRegister;
287 }
288 /// hasIneffecientLEARegs - LEA that uses base and index registers
289 /// where the base is EBP, RBP, or R13
290 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
291  const MachineOperand &Index) {
292  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
293  isRegOperand(Index);
294 }
295 
296 static inline bool hasLEAOffset(const MachineOperand &Offset) {
297  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
298 }
299 
300 // LEA instruction that has all three operands: offset, base and index
301 static inline bool isThreeOperandsLEA(const MachineOperand &Base,
302  const MachineOperand &Index,
303  const MachineOperand &Offset) {
304  return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
305 }
306 
307 static inline int getADDrrFromLEA(int LEAOpcode) {
308  switch (LEAOpcode) {
309  default:
310  llvm_unreachable("Unexpected LEA instruction");
311  case X86::LEA16r:
312  return X86::ADD16rr;
313  case X86::LEA32r:
314  return X86::ADD32rr;
315  case X86::LEA64_32r:
316  case X86::LEA64r:
317  return X86::ADD64rr;
318  }
319 }
320 
321 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
322  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
323  switch (LEAOpcode) {
324  default:
325  llvm_unreachable("Unexpected LEA instruction");
326  case X86::LEA16r:
327  return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
328  case X86::LEA32r:
329  case X86::LEA64_32r:
330  return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
331  case X86::LEA64r:
332  return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
333  }
334 }
335 
336 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
337 /// lea %reg, 1(%reg)
338 /// lea %reg, -1(%reg)
339 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
340  unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
341  unsigned DstReg = LEA.getOperand(0).getReg();
342  unsigned AddrDispOp = 1 + X86::AddrDisp;
343  return SrcReg == DstReg &&
344  LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
345  LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
346  LEA.getOperand(AddrDispOp).isImm() &&
347  (LEA.getOperand(AddrDispOp).getImm() == 1 ||
348  LEA.getOperand(AddrDispOp).getImm() == -1);
349 }
350 
351 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
352  MachineFunction::iterator MFI) const {
353  MachineInstr &MI = *I;
354  int Opcode = MI.getOpcode();
355  if (!isLEA(Opcode))
356  return false;
357 
358  if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
359  int NewOpcode;
360  bool isINC = MI.getOperand(4).getImm() == 1;
361  switch (Opcode) {
362  case X86::LEA16r:
363  NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
364  break;
365  case X86::LEA32r:
366  case X86::LEA64_32r:
367  NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
368  break;
369  case X86::LEA64r:
370  NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
371  break;
372  }
373 
374  MachineInstr *NewMI =
375  BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
376  .add(MI.getOperand(0))
377  .add(MI.getOperand(1));
378  MFI->erase(I);
379  I = static_cast<MachineBasicBlock::iterator>(NewMI);
380  return true;
381  }
382  return false;
383 }
384 
385 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
387  // Process a load, store, or LEA instruction.
388  MachineInstr &MI = *I;
389  const MCInstrDesc &Desc = MI.getDesc();
390  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
391  if (AddrOffset >= 0) {
392  AddrOffset += X86II::getOperandBias(Desc);
393  MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
394  if (p.isReg() && p.getReg() != X86::ESP) {
395  seekLEAFixup(p, I, MFI);
396  }
397  MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
398  if (q.isReg() && q.getReg() != X86::ESP) {
399  seekLEAFixup(q, I, MFI);
400  }
401  }
402 }
403 
404 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
407  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
408  if (MBI != MachineBasicBlock::iterator()) {
409  MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
410  if (NewMI) {
411  ++NumLEAs;
412  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
413  // now to replace with an equivalent LEA...
414  DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
415  MFI->erase(MBI);
417  static_cast<MachineBasicBlock::iterator>(NewMI);
418  processInstruction(J, MFI);
419  }
420  }
421 }
422 
423 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
425  MachineInstr &MI = *I;
426  const int Opcode = MI.getOpcode();
427  if (!isLEA(Opcode))
428  return;
429  if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
430  !TII->isSafeToClobberEFLAGS(*MFI, I))
431  return;
432  const unsigned DstR = MI.getOperand(0).getReg();
433  const unsigned SrcR1 = MI.getOperand(1).getReg();
434  const unsigned SrcR2 = MI.getOperand(3).getReg();
435  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
436  return;
437  if (MI.getOperand(2).getImm() > 1)
438  return;
439  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
440  DEBUG(dbgs() << "FixLEA: Replaced by: ";);
441  MachineInstr *NewMI = nullptr;
442  // Make ADD instruction for two registers writing to LEA's destination
443  if (SrcR1 != 0 && SrcR2 != 0) {
444  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
445  const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
446  NewMI =
447  BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
448  DEBUG(NewMI->dump(););
449  }
450  // Make ADD instruction for immediate
451  if (MI.getOperand(4).getImm() != 0) {
452  const MCInstrDesc &ADDri =
453  TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
454  const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
455  NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
456  .add(SrcR)
457  .addImm(MI.getOperand(4).getImm());
458  DEBUG(NewMI->dump(););
459  }
460  if (NewMI) {
461  MFI->erase(I);
462  I = NewMI;
463  }
464 }
465 
466 MachineInstr *
467 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
469 
470  const int LEAOpcode = MI.getOpcode();
471  if (!isLEA(LEAOpcode))
472  return nullptr;
473 
474  const MachineOperand &Dst = MI.getOperand(0);
475  const MachineOperand &Base = MI.getOperand(1);
476  const MachineOperand &Scale = MI.getOperand(2);
477  const MachineOperand &Index = MI.getOperand(3);
478  const MachineOperand &Offset = MI.getOperand(4);
479  const MachineOperand &Segment = MI.getOperand(5);
480 
481  if (!(isThreeOperandsLEA(Base, Index, Offset) ||
482  hasInefficientLEABaseReg(Base, Index)) ||
483  !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
484  Segment.getReg() != X86::NoRegister)
485  return nullptr;
486 
487  unsigned int DstR = Dst.getReg();
488  unsigned int BaseR = Base.getReg();
489  unsigned int IndexR = Index.getReg();
490  unsigned SSDstR =
491  (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
492  bool IsScale1 = Scale.getImm() == 1;
493  bool IsInefficientBase = isInefficientLEAReg(BaseR);
494  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
495 
496  // Skip these cases since it takes more than 2 instructions
497  // to replace the LEA instruction.
498  if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
499  return nullptr;
500  if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
501  (IsInefficientIndex || !IsScale1))
502  return nullptr;
503 
504  const DebugLoc DL = MI.getDebugLoc();
505  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
506  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
507 
508  DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
509  DEBUG(dbgs() << "FixLEA: Replaced by: ";);
510 
511  // First try to replace LEA with one or two (for the 3-op LEA case)
512  // add instructions:
513  // 1.lea (%base,%index,1), %base => add %index,%base
514  // 2.lea (%base,%index,1), %index => add %base,%index
515  if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
516  const MachineOperand &Src = DstR == BaseR ? Index : Base;
517  MachineInstr *NewMI =
518  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
519  DEBUG(NewMI->dump(););
520  // Create ADD instruction for the Offset in case of 3-Ops LEA.
521  if (hasLEAOffset(Offset)) {
522  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
523  DEBUG(NewMI->dump(););
524  }
525  return NewMI;
526  }
527  // If the base is inefficient try switching the index and base operands,
528  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
529  // lea offset(%base,%index,scale),%dst =>
530  // lea (%base,%index,scale); add offset,%dst
531  if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
532  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
533  .add(Dst)
534  .add(IsInefficientBase ? Index : Base)
535  .add(Scale)
536  .add(IsInefficientBase ? Base : Index)
537  .addImm(0)
538  .add(Segment);
539  DEBUG(NewMI->dump(););
540  // Create ADD instruction for the Offset in case of 3-Ops LEA.
541  if (hasLEAOffset(Offset)) {
542  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
543  DEBUG(NewMI->dump(););
544  }
545  return NewMI;
546  }
547  // Handle the rest of the cases with inefficient base register:
548  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
549  assert(IsInefficientBase && "efficient base should be handled already!");
550 
551  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
552  if (IsScale1 && !hasLEAOffset(Offset)) {
553  TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, Base.isKill());
554  DEBUG(MI.getPrevNode()->dump(););
555 
556  MachineInstr *NewMI =
557  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
558  DEBUG(NewMI->dump(););
559  return NewMI;
560  }
561  // lea offset(%base,%index,scale), %dst =>
562  // lea offset( ,%index,scale), %dst; add %base,%dst
563  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
564  .add(Dst)
565  .addReg(0)
566  .add(Scale)
567  .add(Index)
568  .add(Offset)
569  .add(Segment);
570  DEBUG(NewMI->dump(););
571 
572  NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
573  DEBUG(NewMI->dump(););
574  return NewMI;
575 }
576 
577 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
579 
580  for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
581  if (OptIncDec)
582  if (fixupIncDec(I, MFI))
583  continue;
584 
585  if (OptLEA) {
586  if (MF.getSubtarget<X86Subtarget>().isSLM())
587  processInstructionForSLM(I, MFI);
588 
589  else {
590  if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
591  if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
592  MFI->erase(I);
593  I = NewMI;
594  }
595  } else
596  processInstruction(I, MFI);
597  }
598  }
599  }
600  return false;
601 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static bool isRegOperand(const MachineOperand &Op)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isLEASimpleIncOrDec(MachineInstr &LEA)
isLEASimpleIncOrDec - Does this LEA have one these forms: lea reg, 1(reg) lea reg, -1(reg)
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:383
bool slowLEA() const
Definition: X86Subtarget.h:528
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool getPreviousInstr(MachineBasicBlock::iterator &I, MachineFunction::iterator MFI)
getPreviousInstr - Given a reference to an instruction in a basic block, return a reference to the pr...
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:295
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
static bool isLEA(const int Opcode)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static int getADDrrFromLEA(int LEAOpcode)
static bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index)
hasIneffecientLEARegs - LEA that uses base and index registers where the base is EBP, RBP, or R13
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool slow3OpsLEA() const
Definition: X86Subtarget.h:529
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
static int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
bool isSLM() const
Definition: X86Subtarget.h:551
static bool isInefficientLEAReg(unsigned int Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void initializeFixupLEAPassPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:647
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool slowIncDec() const
Definition: X86Subtarget.h:530
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
#define FIXUPLEA_DESC
Iterator for intrusive lists based on ilist_node.
bool LEAusesAG() const
Definition: X86Subtarget.h:527
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isThreeOperandsLEA(const MachineOperand &Base, const MachineOperand &Index, const MachineOperand &Offset)
#define FIXUPLEA_NAME
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool hasLEAOffset(const MachineOperand &Offset)
#define I(x, y, z)
Definition: MD5.cpp:58
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:527
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Properties which a MachineFunction may have at a given point in time.
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:676