LLVM  7.0.0svn
X86FixupLEAs.cpp
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1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass that finds instructions that can be
11 // re-written as LEA instructions in order to reduce pipeline delays.
12 // When optimizing for size it replaces suitable LEAs with INC or DEC.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86.h"
17 #include "X86InstrInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Support/Debug.h"
26 using namespace llvm;
27 
28 namespace llvm {
30 }
31 
32 #define FIXUPLEA_DESC "X86 LEA Fixup"
33 #define FIXUPLEA_NAME "x86-fixup-LEAs"
34 
35 #define DEBUG_TYPE FIXUPLEA_NAME
36 
37 STATISTIC(NumLEAs, "Number of LEA instructions created");
38 
39 namespace {
40 class FixupLEAPass : public MachineFunctionPass {
41  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
42 
43  /// Loop over all of the instructions in the basic block
44  /// replacing applicable instructions with LEA instructions,
45  /// where appropriate.
46  bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
47 
48 
49  /// Given a machine register, look for the instruction
50  /// which writes it in the current basic block. If found,
51  /// try to replace it with an equivalent LEA instruction.
52  /// If replacement succeeds, then also process the newly created
53  /// instruction.
54  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
56 
57  /// Given a memory access or LEA instruction
58  /// whose address mode uses a base and/or index register, look for
59  /// an opportunity to replace the instruction which sets the base or index
60  /// register with an equivalent LEA instruction.
61  void processInstruction(MachineBasicBlock::iterator &I,
63 
64  /// Given a LEA instruction which is unprofitable
65  /// on Silvermont try to replace it with an equivalent ADD instruction
66  void processInstructionForSLM(MachineBasicBlock::iterator &I,
68 
69 
70  /// Given a LEA instruction which is unprofitable
71  /// on SNB+ try to replace it with other instructions.
72  /// According to Intel's Optimization Reference Manual:
73  /// " For LEA instructions with three source operands and some specific
74  /// situations, instruction latency has increased to 3 cycles, and must
75  /// dispatch via port 1:
76  /// - LEA that has all three source operands: base, index, and offset
77  /// - LEA that uses base and index registers where the base is EBP, RBP,
78  /// or R13
79  /// - LEA that uses RIP relative addressing mode
80  /// - LEA that uses 16-bit addressing mode "
81  /// This function currently handles the first 2 cases only.
82  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
84 
85  /// Look for LEAs that add 1 to reg or subtract 1 from reg
86  /// and convert them to INC or DEC respectively.
87  bool fixupIncDec(MachineBasicBlock::iterator &I,
88  MachineFunction::iterator MFI) const;
89 
90  /// Determine if an instruction references a machine register
91  /// and, if so, whether it reads or writes the register.
92  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
93 
94  /// Step backwards through a basic block, looking
95  /// for an instruction which writes a register within
96  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
100 
101  /// if an instruction can be converted to an
102  /// equivalent LEA, insert the new instruction into the basic block
103  /// and return a pointer to it. Otherwise, return zero.
104  MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
105  MachineBasicBlock::iterator &MBBI) const;
106 
107 public:
108  static char ID;
109 
110  StringRef getPassName() const override { return FIXUPLEA_DESC; }
111 
112  FixupLEAPass() : MachineFunctionPass(ID) {
114  }
115 
116  /// Loop over all of the basic blocks,
117  /// replacing instructions by equivalent LEA instructions
118  /// if needed and when possible.
119  bool runOnMachineFunction(MachineFunction &MF) override;
120 
121  // This pass runs after regalloc and doesn't support VReg operands.
122  MachineFunctionProperties getRequiredProperties() const override {
125  }
126 
127 private:
128  TargetSchedModel TSM;
129  MachineFunction *MF;
130  const X86InstrInfo *TII; // Machine instruction info.
131  bool OptIncDec;
132  bool OptLEA;
133 };
134 }
135 
136 char FixupLEAPass::ID = 0;
137 
138 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
139 
140 MachineInstr *
141 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
142  MachineBasicBlock::iterator &MBBI) const {
143  MachineInstr &MI = *MBBI;
144  switch (MI.getOpcode()) {
145  case X86::MOV32rr:
146  case X86::MOV64rr: {
147  const MachineOperand &Src = MI.getOperand(1);
148  const MachineOperand &Dest = MI.getOperand(0);
149  MachineInstr *NewMI =
150  BuildMI(*MF, MI.getDebugLoc(),
151  TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
152  : X86::LEA64r))
153  .add(Dest)
154  .add(Src)
155  .addImm(1)
156  .addReg(0)
157  .addImm(0)
158  .addReg(0);
159  MFI->insert(MBBI, NewMI); // Insert the new inst
160  return NewMI;
161  }
162  case X86::ADD64ri32:
163  case X86::ADD64ri8:
164  case X86::ADD64ri32_DB:
165  case X86::ADD64ri8_DB:
166  case X86::ADD32ri:
167  case X86::ADD32ri8:
168  case X86::ADD32ri_DB:
169  case X86::ADD32ri8_DB:
170  case X86::ADD16ri:
171  case X86::ADD16ri8:
172  case X86::ADD16ri_DB:
173  case X86::ADD16ri8_DB:
174  if (!MI.getOperand(2).isImm()) {
175  // convertToThreeAddress will call getImm()
176  // which requires isImm() to be true
177  return nullptr;
178  }
179  break;
180  case X86::ADD16rr:
181  case X86::ADD16rr_DB:
182  if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
183  // if src1 != src2, then convertToThreeAddress will
184  // need to create a Virtual register, which we cannot do
185  // after register allocation.
186  return nullptr;
187  }
188  }
189  return TII->convertToThreeAddress(MFI, MI, nullptr);
190 }
191 
192 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
193 
194 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
195  if (skipFunction(Func.getFunction()))
196  return false;
197 
198  MF = &Func;
199  const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
200  OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize();
201  OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
202 
203  if (!OptLEA && !OptIncDec)
204  return false;
205 
206  TSM.init(&Func.getSubtarget());
207  TII = ST.getInstrInfo();
208 
209  LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
210  // Process all basic blocks.
211  for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
212  processBasicBlock(Func, I);
213  LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
214 
215  return true;
216 }
217 
218 FixupLEAPass::RegUsageState
219 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
220  RegUsageState RegUsage = RU_NotUsed;
221  MachineInstr &MI = *I;
222 
223  for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
224  MachineOperand &opnd = MI.getOperand(i);
225  if (opnd.isReg() && opnd.getReg() == p.getReg()) {
226  if (opnd.isDef())
227  return RU_Write;
228  RegUsage = RU_Read;
229  }
230  }
231  return RegUsage;
232 }
233 
234 /// getPreviousInstr - Given a reference to an instruction in a basic
235 /// block, return a reference to the previous instruction in the block,
236 /// wrapping around to the last instruction of the block if the block
237 /// branches to itself.
240  if (I == MFI->begin()) {
241  if (MFI->isPredecessor(&*MFI)) {
242  I = --MFI->end();
243  return true;
244  } else
245  return false;
246  }
247  --I;
248  return true;
249 }
250 
252 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
254  int InstrDistance = 1;
256  static const int INSTR_DISTANCE_THRESHOLD = 5;
257 
258  CurInst = I;
259  bool Found;
260  Found = getPreviousInstr(CurInst, MFI);
261  while (Found && I != CurInst) {
262  if (CurInst->isCall() || CurInst->isInlineAsm())
263  break;
264  if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
265  break; // too far back to make a difference
266  if (usesRegister(p, CurInst) == RU_Write) {
267  return CurInst;
268  }
269  InstrDistance += TSM.computeInstrLatency(&*CurInst);
270  Found = getPreviousInstr(CurInst, MFI);
271  }
273 }
274 
275 static inline bool isLEA(const int Opcode) {
276  return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
277  Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
278 }
279 
280 static inline bool isInefficientLEAReg(unsigned int Reg) {
281  return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
282 }
283 
284 static inline bool isRegOperand(const MachineOperand &Op) {
285  return Op.isReg() && Op.getReg() != X86::NoRegister;
286 }
287 /// hasIneffecientLEARegs - LEA that uses base and index registers
288 /// where the base is EBP, RBP, or R13
289 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
290  const MachineOperand &Index) {
291  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
292  isRegOperand(Index);
293 }
294 
295 static inline bool hasLEAOffset(const MachineOperand &Offset) {
296  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
297 }
298 
299 // LEA instruction that has all three operands: offset, base and index
300 static inline bool isThreeOperandsLEA(const MachineOperand &Base,
301  const MachineOperand &Index,
302  const MachineOperand &Offset) {
303  return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
304 }
305 
306 static inline int getADDrrFromLEA(int LEAOpcode) {
307  switch (LEAOpcode) {
308  default:
309  llvm_unreachable("Unexpected LEA instruction");
310  case X86::LEA16r:
311  return X86::ADD16rr;
312  case X86::LEA32r:
313  return X86::ADD32rr;
314  case X86::LEA64_32r:
315  case X86::LEA64r:
316  return X86::ADD64rr;
317  }
318 }
319 
320 static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
321  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
322  switch (LEAOpcode) {
323  default:
324  llvm_unreachable("Unexpected LEA instruction");
325  case X86::LEA16r:
326  return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
327  case X86::LEA32r:
328  case X86::LEA64_32r:
329  return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
330  case X86::LEA64r:
331  return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
332  }
333 }
334 
335 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
336 /// lea %reg, 1(%reg)
337 /// lea %reg, -1(%reg)
338 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
339  unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
340  unsigned DstReg = LEA.getOperand(0).getReg();
341  unsigned AddrDispOp = 1 + X86::AddrDisp;
342  return SrcReg == DstReg &&
343  LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
344  LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
345  LEA.getOperand(AddrDispOp).isImm() &&
346  (LEA.getOperand(AddrDispOp).getImm() == 1 ||
347  LEA.getOperand(AddrDispOp).getImm() == -1);
348 }
349 
350 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
351  MachineFunction::iterator MFI) const {
352  MachineInstr &MI = *I;
353  int Opcode = MI.getOpcode();
354  if (!isLEA(Opcode))
355  return false;
356 
357  if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
358  int NewOpcode;
359  bool isINC = MI.getOperand(4).getImm() == 1;
360  switch (Opcode) {
361  case X86::LEA16r:
362  NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
363  break;
364  case X86::LEA32r:
365  case X86::LEA64_32r:
366  NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
367  break;
368  case X86::LEA64r:
369  NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
370  break;
371  }
372 
373  MachineInstr *NewMI =
374  BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
375  .add(MI.getOperand(0))
376  .add(MI.getOperand(1));
377  MFI->erase(I);
378  I = static_cast<MachineBasicBlock::iterator>(NewMI);
379  return true;
380  }
381  return false;
382 }
383 
384 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
386  // Process a load, store, or LEA instruction.
387  MachineInstr &MI = *I;
388  const MCInstrDesc &Desc = MI.getDesc();
389  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
390  if (AddrOffset >= 0) {
391  AddrOffset += X86II::getOperandBias(Desc);
392  MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
393  if (p.isReg() && p.getReg() != X86::ESP) {
394  seekLEAFixup(p, I, MFI);
395  }
396  MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
397  if (q.isReg() && q.getReg() != X86::ESP) {
398  seekLEAFixup(q, I, MFI);
399  }
400  }
401 }
402 
403 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
406  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
407  if (MBI != MachineBasicBlock::iterator()) {
408  MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
409  if (NewMI) {
410  ++NumLEAs;
411  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
412  // now to replace with an equivalent LEA...
413  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
414  MFI->erase(MBI);
416  static_cast<MachineBasicBlock::iterator>(NewMI);
417  processInstruction(J, MFI);
418  }
419  }
420 }
421 
422 void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
424  MachineInstr &MI = *I;
425  const int Opcode = MI.getOpcode();
426  if (!isLEA(Opcode))
427  return;
428  if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
429  !TII->isSafeToClobberEFLAGS(*MFI, I))
430  return;
431  const unsigned DstR = MI.getOperand(0).getReg();
432  const unsigned SrcR1 = MI.getOperand(1).getReg();
433  const unsigned SrcR2 = MI.getOperand(3).getReg();
434  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
435  return;
436  if (MI.getOperand(2).getImm() > 1)
437  return;
438  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
439  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
440  MachineInstr *NewMI = nullptr;
441  // Make ADD instruction for two registers writing to LEA's destination
442  if (SrcR1 != 0 && SrcR2 != 0) {
443  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
444  const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
445  NewMI =
446  BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
447  LLVM_DEBUG(NewMI->dump(););
448  }
449  // Make ADD instruction for immediate
450  if (MI.getOperand(4).getImm() != 0) {
451  const MCInstrDesc &ADDri =
452  TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
453  const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
454  NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
455  .add(SrcR)
456  .addImm(MI.getOperand(4).getImm());
457  LLVM_DEBUG(NewMI->dump(););
458  }
459  if (NewMI) {
460  MFI->erase(I);
461  I = NewMI;
462  }
463 }
464 
465 MachineInstr *
466 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
468 
469  const int LEAOpcode = MI.getOpcode();
470  if (!isLEA(LEAOpcode))
471  return nullptr;
472 
473  const MachineOperand &Dst = MI.getOperand(0);
474  const MachineOperand &Base = MI.getOperand(1);
475  const MachineOperand &Scale = MI.getOperand(2);
476  const MachineOperand &Index = MI.getOperand(3);
477  const MachineOperand &Offset = MI.getOperand(4);
478  const MachineOperand &Segment = MI.getOperand(5);
479 
480  if (!(isThreeOperandsLEA(Base, Index, Offset) ||
481  hasInefficientLEABaseReg(Base, Index)) ||
482  !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
483  Segment.getReg() != X86::NoRegister)
484  return nullptr;
485 
486  unsigned int DstR = Dst.getReg();
487  unsigned int BaseR = Base.getReg();
488  unsigned int IndexR = Index.getReg();
489  unsigned SSDstR =
490  (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
491  bool IsScale1 = Scale.getImm() == 1;
492  bool IsInefficientBase = isInefficientLEAReg(BaseR);
493  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
494 
495  // Skip these cases since it takes more than 2 instructions
496  // to replace the LEA instruction.
497  if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
498  return nullptr;
499  if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
500  (IsInefficientIndex || !IsScale1))
501  return nullptr;
502 
503  const DebugLoc DL = MI.getDebugLoc();
504  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
505  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
506 
507  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
508  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
509 
510  // First try to replace LEA with one or two (for the 3-op LEA case)
511  // add instructions:
512  // 1.lea (%base,%index,1), %base => add %index,%base
513  // 2.lea (%base,%index,1), %index => add %base,%index
514  if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
515  const MachineOperand &Src = DstR == BaseR ? Index : Base;
516  MachineInstr *NewMI =
517  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
518  LLVM_DEBUG(NewMI->dump(););
519  // Create ADD instruction for the Offset in case of 3-Ops LEA.
520  if (hasLEAOffset(Offset)) {
521  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
522  LLVM_DEBUG(NewMI->dump(););
523  }
524  return NewMI;
525  }
526  // If the base is inefficient try switching the index and base operands,
527  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
528  // lea offset(%base,%index,scale),%dst =>
529  // lea (%base,%index,scale); add offset,%dst
530  if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
531  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
532  .add(Dst)
533  .add(IsInefficientBase ? Index : Base)
534  .add(Scale)
535  .add(IsInefficientBase ? Base : Index)
536  .addImm(0)
537  .add(Segment);
538  LLVM_DEBUG(NewMI->dump(););
539  // Create ADD instruction for the Offset in case of 3-Ops LEA.
540  if (hasLEAOffset(Offset)) {
541  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
542  LLVM_DEBUG(NewMI->dump(););
543  }
544  return NewMI;
545  }
546  // Handle the rest of the cases with inefficient base register:
547  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
548  assert(IsInefficientBase && "efficient base should be handled already!");
549 
550  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
551  if (IsScale1 && !hasLEAOffset(Offset)) {
552  bool BIK = Base.isKill() && BaseR != IndexR;
553  TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK);
554  LLVM_DEBUG(MI.getPrevNode()->dump(););
555 
556  MachineInstr *NewMI =
557  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
558  LLVM_DEBUG(NewMI->dump(););
559  return NewMI;
560  }
561  // lea offset(%base,%index,scale), %dst =>
562  // lea offset( ,%index,scale), %dst; add %base,%dst
563  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
564  .add(Dst)
565  .addReg(0)
566  .add(Scale)
567  .add(Index)
568  .add(Offset)
569  .add(Segment);
570  LLVM_DEBUG(NewMI->dump(););
571 
572  NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
573  LLVM_DEBUG(NewMI->dump(););
574  return NewMI;
575 }
576 
577 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
579 
580  for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
581  if (OptIncDec)
582  if (fixupIncDec(I, MFI))
583  continue;
584 
585  if (OptLEA) {
586  if (MF.getSubtarget<X86Subtarget>().isSLM())
587  processInstructionForSLM(I, MFI);
588 
589  else {
590  if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
591  if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
592  MFI->erase(I);
593  I = NewMI;
594  }
595  } else
596  processInstruction(I, MFI);
597  }
598  }
599  }
600  return false;
601 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static bool isRegOperand(const MachineOperand &Op)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isLEASimpleIncOrDec(MachineInstr &LEA)
isLEASimpleIncOrDec - Does this LEA have one these forms: lea reg, 1(reg) lea reg, -1(reg)
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:467
bool slowLEA() const
Definition: X86Subtarget.h:629
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:161
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
static bool getPreviousInstr(MachineBasicBlock::iterator &I, MachineFunction::iterator MFI)
getPreviousInstr - Given a reference to an instruction in a basic block, return a reference to the pr...
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:295
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
static bool isLEA(const int Opcode)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static int getADDrrFromLEA(int LEAOpcode)
static bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index)
hasIneffecientLEARegs - LEA that uses base and index registers where the base is EBP, RBP, or R13
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool slow3OpsLEA() const
Definition: X86Subtarget.h:630
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
static int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
bool isSLM() const
Definition: X86Subtarget.h:685
static bool isInefficientLEAReg(unsigned int Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void initializeFixupLEAPassPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:653
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool slowIncDec() const
Definition: X86Subtarget.h:631
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
#define FIXUPLEA_DESC
Iterator for intrusive lists based on ilist_node.
bool LEAusesAG() const
Definition: X86Subtarget.h:628
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isThreeOperandsLEA(const MachineOperand &Base, const MachineOperand &Index, const MachineOperand &Offset)
#define FIXUPLEA_NAME
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool hasLEAOffset(const MachineOperand &Offset)
#define I(x, y, z)
Definition: MD5.cpp:58
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:581
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Properties which a MachineFunction may have at a given point in time.
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:694