LLVM  9.0.0svn
X86FixupLEAs.cpp
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1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass that finds instructions that can be
10 // re-written as LEA instructions in order to reduce pipeline delays.
11 // When optimizing for size it replaces suitable LEAs with INC or DEC.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86.h"
16 #include "X86InstrInfo.h"
17 #include "X86Subtarget.h"
18 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Support/Debug.h"
25 using namespace llvm;
26 
27 #define FIXUPLEA_DESC "X86 LEA Fixup"
28 #define FIXUPLEA_NAME "x86-fixup-LEAs"
29 
30 #define DEBUG_TYPE FIXUPLEA_NAME
31 
32 STATISTIC(NumLEAs, "Number of LEA instructions created");
33 
34 namespace {
35 class FixupLEAPass : public MachineFunctionPass {
36  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
37 
38  /// Loop over all of the instructions in the basic block
39  /// replacing applicable instructions with LEA instructions,
40  /// where appropriate.
41  bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI,
42  bool IsSlowLEA, bool IsSlow3OpsLEA);
43 
44  /// Given a machine register, look for the instruction
45  /// which writes it in the current basic block. If found,
46  /// try to replace it with an equivalent LEA instruction.
47  /// If replacement succeeds, then also process the newly created
48  /// instruction.
49  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
51 
52  /// Given a memory access or LEA instruction
53  /// whose address mode uses a base and/or index register, look for
54  /// an opportunity to replace the instruction which sets the base or index
55  /// register with an equivalent LEA instruction.
56  void processInstruction(MachineBasicBlock::iterator &I,
58 
59  /// Given a LEA instruction which is unprofitable
60  /// on SlowLEA targets try to replace it with an equivalent ADD instruction.
61  void processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
63 
64  /// Given a LEA instruction which is unprofitable
65  /// on SNB+ try to replace it with other instructions.
66  /// According to Intel's Optimization Reference Manual:
67  /// " For LEA instructions with three source operands and some specific
68  /// situations, instruction latency has increased to 3 cycles, and must
69  /// dispatch via port 1:
70  /// - LEA that has all three source operands: base, index, and offset
71  /// - LEA that uses base and index registers where the base is EBP, RBP,
72  /// or R13
73  /// - LEA that uses RIP relative addressing mode
74  /// - LEA that uses 16-bit addressing mode "
75  /// This function currently handles the first 2 cases only.
76  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
78 
79  /// Look for LEAs that add 1 to reg or subtract 1 from reg
80  /// and convert them to INC or DEC respectively.
81  bool fixupIncDec(MachineBasicBlock::iterator &I,
82  MachineFunction::iterator MFI) const;
83 
84  /// Determine if an instruction references a machine register
85  /// and, if so, whether it reads or writes the register.
86  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
87 
88  /// Step backwards through a basic block, looking
89  /// for an instruction which writes a register within
90  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
94 
95  /// if an instruction can be converted to an
96  /// equivalent LEA, insert the new instruction into the basic block
97  /// and return a pointer to it. Otherwise, return zero.
98  MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
99  MachineBasicBlock::iterator &MBBI) const;
100 
101 public:
102  static char ID;
103 
104  StringRef getPassName() const override { return FIXUPLEA_DESC; }
105 
106  FixupLEAPass() : MachineFunctionPass(ID) {
108  }
109 
110  /// Loop over all of the basic blocks,
111  /// replacing instructions by equivalent LEA instructions
112  /// if needed and when possible.
113  bool runOnMachineFunction(MachineFunction &MF) override;
114 
115  // This pass runs after regalloc and doesn't support VReg operands.
116  MachineFunctionProperties getRequiredProperties() const override {
119  }
120 
121 private:
122  TargetSchedModel TSM;
123  MachineFunction *MF;
124  const X86InstrInfo *TII; // Machine instruction info.
125  bool OptIncDec;
126  bool OptLEA;
127 };
128 }
129 
130 char FixupLEAPass::ID = 0;
131 
132 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
133 
134 MachineInstr *
135 FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
136  MachineBasicBlock::iterator &MBBI) const {
137  MachineInstr &MI = *MBBI;
138  switch (MI.getOpcode()) {
139  case X86::MOV32rr:
140  case X86::MOV64rr: {
141  const MachineOperand &Src = MI.getOperand(1);
142  const MachineOperand &Dest = MI.getOperand(0);
143  MachineInstr *NewMI =
144  BuildMI(*MF, MI.getDebugLoc(),
145  TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
146  : X86::LEA64r))
147  .add(Dest)
148  .add(Src)
149  .addImm(1)
150  .addReg(0)
151  .addImm(0)
152  .addReg(0);
153  MFI->insert(MBBI, NewMI); // Insert the new inst
154  return NewMI;
155  }
156  }
157 
158  if (!MI.isConvertibleTo3Addr())
159  return nullptr;
160 
161  switch (MI.getOpcode()) {
162  case X86::ADD64ri32:
163  case X86::ADD64ri8:
164  case X86::ADD64ri32_DB:
165  case X86::ADD64ri8_DB:
166  case X86::ADD32ri:
167  case X86::ADD32ri8:
168  case X86::ADD32ri_DB:
169  case X86::ADD32ri8_DB:
170  case X86::ADD16ri:
171  case X86::ADD16ri8:
172  case X86::ADD16ri_DB:
173  case X86::ADD16ri8_DB:
174  if (!MI.getOperand(2).isImm()) {
175  // convertToThreeAddress will call getImm()
176  // which requires isImm() to be true
177  return nullptr;
178  }
179  break;
180  case X86::ADD16rr:
181  case X86::ADD16rr_DB:
182  if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
183  // if src1 != src2, then convertToThreeAddress will
184  // need to create a Virtual register, which we cannot do
185  // after register allocation.
186  return nullptr;
187  }
188  }
189  return TII->convertToThreeAddress(MFI, MI, nullptr);
190 }
191 
192 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
193 
194 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
195  if (skipFunction(Func.getFunction()))
196  return false;
197 
198  MF = &Func;
199  const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
200  bool IsSlowLEA = ST.slowLEA();
201  bool IsSlow3OpsLEA = ST.slow3OpsLEA();
202 
203  OptIncDec = !ST.slowIncDec() || Func.getFunction().hasOptSize();
204  OptLEA = ST.LEAusesAG() || IsSlowLEA || IsSlow3OpsLEA;
205 
206  if (!OptLEA && !OptIncDec)
207  return false;
208 
209  TSM.init(&Func.getSubtarget());
210  TII = ST.getInstrInfo();
211 
212  LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
213  // Process all basic blocks.
214  for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
215  processBasicBlock(Func, I, IsSlowLEA, IsSlow3OpsLEA);
216  LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
217 
218  return true;
219 }
220 
221 FixupLEAPass::RegUsageState
222 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
223  RegUsageState RegUsage = RU_NotUsed;
224  MachineInstr &MI = *I;
225 
226  for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
227  MachineOperand &opnd = MI.getOperand(i);
228  if (opnd.isReg() && opnd.getReg() == p.getReg()) {
229  if (opnd.isDef())
230  return RU_Write;
231  RegUsage = RU_Read;
232  }
233  }
234  return RegUsage;
235 }
236 
237 /// getPreviousInstr - Given a reference to an instruction in a basic
238 /// block, return a reference to the previous instruction in the block,
239 /// wrapping around to the last instruction of the block if the block
240 /// branches to itself.
243  if (I == MFI->begin()) {
244  if (MFI->isPredecessor(&*MFI)) {
245  I = --MFI->end();
246  return true;
247  } else
248  return false;
249  }
250  --I;
251  return true;
252 }
253 
255 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
257  int InstrDistance = 1;
259  static const int INSTR_DISTANCE_THRESHOLD = 5;
260 
261  CurInst = I;
262  bool Found;
263  Found = getPreviousInstr(CurInst, MFI);
264  while (Found && I != CurInst) {
265  if (CurInst->isCall() || CurInst->isInlineAsm())
266  break;
267  if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
268  break; // too far back to make a difference
269  if (usesRegister(p, CurInst) == RU_Write) {
270  return CurInst;
271  }
272  InstrDistance += TSM.computeInstrLatency(&*CurInst);
273  Found = getPreviousInstr(CurInst, MFI);
274  }
276 }
277 
278 static inline bool isLEA(const unsigned Opcode) {
279  return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
280  Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
281 }
282 
283 static inline bool isInefficientLEAReg(unsigned Reg) {
284  return Reg == X86::EBP || Reg == X86::RBP ||
285  Reg == X86::R13D || Reg == X86::R13;
286 }
287 
288 static inline bool isRegOperand(const MachineOperand &Op) {
289  return Op.isReg() && Op.getReg() != X86::NoRegister;
290 }
291 
292 /// Returns true if this LEA uses base an index registers, and the base register
293 /// is known to be inefficient for the subtarget.
294 // TODO: use a variant scheduling class to model the latency profile
295 // of LEA instructions, and implement this logic as a scheduling predicate.
296 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
297  const MachineOperand &Index) {
298  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
299  isRegOperand(Index);
300 }
301 
302 static inline bool hasLEAOffset(const MachineOperand &Offset) {
303  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
304 }
305 
306 static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
307  switch (LEAOpcode) {
308  default:
309  llvm_unreachable("Unexpected LEA instruction");
310  case X86::LEA16r:
311  return X86::ADD16rr;
312  case X86::LEA32r:
313  return X86::ADD32rr;
314  case X86::LEA64_32r:
315  case X86::LEA64r:
316  return X86::ADD64rr;
317  }
318 }
319 
320 static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
321  const MachineOperand &Offset) {
322  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
323  switch (LEAOpcode) {
324  default:
325  llvm_unreachable("Unexpected LEA instruction");
326  case X86::LEA16r:
327  return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
328  case X86::LEA32r:
329  case X86::LEA64_32r:
330  return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
331  case X86::LEA64r:
332  return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
333  }
334 }
335 
336 /// isLEASimpleIncOrDec - Does this LEA have one these forms:
337 /// lea %reg, 1(%reg)
338 /// lea %reg, -1(%reg)
339 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
340  unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
341  unsigned DstReg = LEA.getOperand(0).getReg();
343  return SrcReg == DstReg &&
344  LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
345  LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
346  AddrDisp.isImm() &&
347  (AddrDisp.getImm() == 1 || AddrDisp.getImm() == -1);
348 }
349 
350 bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
351  MachineFunction::iterator MFI) const {
352  MachineInstr &MI = *I;
353  unsigned Opcode = MI.getOpcode();
354  if (!isLEA(Opcode))
355  return false;
356 
357  if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
358  unsigned NewOpcode;
359  bool isINC = MI.getOperand(1 + X86::AddrDisp).getImm() == 1;
360  switch (Opcode) {
361  case X86::LEA16r:
362  NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
363  break;
364  case X86::LEA32r:
365  case X86::LEA64_32r:
366  NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
367  break;
368  case X86::LEA64r:
369  NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
370  break;
371  }
372 
373  MachineInstr *NewMI =
374  BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
375  .add(MI.getOperand(0))
376  .add(MI.getOperand(1 + X86::AddrBaseReg));
377  MFI->erase(I);
378  I = static_cast<MachineBasicBlock::iterator>(NewMI);
379  return true;
380  }
381  return false;
382 }
383 
384 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
386  // Process a load, store, or LEA instruction.
387  MachineInstr &MI = *I;
388  const MCInstrDesc &Desc = MI.getDesc();
389  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
390  if (AddrOffset >= 0) {
391  AddrOffset += X86II::getOperandBias(Desc);
392  MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
393  if (p.isReg() && p.getReg() != X86::ESP) {
394  seekLEAFixup(p, I, MFI);
395  }
396  MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
397  if (q.isReg() && q.getReg() != X86::ESP) {
398  seekLEAFixup(q, I, MFI);
399  }
400  }
401 }
402 
403 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
406  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
407  if (MBI != MachineBasicBlock::iterator()) {
408  MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
409  if (NewMI) {
410  ++NumLEAs;
411  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
412  // now to replace with an equivalent LEA...
413  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
414  MFI->erase(MBI);
416  static_cast<MachineBasicBlock::iterator>(NewMI);
417  processInstruction(J, MFI);
418  }
419  }
420 }
421 
422 void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
424  MachineInstr &MI = *I;
425  const unsigned Opcode = MI.getOpcode();
426  if (!isLEA(Opcode))
427  return;
428 
429  const MachineOperand &Dst = MI.getOperand(0);
431  const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
434  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
435 
436  if (Segment.getReg() != 0 || !Offset.isImm() ||
437  !TII->isSafeToClobberEFLAGS(*MFI, I))
438  return;
439  const unsigned DstR = Dst.getReg();
440  const unsigned SrcR1 = Base.getReg();
441  const unsigned SrcR2 = Index.getReg();
442  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
443  return;
444  if (Scale.getImm() > 1)
445  return;
446  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
447  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
448  MachineInstr *NewMI = nullptr;
449  // Make ADD instruction for two registers writing to LEA's destination
450  if (SrcR1 != 0 && SrcR2 != 0) {
451  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
452  const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
453  NewMI =
454  BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
455  LLVM_DEBUG(NewMI->dump(););
456  }
457  // Make ADD instruction for immediate
458  if (Offset.getImm() != 0) {
459  const MCInstrDesc &ADDri =
460  TII->get(getADDriFromLEA(Opcode, Offset));
461  const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
462  NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
463  .add(SrcR)
464  .addImm(Offset.getImm());
465  LLVM_DEBUG(NewMI->dump(););
466  }
467  if (NewMI) {
468  MFI->erase(I);
469  I = NewMI;
470  }
471 }
472 
473 MachineInstr *
474 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
476 
477  const unsigned LEAOpcode = MI.getOpcode();
478  if (!isLEA(LEAOpcode))
479  return nullptr;
480 
481  const MachineOperand &Dst = MI.getOperand(0);
483  const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
486  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
487 
488  if (!(TII->isThreeOperandsLEA(MI) ||
489  hasInefficientLEABaseReg(Base, Index)) ||
490  !TII->isSafeToClobberEFLAGS(*MFI, MI) ||
491  Segment.getReg() != X86::NoRegister)
492  return nullptr;
493 
494  unsigned DstR = Dst.getReg();
495  unsigned BaseR = Base.getReg();
496  unsigned IndexR = Index.getReg();
497  unsigned SSDstR =
498  (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
499  bool IsScale1 = Scale.getImm() == 1;
500  bool IsInefficientBase = isInefficientLEAReg(BaseR);
501  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
502 
503  // Skip these cases since it takes more than 2 instructions
504  // to replace the LEA instruction.
505  if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
506  return nullptr;
507  if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
508  (IsInefficientIndex || !IsScale1))
509  return nullptr;
510 
511  const DebugLoc DL = MI.getDebugLoc();
512  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
513  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
514 
515  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
516  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
517 
518  // First try to replace LEA with one or two (for the 3-op LEA case)
519  // add instructions:
520  // 1.lea (%base,%index,1), %base => add %index,%base
521  // 2.lea (%base,%index,1), %index => add %base,%index
522  if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
523  const MachineOperand &Src = DstR == BaseR ? Index : Base;
524  MachineInstr *NewMI =
525  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
526  LLVM_DEBUG(NewMI->dump(););
527  // Create ADD instruction for the Offset in case of 3-Ops LEA.
528  if (hasLEAOffset(Offset)) {
529  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
530  LLVM_DEBUG(NewMI->dump(););
531  }
532  return NewMI;
533  }
534  // If the base is inefficient try switching the index and base operands,
535  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
536  // lea offset(%base,%index,scale),%dst =>
537  // lea (%base,%index,scale); add offset,%dst
538  if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
539  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
540  .add(Dst)
541  .add(IsInefficientBase ? Index : Base)
542  .add(Scale)
543  .add(IsInefficientBase ? Base : Index)
544  .addImm(0)
545  .add(Segment);
546  LLVM_DEBUG(NewMI->dump(););
547  // Create ADD instruction for the Offset in case of 3-Ops LEA.
548  if (hasLEAOffset(Offset)) {
549  NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
550  LLVM_DEBUG(NewMI->dump(););
551  }
552  return NewMI;
553  }
554  // Handle the rest of the cases with inefficient base register:
555  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
556  assert(IsInefficientBase && "efficient base should be handled already!");
557 
558  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
559  if (IsScale1 && !hasLEAOffset(Offset)) {
560  bool BIK = Base.isKill() && BaseR != IndexR;
561  TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK);
562  LLVM_DEBUG(MI.getPrevNode()->dump(););
563 
564  MachineInstr *NewMI =
565  BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
566  LLVM_DEBUG(NewMI->dump(););
567  return NewMI;
568  }
569  // lea offset(%base,%index,scale), %dst =>
570  // lea offset( ,%index,scale), %dst; add %base,%dst
571  MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
572  .add(Dst)
573  .addReg(0)
574  .add(Scale)
575  .add(Index)
576  .add(Offset)
577  .add(Segment);
578  LLVM_DEBUG(NewMI->dump(););
579 
580  NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
581  LLVM_DEBUG(NewMI->dump(););
582  return NewMI;
583 }
584 
585 bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
587  bool IsSlowLEA, bool IsSlow3OpsLEA) {
588  for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
589  if (OptIncDec)
590  if (fixupIncDec(I, MFI))
591  continue;
592 
593  if (OptLEA) {
594  if (IsSlowLEA) {
595  processInstructionForSlowLEA(I, MFI);
596  continue;
597  }
598 
599  if (IsSlow3OpsLEA) {
600  if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
601  MFI->erase(I);
602  I = NewMI;
603  }
604  continue;
605  }
606 
607  processInstruction(I, MFI);
608  }
609  }
610  return false;
611 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static bool isRegOperand(const MachineOperand &Op)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static bool isLEASimpleIncOrDec(MachineInstr &LEA)
isLEASimpleIncOrDec - Does this LEA have one these forms: lea reg, 1(reg) lea reg, -1(reg)
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:600
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:486
bool slowLEA() const
Definition: X86Subtarget.h:655
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
static bool getPreviousInstr(MachineBasicBlock::iterator &I, MachineFunction::iterator MFI)
getPreviousInstr - Given a reference to an instruction in a basic block, return a reference to the pr...
static bool isInefficientLEAReg(unsigned Reg)
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:33
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index)
Returns true if this LEA uses base an index registers, and the base register is known to be inefficie...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool slow3OpsLEA() const
Definition: X86Subtarget.h:656
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:865
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void initializeFixupLEAPassPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:721
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned getADDriFromLEA(unsigned LEAOpcode, const MachineOperand &Offset)
bool slowIncDec() const
Definition: X86Subtarget.h:657
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
#define FIXUPLEA_DESC
Iterator for intrusive lists based on ilist_node.
bool LEAusesAG() const
Definition: X86Subtarget.h:654
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static bool isLEA(const unsigned Opcode)
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static unsigned getADDrrFromLEA(unsigned LEAOpcode)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
#define FIXUPLEA_NAME
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool hasLEAOffset(const MachineOperand &Offset)
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Properties which a MachineFunction may have at a given point in time.
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:762