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X86InstrBuilder.h
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1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file exposes functions that may be used with BuildMI from the
10 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
11 //
12 // The BuildMem function may be used with the BuildMI function to add entire
13 // memory references in a single, typed, function call. X86 memory references
14 // can be very complex expressions (described in the README), so wrapping them
15 // up behind an easier to use interface makes sense. Descriptions of the
16 // functions are included below.
17 //
18 // For reference, the order of operands for memory references is:
19 // (Operand), Base, Scale, Index, Displacement.
20 //
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
24 #define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
25 
26 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include <cassert>
35 
36 namespace llvm {
37 
38 /// X86AddressMode - This struct holds a generalized full x86 address mode.
39 /// The base register can be a frame index, which will eventually be replaced
40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
41 /// also include the offset of a global value.
43  enum {
46  } BaseType;
47 
48  union {
49  unsigned Reg;
51  } Base;
52 
53  unsigned Scale;
54  unsigned IndexReg;
55  int Disp;
56  const GlobalValue *GV;
57  unsigned GVOpFlags;
58 
60  : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
61  GVOpFlags(0) {
62  Base.Reg = 0;
63  }
64 
66  assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
67 
68  if (BaseType == X86AddressMode::RegBase)
69  MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
70  false, false, false, 0, false));
71  else {
73  MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
74  }
75 
77  MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
78  false, false, 0, false));
79 
80  if (GV)
81  MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
82  else
84 
85  MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
86  false, 0, false));
87  }
88 };
89 
90 /// Compute the addressing mode from an machine instruction starting with the
91 /// given operand.
93  unsigned Operand) {
94  X86AddressMode AM;
95  const MachineOperand &Op0 = MI->getOperand(Operand);
96  if (Op0.isReg()) {
98  AM.Base.Reg = Op0.getReg();
99  } else {
101  AM.Base.FrameIndex = Op0.getIndex();
102  }
103 
104  const MachineOperand &Op1 = MI->getOperand(Operand + 1);
105  AM.Scale = Op1.getImm();
106 
107  const MachineOperand &Op2 = MI->getOperand(Operand + 2);
108  AM.IndexReg = Op2.getReg();
109 
110  const MachineOperand &Op3 = MI->getOperand(Operand + 3);
111  if (Op3.isGlobal())
112  AM.GV = Op3.getGlobal();
113  else
114  AM.Disp = Op3.getImm();
115 
116  return AM;
117 }
118 
119 /// addDirectMem - This function is used to add a direct memory reference to the
120 /// current instruction -- that is, a dereference of an address in a register,
121 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
122 ///
123 static inline const MachineInstrBuilder &
124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
125  // Because memory references are always represented with five
126  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
127  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
128 }
129 
130 /// Replace the address used in the instruction with the direct memory
131 /// reference.
132 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
133  unsigned Reg) {
134  // Direct memory address is in a form of: Reg, 1 (Scale), NoReg, 0, NoReg.
135  MI->getOperand(Operand).setReg(Reg);
136  MI->getOperand(Operand + 1).setImm(1);
137  MI->getOperand(Operand + 2).setReg(0);
138  MI->getOperand(Operand + 3).setImm(0);
139  MI->getOperand(Operand + 4).setReg(0);
140 }
141 
142 static inline const MachineInstrBuilder &
144  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
145 }
146 
147 static inline const MachineInstrBuilder &
149  return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
150 }
151 
152 /// addRegOffset - This function is used to add a memory reference of the form
153 /// [Reg + Offset], i.e., one with no scale or index, but with a
154 /// displacement. An example is: DWORD PTR [EAX + 4].
155 ///
156 static inline const MachineInstrBuilder &
158  unsigned Reg, bool isKill, int Offset) {
159  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160 }
161 
162 /// addRegReg - This function is used to add a memory reference of the form:
163 /// [Reg + Reg].
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
165  unsigned Reg1, bool isKill1,
166  unsigned Reg2, bool isKill2) {
167  return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168  .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
169 }
170 
171 static inline const MachineInstrBuilder &
173  const X86AddressMode &AM) {
174  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175 
177  MIB.addReg(AM.Base.Reg);
178  else {
180  MIB.addFrameIndex(AM.Base.FrameIndex);
181  }
182 
183  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184  if (AM.GV)
185  MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186  else
187  MIB.addImm(AM.Disp);
188 
189  return MIB.addReg(0);
190 }
191 
192 /// addFrameReference - This function is used to add a reference to the base of
193 /// an abstract object on the stack frame of the current function. This
194 /// reference has base register as the FrameIndex offset until it is resolved.
195 /// This allows a constant offset to be specified as well...
196 ///
197 static inline const MachineInstrBuilder &
198 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199  MachineInstr *MI = MIB;
200  MachineFunction &MF = *MI->getParent()->getParent();
201  MachineFrameInfo &MFI = MF.getFrameInfo();
202  const MCInstrDesc &MCID = MI->getDesc();
203  auto Flags = MachineMemOperand::MONone;
204  if (MCID.mayLoad())
205  Flags |= MachineMemOperand::MOLoad;
206  if (MCID.mayStore())
210  MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211  return addOffset(MIB.addFrameIndex(FI), Offset)
212  .addMemOperand(MMO);
213 }
214 
215 /// addConstantPoolReference - This function is used to add a reference to the
216 /// base of a constant value spilled to the per-function constant pool. The
217 /// reference uses the abstract ConstantPoolIndex which is retained until
218 /// either machine code emission or assembly output. In PIC mode on x86-32,
219 /// the GlobalBaseReg parameter can be used to make this a
220 /// GlobalBaseReg-relative reference.
221 ///
222 static inline const MachineInstrBuilder &
224  unsigned GlobalBaseReg, unsigned char OpFlags) {
225  //FIXME: factor this
226  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227  .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
228 }
229 
230 } // end namespace llvm
231 
232 #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
const MachineInstrBuilder & add(const MachineOperand &MO) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static const MachineInstrBuilder & addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags)
addConstantPoolReference - This function is used to add a reference to the base of a constant value s...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
const GlobalValue * GV
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:399
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
A description of a memory reference used in the backend.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getKillRegState(bool B)
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const GlobalValue * getGlobal() const
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
void setImm(int64_t immVal)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
const MachineInstrBuilder & addFrameIndex(int Idx) const
enum llvm::X86AddressMode::@507 BaseType
static X86AddressMode getAddressFromInstr(const MachineInstr *MI, unsigned Operand)
Compute the addressing mode from an machine instruction starting with the given operand.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The memory access writes data.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperand class - Representation of each machine instruction operand.
static const MachineInstrBuilder & addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2)
addRegReg - This function is used to add a memory reference of the form: [Reg + Reg].
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
union llvm::X86AddressMode::@508 Base
void getFullAddress(SmallVectorImpl< MachineOperand > &MO)
int64_t getImm() const
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:405
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static const MachineInstrBuilder & addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg)
addDirectMem - This function is used to add a direct memory reference to the current instruction – t...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static const MachineInstrBuilder & addOffset(const MachineInstrBuilder &MIB, int Offset)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand, unsigned Reg)
Replace the address used in the instruction with the direct memory reference.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
X86AddressMode - This struct holds a generalized full x86 address mode.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
static MachineOperand CreateFI(int Idx)
static const MachineInstrBuilder & addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM)